This is an archive of the discontinued LLVM Phabricator instance.

Differential D95113

[RISCV] Add intrinsics for RVV v1.0 VFRSQRTE7 & VFRECE7
ClosedPublic

Authored by arcbbb on Jan 20 2021, 7:22 PM.

Details

Reviewers
craig.topper
evandro
rogfer01
frasercrmck
Commits
rG96677503315e: [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
Summary

It is a new instruction introduced in RISCV-V extension 1.0,
and it depends on D93613.

Diff Detail

Event Timeline

arcbbb created this revision.Jan 20 2021, 7:22 PM
Herald added subscribers: NickHung, luismarques, apazos and 23 others. · View Herald TranscriptJan 20 2021, 7:22 PM
arcbbb requested review of this revision.Jan 20 2021, 7:22 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2021, 7:22 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
craig.topper accepted this revision.Jan 20 2021, 8:09 PM

LGTM

This revision is now accepted and ready to land.Jan 20 2021, 8:09 PM
Harbormaster completed remote builds in B86030: Diff 318092.Jan 20 2021, 11:48 PM
frasercrmck accepted this revision.Jan 21 2021, 1:09 AM

LGTM

Closed by commit rG96677503315e: [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7 (authored by arcbbb). · Explain WhyJan 21 2021, 6:43 PM
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rG96677503315e: [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7.

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
2 lines
lib/
Target/
RISCV/
20 lines
test/
CodeGen/
RISCV/
602 lines
602 lines
602 lines
602 lines

Diff 318388

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 859 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vfnmsub : RISCVTernaryAAXA; defm vfnmsub : RISCVTernaryAAXA;
defm vfwmacc : RISCVTernaryWide; defm vfwmacc : RISCVTernaryWide;
defm vfwnmacc : RISCVTernaryWide; defm vfwnmacc : RISCVTernaryWide;
defm vfwmsac : RISCVTernaryWide; defm vfwmsac : RISCVTernaryWide;
defm vfwnmsac : RISCVTernaryWide; defm vfwnmsac : RISCVTernaryWide;
defm vfsqrt : RISCVUnaryAA; defm vfsqrt : RISCVUnaryAA;
defm vfrsqrte7 : RISCVUnaryAA;
defm vfrece7 : RISCVUnaryAA;
defm vfmin : RISCVBinaryAAX; defm vfmin : RISCVBinaryAAX;
defm vfmax : RISCVBinaryAAX; defm vfmax : RISCVBinaryAAX;
defm vfsgnj : RISCVBinaryAAX; defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX; defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX; defm vfsgnjx : RISCVBinaryAAX;
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 3,207 Lines • ▼ Show 20 Lines
defm PseudoVFWNMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>; defm PseudoVFWNMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFSQRT : VPseudoUnaryV_V; defm PseudoVFSQRT : VPseudoUnaryV_V;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
//===----------------------------------------------------------------------===//
defm PseudoVFRSQRTE7 : VPseudoUnaryV_V;
//===----------------------------------------------------------------------===//
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
defm PseudoVFRECE7 : VPseudoUnaryV_V;
//===----------------------------------------------------------------------===//
// 14.11. Vector Floating-Point Min/Max Instructions // 14.11. Vector Floating-Point Min/Max Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFMIN : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFMIN : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
defm PseudoVFMAX : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFMAX : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 643 Lines • ▼ Show 20 Lines
defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>; defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>; defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
//===----------------------------------------------------------------------===//
defm "" : VPatUnaryV_V<"int_riscv_vfrsqrte7", "PseudoVFRSQRTE7", AllFloatVectors>;
//===----------------------------------------------------------------------===//
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
defm "" : VPatUnaryV_V<"int_riscv_vfrece7", "PseudoVFRECE7", AllFloatVectors>;
//===----------------------------------------------------------------------===//
// 14.11. Vector Floating-Point Min/Max Instructions // 14.11. Vector Floating-Point Min/Max Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/vfrece7-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrece7.nxv1f16(
<vscale x 1 x half>,
i32);
define <vscale x 1 x half> @intrinsic_vfrece7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrece7.nxv1f16(
<vscale x 1 x half> %0,
i32 %1)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrece7.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x half> @intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrece7.mask.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrece7.nxv2f16(
<vscale x 2 x half>,
i32);
define <vscale x 2 x half> @intrinsic_vfrece7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrece7.nxv2f16(
<vscale x 2 x half> %0,
i32 %1)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrece7.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x half> @intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrece7.mask.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrece7.nxv4f16(
<vscale x 4 x half>,
i32);
define <vscale x 4 x half> @intrinsic_vfrece7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrece7.nxv4f16(
<vscale x 4 x half> %0,
i32 %1)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrece7.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x half> @intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrece7.mask.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrece7.nxv8f16(
<vscale x 8 x half>,
i32);
define <vscale x 8 x half> @intrinsic_vfrece7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrece7.nxv8f16(
<vscale x 8 x half> %0,
i32 %1)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrece7.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x half> @intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrece7.mask.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrece7.nxv16f16(
<vscale x 16 x half>,
i32);
define <vscale x 16 x half> @intrinsic_vfrece7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrece7.nxv16f16(
<vscale x 16 x half> %0,
i32 %1)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrece7.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x half> @intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrece7.mask.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %0,
i32 %3)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrece7.nxv32f16(
<vscale x 32 x half>,
i32);
define <vscale x 32 x half> @intrinsic_vfrece7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrece7.nxv32f16(
<vscale x 32 x half> %0,
i32 %1)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrece7.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x half> @intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrece7.mask.nxv32f16(
<vscale x 32 x half> %1,
<vscale x 32 x half> %2,
<vscale x 32 x i1> %0,
i32 %3)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrece7.nxv1f32(
<vscale x 1 x float>,
i32);
define <vscale x 1 x float> @intrinsic_vfrece7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrece7.nxv1f32(
<vscale x 1 x float> %0,
i32 %1)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrece7.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrece7.mask.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrece7.nxv2f32(
<vscale x 2 x float>,
i32);
define <vscale x 2 x float> @intrinsic_vfrece7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrece7.nxv2f32(
<vscale x 2 x float> %0,
i32 %1)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrece7.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrece7.mask.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrece7.nxv4f32(
<vscale x 4 x float>,
i32);
define <vscale x 4 x float> @intrinsic_vfrece7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrece7.nxv4f32(
<vscale x 4 x float> %0,
i32 %1)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrece7.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrece7.mask.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrece7.nxv8f32(
<vscale x 8 x float>,
i32);
define <vscale x 8 x float> @intrinsic_vfrece7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrece7.nxv8f32(
<vscale x 8 x float> %0,
i32 %1)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrece7.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrece7.mask.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrece7.nxv16f32(
<vscale x 16 x float>,
i32);
define <vscale x 16 x float> @intrinsic_vfrece7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrece7.nxv16f32(
<vscale x 16 x float> %0,
i32 %1)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrece7.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrece7.mask.nxv16f32(
<vscale x 16 x float> %1,
<vscale x 16 x float> %2,
<vscale x 16 x i1> %0,
i32 %3)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrece7.nxv1f64(
<vscale x 1 x double>,
i32);
define <vscale x 1 x double> @intrinsic_vfrece7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrece7.nxv1f64(
<vscale x 1 x double> %0,
i32 %1)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrece7.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x double> @intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrece7.mask.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrece7.nxv2f64(
<vscale x 2 x double>,
i32);
define <vscale x 2 x double> @intrinsic_vfrece7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrece7.nxv2f64(
<vscale x 2 x double> %0,
i32 %1)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrece7.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x double> @intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrece7.mask.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrece7.nxv4f64(
<vscale x 4 x double>,
i32);
define <vscale x 4 x double> @intrinsic_vfrece7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrece7.nxv4f64(
<vscale x 4 x double> %0,
i32 %1)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrece7.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x double> @intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrece7.mask.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrece7.nxv8f64(
<vscale x 8 x double>,
i32);
define <vscale x 8 x double> @intrinsic_vfrece7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrece7.nxv8f64(
<vscale x 8 x double> %0,
i32 %1)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrece7.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x double> @intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrece7.mask.nxv8f64(
<vscale x 8 x double> %1,
<vscale x 8 x double> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/vfrece7-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrece7.nxv1f16(
<vscale x 1 x half>,
i64);
define <vscale x 1 x half> @intrinsic_vfrece7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrece7.nxv1f16(
<vscale x 1 x half> %0,
i64 %1)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrece7.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x half> @intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrece7.mask.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrece7.nxv2f16(
<vscale x 2 x half>,
i64);
define <vscale x 2 x half> @intrinsic_vfrece7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrece7.nxv2f16(
<vscale x 2 x half> %0,
i64 %1)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrece7.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x half> @intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrece7.mask.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrece7.nxv4f16(
<vscale x 4 x half>,
i64);
define <vscale x 4 x half> @intrinsic_vfrece7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrece7.nxv4f16(
<vscale x 4 x half> %0,
i64 %1)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrece7.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x half> @intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrece7.mask.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrece7.nxv8f16(
<vscale x 8 x half>,
i64);
define <vscale x 8 x half> @intrinsic_vfrece7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrece7.nxv8f16(
<vscale x 8 x half> %0,
i64 %1)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrece7.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x half> @intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrece7.mask.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrece7.nxv16f16(
<vscale x 16 x half>,
i64);
define <vscale x 16 x half> @intrinsic_vfrece7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrece7.nxv16f16(
<vscale x 16 x half> %0,
i64 %1)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrece7.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x half> @intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrece7.mask.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %0,
i64 %3)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrece7.nxv32f16(
<vscale x 32 x half>,
i64);
define <vscale x 32 x half> @intrinsic_vfrece7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrece7.nxv32f16(
<vscale x 32 x half> %0,
i64 %1)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrece7.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x half> @intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrece7.mask.nxv32f16(
<vscale x 32 x half> %1,
<vscale x 32 x half> %2,
<vscale x 32 x i1> %0,
i64 %3)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrece7.nxv1f32(
<vscale x 1 x float>,
i64);
define <vscale x 1 x float> @intrinsic_vfrece7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrece7.nxv1f32(
<vscale x 1 x float> %0,
i64 %1)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrece7.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrece7.mask.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrece7.nxv2f32(
<vscale x 2 x float>,
i64);
define <vscale x 2 x float> @intrinsic_vfrece7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrece7.nxv2f32(
<vscale x 2 x float> %0,
i64 %1)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrece7.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrece7.mask.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrece7.nxv4f32(
<vscale x 4 x float>,
i64);
define <vscale x 4 x float> @intrinsic_vfrece7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrece7.nxv4f32(
<vscale x 4 x float> %0,
i64 %1)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrece7.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrece7.mask.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrece7.nxv8f32(
<vscale x 8 x float>,
i64);
define <vscale x 8 x float> @intrinsic_vfrece7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrece7.nxv8f32(
<vscale x 8 x float> %0,
i64 %1)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrece7.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrece7.mask.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrece7.nxv16f32(
<vscale x 16 x float>,
i64);
define <vscale x 16 x float> @intrinsic_vfrece7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrece7.nxv16f32(
<vscale x 16 x float> %0,
i64 %1)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrece7.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrece7.mask.nxv16f32(
<vscale x 16 x float> %1,
<vscale x 16 x float> %2,
<vscale x 16 x i1> %0,
i64 %3)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrece7.nxv1f64(
<vscale x 1 x double>,
i64);
define <vscale x 1 x double> @intrinsic_vfrece7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrece7.nxv1f64(
<vscale x 1 x double> %0,
i64 %1)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrece7.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfrece7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrece7.mask.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrece7.nxv2f64(
<vscale x 2 x double>,
i64);
define <vscale x 2 x double> @intrinsic_vfrece7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrece7.nxv2f64(
<vscale x 2 x double> %0,
i64 %1)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrece7.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfrece7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrece7.mask.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrece7.nxv4f64(
<vscale x 4 x double>,
i64);
define <vscale x 4 x double> @intrinsic_vfrece7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrece7.nxv4f64(
<vscale x 4 x double> %0,
i64 %1)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrece7.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfrece7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrece7.mask.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrece7.nxv8f64(
<vscale x 8 x double>,
i64);
define <vscale x 8 x double> @intrinsic_vfrece7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfrece7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrece7.nxv8f64(
<vscale x 8 x double> %0,
i64 %1)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrece7.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrece7_mask_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfrece7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrece7.mask.nxv8f64(
<vscale x 8 x double> %1,
<vscale x 8 x double> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrsqrte7.nxv1f16(
<vscale x 1 x half>,
i32);
define <vscale x 1 x half> @intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrte7.nxv1f16(
<vscale x 1 x half> %0,
i32 %1)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrsqrte7.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x half> @intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrte7.mask.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrsqrte7.nxv2f16(
<vscale x 2 x half>,
i32);
define <vscale x 2 x half> @intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrsqrte7.nxv2f16(
<vscale x 2 x half> %0,
i32 %1)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrsqrte7.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x half> @intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrsqrte7.mask.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrsqrte7.nxv4f16(
<vscale x 4 x half>,
i32);
define <vscale x 4 x half> @intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrsqrte7.nxv4f16(
<vscale x 4 x half> %0,
i32 %1)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrsqrte7.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x half> @intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrsqrte7.mask.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrsqrte7.nxv8f16(
<vscale x 8 x half>,
i32);
define <vscale x 8 x half> @intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrsqrte7.nxv8f16(
<vscale x 8 x half> %0,
i32 %1)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrsqrte7.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x half> @intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrsqrte7.mask.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrsqrte7.nxv16f16(
<vscale x 16 x half>,
i32);
define <vscale x 16 x half> @intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrsqrte7.nxv16f16(
<vscale x 16 x half> %0,
i32 %1)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrsqrte7.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x half> @intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrsqrte7.mask.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %0,
i32 %3)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrsqrte7.nxv32f16(
<vscale x 32 x half>,
i32);
define <vscale x 32 x half> @intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrsqrte7.nxv32f16(
<vscale x 32 x half> %0,
i32 %1)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrsqrte7.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x half> @intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrsqrte7.mask.nxv32f16(
<vscale x 32 x half> %1,
<vscale x 32 x half> %2,
<vscale x 32 x i1> %0,
i32 %3)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrsqrte7.nxv1f32(
<vscale x 1 x float>,
i32);
define <vscale x 1 x float> @intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrsqrte7.nxv1f32(
<vscale x 1 x float> %0,
i32 %1)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrsqrte7.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrsqrte7.mask.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrsqrte7.nxv2f32(
<vscale x 2 x float>,
i32);
define <vscale x 2 x float> @intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrsqrte7.nxv2f32(
<vscale x 2 x float> %0,
i32 %1)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrsqrte7.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrsqrte7.mask.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrsqrte7.nxv4f32(
<vscale x 4 x float>,
i32);
define <vscale x 4 x float> @intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrsqrte7.nxv4f32(
<vscale x 4 x float> %0,
i32 %1)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrsqrte7.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrsqrte7.mask.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrsqrte7.nxv8f32(
<vscale x 8 x float>,
i32);
define <vscale x 8 x float> @intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrsqrte7.nxv8f32(
<vscale x 8 x float> %0,
i32 %1)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrsqrte7.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrsqrte7.mask.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrsqrte7.nxv16f32(
<vscale x 16 x float>,
i32);
define <vscale x 16 x float> @intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrsqrte7.nxv16f32(
<vscale x 16 x float> %0,
i32 %1)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrsqrte7.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrsqrte7.mask.nxv16f32(
<vscale x 16 x float> %1,
<vscale x 16 x float> %2,
<vscale x 16 x i1> %0,
i32 %3)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrsqrte7.nxv1f64(
<vscale x 1 x double>,
i32);
define <vscale x 1 x double> @intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrsqrte7.nxv1f64(
<vscale x 1 x double> %0,
i32 %1)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrsqrte7.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x double> @intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrsqrte7.mask.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %0,
i32 %3)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrsqrte7.nxv2f64(
<vscale x 2 x double>,
i32);
define <vscale x 2 x double> @intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrsqrte7.nxv2f64(
<vscale x 2 x double> %0,
i32 %1)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrsqrte7.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x double> @intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrsqrte7.mask.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
<vscale x 2 x i1> %0,
i32 %3)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrsqrte7.nxv4f64(
<vscale x 4 x double>,
i32);
define <vscale x 4 x double> @intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrsqrte7.nxv4f64(
<vscale x 4 x double> %0,
i32 %1)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrsqrte7.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x double> @intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrsqrte7.mask.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
<vscale x 4 x i1> %0,
i32 %3)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrsqrte7.nxv8f64(
<vscale x 8 x double>,
i32);
define <vscale x 8 x double> @intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrsqrte7.nxv8f64(
<vscale x 8 x double> %0,
i32 %1)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrsqrte7.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x double> @intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrsqrte7.mask.nxv8f64(
<vscale x 8 x double> %1,
<vscale x 8 x double> %2,
<vscale x 8 x i1> %0,
i32 %3)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrsqrte7.nxv1f16(
<vscale x 1 x half>,
i64);
define <vscale x 1 x half> @intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrte7.nxv1f16(
<vscale x 1 x half> %0,
i64 %1)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrsqrte7.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x half> @intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrte7.mask.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrsqrte7.nxv2f16(
<vscale x 2 x half>,
i64);
define <vscale x 2 x half> @intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrsqrte7.nxv2f16(
<vscale x 2 x half> %0,
i64 %1)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfrsqrte7.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x half> @intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrsqrte7.mask.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrsqrte7.nxv4f16(
<vscale x 4 x half>,
i64);
define <vscale x 4 x half> @intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrsqrte7.nxv4f16(
<vscale x 4 x half> %0,
i64 %1)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfrsqrte7.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x half> @intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrsqrte7.mask.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrsqrte7.nxv8f16(
<vscale x 8 x half>,
i64);
define <vscale x 8 x half> @intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrsqrte7.nxv8f16(
<vscale x 8 x half> %0,
i64 %1)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfrsqrte7.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x half> @intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrsqrte7.mask.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrsqrte7.nxv16f16(
<vscale x 16 x half>,
i64);
define <vscale x 16 x half> @intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrsqrte7.nxv16f16(
<vscale x 16 x half> %0,
i64 %1)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfrsqrte7.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x half> @intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrsqrte7.mask.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %0,
i64 %3)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrsqrte7.nxv32f16(
<vscale x 32 x half>,
i64);
define <vscale x 32 x half> @intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrsqrte7.nxv32f16(
<vscale x 32 x half> %0,
i64 %1)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfrsqrte7.mask.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x half> @intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrsqrte7.mask.nxv32f16(
<vscale x 32 x half> %1,
<vscale x 32 x half> %2,
<vscale x 32 x i1> %0,
i64 %3)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrsqrte7.nxv1f32(
<vscale x 1 x float>,
i64);
define <vscale x 1 x float> @intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrsqrte7.nxv1f32(
<vscale x 1 x float> %0,
i64 %1)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfrsqrte7.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrsqrte7.mask.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrsqrte7.nxv2f32(
<vscale x 2 x float>,
i64);
define <vscale x 2 x float> @intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrsqrte7.nxv2f32(
<vscale x 2 x float> %0,
i64 %1)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfrsqrte7.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrsqrte7.mask.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrsqrte7.nxv4f32(
<vscale x 4 x float>,
i64);
define <vscale x 4 x float> @intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrsqrte7.nxv4f32(
<vscale x 4 x float> %0,
i64 %1)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfrsqrte7.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrsqrte7.mask.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrsqrte7.nxv8f32(
<vscale x 8 x float>,
i64);
define <vscale x 8 x float> @intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrsqrte7.nxv8f32(
<vscale x 8 x float> %0,
i64 %1)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfrsqrte7.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrsqrte7.mask.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrsqrte7.nxv16f32(
<vscale x 16 x float>,
i64);
define <vscale x 16 x float> @intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrsqrte7.nxv16f32(
<vscale x 16 x float> %0,
i64 %1)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfrsqrte7.mask.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrsqrte7.mask.nxv16f32(
<vscale x 16 x float> %1,
<vscale x 16 x float> %2,
<vscale x 16 x i1> %0,
i64 %3)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrsqrte7.nxv1f64(
<vscale x 1 x double>,
i64);
define <vscale x 1 x double> @intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrsqrte7.nxv1f64(
<vscale x 1 x double> %0,
i64 %1)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfrsqrte7.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrsqrte7.mask.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %0,
i64 %3)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrsqrte7.nxv2f64(
<vscale x 2 x double>,
i64);
define <vscale x 2 x double> @intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrsqrte7.nxv2f64(
<vscale x 2 x double> %0,
i64 %1)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfrsqrte7.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrsqrte7.mask.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
<vscale x 2 x i1> %0,
i64 %3)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrsqrte7.nxv4f64(
<vscale x 4 x double>,
i64);
define <vscale x 4 x double> @intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrsqrte7.nxv4f64(
<vscale x 4 x double> %0,
i64 %1)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfrsqrte7.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrsqrte7.mask.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
<vscale x 4 x i1> %0,
i64 %3)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrsqrte7.nxv8f64(
<vscale x 8 x double>,
i64);
define <vscale x 8 x double> @intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfrsqrte7.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrsqrte7.nxv8f64(
<vscale x 8 x double> %0,
i64 %1)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfrsqrte7.mask.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrte7_mask_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfrsqrte7.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrsqrte7.mask.nxv8f64(
<vscale x 8 x double> %1,
<vscale x 8 x double> %2,
<vscale x 8 x i1> %0,
i64 %3)
ret <vscale x 8 x double> %a
}