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Differential D94742

[RISCV] Move pack instructions to Zbp extension only.
ClosedPublic

Authored by craig.topper on Jan 14 2021, 7:44 PM.

Details

Reviewers
asb
luismarques
PaoloS
lewis-revill
frasercrmck
simoncook
Commits
rG83c92fdeda6b: [RISCV] Move pack instructions to Zbp extension only.
Summary

Zext.h will need to come back to Zbb, but that only uses specific
encodings.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 14 2021, 7:44 PM
Herald added subscribers: NickHung, evandro, apazos and 22 others. · View Herald TranscriptJan 14 2021, 7:44 PM
craig.topper requested review of this revision.Jan 14 2021, 7:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2021, 7:44 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B85286: Diff 316835.Jan 14 2021, 7:45 PM
craig.topper added a child revision: D94818: [RISCV] Add zext.h instruction to Zbb..Jan 19 2021, 12:18 PM
craig.topper added a parent revision: D94736: [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack..
frasercrmck accepted this revision.Jan 20 2021, 3:54 AM

LGTM

This revision is now accepted and ready to land.Jan 20 2021, 3:54 AM
craig.topper updated this revision to Diff 318045.Jan 20 2021, 3:50 PM

Rebase

Harbormaster completed remote builds in B85999: Diff 318045.Jan 20 2021, 8:41 PM
craig.topper updated this revision to Diff 318236.Jan 21 2021, 9:17 AM

Move pack tests from rv32zbbp-invalid.s to rv32zbp-invalid.s

Harbormaster completed remote builds in B86114: Diff 318236.Jan 21 2021, 10:48 AM
asb accepted this revision.Jan 22 2021, 9:30 AM
Closed by commit rG83c92fdeda6b: [RISCV] Move pack instructions to Zbp extension only. (authored by craig.topper). · Explain WhyJan 22 2021, 12:51 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG83c92fdeda6b: [RISCV] Move pack instructions to Zbp extension only..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
34 lines
test/
CodeGen/
RISCV/
249 lines
206 lines
183 lines
195 lines
MC/
RISCV/
9 lines
9 lines
6 lines
6 lines

Diff 318045

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

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def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>; def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
} // Predicates = [HasStdExtZbp] } // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbe] in { let Predicates = [HasStdExtZbe] in {
def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>; def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>; def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
} // Predicates = [HasStdExtZbe] } // Predicates = [HasStdExtZbe]
let Predicates = [HasStdExtZbbOrZbp] in { let Predicates = [HasStdExtZbp] in {
def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>; def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>; def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
} // Predicates = [HasStdExtZbbOrZbp] def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbm, IsRV64] in { let Predicates = [HasStdExtZbm, IsRV64] in {
def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>; def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>; def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
} // Predicates = [HasStdExtZbm, IsRV64] } // Predicates = [HasStdExtZbm, IsRV64]
let Predicates = [HasStdExtZbbOrZbp] in
def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
let Predicates = [HasStdExtZbf] in let Predicates = [HasStdExtZbf] in
def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>; def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>; def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>; def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
} // Predicates = [HasStdExtZbp] } // Predicates = [HasStdExtZbp]
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def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>; def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbe, IsRV64] in { let Predicates = [HasStdExtZbe, IsRV64] in {
def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>; def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>; def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
} // Predicates = [HasStdExtZbe, IsRV64] } // Predicates = [HasStdExtZbe, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>; def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>; def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
} // Predicates = [HasStdExtZbbOrZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbf, IsRV64] in let Predicates = [HasStdExtZbf, IsRV64] in
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>; def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Future compressed instructions // Future compressed instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 23 Lines
let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in
def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>; def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo Instructions // Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZbb, IsRV32] in { let Predicates = [HasStdExtZbp, IsRV32] in {
def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>; def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV32] } // Predicates = [HasStdExtZbb, IsRV32]
let Predicates = [HasStdExtZbb, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>; def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZba, IsRV64] in { let Predicates = [HasStdExtZba, IsRV64] in {
def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>; def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
} }
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
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let Predicates = [HasStdExtZbb] in { let Predicates = [HasStdExtZbb] in {
def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN GPR:$rs1, GPR:$rs2)>; def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN GPR:$rs1, GPR:$rs2)>;
def : Pat<(smax GPR:$rs1, GPR:$rs2), (MAX GPR:$rs1, GPR:$rs2)>; def : Pat<(smax GPR:$rs1, GPR:$rs2), (MAX GPR:$rs1, GPR:$rs2)>;
def : Pat<(umin GPR:$rs1, GPR:$rs2), (MINU GPR:$rs1, GPR:$rs2)>; def : Pat<(umin GPR:$rs1, GPR:$rs2), (MINU GPR:$rs1, GPR:$rs2)>;
def : Pat<(umax GPR:$rs1, GPR:$rs2), (MAXU GPR:$rs1, GPR:$rs2)>; def : Pat<(umax GPR:$rs1, GPR:$rs2), (MAXU GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbb] } // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16))), def : Pat<(or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16))),
(PACK GPR:$rs1, GPR:$rs2)>; (PACK GPR:$rs1, GPR:$rs2)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in let Predicates = [HasStdExtZbp, IsRV64] in
def : Pat<(or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32))), def : Pat<(or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32))),
(PACK GPR:$rs1, GPR:$rs2)>; (PACK GPR:$rs1, GPR:$rs2)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16))), def : Pat<(or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16))),
(PACKU GPR:$rs1, GPR:$rs2)>; (PACKU GPR:$rs1, GPR:$rs2)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in let Predicates = [HasStdExtZbp, IsRV64] in
def : Pat<(or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32))), def : Pat<(or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32))),
(PACKU GPR:$rs1, GPR:$rs2)>; (PACKU GPR:$rs1, GPR:$rs2)>;
let Predicates = [HasStdExtZbbOrZbp] in let Predicates = [HasStdExtZbp] in
def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00), def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00),
(and GPR:$rs1, 0x00FF)), (and GPR:$rs1, 0x00FF)),
(PACKH GPR:$rs1, GPR:$rs2)>; (PACKH GPR:$rs1, GPR:$rs2)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(and GPR:$rs, 0x0000FFFF), (PACK GPR:$rs, X0)>; def : Pat<(and GPR:$rs, 0x0000FFFF), (PACK GPR:$rs, X0)>;
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def : Pat<(and GPR:$rs, 0x000000000000FFFF), (PACKW GPR:$rs, X0)>; def : Pat<(and GPR:$rs, 0x000000000000FFFF), (PACKW GPR:$rs, X0)>;
} }
let Predicates = [HasStdExtZbp, IsRV32] in { let Predicates = [HasStdExtZbp, IsRV32] in {
def : Pat<(or (or (and (shl GPR:$rs1, (i32 8)), (i32 0x00FF0000)), def : Pat<(or (or (and (shl GPR:$rs1, (i32 8)), (i32 0x00FF0000)),
(and GPR:$rs1, (i32 0xFF0000FF))), (and GPR:$rs1, (i32 0xFF0000FF))),
(and (srl GPR:$rs1, (i32 8)), (i32 0x0000FF00))), (and (srl GPR:$rs1, (i32 8)), (i32 0x0000FF00))),
(SHFLI GPR:$rs1, (i32 8))>; (SHFLI GPR:$rs1, (i32 8))>;
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def : Pat<(and (add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)), def : Pat<(and (add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
(i64 0xFFFFFFFF)), (i64 0xFFFFFFFF)),
(CLZW GPR:$rs1)>; (CLZW GPR:$rs1)>;
def : Pat<(cttz (or GPR:$rs1, (i64 0x100000000))), def : Pat<(cttz (or GPR:$rs1, (i64 0x100000000))),
(CTZW GPR:$rs1)>; (CTZW GPR:$rs1)>;
def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (CPOPW GPR:$rs1)>; def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (CPOPW GPR:$rs1)>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)), def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)),
(and GPR:$rs1, 0x000000000000FFFF)), (and GPR:$rs1, 0x000000000000FFFF)),
i32), i32),
(PACKW GPR:$rs1, GPR:$rs2)>; (PACKW GPR:$rs1, GPR:$rs2)>;
def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
(srl (and GPR:$rs1, 0x00000000FFFF0000), (srl (and GPR:$rs1, 0x00000000FFFF0000),
(i64 16))), (i64 16))),
(PACKUW GPR:$rs1, GPR:$rs2)>; (PACKUW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbbOrZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]

llvm/test/CodeGen/RISCV/rv32Zbbp.ll

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; RV32IBP-NEXT: srli a0, a0, 31 ; RV32IBP-NEXT: srli a0, a0, 31
; RV32IBP-NEXT: slli a1, a1, 1 ; RV32IBP-NEXT: slli a1, a1, 1
; RV32IBP-NEXT: or a1, a1, a0 ; RV32IBP-NEXT: or a1, a1, a0
; RV32IBP-NEXT: mv a0, a2 ; RV32IBP-NEXT: mv a0, a2
; RV32IBP-NEXT: ret ; RV32IBP-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %1 ret i64 %1
} }
define i32 @pack_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: pack_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: pack_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: pack a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: pack_i32:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: pack a0, a0, a1
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: pack_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: pack a0, a0, a1
; RV32IBP-NEXT: ret
%shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl
ret i32 %or
}
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: pack_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret
;
; RV32IB-LABEL: pack_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: mv a1, a2
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: pack_i64:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: mv a1, a2
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: pack_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: mv a1, a2
; RV32IBP-NEXT: ret
%shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl
ret i64 %or
}
define i32 @packu_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packu_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lui a2, 1048560
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packu_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packu a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: packu_i32:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: packu a0, a0, a1
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: packu_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packu a0, a0, a1
; RV32IBP-NEXT: ret
%shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr
ret i32 %or
}
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packu_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packu_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: mv a0, a1
; RV32IB-NEXT: mv a1, a3
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: packu_i64:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: mv a0, a1
; RV32IBB-NEXT: mv a1, a3
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: packu_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: mv a0, a1
; RV32IBP-NEXT: mv a1, a3
; RV32IBP-NEXT: ret
%shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr
ret i64 %or
}
define i32 @packh_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packh_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packh_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packh a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: packh_i32:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: packh a0, a0, a1
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: packh_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packh a0, a0, a1
; RV32IBP-NEXT: ret
%and = and i32 %a, 255
%and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280
%or = or i32 %shl, %and
ret i32 %or
}
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packh_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a2, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packh_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packh a0, a0, a2
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: packh_i64:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: packh a0, a0, a2
; RV32IBB-NEXT: mv a1, zero
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: packh_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packh a0, a0, a2
; RV32IBP-NEXT: mv a1, zero
; RV32IBP-NEXT: ret
%and = and i64 %a, 255
%and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280
%or = or i64 %shl, %and
ret i64 %or
}
define i32 @zexth_i32(i32 %a) nounwind {
; RV32I-LABEL: zexth_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: zexth_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: zext.h a0, a0
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: zexth_i32:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: zext.h a0, a0
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: zexth_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: pack a0, a0, zero
; RV32IBP-NEXT: ret
%and = and i32 %a, 65535
ret i32 %and
}
define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-LABEL: zexth_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
; RV32IB-LABEL: zexth_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: zext.h a0, a0
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: zexth_i64:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: zext.h a0, a0
; RV32IBB-NEXT: mv a1, zero
; RV32IBB-NEXT: ret
;
; RV32IBP-LABEL: zexth_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: pack a0, a0, zero
; RV32IBP-NEXT: mv a1, zero
; RV32IBP-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
}

llvm/test/CodeGen/RISCV/rv32Zbp.ll

Show First 20 Lines • Show All 3,429 Lines • ▼ Show 20 Lines; RV32IBP-NEXT: ret
%shl = shl i64 %a, 8 %shl = shl i64 %a, 8
%and1 = and i64 %shl, 71776119077928960 %and1 = and i64 %shl, 71776119077928960
%or = or i64 %and1, %and %or = or i64 %and1, %and
%shr = lshr i64 %a, 8 %shr = lshr i64 %a, 8
%and2 = and i64 %shr, 280375465148160 %and2 = and i64 %shr, 280375465148160
%or3 = or i64 %or, %and2 %or3 = or i64 %or, %and2
ret i64 %or3 ret i64 %or3
} }
define i32 @pack_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: pack_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: pack_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: pack a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: pack_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: pack a0, a0, a1
; RV32IBP-NEXT: ret
%shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl
ret i32 %or
}
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: pack_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret
;
; RV32IB-LABEL: pack_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: mv a1, a2
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: pack_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: mv a1, a2
; RV32IBP-NEXT: ret
%shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl
ret i64 %or
}
define i32 @packu_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packu_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lui a2, 1048560
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packu_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packu a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: packu_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packu a0, a0, a1
; RV32IBP-NEXT: ret
%shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr
ret i32 %or
}
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
; extension introduce instructions suitable for this pattern.
define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packu_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packu_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: mv a0, a1
; RV32IB-NEXT: mv a1, a3
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: packu_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: mv a0, a1
; RV32IBP-NEXT: mv a1, a3
; RV32IBP-NEXT: ret
%shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr
ret i64 %or
}
define i32 @packh_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packh_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packh_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packh a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: packh_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packh a0, a0, a1
; RV32IBP-NEXT: ret
%and = and i32 %a, 255
%and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280
%or = or i32 %shl, %and
ret i32 %or
}
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packh_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: slli a1, a2, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
; RV32IB-LABEL: packh_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: packh a0, a0, a2
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: packh_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: packh a0, a0, a2
; RV32IBP-NEXT: mv a1, zero
; RV32IBP-NEXT: ret
%and = and i64 %a, 255
%and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280
%or = or i64 %shl, %and
ret i64 %or
}
define i32 @zexth_i32(i32 %a) nounwind {
; RV32I-LABEL: zexth_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: zexth_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: zext.h a0, a0
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: zexth_i32:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: zext.h a0, a0
; RV32IBP-NEXT: ret
%and = and i32 %a, 65535
ret i32 %and
}
define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-LABEL: zexth_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
; RV32IB-LABEL: zexth_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: zext.h a0, a0
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
; RV32IBP-LABEL: zexth_i64:
; RV32IBP: # %bb.0:
; RV32IBP-NEXT: zext.h a0, a0
; RV32IBP-NEXT: mv a1, zero
; RV32IBP-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
}

llvm/test/CodeGen/RISCV/rv64Zbbp.ll

Show First 20 Lines • Show All 603 Lines • ▼ Show 20 Lines
; ;
; RV64IBP-LABEL: rori_i64_fshr: ; RV64IBP-LABEL: rori_i64_fshr:
; RV64IBP: # %bb.0: ; RV64IBP: # %bb.0:
; RV64IBP-NEXT: rori a0, a0, 63 ; RV64IBP-NEXT: rori a0, a0, 63
; RV64IBP-NEXT: ret ; RV64IBP-NEXT: ret
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63) %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %1 ret i64 %1
} }
define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: pack_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: pack_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: pack_i32:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: packw a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: pack_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packw a0, a0, a1
; RV64IBP-NEXT: ret
%shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl
ret i32 %or
}
define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: pack_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: pack_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: pack a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: pack_i64:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: pack a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: pack_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: pack a0, a0, a1
; RV64IBP-NEXT: ret
%shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl
ret i64 %or
}
define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packu_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packu_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packuw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: packu_i32:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: packuw a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: packu_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packuw a0, a0, a1
; RV64IBP-NEXT: ret
%shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr
ret i32 %or
}
define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packu_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a2, zero, -1
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packu_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packu a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: packu_i64:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: packu a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: packu_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packu a0, a0, a1
; RV64IBP-NEXT: ret
%shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr
ret i64 %or
}
define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packh_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packh_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packh a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: packh_i32:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: packh a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: packh_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packh a0, a0, a1
; RV64IBP-NEXT: ret
%and = and i32 %a, 255
%and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280
%or = or i32 %shl, %and
ret i32 %or
}
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packh_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packh a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: packh_i64:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: packh a0, a0, a1
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: packh_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packh a0, a0, a1
; RV64IBP-NEXT: ret
%and = and i64 %a, 255
%and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280
%or = or i64 %shl, %and
ret i64 %or
}

llvm/test/CodeGen/RISCV/rv64Zbp.ll

Show First 20 Lines • Show All 3,915 Lines • ▼ Show 20 Lines; RV64IBP-NEXT: ret
%shl = shl i64 %a, 16 %shl = shl i64 %a, 16
%and1 = and i64 %shl, 281470681743360 %and1 = and i64 %shl, 281470681743360
%or = or i64 %and1, %and %or = or i64 %and1, %and
%shr = lshr i64 %a, 16 %shr = lshr i64 %a, 16
%and2 = and i64 %shr, 4294901760 %and2 = and i64 %shr, 4294901760
%or3 = or i64 %or, %and2 %or3 = or i64 %or, %and2
ret i64 %or3 ret i64 %or3
} }
define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: pack_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: pack_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: pack_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packw a0, a0, a1
; RV64IBP-NEXT: ret
%shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16
%or = or i32 %shl1, %shl
ret i32 %or
}
define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: pack_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: pack_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: pack a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: pack_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: pack a0, a0, a1
; RV64IBP-NEXT: ret
%shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32
%or = or i64 %shl1, %shl
ret i64 %or
}
define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packu_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packu_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packuw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: packu_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packuw a0, a0, a1
; RV64IBP-NEXT: ret
%shr = lshr i32 %a, 16
%shr1 = and i32 %b, -65536
%or = or i32 %shr1, %shr
ret i32 %or
}
define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packu_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a2, zero, -1
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packu_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packu a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: packu_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packu a0, a0, a1
; RV64IBP-NEXT: ret
%shr = lshr i64 %a, 32
%shr1 = and i64 %b, -4294967296
%or = or i64 %shr1, %shr
ret i64 %or
}
define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packh_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packh_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packh a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: packh_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packh a0, a0, a1
; RV64IBP-NEXT: ret
%and = and i32 %a, 255
%and1 = shl i32 %b, 8
%shl = and i32 %and1, 65280
%or = or i32 %shl, %and
ret i32 %or
}
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IB-LABEL: packh_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: packh a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: packh_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: packh a0, a0, a1
; RV64IBP-NEXT: ret
%and = and i64 %a, 255
%and1 = shl i64 %b, 8
%shl = and i64 %and1, 65280
%or = or i64 %shl, %and
ret i64 %or
}
define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: zexth_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: zext.h a0, a0
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: zexth_i32:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: zext.h a0, a0
; RV64IBP-NEXT: ret
%and = and i32 %a, 65535
ret i32 %and
}
define i64 @zexth_i64(i64 %a) nounwind {
; RV64I-LABEL: zexth_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: zexth_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: zext.h a0, a0
; RV64IB-NEXT: ret
;
; RV64IBP-LABEL: zexth_i64:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: zext.h a0, a0
; RV64IBP-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
}

llvm/test/MC/RISCV/rv32zbbp-valid.s

Show All 34 Lines
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60] # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
ror t0, t1, t2 ror t0, t1, t2
# CHECK-ASM-AND-OBJ: rori t0, t1, 31 # CHECK-ASM-AND-OBJ: rori t0, t1, 31
# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61] # CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
rori t0, t1, 31 rori t0, t1, 31
# CHECK-ASM-AND-OBJ: rori t0, t1, 0 # CHECK-ASM-AND-OBJ: rori t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60] # CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
rori t0, t1, 0 rori t0, t1, 0
# CHECK-ASM-AND-OBJ: pack t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
pack t0, t1, t2
# CHECK-ASM-AND-OBJ: packu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
packu t0, t1, t2
# CHECK-ASM-AND-OBJ: packh t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
packh t0, t1, t2

llvm/test/MC/RISCV/rv32zbp-valid.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08] # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08]
unshfl t0, t1, t2 unshfl t0, t1, t2
# CHECK-ASM-AND-OBJ: shfli t0, t1, 0 # CHECK-ASM-AND-OBJ: shfli t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x12,0x03,0x08] # CHECK-ASM: encoding: [0x93,0x12,0x03,0x08]
shfli t0, t1, 0 shfli t0, t1, 0
# CHECK-ASM-AND-OBJ: unshfli t0, t1, 0 # CHECK-ASM-AND-OBJ: unshfli t0, t1, 0
# CHECK-ASM: encoding: [0x93,0x52,0x03,0x08] # CHECK-ASM: encoding: [0x93,0x52,0x03,0x08]
unshfli t0, t1, 0 unshfli t0, t1, 0
# CHECK-ASM-AND-OBJ: pack t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
pack t0, t1, t2
# CHECK-ASM-AND-OBJ: packu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
packu t0, t1, t2
# CHECK-ASM-AND-OBJ: packh t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
packh t0, t1, t2

llvm/test/MC/RISCV/rv64zbbp-valid.s

Show All 25 Lines
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60] # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
rorw t0, t1, t2 rorw t0, t1, t2
# CHECK-ASM-AND-OBJ: roriw t0, t1, 31 # CHECK-ASM-AND-OBJ: roriw t0, t1, 31
# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61] # CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
roriw t0, t1, 31 roriw t0, t1, 31
# CHECK-ASM-AND-OBJ: roriw t0, t1, 0 # CHECK-ASM-AND-OBJ: roriw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60] # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
roriw t0, t1, 0 roriw t0, t1, 0
# CHECK-ASM-AND-OBJ: packw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
packw t0, t1, t2
# CHECK-ASM-AND-OBJ: packuw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x48]
packuw t0, t1, t2

llvm/test/MC/RISCV/rv64zbp-valid.s

Show All 36 Lines
# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x68] # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x68]
greviw t0, t1, 0 greviw t0, t1, 0
# CHECK-ASM-AND-OBJ: shflw t0, t1, t2 # CHECK-ASM-AND-OBJ: shflw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x08] # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x08]
shflw t0, t1, t2 shflw t0, t1, t2
# CHECK-ASM-AND-OBJ: unshflw t0, t1, t2 # CHECK-ASM-AND-OBJ: unshflw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x08] # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x08]
unshflw t0, t1, t2 unshflw t0, t1, t2
# CHECK-ASM-AND-OBJ: packw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
packw t0, t1, t2
# CHECK-ASM-AND-OBJ: packuw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x48]
packuw t0, t1, t2