[RISCV] Add intrinsics for vector AMO instructions

[arcbbb]

Summary

Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
vamomin, vamomax, vamominu, vamomaxu intrinsics.

[khchen]

llvm/include/llvm/IR/IntrinsicsRISCV.td

589

based on https://reviews.llvm.org/D93359#inline-872142
Could we do the similar thing like vlxe/vsxe did here?

[arcbbb]

llvm/include/llvm/IR/IntrinsicsRISCV.td

589

Good idea, thanks!

[arcbbb]

address @khchen's comment

[arcbbb]

add double type for vamoswap-rv32.ll

[asb]

Nitpick: this would be better titled "[RISCV] Add intrinsics for vector AMO instructions" - I was a little confused seeing the title come past :)

[arcbbb]

In D94589#2498139, @asb wrote:

Nitpick: this would be better titled "[RISCV] Add intrinsics for vector AMO instructions" - I was a little confused seeing the title come past :)

Ah, sorry for the confusing. I have changed the title.

[khchen]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

107

vlxe and vlse have the same logic and I think they can reuse above utility functions, right?
Do you have a plan to update them (vlxe and vlse) and make the same logic with consistent implementation? maybe it could be in another patch.

3228

Should it have HasStdExtV predicate?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

3228

I think FeatureExtZvamo implies HasStdExtV in RISCV.td

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

476

Is the value the same type as the result? Can we use LLVMMatchType<0> for it?

[arcbbb]

1. fix value type to match result type
2. share octuple utility function with vlxei & vsxei patterns

[arcbbb]

llvm/include/llvm/IR/IntrinsicsRISCV.td

476

yes, thanks!

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

107

sure!

[khchen]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

905

Why is this !sra not !srl?

2542

same here.

[arcbbb]

changed sra to srl

[khchen]

LGTM

[craig.topper]

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td

                     [LLVMMatchType<0>, llvm_anyvector_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic;
+  // For atomic operations without mask
+  // Input: (base, index, value, vl)
+  class RISCVAMONoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, llvm_anyvector_ty,
+                     llvm_anyint_ty],
+                    [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
+  // For atomic operations with mask
+  // Input: (base, index, value, mask, vl)
+  class RISCVAMOMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, llvm_anyvector_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
 
   multiclass RISCVUSLoad {
     def "int_riscv_" # NAME : RISCVUSLoad;

     def "int_riscv_" #NAME :RISCVConversionNoMask;
     def "int_riscv_" # NAME # "_mask" : RISCVConversionMask;
   }
+  multiclass RISCVAMO {
+    foreach eew = [8, 16, 32, 64] in {
+      def "int_riscv_" # NAME # "ei" # eew : RISCVAMONoMask;
+      def "int_riscv_" # NAME # "ei" # eew # "_mask" : RISCVAMOMask;
+    }
+  }
 
   defm vle : RISCVUSLoad;
   defm vleff : RISCVUSLoad;

   defm vsxe: RISCVIStore;
   defm vsuxe: RISCVIStore;
 
+  defm vamoswap : RISCVAMO;
+  defm vamoadd : RISCVAMO;
+  defm vamoxor : RISCVAMO;
+  defm vamoand : RISCVAMO;
+  defm vamoor : RISCVAMO;
+  defm vamomin : RISCVAMO;
+  defm vamomax : RISCVAMO;
+  defm vamominu : RISCVAMO;
+  defm vamomaxu : RISCVAMO;
+
   defm vadd : RISCVBinaryAAX;
   defm vsub : RISCVBinaryAAX;
   defm vrsub : RISCVBinaryAAX;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

   list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
 }
 
+class MxSet<int eew> {
+  list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+                           !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+                           !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
+                           !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
+}
+
 class shift_amount<int num> {
   int val = !if(!eq(num, 1), 0, !add(1, shift_amount<!srl(num, 1)>.val));
 }
 
+class octuple_from_str<string MX> {
+  int ret = !cond(!eq(MX, "MF8") : 1,
+                        !eq(MX, "MF4") : 2,
+                        !eq(MX, "MF2") : 4,
+                        !eq(MX, "M1") : 8,
+                        !eq(MX, "M2") : 16,
+                        !eq(MX, "M4") : 32,
+                        !eq(MX, "M8") : 64);
+}
+
+class octuple_to_str<int octuple> {
+  string ret = !if(!eq(octuple, 1), "MF8",
+                   !if(!eq(octuple, 2), "MF4",
+                   !if(!eq(octuple, 4), "MF2",
+                   !if(!eq(octuple, 8), "M1",
+                   !if(!eq(octuple, 16), "M2",
+                   !if(!eq(octuple, 32), "M4",
+                   !if(!eq(octuple, 64), "M8",
+                   "NoDef")))))));
+}
+
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
 def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
 

   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoAMOWDNoMask<VReg RetClass,
+                         VReg Op1Class> :
+        Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
+               (ins GPR:$rs1,
+                    Op1Class:$vs2,
+                    GetVRegNoV0<RetClass>.R:$vd,
+                    GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 1;
+  let mayStore = 1;
+  let hasSideEffects = 1;
+  let usesCustomInserter = 1;
+  let Constraints = "$vd_wd = $vd";
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoAMOWDMask<VReg RetClass,
+                       VReg Op1Class> :
+        Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
+               (ins GPR:$rs1,
+                    Op1Class:$vs2,
+                    GetVRegNoV0<RetClass>.R:$vd,
+                    VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 1;
+  let mayStore = 1;
+  let hasSideEffects = 1;
+  let usesCustomInserter = 1;
+  let Constraints = "$vd_wd = $vd";
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+multiclass VPseudoAMOEI<int eew> {
+  // Standard scalar AMO supports 32, 64, and 128 Mem data bits,
+  // and in the base vector "V" extension, only SEW up to ELEN = max(XLEN, FLEN)
+  // are required to be supported.
+  // therefore only [32, 64] is allowed here.
+  foreach sew = [32, 64] in {
+    foreach lmul = MxSet<sew>.m in {
+      defvar octuple_lmul = octuple_from_str<lmul.MX>.ret;
+      // Calculate emul = eew * lmul / sew
+      defvar octuple_emul = !sra(!mul(eew, octuple_lmul), shift_amount<sew>.val);
+      if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+        defvar emulMX = octuple_to_str<octuple_emul>.ret;
+        defvar lmulMX = octuple_to_str<octuple_lmul>.ret;
+        defvar emul= !cast<LMULInfo>("V_" # emulMX);
+        defvar lmul = !cast<LMULInfo>("V_" # lmulMX);
+        let VLMul = lmul.value in {
+          def "_WD_" # lmulMX # "_" # emulMX : VPseudoAMOWDNoMask<lmul.vrclass, emul.vrclass>;
+          def "_WD_" # lmulMX # "_" # emulMX # "_MASK" : VPseudoAMOWDMask<lmul.vrclass, emul.vrclass>;
+        }
+      }
+    }
+  }
+}
+
+multiclass VPseudoAMO {
+  foreach eew = EEWList in
+    defm "EI" # eew : VPseudoAMOEI<eew>;
+}
+
 multiclass VPseudoUSLoad {
   foreach lmul = MxList.m in {
     defvar LInfo = lmul.MX;

                     (mask_type V0),
                     (NoX0 GPR:$vl), sew)>;
 
+class VPatAMOWDNoMask<string intrinsic_name,
+                    string inst,
+                    ValueType result_type,
+                    ValueType op1_type,
+                    int sew,
+                    LMULInfo vlmul,
+                    LMULInfo emul,
+                    VReg op1_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                    GPR:$rs1,
+                    (op1_type op1_reg_class:$vs2),
+                    (result_type vlmul.vrclass:$vd),
+                    (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX)
+                    $rs1, $vs2, $vd,
+                    (NoX0 GPR:$vl), sew)>;
+
+class VPatAMOWDMask<string intrinsic_name,
+                    string inst,
+                    ValueType result_type,
+                    ValueType op1_type,
+                    ValueType mask_type,
+                    int sew,
+                    LMULInfo vlmul,
+                    LMULInfo emul,
+                    VReg op1_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name # "_mask")
+                    GPR:$rs1,
+                    (op1_type op1_reg_class:$vs2),
+                    (result_type vlmul.vrclass:$vd),
+                    (mask_type V0),
+                    (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX # "_MASK")
+                    $rs1, $vs2, $vd,
+                    (mask_type V0), (NoX0 GPR:$vl), sew)>;
+
 multiclass VPatUSLoad<string intrinsic,
                       string inst,
                       LLVMType type,

   }
 }
 
+multiclass VPatAMOWD<string intrinsic,
+                     string inst,
+                     ValueType result_type,
+                     ValueType offset_type,
+                     ValueType mask_type,
+                     int sew,
+                     LMULInfo vlmul,
+                     LMULInfo emul,
+                     VReg op1_reg_class>
+{
+  def : VPatAMOWDNoMask<intrinsic, inst, result_type, offset_type,
+                        sew, vlmul, emul, op1_reg_class>;
+  def : VPatAMOWDMask<intrinsic, inst, result_type, offset_type,
+                      mask_type, sew, vlmul, emul, op1_reg_class>;
+}
+
+multiclass VPatAMOV_WD<string intrinsic,
+                       string inst,
+                       list<VTypeInfo> vtilist> {
+  foreach eew = EEWList in {
+    foreach vti = vtilist in {
+      if !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64)) then {
+        defvar octuple_lmul = octuple_from_str<vti.LMul.MX>.ret;
+        // Calculate emul = eew * lmul / sew
+        defvar octuple_emul = !sra(!mul(eew, octuple_lmul), shift_amount<vti.SEW>.val);
+        if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+          defvar emulMX = octuple_to_str<octuple_emul>.ret;
+          defvar offsetVti = !cast<VTypeInfo>("VI" # eew # emulMX);
+          defvar intrinsic_ei = intrinsic # "ei" # eew;
+          defvar inst_ei = inst # "EI" # eew;
+          defm : VPatAMOWD<intrinsic_ei, inst_ei,
+                           vti.Vector, offsetVti.Vector,
+                           vti.Mask, vti.SEW, vti.LMul, offsetVti.LMul, offsetVti.RegClass>;
+        }
+      }
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo instructions
 //===----------------------------------------------------------------------===//

 }
 
 //===----------------------------------------------------------------------===//
+// 8. Vector AMO Operations
+//===----------------------------------------------------------------------===//
+defm PseudoVAMOSWAP : VPseudoAMO;
+defm PseudoVAMOADD : VPseudoAMO;
+defm PseudoVAMOXOR : VPseudoAMO;
+defm PseudoVAMOAND : VPseudoAMO;
+defm PseudoVAMOOR : VPseudoAMO;
+defm PseudoVAMOMIN : VPseudoAMO;
+defm PseudoVAMOMAX : VPseudoAMO;
+defm PseudoVAMOMINU : VPseudoAMO;
+defm PseudoVAMOMAXU : VPseudoAMO;
+
+//===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//
 

     }
   }
 }
+} // Predicates = [HasStdExtV]
 
+//===----------------------------------------------------------------------===//
+// 8. Vector AMO Operations
+//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtZvamo] in {
+  defm "" : VPatAMOV_WD<"int_riscv_vamoswap", "PseudoVAMOSWAP", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamoadd", "PseudoVAMOADD", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamoxor", "PseudoVAMOXOR", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamoand", "PseudoVAMOAND", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamoor", "PseudoVAMOOR", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamomin", "PseudoVAMOMIN", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamomax", "PseudoVAMOMAX", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamominu", "PseudoVAMOMINU", AllIntegerVectors>;
+  defm "" : VPatAMOV_WD<"int_riscv_vamomaxu", "PseudoVAMOMAXU", AllIntegerVectors>;
+} // Predicates = [HasStdExtZvamo]
+
+let Predicates = [HasStdExtZvamo, HasStdExtF] in {
+  defm "" : VPatAMOV_WD<"int_riscv_vamoswap", "PseudoVAMOSWAP", AllFloatVectors>;
+} // Predicates = [HasStdExtZvamo, HasStdExtF]
 
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [HasStdExtV] in {
 //===----------------------------------------------------------------------===//
 // 12.1. Vector Single-Width Integer Add and Subtract
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/vamoaddei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoaddei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoaddei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoaddei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoaddei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoaddei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoaddei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoaddei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoaddei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoaddei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoaddei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoaddei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoaddei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoaddei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoaddei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoaddei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoaddei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoaddei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoaddei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoaddei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoaddei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoaddei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoaddei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoaddei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoaddei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoaddei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoaddei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoaddei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoaddei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoaddei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoandei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoandei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoandei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoandei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoandei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoandei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoandei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoandei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoandei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoandei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoandei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoandei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoandei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoandei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoandei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoandei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoandei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoandei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoandei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoandei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoandei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoandei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoandei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoandei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoandei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoandei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoandei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoandei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoandei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoandei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamomaxei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamomaxei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamomaxuei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamomaxuei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxuei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxuei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxuei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxuei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxuei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxuei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxuei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxuei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxuei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxuei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxuei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxuei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxuei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxuei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxuei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxuei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxuei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxuei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxuei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxuei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxuei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxuei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxuei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxuei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxuei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxuei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamomaxuei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxuei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamominei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamominei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamominuei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamominuei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominuei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominuei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamominuei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominuei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominuei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamominuei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominuei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominuei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamominuei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominuei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominuei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamominuei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominuei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominuei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamominuei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominuei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominuei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamominuei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominuei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominuei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamominuei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominuei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominuei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamominuei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominuei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominuei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominuei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamominuei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoorei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoorei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoorei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoorei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoorei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoorei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoorei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoorei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoorei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoorei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoorei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoorei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoorei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoorei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoorei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoorei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoorei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoorei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoorei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoorei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoorei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoorei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoorei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoorei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoorei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoorei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoorei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoorei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoorei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoorei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoswapei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei32.nxv1f32.nxv1i32(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei32_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei32.nxv1f32.nxv1i32(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei32.mask.nxv1f32.nxv1i32(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei32_mask_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei32.mask.nxv1f32.nxv1i32(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei32.nxv2f32.nxv2i32(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei32_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei32.nxv2f32.nxv2i32(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei32.mask.nxv2f32.nxv2i32(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei32_mask_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei32.mask.nxv2f32.nxv2i32(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei32.nxv4f32.nxv4i32(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei32_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei32.nxv4f32.nxv4i32(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei32.mask.nxv4f32.nxv4i32(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei32_mask_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei32.mask.nxv4f32.nxv4i32(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei32.nxv8f32.nxv8i32(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei32_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei32.nxv8f32.nxv8i32(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei32.mask.nxv8f32.nxv8i32(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei32_mask_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei32.mask.nxv8f32.nxv8i32(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei32.nxv16f32.nxv16i32(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei32_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei32.nxv16f32.nxv16i32(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x float> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei32.mask.nxv16f32.nxv16i32(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei32_mask_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei32.mask.nxv16f32.nxv16i32(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei16.nxv1f32.nxv1i16(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei16_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei16.nxv1f32.nxv1i16(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei16.mask.nxv1f32.nxv1i16(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei16_mask_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei16.mask.nxv1f32.nxv1i16(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei16.nxv2f32.nxv2i16(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei16_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei16.nxv2f32.nxv2i16(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei16.mask.nxv2f32.nxv2i16(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei16_mask_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei16.mask.nxv2f32.nxv2i16(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei16.nxv4f32.nxv4i16(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei16_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei16.nxv4f32.nxv4i16(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei16.mask.nxv4f32.nxv4i16(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei16_mask_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei16.mask.nxv4f32.nxv4i16(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei16.nxv8f32.nxv8i16(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei16_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei16.nxv8f32.nxv8i16(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei16.mask.nxv8f32.nxv8i16(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei16_mask_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei16.mask.nxv8f32.nxv8i16(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei16.nxv16f32.nxv16i16(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei16_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv16f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei16.nxv16f32.nxv16i16(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x float> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei16.mask.nxv16f32.nxv16i16(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei16_mask_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv16f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei16.mask.nxv16f32.nxv16i16(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei8.nxv1f32.nxv1i8(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei8_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei8.nxv1f32.nxv1i8(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei8.mask.nxv1f32.nxv1i8(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei8_mask_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei8.mask.nxv1f32.nxv1i8(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei8.nxv2f32.nxv2i8(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei8_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei8.nxv2f32.nxv2i8(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei8.mask.nxv2f32.nxv2i8(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei8_mask_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei8.mask.nxv2f32.nxv2i8(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei8.nxv4f32.nxv4i8(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei8_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei8.nxv4f32.nxv4i8(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei8.mask.nxv4f32.nxv4i8(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei8_mask_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei8.mask.nxv4f32.nxv4i8(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei8.nxv8f32.nxv8i8(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei8_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei8.nxv8f32.nxv8i8(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei8.mask.nxv8f32.nxv8i8(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei8_mask_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei8.mask.nxv8f32.nxv8i8(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei8.nxv16f32.nxv16i8(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei8_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv16f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei8.nxv16f32.nxv16i8(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x float> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei8.mask.nxv16f32.nxv16i8(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei8_mask_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv16f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei8.mask.nxv16f32.nxv16i8(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoswapei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei64.nxv1f32.nxv1i64(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei64_v_nxv1f32_nxv1i64(<vscale x 1 x float> *%0, <vscale x 1 x i64> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei64.nxv1f32.nxv1i64(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei64.mask.nxv1f32.nxv1i64(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei64_mask_v_nxv1f32_nxv1i64(<vscale x 1 x float> *%0, <vscale x 1 x i64> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei64.mask.nxv1f32.nxv1i64(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei64.nxv2f32.nxv2i64(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei64_v_nxv2f32_nxv2i64(<vscale x 2 x float> *%0, <vscale x 2 x i64> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei64.nxv2f32.nxv2i64(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei64.mask.nxv2f32.nxv2i64(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei64_mask_v_nxv2f32_nxv2i64(<vscale x 2 x float> *%0, <vscale x 2 x i64> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei64.mask.nxv2f32.nxv2i64(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei64.nxv4f32.nxv4i64(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei64_v_nxv4f32_nxv4i64(<vscale x 4 x float> *%0, <vscale x 4 x i64> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei64.nxv4f32.nxv4i64(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei64.mask.nxv4f32.nxv4i64(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei64_mask_v_nxv4f32_nxv4i64(<vscale x 4 x float> *%0, <vscale x 4 x i64> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei64.mask.nxv4f32.nxv4i64(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei64.nxv8f32.nxv8i64(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei64_v_nxv8f32_nxv8i64(<vscale x 8 x float> *%0, <vscale x 8 x i64> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei64.nxv8f32.nxv8i64(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei64.mask.nxv8f32.nxv8i64(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei64_mask_v_nxv8f32_nxv8i64(<vscale x 8 x float> *%0, <vscale x 8 x i64> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei64.mask.nxv8f32.nxv8i64(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei64.nxv1f64.nxv1i64(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei64_v_nxv1f64_nxv1i64(<vscale x 1 x double> *%0, <vscale x 1 x i64> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei64.nxv1f64.nxv1i64(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei64.mask.nxv1f64.nxv1i64(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei64_mask_v_nxv1f64_nxv1i64(<vscale x 1 x double> *%0, <vscale x 1 x i64> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei64.mask.nxv1f64.nxv1i64(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei64.nxv2f64.nxv2i64(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei64_v_nxv2f64_nxv2i64(<vscale x 2 x double> *%0, <vscale x 2 x i64> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei64.nxv2f64.nxv2i64(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei64.mask.nxv2f64.nxv2i64(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei64_mask_v_nxv2f64_nxv2i64(<vscale x 2 x double> *%0, <vscale x 2 x i64> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei64.mask.nxv2f64.nxv2i64(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei64.nxv4f64.nxv4i64(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei64_v_nxv4f64_nxv4i64(<vscale x 4 x double> *%0, <vscale x 4 x i64> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei64.nxv4f64.nxv4i64(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei64.mask.nxv4f64.nxv4i64(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei64_mask_v_nxv4f64_nxv4i64(<vscale x 4 x double> *%0, <vscale x 4 x i64> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei64.mask.nxv4f64.nxv4i64(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei64.nxv8f64.nxv8i64(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei64_v_nxv8f64_nxv8i64(<vscale x 8 x double> *%0, <vscale x 8 x i64> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_v_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei64.nxv8f64.nxv8i64(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x double> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei64.mask.nxv8f64.nxv8i64(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei64_mask_v_nxv8f64_nxv8i64(<vscale x 8 x double> *%0, <vscale x 8 x i64> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei64_mask_v_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei64.mask.nxv8f64.nxv8i64(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei32.nxv1f32.nxv1i32(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei32_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei32.nxv1f32.nxv1i32(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei32.mask.nxv1f32.nxv1i32(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei32_mask_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei32.mask.nxv1f32.nxv1i32(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei32.nxv2f32.nxv2i32(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei32_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei32.nxv2f32.nxv2i32(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei32.mask.nxv2f32.nxv2i32(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei32_mask_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei32.mask.nxv2f32.nxv2i32(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei32.nxv4f32.nxv4i32(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei32_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei32.nxv4f32.nxv4i32(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei32.mask.nxv4f32.nxv4i32(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei32_mask_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei32.mask.nxv4f32.nxv4i32(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei32.nxv8f32.nxv8i32(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei32_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei32.nxv8f32.nxv8i32(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei32.mask.nxv8f32.nxv8i32(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei32_mask_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei32.mask.nxv8f32.nxv8i32(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei32.nxv16f32.nxv16i32(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei32_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei32.nxv16f32.nxv16i32(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x float> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei32.mask.nxv16f32.nxv16i32(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei32_mask_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei32.mask.nxv16f32.nxv16i32(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei32.nxv1f64.nxv1i32(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei32_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei32.nxv1f64.nxv1i32(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei32.mask.nxv1f64.nxv1i32(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei32_mask_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei32.mask.nxv1f64.nxv1i32(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei32.nxv2f64.nxv2i32(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei32_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei32.nxv2f64.nxv2i32(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei32.mask.nxv2f64.nxv2i32(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei32_mask_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei32.mask.nxv2f64.nxv2i32(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei32.nxv4f64.nxv4i32(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei32_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei32.nxv4f64.nxv4i32(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei32.mask.nxv4f64.nxv4i32(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei32_mask_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei32.mask.nxv4f64.nxv4i32(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei32.nxv8f64.nxv8i32(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei32_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_v_nxv8f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei32.nxv8f64.nxv8i32(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x double> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei32.mask.nxv8f64.nxv8i32(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei32_mask_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei32_mask_v_nxv8f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei32.mask.nxv8f64.nxv8i32(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei16.nxv1f32.nxv1i16(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei16_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei16.nxv1f32.nxv1i16(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei16.mask.nxv1f32.nxv1i16(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei16_mask_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei16.mask.nxv1f32.nxv1i16(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei16.nxv2f32.nxv2i16(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei16_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei16.nxv2f32.nxv2i16(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei16.mask.nxv2f32.nxv2i16(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei16_mask_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei16.mask.nxv2f32.nxv2i16(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei16.nxv4f32.nxv4i16(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei16_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei16.nxv4f32.nxv4i16(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei16.mask.nxv4f32.nxv4i16(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei16_mask_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei16.mask.nxv4f32.nxv4i16(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei16.nxv8f32.nxv8i16(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei16_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei16.nxv8f32.nxv8i16(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei16.mask.nxv8f32.nxv8i16(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei16_mask_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei16.mask.nxv8f32.nxv8i16(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei16.nxv16f32.nxv16i16(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei16_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv16f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei16.nxv16f32.nxv16i16(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x float> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei16.mask.nxv16f32.nxv16i16(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei16_mask_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv16f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei16.mask.nxv16f32.nxv16i16(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei16.nxv1f64.nxv1i16(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei16_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei16.nxv1f64.nxv1i16(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei16.mask.nxv1f64.nxv1i16(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei16_mask_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei16.mask.nxv1f64.nxv1i16(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei16.nxv2f64.nxv2i16(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei16_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei16.nxv2f64.nxv2i16(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei16.mask.nxv2f64.nxv2i16(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei16_mask_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei16.mask.nxv2f64.nxv2i16(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei16.nxv4f64.nxv4i16(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei16_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei16.nxv4f64.nxv4i16(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei16.mask.nxv4f64.nxv4i16(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei16_mask_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei16.mask.nxv4f64.nxv4i16(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei16.nxv8f64.nxv8i16(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei16_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_v_nxv8f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei16.nxv8f64.nxv8i16(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x double> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei16.mask.nxv8f64.nxv8i16(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei16_mask_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei16_mask_v_nxv8f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei16.mask.nxv8f64.nxv8i16(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswapei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswapei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoswapei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswapei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswapei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoswapei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswapei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswapei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoswapei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswapei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswapei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoswapei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswapei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswapei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoswapei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswapei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswapei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoswapei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswapei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswapei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoswapei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswapei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswapei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoswapei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswapei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswapei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoswapei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei8.nxv1f32.nxv1i8(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei8_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei8.nxv1f32.nxv1i8(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswapei8.mask.nxv1f32.nxv1i8(
+  <vscale x 1 x float>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswapei8_mask_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vamoswapei8.mask.nxv1f32.nxv1i8(
+    <vscale x 1 x float> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei8.nxv2f32.nxv2i8(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei8_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei8.nxv2f32.nxv2i8(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswapei8.mask.nxv2f32.nxv2i8(
+  <vscale x 2 x float>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswapei8_mask_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vamoswapei8.mask.nxv2f32.nxv2i8(
+    <vscale x 2 x float> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei8.nxv4f32.nxv4i8(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei8_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei8.nxv4f32.nxv4i8(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswapei8.mask.nxv4f32.nxv4i8(
+  <vscale x 4 x float>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswapei8_mask_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vamoswapei8.mask.nxv4f32.nxv4i8(
+    <vscale x 4 x float> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei8.nxv8f32.nxv8i8(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei8_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei8.nxv8f32.nxv8i8(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswapei8.mask.nxv8f32.nxv8i8(
+  <vscale x 8 x float>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswapei8_mask_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vamoswapei8.mask.nxv8f32.nxv8i8(
+    <vscale x 8 x float> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei8.nxv16f32.nxv16i8(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei8_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv16f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei8.nxv16f32.nxv16i8(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x float> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswapei8.mask.nxv16f32.nxv16i8(
+  <vscale x 16 x float>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswapei8_mask_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv16f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vamoswapei8.mask.nxv16f32.nxv16i8(
+    <vscale x 16 x float> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei8.nxv1f64.nxv1i8(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei8_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei8.nxv1f64.nxv1i8(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswapei8.mask.nxv1f64.nxv1i8(
+  <vscale x 1 x double>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswapei8_mask_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vamoswapei8.mask.nxv1f64.nxv1i8(
+    <vscale x 1 x double> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei8.nxv2f64.nxv2i8(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei8_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei8.nxv2f64.nxv2i8(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswapei8.mask.nxv2f64.nxv2i8(
+  <vscale x 2 x double>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswapei8_mask_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vamoswapei8.mask.nxv2f64.nxv2i8(
+    <vscale x 2 x double> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei8.nxv4f64.nxv4i8(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei8_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei8.nxv4f64.nxv4i8(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswapei8.mask.nxv4f64.nxv4i8(
+  <vscale x 4 x double>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswapei8_mask_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vamoswapei8.mask.nxv4f64.nxv4i8(
+    <vscale x 4 x double> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei8.nxv8f64.nxv8i8(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei8_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_v_nxv8f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei8.nxv8f64.nxv8i8(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x double> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswapei8.mask.nxv8f64.nxv8i8(
+  <vscale x 8 x double>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswapei8_mask_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswapei8_mask_v_nxv8f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vamoswapei8.mask.nxv8f64.nxv8i8(
+    <vscale x 8 x double> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoxorei-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}

llvm/test/CodeGen/RISCV/rvv/vamoxorei-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei64.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei64_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei64.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei64.mask.nxv1i32.nxv1i64(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei64_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei64.mask.nxv1i32.nxv1i64(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei64.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei64_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei64.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei64.mask.nxv2i32.nxv2i64(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei64_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei64.mask.nxv2i32.nxv2i64(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei64.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei64_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei64.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei64.mask.nxv4i32.nxv4i64(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei64_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei64.mask.nxv4i32.nxv4i64(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei64.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei64_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v28, (a0), v16, v28
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei64.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei64.mask.nxv8i32.nxv8i64(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei64_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei64.mask.nxv8i32.nxv8i64(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei64.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei64_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei64.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei64.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei64_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei64.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei64.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei64_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei64.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei64.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei64_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei64.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei64.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei64_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei64.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei64.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei64_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei64.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei64.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei64_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei64.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei64.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei64_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei64_mask_v_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei64.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei32.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei32_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei32.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei32.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei32_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei32.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei32.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei32_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei32.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei32.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei32_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei32.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei32.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei32_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei32.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei32.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei32_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei32.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei32.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei32_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei32.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei32.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei32_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei32.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei32.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei32_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei32.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei32.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei32_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei32.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei32.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei32_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei32.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei32.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei32_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei32.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei32.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei32_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei32.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei32.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei32_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei32.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei32.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei32_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei32.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei32.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei32_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei32.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei32.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei32_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei32.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei32.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei32_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei32_mask_v_nxv8i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei32.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei16.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei16_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei16.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei16.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei16_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei16.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei16.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei16_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei16.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei16.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei16_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei16.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei16.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei16_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei16.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei16.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei16_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei16.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei16.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei16_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei16.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei16.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei16_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei16.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei16.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei16_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei16.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei16.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei16_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv16i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei16.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei16.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei16_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei16.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei16.mask.nxv1i64.nxv1i16(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei16_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei16.mask.nxv1i64.nxv1i16(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei16.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei16_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei16.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei16.mask.nxv2i64.nxv2i16(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei16_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei16.mask.nxv2i64.nxv2i16(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei16.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei16_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei16.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei16.mask.nxv4i64.nxv4i16(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei16_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei16.mask.nxv4i64.nxv4i16(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei16.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei16_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei16.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei16.mask.nxv8i64.nxv8i16(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei16_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei16_mask_v_nxv8i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei16.mask.nxv8i64.nxv8i16(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei8.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei8_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei8.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxorei8.mask.nxv1i32.nxv1i8(
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxorei8_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vamoxorei8.mask.nxv1i32.nxv1i8(
+    <vscale x 1 x i32> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei8.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei8_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei8.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxorei8.mask.nxv2i32.nxv2i8(
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxorei8_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vamoxorei8.mask.nxv2i32.nxv2i8(
+    <vscale x 2 x i32> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei8.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei8_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei8.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxorei8.mask.nxv4i32.nxv4i8(
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxorei8_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vamoxorei8.mask.nxv4i32.nxv4i8(
+    <vscale x 4 x i32> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei8.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei8_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei8.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxorei8.mask.nxv8i32.nxv8i8(
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxorei8_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vamoxorei8.mask.nxv8i32.nxv8i8(
+    <vscale x 8 x i32> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei8.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei8_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei8.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxorei8.mask.nxv16i32.nxv16i8(
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxorei8_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv16i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vamoxorei8.mask.nxv16i32.nxv16i8(
+    <vscale x 16 x i32> *%0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei8.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei8_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei8.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxorei8.mask.nxv1i64.nxv1i8(
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxorei8_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vamoxorei8.mask.nxv1i64.nxv1i8(
+    <vscale x 1 x i64> *%0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei8.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei8_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei8.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxorei8.mask.nxv2i64.nxv2i8(
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxorei8_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vamoxorei8.mask.nxv2i64.nxv2i8(
+    <vscale x 2 x i64> *%0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei8.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei8_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei8.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxorei8.mask.nxv4i64.nxv4i8(
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxorei8_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vamoxorei8.mask.nxv4i64.nxv4i8(
+    <vscale x 4 x i64> *%0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei8.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei8_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei8.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxorei8.mask.nxv8i64.nxv8i8(
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxorei8_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxorei8_mask_v_nxv8i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT:    vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vamoxorei8.mask.nxv8i64.nxv8i8(
+    <vscale x 8 x i64> *%0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}