[AArch64] Add BRB IALL and BRB INJ instructions

[tmatheson]

Summary

BRB IALL: Invalidate the Branch Record Buffer
BRB INJ: Branch Record Injection into the Branch Record Buffer

Parser changes based on work by Simon Tatham.

These are two-word mnemonics. The assembly parser works by special-casing
the mnemonic in order to parse the second word as a plain identifier token.

[chill]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

3782

Would it be possible to accept both lower and upper case of the keyword operands?
e.g. with https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64InstrFormats.td#L11289

[tmatheson]

Accept both lower and upper case of the keyword operands

[MarkMurrayARM]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

837

Can these two not be combined with the bits 7-5 and the "iall"/"inj" parameterised?

[tmatheson]

Combine BRB_IALL and BRB_INJ common parts into class BRBEI

[MarkMurrayARM]

LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def DSBnXS  : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
   let Predicates = [HasXS];
 }
 
 let Predicates = [HasWFxT] in {
 def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
 def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
 }
 
+// Branch Record Buffer two-word mnemonic instructions
+class BRBEI<bits<3> op2, string keyword>
+    : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {
+  let Inst{31-8} = 0b110101010000100101110010;
+  let Inst{7-5} = op2;
+  let Predicates = [HasBRBE];
 }
+def BRB_IALL: BRBEI<0b100, "\tiall">;
+def BRB_INJ:  BRBEI<0b101, "\tinj">;
+
+}
+
+// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ
+def : TokenAlias<"INJ", "inj">;
+def : TokenAlias<"IALL", "iall">;
 
 // ARMv8.2-A Dot Product
 let Predicates = [HasDotProd] in {
 defm SDOT : SIMDThreeSameVectorDot<0, 0, "sdot", int_aarch64_neon_sdot>;
 defm UDOT : SIMDThreeSameVectorDot<1, 0, "udot", int_aarch64_neon_udot>;
 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, 0, 0b10, "sdot", int_aarch64_neon_sdot>;
 defm UDOTlane : SIMDThreeSameVectorDotIndex<1, 0, 0b10, "udot", int_aarch64_neon_udot>;
 }
 
 // ARMv8.6-A BFloat
 let Predicates = [HasBF16] in {
 defm BFDOT       : SIMDThreeSameVectorBFDot<1, "bfdot">;
 defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">;
 def BFMMLA       : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">;
 def BFMLALB      : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

private:
   void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
   AArch64CC::CondCode parseCondCodeString(StringRef Cond);
   bool parseCondCode(OperandVector &Operands, bool invertCondCode);
   unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
   bool parseRegister(OperandVector &Operands);
   bool parseSymbolicImmVal(const MCExpr *&ImmVal);
   bool parseNeonVectorList(OperandVector &Operands);
   bool parseOptionalMulOperand(OperandVector &Operands);
+  bool parseKeywordOperand(OperandVector &Operands);
   bool parseOperand(OperandVector &Operands, bool isCondCode,
                     bool invertCondCode);
   bool parseImmExpr(int64_t &Out);
   bool parseComma();
   bool parseRegisterInRange(unsigned &Out, unsigned Base, unsigned First,
                             unsigned Last);
 
   bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
if (!Parser.parseExpression(ImmVal))
             getContext()));
         return MatchOperand_Success;
       }
   }
 
   return Error(getLoc(), "expected 'vl' or '#<imm>'");
 }
 
+bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  auto Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier))
+    return true;
+  Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
+                                                 Tok.getLoc(), getContext()));
+  Parser.Lex();
+  return false;
+}
+
 /// parseOperand - Parse a arm instruction operand.  For now this parses the
 /// operand regardless of the mnemonic.
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                   bool invertCondCode) {
   MCAsmParser &Parser = getParser();
 
   OperandMatchResultTy ResTy =
       MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/ true);
if (!parseOptionalMulOperand(Operands))
       return false;
 
     // This could be an optional "shift" or "extend" operand.
     OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
     // We can only continue if no tokens were eaten.
     if (GotShift != MatchOperand_NoMatch)
       return GotShift;
 
+    // If this is a two-word mnemonic, parse its special keyword
+    // operand as an identifier.
+    if (Mnemonic == "brb")
+      return parseKeywordOperand(Operands);
+
     // This was not a register so parse other operands that start with an
     // identifier (like labels) as expressions and create them as immediates.
     const MCExpr *IdVal;
     S = getLoc();
     if (getParser().parseExpression(IdVal))
       return true;
     E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
     Operands.push_back(AArch64Operand::CreateImm(IdVal, S, E, getContext()));

llvm/test/MC/AArch64/brbe.s

 // ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
 
 msr BRBTGT31_EL1, x4
 mrs x5, BRBTGT31_EL1
 // ERROR: [[@LINE-2]]:5: error: expected writable system register
 // CHECK: mrs     x5, BRBTGT31_EL1        // encoding: [0xc5,0x8f,0x31,0xd5]
 // ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
 // ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
+
+brb iall
+brb inj
+// CHECK: brb iall  // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj   // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+
+brb IALL
+brb INJ
+// CHECK: brb iall  // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj   // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe