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Differential D92841

[RISCV][NFC] Regenerate RISCV CodeGen tests
ClosedPublic

Authored by mundaym on Dec 8 2020, 6:05 AM.

Details

Reviewers
asb
luismarques
lenary
Commits
rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests
Summary

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Diff Detail

Unit TestsFailed

TimeTest
60 msx64 windows > LLVM.CodeGen/XCore::threads.ll

Event Timeline

mundaym created this revision.Dec 8 2020, 6:05 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 28 others. · View Herald TranscriptDec 8 2020, 6:05 AM
mundaym requested review of this revision.Dec 8 2020, 6:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 8 2020, 6:05 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
mundaym added reviewers: asb, luismarques, lenary.Dec 8 2020, 6:09 AM
lenary added a comment.Dec 8 2020, 6:48 AM

The spills look right to me. The question we're not sure of is the appearance of the @plt suffixes on all the external calls.

jrtc27 added a comment.Dec 8 2020, 7:00 AM
In D92841#2439763, @lenary wrote:

The spills look right to me. The question we're not sure of is the appearance of the @plt suffixes on all the external calls.

RISC-V's calls are a mess. Without @plt you get an R_RISCV_CALL, and with @plt you get an R_RISCV_CALL_PLT. In LLD both are treated identically. In binutils, the latter always works (it'll get a PLT stub if needed, but not otherwise), whereas the former can cause weird things to happen if you need a PLT stub (and it's dependent on what other relocations for the symbol exist IIRC). Basically, R_RISCV_CALL should never have existed and R_RISCV_CALL_PLT should have been R_RISCV_CALL, but if you want to support linking with binutils then you need the @plt suffix unless you know the symbol will always be local.

See https://github.com/riscv/riscv-elf-psabi-doc/issues/98, https://sourceware.org/bugzilla/show_bug.cgi?id=24685 and D63076.

@MaskRay am I missing anything?

Harbormaster completed remote builds in B81439: Diff 310163.Dec 8 2020, 7:01 AM
lenary added a comment.Dec 8 2020, 1:05 PM

@jrtc27 it sounds like adding @plt into all the tests won't break anything, and will catch if future changes default to non-plt calls, so this change is an improvement?

jrtc27 added a comment.Dec 8 2020, 1:06 PM
In D92841#2440962, @lenary wrote:

@jrtc27 it sounds like adding @plt into all the tests won't break anything, and will catch if future changes default to non-plt calls, so this change is an improvement?

Yes I believe so.

lenary accepted this revision.Dec 8 2020, 2:19 PM

LGTM

This revision is now accepted and ready to land.Dec 8 2020, 2:19 PM
This revision was landed with ongoing or failed builds.Dec 9 2020, 11:43 AM
Closed by commit rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests (authored by mundaym, committed by luismarques). · Explain Why
This revision was automatically updated to reflect the committed changes.
luismarques added a commit: rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests.

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Diff 310163

llvm/test/CodeGen/RISCV/alloca.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
declare void @notdead(i8*) declare void @notdead(i8*)
; These tests must ensure the stack pointer is restored using the frame ; These tests must ensure the stack pointer is restored using the frame
; pointer ; pointer
define void @simple_alloca(i32 %n) nounwind { define void @simple_alloca(i32 %n) nounwind {
; RV32I-LABEL: simple_alloca: ; RV32I-LABEL: simple_alloca:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: call notdead ; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
call void @notdead(i8* %1) call void @notdead(i8* %1)
ret void ret void
} }
declare i8* @llvm.stacksave() declare i8* @llvm.stacksave()
declare void @llvm.stackrestore(i8*) declare void @llvm.stackrestore(i8*)
define void @scoped_alloca(i32 %n) nounwind { define void @scoped_alloca(i32 %n) nounwind {
; RV32I-LABEL: scoped_alloca: ; RV32I-LABEL: scoped_alloca:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv s1, sp ; RV32I-NEXT: mv s1, sp
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: call notdead ; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: mv sp, s1 ; RV32I-NEXT: mv sp, s1
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%sp = call i8* @llvm.stacksave() %sp = call i8* @llvm.stacksave()
%addr = alloca i8, i32 %n %addr = alloca i8, i32 %n
call void @notdead(i8* %addr) call void @notdead(i8* %addr)
call void @llvm.stackrestore(i8* %sp) call void @llvm.stackrestore(i8* %sp)
ret void ret void
} }
declare void @func(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @func(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
; Check that outgoing arguments passed on the stack do not corrupt a ; Check that outgoing arguments passed on the stack do not corrupt a
; variable-sized stack object. ; variable-sized stack object.
define void @alloca_callframe(i32 %n) nounwind { define void @alloca_callframe(i32 %n) nounwind {
; RV32I-LABEL: alloca_callframe: ; RV32I-LABEL: alloca_callframe:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a1, zero, 12 ; RV32I-NEXT: addi a1, zero, 12
; RV32I-NEXT: sw a1, 12(sp) ; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a1, zero, 11 ; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, zero, 10 ; RV32I-NEXT: addi a1, zero, 10
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi t0, zero, 9 ; RV32I-NEXT: addi t0, zero, 9
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 6 ; RV32I-NEXT: addi a5, zero, 6
; RV32I-NEXT: addi a6, zero, 7 ; RV32I-NEXT: addi a6, zero, 7
; RV32I-NEXT: addi a7, zero, 8 ; RV32I-NEXT: addi a7, zero, 8
; RV32I-NEXT: sw t0, 0(sp) ; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: call func ; RV32I-NEXT: call func@plt
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8,
i32 9, i32 10, i32 11, i32 12) i32 9, i32 10, i32 11, i32 12)
ret void ret void
} }

llvm/test/CodeGen/RISCV/analyze-branch.ll

Show All 10 Lines
; !0 corresponds to a branch being taken, !1 to not being takne. ; !0 corresponds to a branch being taken, !1 to not being takne.
!0 = !{!"branch_weights", i32 64, i32 4} !0 = !{!"branch_weights", i32 64, i32 4}
!1 = !{!"branch_weights", i32 4, i32 64} !1 = !{!"branch_weights", i32 4, i32 64}
define void @test_bcc_fallthrough_taken(i32 %in) nounwind { define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
; RV32I-LABEL: test_bcc_fallthrough_taken: ; RV32I-LABEL: test_bcc_fallthrough_taken:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3 ; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true ; RV32I-NEXT: # %bb.1: # %true
; RV32I-NEXT: call test_true ; RV32I-NEXT: call test_true@plt
; RV32I-NEXT: .LBB0_2: # %true ; RV32I-NEXT: .LBB0_2: # %true
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_3: # %false ; RV32I-NEXT: .LBB0_3: # %false
; RV32I-NEXT: call test_false ; RV32I-NEXT: call test_false@plt
; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: j .LBB0_2
%tst = icmp eq i32 %in, 42 %tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !0 br i1 %tst, label %true, label %false, !prof !0
; Expected layout order is: Entry, TrueBlock, FalseBlock ; Expected layout order is: Entry, TrueBlock, FalseBlock
; Entry->TrueBlock is the common path, which should be taken whenever the ; Entry->TrueBlock is the common path, which should be taken whenever the
; conditional branch is false. ; conditional branch is false.
true: true:
call void @test_true() call void @test_true()
ret void ret void
false: false:
call void @test_false() call void @test_false()
ret void ret void
} }
define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind { define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I-LABEL: test_bcc_fallthrough_nottaken: ; RV32I-LABEL: test_bcc_fallthrough_nottaken:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3 ; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false ; RV32I-NEXT: # %bb.1: # %false
; RV32I-NEXT: call test_false ; RV32I-NEXT: call test_false@plt
; RV32I-NEXT: .LBB1_2: # %true ; RV32I-NEXT: .LBB1_2: # %true
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_3: # %true ; RV32I-NEXT: .LBB1_3: # %true
; RV32I-NEXT: call test_true ; RV32I-NEXT: call test_true@plt
; RV32I-NEXT: j .LBB1_2 ; RV32I-NEXT: j .LBB1_2
%tst = icmp eq i32 %in, 42 %tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !1 br i1 %tst, label %true, label %false, !prof !1
; Expected layout order is: Entry, FalseBlock, TrueBlock ; Expected layout order is: Entry, FalseBlock, TrueBlock
; Entry->FalseBlock is the common path, which should be taken whenever the ; Entry->FalseBlock is the common path, which should be taken whenever the
; conditional branch is false ; conditional branch is false
Show All 10 Lines

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: .LBB0_3: ; RV32IA-NEXT: .LBB0_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: .LBB1_3: ; RV32IA-NEXT: .LBB1_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_acquire: ; RV32I-LABEL: cmpxchg_i8_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: .LBB2_3: ; RV32IA-NEXT: .LBB2_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_acquire: ; RV64I-LABEL: cmpxchg_i8_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_monotonic: ; RV32I-LABEL: cmpxchg_i8_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_monotonic: ; RV32IA-LABEL: cmpxchg_i8_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: .LBB3_3: ; RV32IA-NEXT: .LBB3_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_monotonic: ; RV64I-LABEL: cmpxchg_i8_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_monotonic: ; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_acquire: ; RV32I-LABEL: cmpxchg_i8_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_acquire: ; RV32IA-LABEL: cmpxchg_i8_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: .LBB4_3: ; RV32IA-NEXT: .LBB4_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_acquire: ; RV64I-LABEL: cmpxchg_i8_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_acquire: ; RV64IA-LABEL: cmpxchg_i8_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: .LBB5_3: ; RV32IA-NEXT: .LBB5_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: .LBB6_3: ; RV32IA-NEXT: .LBB6_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: .LBB7_3: ; RV32IA-NEXT: .LBB7_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: .LBB8_3: ; RV32IA-NEXT: .LBB8_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: .LBB9_3: ; RV32IA-NEXT: .LBB9_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB10_1 ; RV32IA-NEXT: bnez a4, .LBB10_1
; RV32IA-NEXT: .LBB10_3: ; RV32IA-NEXT: .LBB10_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB11_1 ; RV32IA-NEXT: bnez a4, .LBB11_1
; RV32IA-NEXT: .LBB11_3: ; RV32IA-NEXT: .LBB11_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_acquire: ; RV32I-LABEL: cmpxchg_i16_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB12_1 ; RV32IA-NEXT: bnez a4, .LBB12_1
; RV32IA-NEXT: .LBB12_3: ; RV32IA-NEXT: .LBB12_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_acquire: ; RV64I-LABEL: cmpxchg_i16_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_monotonic: ; RV32I-LABEL: cmpxchg_i16_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_monotonic: ; RV32IA-LABEL: cmpxchg_i16_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB13_1 ; RV32IA-NEXT: bnez a4, .LBB13_1
; RV32IA-NEXT: .LBB13_3: ; RV32IA-NEXT: .LBB13_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_monotonic: ; RV64I-LABEL: cmpxchg_i16_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_monotonic: ; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_acquire: ; RV32I-LABEL: cmpxchg_i16_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_acquire: ; RV32IA-LABEL: cmpxchg_i16_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB14_1 ; RV32IA-NEXT: bnez a4, .LBB14_1
; RV32IA-NEXT: .LBB14_3: ; RV32IA-NEXT: .LBB14_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_acquire: ; RV64I-LABEL: cmpxchg_i16_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_acquire: ; RV64IA-LABEL: cmpxchg_i16_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB15_1 ; RV32IA-NEXT: bnez a4, .LBB15_1
; RV32IA-NEXT: .LBB15_3: ; RV32IA-NEXT: .LBB15_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB16_1 ; RV32IA-NEXT: bnez a4, .LBB16_1
; RV32IA-NEXT: .LBB16_3: ; RV32IA-NEXT: .LBB16_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB17_1 ; RV32IA-NEXT: bnez a4, .LBB17_1
; RV32IA-NEXT: .LBB17_3: ; RV32IA-NEXT: .LBB17_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB18_1 ; RV32IA-NEXT: bnez a4, .LBB18_1
; RV32IA-NEXT: .LBB18_3: ; RV32IA-NEXT: .LBB18_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB19_1 ; RV32IA-NEXT: bnez a4, .LBB19_1
; RV32IA-NEXT: .LBB19_3: ; RV32IA-NEXT: .LBB19_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB20_3 ; RV32IA-NEXT: bne a3, a1, .LBB20_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB20_1 ; RV32IA-NEXT: bnez a4, .LBB20_1
; RV32IA-NEXT: .LBB20_3: ; RV32IA-NEXT: .LBB20_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB20_3 ; RV64IA-NEXT: bne a3, a1, .LBB20_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB20_1 ; RV64IA-NEXT: bnez a4, .LBB20_1
; RV64IA-NEXT: .LBB20_3: ; RV64IA-NEXT: .LBB20_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i32_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i32_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB21_3 ; RV32IA-NEXT: bne a3, a1, .LBB21_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB21_1 ; RV32IA-NEXT: bnez a4, .LBB21_1
; RV32IA-NEXT: .LBB21_3: ; RV32IA-NEXT: .LBB21_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB21_3 ; RV64IA-NEXT: bne a3, a1, .LBB21_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB21_1 ; RV64IA-NEXT: bnez a4, .LBB21_1
; RV64IA-NEXT: .LBB21_3: ; RV64IA-NEXT: .LBB21_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acquire_acquire: ; RV32I-LABEL: cmpxchg_i32_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i32_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB22_3 ; RV32IA-NEXT: bne a3, a1, .LBB22_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB22_1 ; RV32IA-NEXT: bnez a4, .LBB22_1
; RV32IA-NEXT: .LBB22_3: ; RV32IA-NEXT: .LBB22_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acquire_acquire: ; RV64I-LABEL: cmpxchg_i32_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB22_3 ; RV64IA-NEXT: bne a3, a1, .LBB22_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB22_1 ; RV64IA-NEXT: bnez a4, .LBB22_1
; RV64IA-NEXT: .LBB22_3: ; RV64IA-NEXT: .LBB22_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_release_monotonic: ; RV32I-LABEL: cmpxchg_i32_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_release_monotonic: ; RV32IA-LABEL: cmpxchg_i32_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB23_3 ; RV32IA-NEXT: bne a3, a1, .LBB23_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB23_1 ; RV32IA-NEXT: bnez a4, .LBB23_1
; RV32IA-NEXT: .LBB23_3: ; RV32IA-NEXT: .LBB23_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_release_monotonic: ; RV64I-LABEL: cmpxchg_i32_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_release_monotonic: ; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB23_3 ; RV64IA-NEXT: bne a3, a1, .LBB23_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB23_1 ; RV64IA-NEXT: bnez a4, .LBB23_1
; RV64IA-NEXT: .LBB23_3: ; RV64IA-NEXT: .LBB23_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_release_acquire: ; RV32I-LABEL: cmpxchg_i32_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_release_acquire: ; RV32IA-LABEL: cmpxchg_i32_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB24_3 ; RV32IA-NEXT: bne a3, a1, .LBB24_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB24_1 ; RV32IA-NEXT: bnez a4, .LBB24_1
; RV32IA-NEXT: .LBB24_3: ; RV32IA-NEXT: .LBB24_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_release_acquire: ; RV64I-LABEL: cmpxchg_i32_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_release_acquire: ; RV64IA-LABEL: cmpxchg_i32_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB24_3 ; RV64IA-NEXT: bne a3, a1, .LBB24_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB24_1 ; RV64IA-NEXT: bnez a4, .LBB24_1
; RV64IA-NEXT: .LBB24_3: ; RV64IA-NEXT: .LBB24_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
ret void ret void
} }
define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB25_3 ; RV32IA-NEXT: bne a3, a1, .LBB25_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB25_1 ; RV32IA-NEXT: bnez a4, .LBB25_1
; RV32IA-NEXT: .LBB25_3: ; RV32IA-NEXT: .LBB25_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB25_3 ; RV64IA-NEXT: bne a3, a1, .LBB25_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB25_1 ; RV64IA-NEXT: bnez a4, .LBB25_1
; RV64IA-NEXT: .LBB25_3: ; RV64IA-NEXT: .LBB25_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB26_3 ; RV32IA-NEXT: bne a3, a1, .LBB26_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB26_1 ; RV32IA-NEXT: bnez a4, .LBB26_1
; RV32IA-NEXT: .LBB26_3: ; RV32IA-NEXT: .LBB26_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB26_3 ; RV64IA-NEXT: bne a3, a1, .LBB26_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB26_1 ; RV64IA-NEXT: bnez a4, .LBB26_1
; RV64IA-NEXT: .LBB26_3: ; RV64IA-NEXT: .LBB26_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB27_3 ; RV32IA-NEXT: bne a3, a1, .LBB27_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB27_1 ; RV32IA-NEXT: bnez a4, .LBB27_1
; RV32IA-NEXT: .LBB27_3: ; RV32IA-NEXT: .LBB27_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB27_3 ; RV64IA-NEXT: bne a3, a1, .LBB27_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB27_1 ; RV64IA-NEXT: bnez a4, .LBB27_1
; RV64IA-NEXT: .LBB27_3: ; RV64IA-NEXT: .LBB27_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB28_3 ; RV32IA-NEXT: bne a3, a1, .LBB28_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB28_1 ; RV32IA-NEXT: bnez a4, .LBB28_1
; RV32IA-NEXT: .LBB28_3: ; RV32IA-NEXT: .LBB28_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB28_3 ; RV64IA-NEXT: bne a3, a1, .LBB28_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB28_1 ; RV64IA-NEXT: bnez a4, .LBB28_1
; RV64IA-NEXT: .LBB28_3: ; RV64IA-NEXT: .LBB28_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB29_3 ; RV32IA-NEXT: bne a3, a1, .LBB29_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB29_1 ; RV32IA-NEXT: bnez a4, .LBB29_1
; RV32IA-NEXT: .LBB29_3: ; RV32IA-NEXT: .LBB29_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB29_3 ; RV64IA-NEXT: bne a3, a1, .LBB29_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB29_1 ; RV64IA-NEXT: bnez a4, .LBB29_1
; RV64IA-NEXT: .LBB29_3: ; RV64IA-NEXT: .LBB29_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4 ; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB30_3 ; RV64IA-NEXT: bne a3, a1, .LBB30_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB30_1 ; RV64IA-NEXT: bnez a4, .LBB30_1
; RV64IA-NEXT: .LBB30_3: ; RV64IA-NEXT: .LBB30_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB31_3 ; RV64IA-NEXT: bne a3, a1, .LBB31_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB31_1 ; RV64IA-NEXT: bnez a4, .LBB31_1
; RV64IA-NEXT: .LBB31_3: ; RV64IA-NEXT: .LBB31_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_acquire: ; RV32I-LABEL: cmpxchg_i64_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i64_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_acquire: ; RV64I-LABEL: cmpxchg_i64_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i64_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB32_3 ; RV64IA-NEXT: bne a3, a1, .LBB32_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB32_1 ; RV64IA-NEXT: bnez a4, .LBB32_1
; RV64IA-NEXT: .LBB32_3: ; RV64IA-NEXT: .LBB32_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_monotonic: ; RV32I-LABEL: cmpxchg_i64_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_monotonic: ; RV32IA-LABEL: cmpxchg_i64_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_monotonic: ; RV64I-LABEL: cmpxchg_i64_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_release_monotonic: ; RV64IA-LABEL: cmpxchg_i64_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB33_3 ; RV64IA-NEXT: bne a3, a1, .LBB33_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB33_1 ; RV64IA-NEXT: bnez a4, .LBB33_1
; RV64IA-NEXT: .LBB33_3: ; RV64IA-NEXT: .LBB33_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_acquire: ; RV32I-LABEL: cmpxchg_i64_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_acquire: ; RV32IA-LABEL: cmpxchg_i64_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_acquire: ; RV64I-LABEL: cmpxchg_i64_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_release_acquire: ; RV64IA-LABEL: cmpxchg_i64_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB34_3 ; RV64IA-NEXT: bne a3, a1, .LBB34_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB34_1 ; RV64IA-NEXT: bnez a4, .LBB34_1
; RV64IA-NEXT: .LBB34_3: ; RV64IA-NEXT: .LBB34_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB35_3 ; RV64IA-NEXT: bne a3, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB35_1 ; RV64IA-NEXT: bnez a4, .LBB35_1
; RV64IA-NEXT: .LBB35_3: ; RV64IA-NEXT: .LBB35_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB36_3 ; RV64IA-NEXT: bne a3, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB36_1 ; RV64IA-NEXT: bnez a4, .LBB36_1
; RV64IA-NEXT: .LBB36_3: ; RV64IA-NEXT: .LBB36_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB37_3 ; RV64IA-NEXT: bne a3, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB37_1 ; RV64IA-NEXT: bnez a4, .LBB37_1
; RV64IA-NEXT: .LBB37_3: ; RV64IA-NEXT: .LBB37_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB38_3 ; RV64IA-NEXT: bne a3, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB38_1 ; RV64IA-NEXT: bnez a4, .LBB38_1
; RV64IA-NEXT: .LBB38_3: ; RV64IA-NEXT: .LBB38_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB39_3 ; RV64IA-NEXT: bne a3, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB39_1 ; RV64IA-NEXT: bnez a4, .LBB39_1
; RV64IA-NEXT: .LBB39_3: ; RV64IA-NEXT: .LBB39_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_unordered: ; RV32I-LABEL: atomic_load_i8_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_unordered: ; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_unordered: ; RV64I-LABEL: atomic_load_i8_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_unordered: ; RV64IA-LABEL: atomic_load_i8_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a unordered, align 1 %1 = load atomic i8, i8* %a unordered, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_monotonic: ; RV32I-LABEL: atomic_load_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_monotonic: ; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_monotonic: ; RV64I-LABEL: atomic_load_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_monotonic: ; RV64IA-LABEL: atomic_load_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a monotonic, align 1 %1 = load atomic i8, i8* %a monotonic, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { define i8 @atomic_load_i8_acquire(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_acquire: ; RV32I-LABEL: atomic_load_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_acquire: ; RV32IA-LABEL: atomic_load_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_acquire: ; RV64I-LABEL: atomic_load_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_acquire: ; RV64IA-LABEL: atomic_load_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a acquire, align 1 %1 = load atomic i8, i8* %a acquire, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_seq_cst: ; RV32I-LABEL: atomic_load_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_seq_cst: ; RV32IA-LABEL: atomic_load_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_seq_cst: ; RV64I-LABEL: atomic_load_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_seq_cst: ; RV64IA-LABEL: atomic_load_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a seq_cst, align 1 %1 = load atomic i8, i8* %a seq_cst, align 1
ret i8 %1 ret i8 %1
} }
define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { define i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_unordered: ; RV32I-LABEL: atomic_load_i16_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_unordered: ; RV32IA-LABEL: atomic_load_i16_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_unordered: ; RV64I-LABEL: atomic_load_i16_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_unordered: ; RV64IA-LABEL: atomic_load_i16_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a unordered, align 2 %1 = load atomic i16, i16* %a unordered, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_monotonic: ; RV32I-LABEL: atomic_load_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_monotonic: ; RV32IA-LABEL: atomic_load_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_monotonic: ; RV64I-LABEL: atomic_load_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_monotonic: ; RV64IA-LABEL: atomic_load_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a monotonic, align 2 %1 = load atomic i16, i16* %a monotonic, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { define i16 @atomic_load_i16_acquire(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_acquire: ; RV32I-LABEL: atomic_load_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_acquire: ; RV32IA-LABEL: atomic_load_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_acquire: ; RV64I-LABEL: atomic_load_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_acquire: ; RV64IA-LABEL: atomic_load_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a acquire, align 2 %1 = load atomic i16, i16* %a acquire, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_seq_cst: ; RV32I-LABEL: atomic_load_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_seq_cst: ; RV32IA-LABEL: atomic_load_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_seq_cst: ; RV64I-LABEL: atomic_load_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_seq_cst: ; RV64IA-LABEL: atomic_load_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a seq_cst, align 2 %1 = load atomic i16, i16* %a seq_cst, align 2
ret i16 %1 ret i16 %1
} }
define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { define i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_unordered: ; RV32I-LABEL: atomic_load_i32_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_unordered: ; RV32IA-LABEL: atomic_load_i32_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_unordered: ; RV64I-LABEL: atomic_load_i32_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_unordered: ; RV64IA-LABEL: atomic_load_i32_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a unordered, align 4 %1 = load atomic i32, i32* %a unordered, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_monotonic: ; RV32I-LABEL: atomic_load_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_monotonic: ; RV32IA-LABEL: atomic_load_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_monotonic: ; RV64I-LABEL: atomic_load_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_monotonic: ; RV64IA-LABEL: atomic_load_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a monotonic, align 4 %1 = load atomic i32, i32* %a monotonic, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { define i32 @atomic_load_i32_acquire(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_acquire: ; RV32I-LABEL: atomic_load_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_acquire: ; RV32IA-LABEL: atomic_load_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_acquire: ; RV64I-LABEL: atomic_load_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_acquire: ; RV64IA-LABEL: atomic_load_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a acquire, align 4 %1 = load atomic i32, i32* %a acquire, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_seq_cst: ; RV32I-LABEL: atomic_load_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_seq_cst: ; RV32IA-LABEL: atomic_load_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_seq_cst: ; RV64I-LABEL: atomic_load_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_seq_cst: ; RV64IA-LABEL: atomic_load_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a seq_cst, align 4 %1 = load atomic i32, i32* %a seq_cst, align 4
ret i32 %1 ret i32 %1
} }
define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { define i64 @atomic_load_i64_unordered(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_unordered: ; RV32I-LABEL: atomic_load_i64_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_unordered: ; RV32IA-LABEL: atomic_load_i64_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a1, zero ; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_unordered: ; RV64I-LABEL: atomic_load_i64_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_unordered: ; RV64IA-LABEL: atomic_load_i64_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a unordered, align 8 %1 = load atomic i64, i64* %a unordered, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_monotonic: ; RV32I-LABEL: atomic_load_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_monotonic: ; RV32IA-LABEL: atomic_load_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a1, zero ; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_monotonic: ; RV64I-LABEL: atomic_load_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_monotonic: ; RV64IA-LABEL: atomic_load_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a monotonic, align 8 %1 = load atomic i64, i64* %a monotonic, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { define i64 @atomic_load_i64_acquire(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_acquire: ; RV32I-LABEL: atomic_load_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_acquire: ; RV32IA-LABEL: atomic_load_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a1, zero, 2 ; RV32IA-NEXT: addi a1, zero, 2
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_acquire: ; RV64I-LABEL: atomic_load_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_acquire: ; RV64IA-LABEL: atomic_load_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a acquire, align 8 %1 = load atomic i64, i64* %a acquire, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_seq_cst: ; RV32I-LABEL: atomic_load_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_seq_cst: ; RV32IA-LABEL: atomic_load_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a1, zero, 5 ; RV32IA-NEXT: addi a1, zero, 5
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_seq_cst: ; RV64I-LABEL: atomic_load_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_seq_cst: ; RV64IA-LABEL: atomic_load_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a seq_cst, align 8 %1 = load atomic i64, i64* %a seq_cst, align 8
ret i64 %1 ret i64 %1
} }
define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_unordered: ; RV32I-LABEL: atomic_store_i8_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_unordered: ; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_unordered: ; RV64I-LABEL: atomic_store_i8_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_unordered: ; RV64IA-LABEL: atomic_store_i8_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a unordered, align 1 store atomic i8 %b, i8* %a unordered, align 1
ret void ret void
} }
define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_monotonic: ; RV32I-LABEL: atomic_store_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_monotonic: ; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_monotonic: ; RV64I-LABEL: atomic_store_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_monotonic: ; RV64IA-LABEL: atomic_store_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a monotonic, align 1 store atomic i8 %b, i8* %a monotonic, align 1
ret void ret void
} }
define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_release: ; RV32I-LABEL: atomic_store_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_release: ; RV32IA-LABEL: atomic_store_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_release: ; RV64I-LABEL: atomic_store_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_release: ; RV64IA-LABEL: atomic_store_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a release, align 1 store atomic i8 %b, i8* %a release, align 1
ret void ret void
} }
define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_seq_cst: ; RV32I-LABEL: atomic_store_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_seq_cst: ; RV32IA-LABEL: atomic_store_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_seq_cst: ; RV64I-LABEL: atomic_store_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_seq_cst: ; RV64IA-LABEL: atomic_store_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a seq_cst, align 1 store atomic i8 %b, i8* %a seq_cst, align 1
ret void ret void
} }
define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_unordered: ; RV32I-LABEL: atomic_store_i16_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_unordered: ; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_unordered: ; RV64I-LABEL: atomic_store_i16_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_unordered: ; RV64IA-LABEL: atomic_store_i16_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a unordered, align 2 store atomic i16 %b, i16* %a unordered, align 2
ret void ret void
} }
define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_monotonic: ; RV32I-LABEL: atomic_store_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_monotonic: ; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_monotonic: ; RV64I-LABEL: atomic_store_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_monotonic: ; RV64IA-LABEL: atomic_store_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a monotonic, align 2 store atomic i16 %b, i16* %a monotonic, align 2
ret void ret void
} }
define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_release: ; RV32I-LABEL: atomic_store_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_release: ; RV32IA-LABEL: atomic_store_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_release: ; RV64I-LABEL: atomic_store_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_release: ; RV64IA-LABEL: atomic_store_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a release, align 2 store atomic i16 %b, i16* %a release, align 2
ret void ret void
} }
define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_seq_cst: ; RV32I-LABEL: atomic_store_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_seq_cst: ; RV32IA-LABEL: atomic_store_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_seq_cst: ; RV64I-LABEL: atomic_store_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_seq_cst: ; RV64IA-LABEL: atomic_store_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a seq_cst, align 2 store atomic i16 %b, i16* %a seq_cst, align 2
ret void ret void
} }
define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_unordered: ; RV32I-LABEL: atomic_store_i32_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_unordered: ; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_unordered: ; RV64I-LABEL: atomic_store_i32_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_unordered: ; RV64IA-LABEL: atomic_store_i32_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a unordered, align 4 store atomic i32 %b, i32* %a unordered, align 4
ret void ret void
} }
define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_monotonic: ; RV32I-LABEL: atomic_store_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_monotonic: ; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_monotonic: ; RV64I-LABEL: atomic_store_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_monotonic: ; RV64IA-LABEL: atomic_store_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a monotonic, align 4 store atomic i32 %b, i32* %a monotonic, align 4
ret void ret void
} }
define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_release: ; RV32I-LABEL: atomic_store_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_release: ; RV32IA-LABEL: atomic_store_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_release: ; RV64I-LABEL: atomic_store_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_release: ; RV64IA-LABEL: atomic_store_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a release, align 4 store atomic i32 %b, i32* %a release, align 4
ret void ret void
} }
define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_seq_cst: ; RV32I-LABEL: atomic_store_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_seq_cst: ; RV32IA-LABEL: atomic_store_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_seq_cst: ; RV64I-LABEL: atomic_store_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_seq_cst: ; RV64IA-LABEL: atomic_store_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a seq_cst, align 4 store atomic i32 %b, i32* %a seq_cst, align 4
ret void ret void
} }
define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_unordered: ; RV32I-LABEL: atomic_store_i64_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_unordered: ; RV32IA-LABEL: atomic_store_i64_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_unordered: ; RV64I-LABEL: atomic_store_i64_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_unordered: ; RV64IA-LABEL: atomic_store_i64_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a unordered, align 8 store atomic i64 %b, i64* %a unordered, align 8
ret void ret void
} }
define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_monotonic: ; RV32I-LABEL: atomic_store_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_monotonic: ; RV32IA-LABEL: atomic_store_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_monotonic: ; RV64I-LABEL: atomic_store_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_monotonic: ; RV64IA-LABEL: atomic_store_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a monotonic, align 8 store atomic i64 %b, i64* %a monotonic, align 8
ret void ret void
} }
define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_release: ; RV32I-LABEL: atomic_store_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_release: ; RV32IA-LABEL: atomic_store_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_release: ; RV64I-LABEL: atomic_store_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_release: ; RV64IA-LABEL: atomic_store_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a release, align 8 store atomic i64 %b, i64* %a release, align 8
ret void ret void
} }
define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_seq_cst: ; RV32I-LABEL: atomic_store_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_seq_cst: ; RV32IA-LABEL: atomic_store_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_seq_cst: ; RV64I-LABEL: atomic_store_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_seq_cst: ; RV64IA-LABEL: atomic_store_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a seq_cst, align 8 store atomic i64 %b, i64* %a seq_cst, align 8
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-rmw.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b monotonic %1 = atomicrmw xchg i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acquire: ; RV32I-LABEL: atomicrmw_xchg_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acquire: ; RV64I-LABEL: atomicrmw_xchg_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acquire %1 = atomicrmw xchg i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_release: ; RV32I-LABEL: atomicrmw_xchg_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_release: ; RV32IA-LABEL: atomicrmw_xchg_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_release: ; RV64I-LABEL: atomicrmw_xchg_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-LABEL: atomicrmw_xchg_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b release %1 = atomicrmw xchg i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acq_rel %1 = atomicrmw xchg i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b seq_cst %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_monotonic: ; RV32I-LABEL: atomicrmw_add_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_monotonic: ; RV32IA-LABEL: atomicrmw_add_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_monotonic: ; RV64I-LABEL: atomicrmw_add_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b monotonic %1 = atomicrmw add i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acquire: ; RV32I-LABEL: atomicrmw_add_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acquire: ; RV32IA-LABEL: atomicrmw_add_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acquire: ; RV64I-LABEL: atomicrmw_add_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-LABEL: atomicrmw_add_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acquire %1 = atomicrmw add i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_release: ; RV32I-LABEL: atomicrmw_add_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_release: ; RV32IA-LABEL: atomicrmw_add_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_release: ; RV64I-LABEL: atomicrmw_add_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_release: ; RV64IA-LABEL: atomicrmw_add_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b release %1 = atomicrmw add i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acq_rel: ; RV32I-LABEL: atomicrmw_add_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acq_rel: ; RV64I-LABEL: atomicrmw_add_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acq_rel %1 = atomicrmw add i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_seq_cst: ; RV32I-LABEL: atomicrmw_add_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_seq_cst: ; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b seq_cst %1 = atomicrmw add i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_monotonic: ; RV32I-LABEL: atomicrmw_sub_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB10_1 ; RV32IA-NEXT: bnez a5, .LBB10_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_monotonic: ; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b monotonic %1 = atomicrmw sub i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acquire: ; RV32I-LABEL: atomicrmw_sub_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acquire: ; RV32IA-LABEL: atomicrmw_sub_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB11_1 ; RV32IA-NEXT: bnez a5, .LBB11_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acquire: ; RV64I-LABEL: atomicrmw_sub_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acquire %1 = atomicrmw sub i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_release: ; RV32I-LABEL: atomicrmw_sub_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_release: ; RV32IA-LABEL: atomicrmw_sub_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: bnez a5, .LBB12_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_release: ; RV64I-LABEL: atomicrmw_sub_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_release: ; RV64IA-LABEL: atomicrmw_sub_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b release %1 = atomicrmw sub i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: bnez a5, .LBB13_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acq_rel %1 = atomicrmw sub i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: bnez a5, .LBB14_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b seq_cst %1 = atomicrmw sub i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_monotonic: ; RV32I-LABEL: atomicrmw_and_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_monotonic: ; RV32IA-LABEL: atomicrmw_and_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2) ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_monotonic: ; RV64I-LABEL: atomicrmw_and_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b monotonic %1 = atomicrmw and i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acquire: ; RV32I-LABEL: atomicrmw_and_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acquire: ; RV32IA-LABEL: atomicrmw_and_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acquire: ; RV64I-LABEL: atomicrmw_and_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-LABEL: atomicrmw_and_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acquire %1 = atomicrmw and i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_release: ; RV32I-LABEL: atomicrmw_and_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_release: ; RV32IA-LABEL: atomicrmw_and_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_release: ; RV64I-LABEL: atomicrmw_and_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_release: ; RV64IA-LABEL: atomicrmw_and_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b release %1 = atomicrmw and i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acq_rel: ; RV32I-LABEL: atomicrmw_and_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acq_rel: ; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acq_rel %1 = atomicrmw and i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_seq_cst: ; RV32I-LABEL: atomicrmw_and_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_seq_cst: ; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b seq_cst %1 = atomicrmw and i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_monotonic: ; RV32I-LABEL: atomicrmw_nand_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB20_1 ; RV32IA-NEXT: bnez a5, .LBB20_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_monotonic: ; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b monotonic %1 = atomicrmw nand i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acquire: ; RV32I-LABEL: atomicrmw_nand_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acquire: ; RV32IA-LABEL: atomicrmw_nand_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB21_1 ; RV32IA-NEXT: bnez a5, .LBB21_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acquire: ; RV64I-LABEL: atomicrmw_nand_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acquire %1 = atomicrmw nand i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_release: ; RV32I-LABEL: atomicrmw_nand_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_release: ; RV32IA-LABEL: atomicrmw_nand_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB22_1 ; RV32IA-NEXT: bnez a5, .LBB22_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_release: ; RV64I-LABEL: atomicrmw_nand_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_release: ; RV64IA-LABEL: atomicrmw_nand_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b release %1 = atomicrmw nand i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB23_1 ; RV32IA-NEXT: bnez a5, .LBB23_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acq_rel %1 = atomicrmw nand i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: bnez a5, .LBB24_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b seq_cst %1 = atomicrmw nand i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_monotonic: ; RV32I-LABEL: atomicrmw_or_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_monotonic: ; RV32IA-LABEL: atomicrmw_or_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2) ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_monotonic: ; RV64I-LABEL: atomicrmw_or_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2) ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b monotonic %1 = atomicrmw or i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acquire: ; RV32I-LABEL: atomicrmw_or_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acquire: ; RV32IA-LABEL: atomicrmw_or_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acquire: ; RV64I-LABEL: atomicrmw_or_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-LABEL: atomicrmw_or_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acquire %1 = atomicrmw or i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_release: ; RV32I-LABEL: atomicrmw_or_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_release: ; RV32IA-LABEL: atomicrmw_or_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_release: ; RV64I-LABEL: atomicrmw_or_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_release: ; RV64IA-LABEL: atomicrmw_or_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b release %1 = atomicrmw or i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acq_rel: ; RV32I-LABEL: atomicrmw_or_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acq_rel: ; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acq_rel %1 = atomicrmw or i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_seq_cst: ; RV32I-LABEL: atomicrmw_or_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_seq_cst: ; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b seq_cst %1 = atomicrmw or i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_monotonic: ; RV32I-LABEL: atomicrmw_xor_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2) ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_monotonic: ; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2) ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b monotonic %1 = atomicrmw xor i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acquire: ; RV32I-LABEL: atomicrmw_xor_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acquire: ; RV32IA-LABEL: atomicrmw_xor_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acquire: ; RV64I-LABEL: atomicrmw_xor_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acquire %1 = atomicrmw xor i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_release: ; RV32I-LABEL: atomicrmw_xor_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_release: ; RV32IA-LABEL: atomicrmw_xor_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_release: ; RV64I-LABEL: atomicrmw_xor_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_release: ; RV64IA-LABEL: atomicrmw_xor_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b release %1 = atomicrmw xor i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acq_rel %1 = atomicrmw xor i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b seq_cst %1 = atomicrmw xor i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_monotonic: ; RV32I-LABEL: atomicrmw_max_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB35_2 ; RV32I-NEXT: j .LBB35_2
; RV32I-NEXT: .LBB35_1: # %atomicrmw.start ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB35_1 ; RV32I-NEXT: blt s1, a0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB35_1 ; RV32IA-NEXT: bnez a2, .LBB35_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB35_1 ; RV64I-NEXT: blt s1, a0, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b monotonic %1 = atomicrmw max i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acquire: ; RV32I-LABEL: atomicrmw_max_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB36_2 ; RV32I-NEXT: j .LBB36_2
; RV32I-NEXT: .LBB36_1: # %atomicrmw.start ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB36_4 ; RV32I-NEXT: bnez a0, .LBB36_4
; RV32I-NEXT: .LBB36_2: # %atomicrmw.start ; RV32I-NEXT: .LBB36_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB36_1 ; RV32I-NEXT: blt s1, a0, .LBB36_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB36_1 ; RV32I-NEXT: j .LBB36_1
; RV32I-NEXT: .LBB36_4: # %atomicrmw.end ; RV32I-NEXT: .LBB36_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acquire: ; RV32IA-LABEL: atomicrmw_max_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB36_1 ; RV32IA-NEXT: bnez a2, .LBB36_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acquire: ; RV64I-LABEL: atomicrmw_max_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB36_2 ; RV64I-NEXT: j .LBB36_2
; RV64I-NEXT: .LBB36_1: # %atomicrmw.start ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB36_4 ; RV64I-NEXT: bnez a0, .LBB36_4
; RV64I-NEXT: .LBB36_2: # %atomicrmw.start ; RV64I-NEXT: .LBB36_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB36_1 ; RV64I-NEXT: blt s1, a0, .LBB36_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB36_1 ; RV64I-NEXT: j .LBB36_1
; RV64I-NEXT: .LBB36_4: # %atomicrmw.end ; RV64I-NEXT: .LBB36_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acquire %1 = atomicrmw max i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_release: ; RV32I-LABEL: atomicrmw_max_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB37_2 ; RV32I-NEXT: j .LBB37_2
; RV32I-NEXT: .LBB37_1: # %atomicrmw.start ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB37_4 ; RV32I-NEXT: bnez a0, .LBB37_4
; RV32I-NEXT: .LBB37_2: # %atomicrmw.start ; RV32I-NEXT: .LBB37_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB37_1 ; RV32I-NEXT: blt s1, a0, .LBB37_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB37_1 ; RV32I-NEXT: j .LBB37_1
; RV32I-NEXT: .LBB37_4: # %atomicrmw.end ; RV32I-NEXT: .LBB37_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_release: ; RV32IA-LABEL: atomicrmw_max_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB37_1 ; RV32IA-NEXT: bnez a2, .LBB37_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_release: ; RV64I-LABEL: atomicrmw_max_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB37_2 ; RV64I-NEXT: j .LBB37_2
; RV64I-NEXT: .LBB37_1: # %atomicrmw.start ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB37_4 ; RV64I-NEXT: bnez a0, .LBB37_4
; RV64I-NEXT: .LBB37_2: # %atomicrmw.start ; RV64I-NEXT: .LBB37_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB37_1 ; RV64I-NEXT: blt s1, a0, .LBB37_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB37_1 ; RV64I-NEXT: j .LBB37_1
; RV64I-NEXT: .LBB37_4: # %atomicrmw.end ; RV64I-NEXT: .LBB37_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_release: ; RV64IA-LABEL: atomicrmw_max_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b release %1 = atomicrmw max i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acq_rel: ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB38_2 ; RV32I-NEXT: j .LBB38_2
; RV32I-NEXT: .LBB38_1: # %atomicrmw.start ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB38_4 ; RV32I-NEXT: bnez a0, .LBB38_4
; RV32I-NEXT: .LBB38_2: # %atomicrmw.start ; RV32I-NEXT: .LBB38_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB38_1 ; RV32I-NEXT: blt s1, a0, .LBB38_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB38_1 ; RV32I-NEXT: j .LBB38_1
; RV32I-NEXT: .LBB38_4: # %atomicrmw.end ; RV32I-NEXT: .LBB38_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB38_1 ; RV32IA-NEXT: bnez a2, .LBB38_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acq_rel: ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB38_2 ; RV64I-NEXT: j .LBB38_2
; RV64I-NEXT: .LBB38_1: # %atomicrmw.start ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB38_4 ; RV64I-NEXT: bnez a0, .LBB38_4
; RV64I-NEXT: .LBB38_2: # %atomicrmw.start ; RV64I-NEXT: .LBB38_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB38_1 ; RV64I-NEXT: blt s1, a0, .LBB38_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB38_1 ; RV64I-NEXT: j .LBB38_1
; RV64I-NEXT: .LBB38_4: # %atomicrmw.end ; RV64I-NEXT: .LBB38_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acq_rel %1 = atomicrmw max i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_seq_cst: ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB39_2 ; RV32I-NEXT: j .LBB39_2
; RV32I-NEXT: .LBB39_1: # %atomicrmw.start ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB39_4 ; RV32I-NEXT: bnez a0, .LBB39_4
; RV32I-NEXT: .LBB39_2: # %atomicrmw.start ; RV32I-NEXT: .LBB39_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB39_1 ; RV32I-NEXT: blt s1, a0, .LBB39_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB39_1 ; RV32I-NEXT: j .LBB39_1
; RV32I-NEXT: .LBB39_4: # %atomicrmw.end ; RV32I-NEXT: .LBB39_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB39_1 ; RV32IA-NEXT: bnez a2, .LBB39_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB39_2 ; RV64I-NEXT: j .LBB39_2
; RV64I-NEXT: .LBB39_1: # %atomicrmw.start ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB39_4 ; RV64I-NEXT: bnez a0, .LBB39_4
; RV64I-NEXT: .LBB39_2: # %atomicrmw.start ; RV64I-NEXT: .LBB39_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB39_1 ; RV64I-NEXT: blt s1, a0, .LBB39_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB39_1 ; RV64I-NEXT: j .LBB39_1
; RV64I-NEXT: .LBB39_4: # %atomicrmw.end ; RV64I-NEXT: .LBB39_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b seq_cst %1 = atomicrmw max i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic: ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB40_2 ; RV32I-NEXT: j .LBB40_2
; RV32I-NEXT: .LBB40_1: # %atomicrmw.start ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB40_4 ; RV32I-NEXT: bnez a0, .LBB40_4
; RV32I-NEXT: .LBB40_2: # %atomicrmw.start ; RV32I-NEXT: .LBB40_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB40_1 ; RV32I-NEXT: bge s1, a0, .LBB40_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: j .LBB40_1
; RV32I-NEXT: .LBB40_4: # %atomicrmw.end ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB40_1 ; RV32IA-NEXT: bnez a2, .LBB40_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB40_2 ; RV64I-NEXT: j .LBB40_2
; RV64I-NEXT: .LBB40_1: # %atomicrmw.start ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB40_4 ; RV64I-NEXT: bnez a0, .LBB40_4
; RV64I-NEXT: .LBB40_2: # %atomicrmw.start ; RV64I-NEXT: .LBB40_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB40_1 ; RV64I-NEXT: bge s1, a0, .LBB40_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: j .LBB40_1
; RV64I-NEXT: .LBB40_4: # %atomicrmw.end ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b monotonic %1 = atomicrmw min i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acquire: ; RV32I-LABEL: atomicrmw_min_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB41_2 ; RV32I-NEXT: j .LBB41_2
; RV32I-NEXT: .LBB41_1: # %atomicrmw.start ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB41_4 ; RV32I-NEXT: bnez a0, .LBB41_4
; RV32I-NEXT: .LBB41_2: # %atomicrmw.start ; RV32I-NEXT: .LBB41_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB41_1 ; RV32I-NEXT: bge s1, a0, .LBB41_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: j .LBB41_1
; RV32I-NEXT: .LBB41_4: # %atomicrmw.end ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acquire: ; RV32IA-LABEL: atomicrmw_min_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB41_1 ; RV32IA-NEXT: bnez a2, .LBB41_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acquire: ; RV64I-LABEL: atomicrmw_min_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB41_2 ; RV64I-NEXT: j .LBB41_2
; RV64I-NEXT: .LBB41_1: # %atomicrmw.start ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB41_4 ; RV64I-NEXT: bnez a0, .LBB41_4
; RV64I-NEXT: .LBB41_2: # %atomicrmw.start ; RV64I-NEXT: .LBB41_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB41_1 ; RV64I-NEXT: bge s1, a0, .LBB41_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: j .LBB41_1
; RV64I-NEXT: .LBB41_4: # %atomicrmw.end ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acquire %1 = atomicrmw min i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_release: ; RV32I-LABEL: atomicrmw_min_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB42_2 ; RV32I-NEXT: j .LBB42_2
; RV32I-NEXT: .LBB42_1: # %atomicrmw.start ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB42_4 ; RV32I-NEXT: bnez a0, .LBB42_4
; RV32I-NEXT: .LBB42_2: # %atomicrmw.start ; RV32I-NEXT: .LBB42_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB42_1 ; RV32I-NEXT: bge s1, a0, .LBB42_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: j .LBB42_1
; RV32I-NEXT: .LBB42_4: # %atomicrmw.end ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_release: ; RV32IA-LABEL: atomicrmw_min_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB42_1 ; RV32IA-NEXT: bnez a2, .LBB42_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_release: ; RV64I-LABEL: atomicrmw_min_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB42_2 ; RV64I-NEXT: j .LBB42_2
; RV64I-NEXT: .LBB42_1: # %atomicrmw.start ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB42_4 ; RV64I-NEXT: bnez a0, .LBB42_4
; RV64I-NEXT: .LBB42_2: # %atomicrmw.start ; RV64I-NEXT: .LBB42_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB42_1 ; RV64I-NEXT: bge s1, a0, .LBB42_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: j .LBB42_1
; RV64I-NEXT: .LBB42_4: # %atomicrmw.end ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_release: ; RV64IA-LABEL: atomicrmw_min_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b release %1 = atomicrmw min i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acq_rel: ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB43_2 ; RV32I-NEXT: j .LBB43_2
; RV32I-NEXT: .LBB43_1: # %atomicrmw.start ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB43_4 ; RV32I-NEXT: bnez a0, .LBB43_4
; RV32I-NEXT: .LBB43_2: # %atomicrmw.start ; RV32I-NEXT: .LBB43_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB43_1 ; RV32I-NEXT: bge s1, a0, .LBB43_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: j .LBB43_1
; RV32I-NEXT: .LBB43_4: # %atomicrmw.end ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB43_1 ; RV32IA-NEXT: bnez a2, .LBB43_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acq_rel: ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB43_2 ; RV64I-NEXT: j .LBB43_2
; RV64I-NEXT: .LBB43_1: # %atomicrmw.start ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB43_4 ; RV64I-NEXT: bnez a0, .LBB43_4
; RV64I-NEXT: .LBB43_2: # %atomicrmw.start ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB43_1 ; RV64I-NEXT: bge s1, a0, .LBB43_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: j .LBB43_1
; RV64I-NEXT: .LBB43_4: # %atomicrmw.end ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acq_rel %1 = atomicrmw min i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_seq_cst: ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB44_2 ; RV32I-NEXT: j .LBB44_2
; RV32I-NEXT: .LBB44_1: # %atomicrmw.start ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB44_4 ; RV32I-NEXT: bnez a0, .LBB44_4
; RV32I-NEXT: .LBB44_2: # %atomicrmw.start ; RV32I-NEXT: .LBB44_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB44_1 ; RV32I-NEXT: bge s1, a0, .LBB44_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_4: # %atomicrmw.end ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB44_1 ; RV32IA-NEXT: bnez a2, .LBB44_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB44_2 ; RV64I-NEXT: j .LBB44_2
; RV64I-NEXT: .LBB44_1: # %atomicrmw.start ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB44_1 ; RV64I-NEXT: bge s1, a0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b seq_cst %1 = atomicrmw min i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic: ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB45_2 ; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB45_4 ; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB45_1 ; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB45_1 ; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end ; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB45_1 ; RV32IA-NEXT: bnez a5, .LBB45_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB45_2 ; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB45_4 ; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB45_1 ; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB45_1 ; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end ; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b monotonic %1 = atomicrmw umax i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acquire: ; RV32I-LABEL: atomicrmw_umax_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB46_2 ; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB46_4 ; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB46_1 ; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end ; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA-LABEL: atomicrmw_umax_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB46_1 ; RV32IA-NEXT: bnez a5, .LBB46_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acquire: ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB46_2 ; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB46_1 ; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acquire %1 = atomicrmw umax i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_release: ; RV32I-LABEL: atomicrmw_umax_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB47_2 ; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB47_4 ; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB47_1 ; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB47_1 ; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end ; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_release: ; RV32IA-LABEL: atomicrmw_umax_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB47_1 ; RV32IA-NEXT: bnez a5, .LBB47_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_release: ; RV64I-LABEL: atomicrmw_umax_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB47_2 ; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB47_4 ; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB47_1 ; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB47_1 ; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end ; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_release: ; RV64IA-LABEL: atomicrmw_umax_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b release %1 = atomicrmw umax i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB48_2 ; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB48_4 ; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB48_1 ; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB48_1 ; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end ; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB48_1 ; RV32IA-NEXT: bnez a5, .LBB48_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB48_2 ; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB48_4 ; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB48_1 ; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB48_1 ; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end ; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acq_rel %1 = atomicrmw umax i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB49_2 ; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB49_4 ; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB49_1 ; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB49_1 ; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end ; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: bnez a5, .LBB49_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB49_2 ; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB49_4 ; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB49_1 ; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB49_1 ; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end ; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b seq_cst %1 = atomicrmw umax i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic: ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB50_2 ; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB50_4 ; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB50_1 ; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB50_1 ; RV32IA-NEXT: bnez a5, .LBB50_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB50_2 ; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB50_4 ; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB50_1 ; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b monotonic %1 = atomicrmw umin i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acquire: ; RV32I-LABEL: atomicrmw_umin_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB51_2 ; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB51_4 ; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB51_1 ; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA-LABEL: atomicrmw_umin_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB51_1 ; RV32IA-NEXT: bnez a5, .LBB51_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acquire: ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB51_2 ; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB51_4 ; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB51_1 ; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acquire %1 = atomicrmw umin i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_release: ; RV32I-LABEL: atomicrmw_umin_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB52_2 ; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB52_4 ; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB52_1 ; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_release: ; RV32IA-LABEL: atomicrmw_umin_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB52_1 ; RV32IA-NEXT: bnez a5, .LBB52_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_release: ; RV64I-LABEL: atomicrmw_umin_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB52_2 ; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB52_4 ; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB52_1 ; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_release: ; RV64IA-LABEL: atomicrmw_umin_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b release %1 = atomicrmw umin i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB53_2 ; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB53_4 ; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB53_1 ; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB53_1 ; RV32IA-NEXT: bnez a5, .LBB53_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB53_2 ; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB53_4 ; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB53_1 ; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acq_rel %1 = atomicrmw umin i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB54_2 ; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB54_4 ; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB54_1 ; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: bnez a5, .LBB54_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB54_2 ; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB54_4 ; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB54_1 ; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b seq_cst %1 = atomicrmw umin i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB55_1 ; RV32IA-NEXT: bnez a5, .LBB55_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b monotonic %1 = atomicrmw xchg i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acquire: ; RV32I-LABEL: atomicrmw_xchg_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB56_1 ; RV32IA-NEXT: bnez a5, .LBB56_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acquire: ; RV64I-LABEL: atomicrmw_xchg_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acquire %1 = atomicrmw xchg i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_release: ; RV32I-LABEL: atomicrmw_xchg_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_release: ; RV32IA-LABEL: atomicrmw_xchg_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB57_1 ; RV32IA-NEXT: bnez a5, .LBB57_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_release: ; RV64I-LABEL: atomicrmw_xchg_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-LABEL: atomicrmw_xchg_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b release %1 = atomicrmw xchg i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB58_1 ; RV32IA-NEXT: bnez a5, .LBB58_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acq_rel %1 = atomicrmw xchg i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: bnez a5, .LBB59_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b seq_cst %1 = atomicrmw xchg i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_monotonic: ; RV32I-LABEL: atomicrmw_add_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_monotonic: ; RV32IA-LABEL: atomicrmw_add_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB60_1 ; RV32IA-NEXT: bnez a5, .LBB60_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_monotonic: ; RV64I-LABEL: atomicrmw_add_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b monotonic %1 = atomicrmw add i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acquire: ; RV32I-LABEL: atomicrmw_add_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acquire: ; RV32IA-LABEL: atomicrmw_add_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB61_1 ; RV32IA-NEXT: bnez a5, .LBB61_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acquire: ; RV64I-LABEL: atomicrmw_add_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-LABEL: atomicrmw_add_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acquire %1 = atomicrmw add i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_release: ; RV32I-LABEL: atomicrmw_add_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_release: ; RV32IA-LABEL: atomicrmw_add_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB62_1 ; RV32IA-NEXT: bnez a5, .LBB62_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_release: ; RV64I-LABEL: atomicrmw_add_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_release: ; RV64IA-LABEL: atomicrmw_add_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b release %1 = atomicrmw add i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acq_rel: ; RV32I-LABEL: atomicrmw_add_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB63_1 ; RV32IA-NEXT: bnez a5, .LBB63_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acq_rel: ; RV64I-LABEL: atomicrmw_add_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acq_rel %1 = atomicrmw add i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_seq_cst: ; RV32I-LABEL: atomicrmw_add_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB64_1 ; RV32IA-NEXT: bnez a5, .LBB64_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_seq_cst: ; RV64I-LABEL: atomicrmw_add_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b seq_cst %1 = atomicrmw add i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_monotonic: ; RV32I-LABEL: atomicrmw_sub_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB65_1 ; RV32IA-NEXT: bnez a5, .LBB65_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_monotonic: ; RV64I-LABEL: atomicrmw_sub_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b monotonic %1 = atomicrmw sub i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acquire: ; RV32I-LABEL: atomicrmw_sub_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acquire: ; RV32IA-LABEL: atomicrmw_sub_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB66_1 ; RV32IA-NEXT: bnez a5, .LBB66_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acquire: ; RV64I-LABEL: atomicrmw_sub_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-LABEL: atomicrmw_sub_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acquire %1 = atomicrmw sub i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_release: ; RV32I-LABEL: atomicrmw_sub_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_release: ; RV32IA-LABEL: atomicrmw_sub_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB67_1 ; RV32IA-NEXT: bnez a5, .LBB67_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_release: ; RV64I-LABEL: atomicrmw_sub_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_release: ; RV64IA-LABEL: atomicrmw_sub_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b release %1 = atomicrmw sub i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB68_1 ; RV32IA-NEXT: bnez a5, .LBB68_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acq_rel %1 = atomicrmw sub i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB69_1 ; RV32IA-NEXT: bnez a5, .LBB69_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b seq_cst %1 = atomicrmw sub i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_monotonic: ; RV32I-LABEL: atomicrmw_and_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_monotonic: ; RV32IA-LABEL: atomicrmw_and_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2) ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_monotonic: ; RV64I-LABEL: atomicrmw_and_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b monotonic %1 = atomicrmw and i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acquire: ; RV32I-LABEL: atomicrmw_and_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acquire: ; RV32IA-LABEL: atomicrmw_and_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acquire: ; RV64I-LABEL: atomicrmw_and_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-LABEL: atomicrmw_and_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acquire %1 = atomicrmw and i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_release: ; RV32I-LABEL: atomicrmw_and_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_release: ; RV32IA-LABEL: atomicrmw_and_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_release: ; RV64I-LABEL: atomicrmw_and_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_release: ; RV64IA-LABEL: atomicrmw_and_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b release %1 = atomicrmw and i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acq_rel: ; RV32I-LABEL: atomicrmw_and_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acq_rel: ; RV64I-LABEL: atomicrmw_and_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acq_rel %1 = atomicrmw and i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_seq_cst: ; RV32I-LABEL: atomicrmw_and_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_seq_cst: ; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b seq_cst %1 = atomicrmw and i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_monotonic: ; RV32I-LABEL: atomicrmw_nand_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB75_1 ; RV32IA-NEXT: bnez a5, .LBB75_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_monotonic: ; RV64I-LABEL: atomicrmw_nand_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b monotonic %1 = atomicrmw nand i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acquire: ; RV32I-LABEL: atomicrmw_nand_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acquire: ; RV32IA-LABEL: atomicrmw_nand_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB76_1 ; RV32IA-NEXT: bnez a5, .LBB76_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acquire: ; RV64I-LABEL: atomicrmw_nand_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-LABEL: atomicrmw_nand_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acquire %1 = atomicrmw nand i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_release: ; RV32I-LABEL: atomicrmw_nand_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_release: ; RV32IA-LABEL: atomicrmw_nand_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB77_1 ; RV32IA-NEXT: bnez a5, .LBB77_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_release: ; RV64I-LABEL: atomicrmw_nand_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_release: ; RV64IA-LABEL: atomicrmw_nand_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b release %1 = atomicrmw nand i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB78_1 ; RV32IA-NEXT: bnez a5, .LBB78_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acq_rel %1 = atomicrmw nand i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB79_1 ; RV32IA-NEXT: bnez a5, .LBB79_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b seq_cst %1 = atomicrmw nand i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_monotonic: ; RV32I-LABEL: atomicrmw_or_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_monotonic: ; RV32IA-LABEL: atomicrmw_or_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2) ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_monotonic: ; RV64I-LABEL: atomicrmw_or_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2) ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b monotonic %1 = atomicrmw or i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acquire: ; RV32I-LABEL: atomicrmw_or_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acquire: ; RV32IA-LABEL: atomicrmw_or_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acquire: ; RV64I-LABEL: atomicrmw_or_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-LABEL: atomicrmw_or_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acquire %1 = atomicrmw or i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_release: ; RV32I-LABEL: atomicrmw_or_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_release: ; RV32IA-LABEL: atomicrmw_or_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_release: ; RV64I-LABEL: atomicrmw_or_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_release: ; RV64IA-LABEL: atomicrmw_or_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b release %1 = atomicrmw or i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acq_rel: ; RV32I-LABEL: atomicrmw_or_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acq_rel: ; RV64I-LABEL: atomicrmw_or_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acq_rel %1 = atomicrmw or i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_seq_cst: ; RV32I-LABEL: atomicrmw_or_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_seq_cst: ; RV64I-LABEL: atomicrmw_or_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b seq_cst %1 = atomicrmw or i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_monotonic: ; RV32I-LABEL: atomicrmw_xor_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2) ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_monotonic: ; RV64I-LABEL: atomicrmw_xor_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2) ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b monotonic %1 = atomicrmw xor i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acquire: ; RV32I-LABEL: atomicrmw_xor_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acquire: ; RV32IA-LABEL: atomicrmw_xor_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acquire: ; RV64I-LABEL: atomicrmw_xor_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acquire %1 = atomicrmw xor i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_release: ; RV32I-LABEL: atomicrmw_xor_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_release: ; RV32IA-LABEL: atomicrmw_xor_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_release: ; RV64I-LABEL: atomicrmw_xor_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_release: ; RV64IA-LABEL: atomicrmw_xor_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b release %1 = atomicrmw xor i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acq_rel %1 = atomicrmw xor i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b seq_cst %1 = atomicrmw xor i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_monotonic: ; RV32I-LABEL: atomicrmw_max_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB90_2 ; RV32I-NEXT: j .LBB90_2
; RV32I-NEXT: .LBB90_1: # %atomicrmw.start ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB90_4 ; RV32I-NEXT: bnez a0, .LBB90_4
; RV32I-NEXT: .LBB90_2: # %atomicrmw.start ; RV32I-NEXT: .LBB90_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB90_1 ; RV32I-NEXT: blt s1, a0, .LBB90_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB90_1 ; RV32I-NEXT: j .LBB90_1
; RV32I-NEXT: .LBB90_4: # %atomicrmw.end ; RV32I-NEXT: .LBB90_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB90_1 ; RV32IA-NEXT: bnez a2, .LBB90_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB90_2 ; RV64I-NEXT: j .LBB90_2
; RV64I-NEXT: .LBB90_1: # %atomicrmw.start ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB90_4 ; RV64I-NEXT: bnez a0, .LBB90_4
; RV64I-NEXT: .LBB90_2: # %atomicrmw.start ; RV64I-NEXT: .LBB90_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB90_1 ; RV64I-NEXT: blt s1, a0, .LBB90_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB90_1 ; RV64I-NEXT: j .LBB90_1
; RV64I-NEXT: .LBB90_4: # %atomicrmw.end ; RV64I-NEXT: .LBB90_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b monotonic %1 = atomicrmw max i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acquire: ; RV32I-LABEL: atomicrmw_max_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB91_2 ; RV32I-NEXT: j .LBB91_2
; RV32I-NEXT: .LBB91_1: # %atomicrmw.start ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB91_4 ; RV32I-NEXT: bnez a0, .LBB91_4
; RV32I-NEXT: .LBB91_2: # %atomicrmw.start ; RV32I-NEXT: .LBB91_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB91_1 ; RV32I-NEXT: blt s1, a0, .LBB91_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB91_1 ; RV32I-NEXT: j .LBB91_1
; RV32I-NEXT: .LBB91_4: # %atomicrmw.end ; RV32I-NEXT: .LBB91_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acquire: ; RV32IA-LABEL: atomicrmw_max_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB91_1 ; RV32IA-NEXT: bnez a2, .LBB91_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acquire: ; RV64I-LABEL: atomicrmw_max_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB91_2 ; RV64I-NEXT: j .LBB91_2
; RV64I-NEXT: .LBB91_1: # %atomicrmw.start ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB91_4 ; RV64I-NEXT: bnez a0, .LBB91_4
; RV64I-NEXT: .LBB91_2: # %atomicrmw.start ; RV64I-NEXT: .LBB91_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB91_1 ; RV64I-NEXT: blt s1, a0, .LBB91_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB91_1 ; RV64I-NEXT: j .LBB91_1
; RV64I-NEXT: .LBB91_4: # %atomicrmw.end ; RV64I-NEXT: .LBB91_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-LABEL: atomicrmw_max_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acquire %1 = atomicrmw max i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_release: ; RV32I-LABEL: atomicrmw_max_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB92_2 ; RV32I-NEXT: j .LBB92_2
; RV32I-NEXT: .LBB92_1: # %atomicrmw.start ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB92_4 ; RV32I-NEXT: bnez a0, .LBB92_4
; RV32I-NEXT: .LBB92_2: # %atomicrmw.start ; RV32I-NEXT: .LBB92_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB92_1 ; RV32I-NEXT: blt s1, a0, .LBB92_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB92_1 ; RV32I-NEXT: j .LBB92_1
; RV32I-NEXT: .LBB92_4: # %atomicrmw.end ; RV32I-NEXT: .LBB92_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_release: ; RV32IA-LABEL: atomicrmw_max_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB92_1 ; RV32IA-NEXT: bnez a2, .LBB92_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_release: ; RV64I-LABEL: atomicrmw_max_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB92_2 ; RV64I-NEXT: j .LBB92_2
; RV64I-NEXT: .LBB92_1: # %atomicrmw.start ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB92_4 ; RV64I-NEXT: bnez a0, .LBB92_4
; RV64I-NEXT: .LBB92_2: # %atomicrmw.start ; RV64I-NEXT: .LBB92_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB92_1 ; RV64I-NEXT: blt s1, a0, .LBB92_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB92_1 ; RV64I-NEXT: j .LBB92_1
; RV64I-NEXT: .LBB92_4: # %atomicrmw.end ; RV64I-NEXT: .LBB92_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_release: ; RV64IA-LABEL: atomicrmw_max_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b release %1 = atomicrmw max i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acq_rel: ; RV32I-LABEL: atomicrmw_max_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB93_2 ; RV32I-NEXT: j .LBB93_2
; RV32I-NEXT: .LBB93_1: # %atomicrmw.start ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB93_4 ; RV32I-NEXT: bnez a0, .LBB93_4
; RV32I-NEXT: .LBB93_2: # %atomicrmw.start ; RV32I-NEXT: .LBB93_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB93_1 ; RV32I-NEXT: blt s1, a0, .LBB93_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB93_1 ; RV32I-NEXT: j .LBB93_1
; RV32I-NEXT: .LBB93_4: # %atomicrmw.end ; RV32I-NEXT: .LBB93_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB93_1 ; RV32IA-NEXT: bnez a2, .LBB93_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acq_rel: ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB93_2 ; RV64I-NEXT: j .LBB93_2
; RV64I-NEXT: .LBB93_1: # %atomicrmw.start ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB93_4 ; RV64I-NEXT: bnez a0, .LBB93_4
; RV64I-NEXT: .LBB93_2: # %atomicrmw.start ; RV64I-NEXT: .LBB93_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB93_1 ; RV64I-NEXT: blt s1, a0, .LBB93_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB93_1 ; RV64I-NEXT: j .LBB93_1
; RV64I-NEXT: .LBB93_4: # %atomicrmw.end ; RV64I-NEXT: .LBB93_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acq_rel %1 = atomicrmw max i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_seq_cst: ; RV32I-LABEL: atomicrmw_max_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB94_2 ; RV32I-NEXT: j .LBB94_2
; RV32I-NEXT: .LBB94_1: # %atomicrmw.start ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB94_4 ; RV32I-NEXT: bnez a0, .LBB94_4
; RV32I-NEXT: .LBB94_2: # %atomicrmw.start ; RV32I-NEXT: .LBB94_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB94_1 ; RV32I-NEXT: blt s1, a0, .LBB94_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB94_1 ; RV32I-NEXT: j .LBB94_1
; RV32I-NEXT: .LBB94_4: # %atomicrmw.end ; RV32I-NEXT: .LBB94_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB94_1 ; RV32IA-NEXT: bnez a2, .LBB94_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB94_2 ; RV64I-NEXT: j .LBB94_2
; RV64I-NEXT: .LBB94_1: # %atomicrmw.start ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB94_4 ; RV64I-NEXT: bnez a0, .LBB94_4
; RV64I-NEXT: .LBB94_2: # %atomicrmw.start ; RV64I-NEXT: .LBB94_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB94_1 ; RV64I-NEXT: blt s1, a0, .LBB94_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB94_1 ; RV64I-NEXT: j .LBB94_1
; RV64I-NEXT: .LBB94_4: # %atomicrmw.end ; RV64I-NEXT: .LBB94_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b seq_cst %1 = atomicrmw max i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic: ; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB95_2 ; RV32I-NEXT: j .LBB95_2
; RV32I-NEXT: .LBB95_1: # %atomicrmw.start ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB95_4 ; RV32I-NEXT: bnez a0, .LBB95_4
; RV32I-NEXT: .LBB95_2: # %atomicrmw.start ; RV32I-NEXT: .LBB95_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB95_1 ; RV32I-NEXT: bge s1, a0, .LBB95_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: j .LBB95_1
; RV32I-NEXT: .LBB95_4: # %atomicrmw.end ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB95_1 ; RV32IA-NEXT: bnez a2, .LBB95_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB95_2 ; RV64I-NEXT: j .LBB95_2
; RV64I-NEXT: .LBB95_1: # %atomicrmw.start ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB95_4 ; RV64I-NEXT: bnez a0, .LBB95_4
; RV64I-NEXT: .LBB95_2: # %atomicrmw.start ; RV64I-NEXT: .LBB95_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB95_1 ; RV64I-NEXT: bge s1, a0, .LBB95_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: j .LBB95_1
; RV64I-NEXT: .LBB95_4: # %atomicrmw.end ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b monotonic %1 = atomicrmw min i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acquire: ; RV32I-LABEL: atomicrmw_min_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB96_2 ; RV32I-NEXT: j .LBB96_2
; RV32I-NEXT: .LBB96_1: # %atomicrmw.start ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB96_4 ; RV32I-NEXT: bnez a0, .LBB96_4
; RV32I-NEXT: .LBB96_2: # %atomicrmw.start ; RV32I-NEXT: .LBB96_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB96_1 ; RV32I-NEXT: bge s1, a0, .LBB96_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: j .LBB96_1
; RV32I-NEXT: .LBB96_4: # %atomicrmw.end ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acquire: ; RV32IA-LABEL: atomicrmw_min_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB96_1 ; RV32IA-NEXT: bnez a2, .LBB96_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acquire: ; RV64I-LABEL: atomicrmw_min_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB96_2 ; RV64I-NEXT: j .LBB96_2
; RV64I-NEXT: .LBB96_1: # %atomicrmw.start ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB96_4 ; RV64I-NEXT: bnez a0, .LBB96_4
; RV64I-NEXT: .LBB96_2: # %atomicrmw.start ; RV64I-NEXT: .LBB96_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB96_1 ; RV64I-NEXT: bge s1, a0, .LBB96_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: j .LBB96_1
; RV64I-NEXT: .LBB96_4: # %atomicrmw.end ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-LABEL: atomicrmw_min_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acquire %1 = atomicrmw min i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_release: ; RV32I-LABEL: atomicrmw_min_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB97_2 ; RV32I-NEXT: j .LBB97_2
; RV32I-NEXT: .LBB97_1: # %atomicrmw.start ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB97_4 ; RV32I-NEXT: bnez a0, .LBB97_4
; RV32I-NEXT: .LBB97_2: # %atomicrmw.start ; RV32I-NEXT: .LBB97_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB97_1 ; RV32I-NEXT: bge s1, a0, .LBB97_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: j .LBB97_1
; RV32I-NEXT: .LBB97_4: # %atomicrmw.end ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_release: ; RV32IA-LABEL: atomicrmw_min_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB97_1 ; RV32IA-NEXT: bnez a2, .LBB97_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_release: ; RV64I-LABEL: atomicrmw_min_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB97_2 ; RV64I-NEXT: j .LBB97_2
; RV64I-NEXT: .LBB97_1: # %atomicrmw.start ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB97_4 ; RV64I-NEXT: bnez a0, .LBB97_4
; RV64I-NEXT: .LBB97_2: # %atomicrmw.start ; RV64I-NEXT: .LBB97_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB97_1 ; RV64I-NEXT: bge s1, a0, .LBB97_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: j .LBB97_1
; RV64I-NEXT: .LBB97_4: # %atomicrmw.end ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_release: ; RV64IA-LABEL: atomicrmw_min_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b release %1 = atomicrmw min i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acq_rel: ; RV32I-LABEL: atomicrmw_min_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB98_2 ; RV32I-NEXT: j .LBB98_2
; RV32I-NEXT: .LBB98_1: # %atomicrmw.start ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB98_4 ; RV32I-NEXT: bnez a0, .LBB98_4
; RV32I-NEXT: .LBB98_2: # %atomicrmw.start ; RV32I-NEXT: .LBB98_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB98_1 ; RV32I-NEXT: bge s1, a0, .LBB98_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: j .LBB98_1
; RV32I-NEXT: .LBB98_4: # %atomicrmw.end ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB98_1 ; RV32IA-NEXT: bnez a2, .LBB98_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acq_rel: ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB98_2 ; RV64I-NEXT: j .LBB98_2
; RV64I-NEXT: .LBB98_1: # %atomicrmw.start ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB98_4 ; RV64I-NEXT: bnez a0, .LBB98_4
; RV64I-NEXT: .LBB98_2: # %atomicrmw.start ; RV64I-NEXT: .LBB98_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB98_1 ; RV64I-NEXT: bge s1, a0, .LBB98_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: j .LBB98_1
; RV64I-NEXT: .LBB98_4: # %atomicrmw.end ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acq_rel %1 = atomicrmw min i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_seq_cst: ; RV32I-LABEL: atomicrmw_min_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB99_2 ; RV32I-NEXT: j .LBB99_2
; RV32I-NEXT: .LBB99_1: # %atomicrmw.start ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB99_4 ; RV32I-NEXT: bnez a0, .LBB99_4
; RV32I-NEXT: .LBB99_2: # %atomicrmw.start ; RV32I-NEXT: .LBB99_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB99_1 ; RV32I-NEXT: bge s1, a0, .LBB99_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: j .LBB99_1
; RV32I-NEXT: .LBB99_4: # %atomicrmw.end ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB99_1 ; RV32IA-NEXT: bnez a2, .LBB99_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB99_2 ; RV64I-NEXT: j .LBB99_2
; RV64I-NEXT: .LBB99_1: # %atomicrmw.start ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB99_4 ; RV64I-NEXT: bnez a0, .LBB99_4
; RV64I-NEXT: .LBB99_2: # %atomicrmw.start ; RV64I-NEXT: .LBB99_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB99_1 ; RV64I-NEXT: bge s1, a0, .LBB99_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: j .LBB99_1
; RV64I-NEXT: .LBB99_4: # %atomicrmw.end ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b seq_cst %1 = atomicrmw min i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_monotonic: ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: j .LBB100_2
; RV32I-NEXT: .LBB100_1: # %atomicrmw.start ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB100_4 ; RV32I-NEXT: bnez a0, .LBB100_4
; RV32I-NEXT: .LBB100_2: # %atomicrmw.start ; RV32I-NEXT: .LBB100_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB100_1 ; RV32I-NEXT: bltu s1, a0, .LBB100_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB100_1 ; RV32I-NEXT: j .LBB100_1
; RV32I-NEXT: .LBB100_4: # %atomicrmw.end ; RV32I-NEXT: .LBB100_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB100_1 ; RV32IA-NEXT: bnez a5, .LBB100_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: j .LBB100_2
; RV64I-NEXT: .LBB100_1: # %atomicrmw.start ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB100_4 ; RV64I-NEXT: bnez a0, .LBB100_4
; RV64I-NEXT: .LBB100_2: # %atomicrmw.start ; RV64I-NEXT: .LBB100_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB100_1 ; RV64I-NEXT: bltu s1, a0, .LBB100_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB100_1 ; RV64I-NEXT: j .LBB100_1
; RV64I-NEXT: .LBB100_4: # %atomicrmw.end ; RV64I-NEXT: .LBB100_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b monotonic %1 = atomicrmw umax i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acquire: ; RV32I-LABEL: atomicrmw_umax_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: j .LBB101_2
; RV32I-NEXT: .LBB101_1: # %atomicrmw.start ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB101_4 ; RV32I-NEXT: bnez a0, .LBB101_4
; RV32I-NEXT: .LBB101_2: # %atomicrmw.start ; RV32I-NEXT: .LBB101_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB101_1 ; RV32I-NEXT: bltu s1, a0, .LBB101_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB101_1 ; RV32I-NEXT: j .LBB101_1
; RV32I-NEXT: .LBB101_4: # %atomicrmw.end ; RV32I-NEXT: .LBB101_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA-LABEL: atomicrmw_umax_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB101_1 ; RV32IA-NEXT: bnez a5, .LBB101_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acquire: ; RV64I-LABEL: atomicrmw_umax_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: j .LBB101_2
; RV64I-NEXT: .LBB101_1: # %atomicrmw.start ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB101_4 ; RV64I-NEXT: bnez a0, .LBB101_4
; RV64I-NEXT: .LBB101_2: # %atomicrmw.start ; RV64I-NEXT: .LBB101_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB101_1 ; RV64I-NEXT: bltu s1, a0, .LBB101_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB101_1 ; RV64I-NEXT: j .LBB101_1
; RV64I-NEXT: .LBB101_4: # %atomicrmw.end ; RV64I-NEXT: .LBB101_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acquire %1 = atomicrmw umax i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_release: ; RV32I-LABEL: atomicrmw_umax_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: j .LBB102_2
; RV32I-NEXT: .LBB102_1: # %atomicrmw.start ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB102_4 ; RV32I-NEXT: bnez a0, .LBB102_4
; RV32I-NEXT: .LBB102_2: # %atomicrmw.start ; RV32I-NEXT: .LBB102_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB102_1 ; RV32I-NEXT: bltu s1, a0, .LBB102_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB102_1 ; RV32I-NEXT: j .LBB102_1
; RV32I-NEXT: .LBB102_4: # %atomicrmw.end ; RV32I-NEXT: .LBB102_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_release: ; RV32IA-LABEL: atomicrmw_umax_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB102_1 ; RV32IA-NEXT: bnez a5, .LBB102_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_release: ; RV64I-LABEL: atomicrmw_umax_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: j .LBB102_2
; RV64I-NEXT: .LBB102_1: # %atomicrmw.start ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB102_4 ; RV64I-NEXT: bnez a0, .LBB102_4
; RV64I-NEXT: .LBB102_2: # %atomicrmw.start ; RV64I-NEXT: .LBB102_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB102_1 ; RV64I-NEXT: bltu s1, a0, .LBB102_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB102_1 ; RV64I-NEXT: j .LBB102_1
; RV64I-NEXT: .LBB102_4: # %atomicrmw.end ; RV64I-NEXT: .LBB102_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_release: ; RV64IA-LABEL: atomicrmw_umax_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b release %1 = atomicrmw umax i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: j .LBB103_2
; RV32I-NEXT: .LBB103_1: # %atomicrmw.start ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB103_4 ; RV32I-NEXT: bnez a0, .LBB103_4
; RV32I-NEXT: .LBB103_2: # %atomicrmw.start ; RV32I-NEXT: .LBB103_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB103_1 ; RV32I-NEXT: bltu s1, a0, .LBB103_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB103_1 ; RV32I-NEXT: j .LBB103_1
; RV32I-NEXT: .LBB103_4: # %atomicrmw.end ; RV32I-NEXT: .LBB103_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB103_1 ; RV32IA-NEXT: bnez a5, .LBB103_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: j .LBB103_2
; RV64I-NEXT: .LBB103_1: # %atomicrmw.start ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB103_4 ; RV64I-NEXT: bnez a0, .LBB103_4
; RV64I-NEXT: .LBB103_2: # %atomicrmw.start ; RV64I-NEXT: .LBB103_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB103_1 ; RV64I-NEXT: bltu s1, a0, .LBB103_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB103_1 ; RV64I-NEXT: j .LBB103_1
; RV64I-NEXT: .LBB103_4: # %atomicrmw.end ; RV64I-NEXT: .LBB103_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acq_rel %1 = atomicrmw umax i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: j .LBB104_2
; RV32I-NEXT: .LBB104_1: # %atomicrmw.start ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB104_4 ; RV32I-NEXT: bnez a0, .LBB104_4
; RV32I-NEXT: .LBB104_2: # %atomicrmw.start ; RV32I-NEXT: .LBB104_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB104_1 ; RV32I-NEXT: bltu s1, a0, .LBB104_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB104_1 ; RV32I-NEXT: j .LBB104_1
; RV32I-NEXT: .LBB104_4: # %atomicrmw.end ; RV32I-NEXT: .LBB104_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: bnez a5, .LBB104_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: j .LBB104_2
; RV64I-NEXT: .LBB104_1: # %atomicrmw.start ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB104_4 ; RV64I-NEXT: bnez a0, .LBB104_4
; RV64I-NEXT: .LBB104_2: # %atomicrmw.start ; RV64I-NEXT: .LBB104_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB104_1 ; RV64I-NEXT: bltu s1, a0, .LBB104_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB104_1 ; RV64I-NEXT: j .LBB104_1
; RV64I-NEXT: .LBB104_4: # %atomicrmw.end ; RV64I-NEXT: .LBB104_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b seq_cst %1 = atomicrmw umax i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_monotonic: ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: j .LBB105_2
; RV32I-NEXT: .LBB105_1: # %atomicrmw.start ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB105_4 ; RV32I-NEXT: bnez a0, .LBB105_4
; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB105_1 ; RV32I-NEXT: bgeu s1, a0, .LBB105_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: j .LBB105_1
; RV32I-NEXT: .LBB105_4: # %atomicrmw.end ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB105_1 ; RV32IA-NEXT: bnez a5, .LBB105_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: j .LBB105_2
; RV64I-NEXT: .LBB105_1: # %atomicrmw.start ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB105_4 ; RV64I-NEXT: bnez a0, .LBB105_4
; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB105_1 ; RV64I-NEXT: bgeu s1, a0, .LBB105_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: j .LBB105_1
; RV64I-NEXT: .LBB105_4: # %atomicrmw.end ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b monotonic %1 = atomicrmw umin i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acquire: ; RV32I-LABEL: atomicrmw_umin_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: j .LBB106_2
; RV32I-NEXT: .LBB106_1: # %atomicrmw.start ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB106_4 ; RV32I-NEXT: bnez a0, .LBB106_4
; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB106_1 ; RV32I-NEXT: bgeu s1, a0, .LBB106_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: j .LBB106_1
; RV32I-NEXT: .LBB106_4: # %atomicrmw.end ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA-LABEL: atomicrmw_umin_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB106_1 ; RV32IA-NEXT: bnez a5, .LBB106_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acquire: ; RV64I-LABEL: atomicrmw_umin_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: j .LBB106_2
; RV64I-NEXT: .LBB106_1: # %atomicrmw.start ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB106_4 ; RV64I-NEXT: bnez a0, .LBB106_4
; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB106_1 ; RV64I-NEXT: bgeu s1, a0, .LBB106_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: j .LBB106_1
; RV64I-NEXT: .LBB106_4: # %atomicrmw.end ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acquire %1 = atomicrmw umin i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_release: ; RV32I-LABEL: atomicrmw_umin_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: j .LBB107_2
; RV32I-NEXT: .LBB107_1: # %atomicrmw.start ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB107_4 ; RV32I-NEXT: bnez a0, .LBB107_4
; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB107_1 ; RV32I-NEXT: bgeu s1, a0, .LBB107_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: j .LBB107_1
; RV32I-NEXT: .LBB107_4: # %atomicrmw.end ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_release: ; RV32IA-LABEL: atomicrmw_umin_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB107_1 ; RV32IA-NEXT: bnez a5, .LBB107_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_release: ; RV64I-LABEL: atomicrmw_umin_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: j .LBB107_2
; RV64I-NEXT: .LBB107_1: # %atomicrmw.start ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB107_4 ; RV64I-NEXT: bnez a0, .LBB107_4
; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB107_1 ; RV64I-NEXT: bgeu s1, a0, .LBB107_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: j .LBB107_1
; RV64I-NEXT: .LBB107_4: # %atomicrmw.end ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_release: ; RV64IA-LABEL: atomicrmw_umin_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b release %1 = atomicrmw umin i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: j .LBB108_2
; RV32I-NEXT: .LBB108_1: # %atomicrmw.start ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB108_4 ; RV32I-NEXT: bnez a0, .LBB108_4
; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB108_1 ; RV32I-NEXT: bgeu s1, a0, .LBB108_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: j .LBB108_1
; RV32I-NEXT: .LBB108_4: # %atomicrmw.end ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB108_1 ; RV32IA-NEXT: bnez a5, .LBB108_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: j .LBB108_2
; RV64I-NEXT: .LBB108_1: # %atomicrmw.start ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB108_4 ; RV64I-NEXT: bnez a0, .LBB108_4
; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB108_1 ; RV64I-NEXT: bgeu s1, a0, .LBB108_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: j .LBB108_1
; RV64I-NEXT: .LBB108_4: # %atomicrmw.end ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acq_rel %1 = atomicrmw umin i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: j .LBB109_2
; RV32I-NEXT: .LBB109_1: # %atomicrmw.start ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB109_4 ; RV32I-NEXT: bnez a0, .LBB109_4
; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB109_1 ; RV32I-NEXT: bgeu s1, a0, .LBB109_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: j .LBB109_1
; RV32I-NEXT: .LBB109_4: # %atomicrmw.end ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: bnez a5, .LBB109_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: j .LBB109_2
; RV64I-NEXT: .LBB109_1: # %atomicrmw.start ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB109_4 ; RV64I-NEXT: bnez a0, .LBB109_4
; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB109_1 ; RV64I-NEXT: bgeu s1, a0, .LBB109_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: j .LBB109_1
; RV64I-NEXT: .LBB109_4: # %atomicrmw.end ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b seq_cst %1 = atomicrmw umin i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w a0, a1, (a0) ; RV32IA-NEXT: amoswap.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w a0, a1, (a0) ; RV64IA-NEXT: amoswap.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b monotonic %1 = atomicrmw xchg i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_acquire: ; RV32I-LABEL: atomicrmw_xchg_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_acquire: ; RV64I-LABEL: atomicrmw_xchg_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b acquire %1 = atomicrmw xchg i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_release: ; RV32I-LABEL: atomicrmw_xchg_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_release: ; RV32IA-LABEL: atomicrmw_xchg_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_release: ; RV64I-LABEL: atomicrmw_xchg_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_release: ; RV64IA-LABEL: atomicrmw_xchg_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b release %1 = atomicrmw xchg i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b acq_rel %1 = atomicrmw xchg i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b seq_cst %1 = atomicrmw xchg i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_monotonic: ; RV32I-LABEL: atomicrmw_add_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_monotonic: ; RV32IA-LABEL: atomicrmw_add_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_monotonic: ; RV64I-LABEL: atomicrmw_add_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_monotonic: ; RV64IA-LABEL: atomicrmw_add_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b monotonic %1 = atomicrmw add i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_acquire: ; RV32I-LABEL: atomicrmw_add_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_acquire: ; RV32IA-LABEL: atomicrmw_add_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_acquire: ; RV64I-LABEL: atomicrmw_add_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_acquire: ; RV64IA-LABEL: atomicrmw_add_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b acquire %1 = atomicrmw add i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_release: ; RV32I-LABEL: atomicrmw_add_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_release: ; RV32IA-LABEL: atomicrmw_add_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_release: ; RV64I-LABEL: atomicrmw_add_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_release: ; RV64IA-LABEL: atomicrmw_add_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b release %1 = atomicrmw add i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_acq_rel: ; RV32I-LABEL: atomicrmw_add_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_acq_rel: ; RV64I-LABEL: atomicrmw_add_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b acq_rel %1 = atomicrmw add i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_seq_cst: ; RV32I-LABEL: atomicrmw_add_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_seq_cst: ; RV64I-LABEL: atomicrmw_add_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b seq_cst %1 = atomicrmw add i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_monotonic: ; RV32I-LABEL: atomicrmw_sub_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_monotonic: ; RV64I-LABEL: atomicrmw_sub_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b monotonic %1 = atomicrmw sub i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_acquire: ; RV32I-LABEL: atomicrmw_sub_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_acquire: ; RV32IA-LABEL: atomicrmw_sub_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_acquire: ; RV64I-LABEL: atomicrmw_sub_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_acquire: ; RV64IA-LABEL: atomicrmw_sub_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b acquire %1 = atomicrmw sub i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_release: ; RV32I-LABEL: atomicrmw_sub_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_release: ; RV32IA-LABEL: atomicrmw_sub_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_release: ; RV64I-LABEL: atomicrmw_sub_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_release: ; RV64IA-LABEL: atomicrmw_sub_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b release %1 = atomicrmw sub i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b acq_rel %1 = atomicrmw sub i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b seq_cst %1 = atomicrmw sub i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_monotonic: ; RV32I-LABEL: atomicrmw_and_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_monotonic: ; RV32IA-LABEL: atomicrmw_and_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w a0, a1, (a0) ; RV32IA-NEXT: amoand.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_monotonic: ; RV64I-LABEL: atomicrmw_and_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_monotonic: ; RV64IA-LABEL: atomicrmw_and_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w a0, a1, (a0) ; RV64IA-NEXT: amoand.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b monotonic %1 = atomicrmw and i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_acquire: ; RV32I-LABEL: atomicrmw_and_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_acquire: ; RV32IA-LABEL: atomicrmw_and_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_acquire: ; RV64I-LABEL: atomicrmw_and_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_acquire: ; RV64IA-LABEL: atomicrmw_and_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b acquire %1 = atomicrmw and i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_release: ; RV32I-LABEL: atomicrmw_and_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_release: ; RV32IA-LABEL: atomicrmw_and_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_release: ; RV64I-LABEL: atomicrmw_and_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_release: ; RV64IA-LABEL: atomicrmw_and_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b release %1 = atomicrmw and i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_acq_rel: ; RV32I-LABEL: atomicrmw_and_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_acq_rel: ; RV64I-LABEL: atomicrmw_and_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b acq_rel %1 = atomicrmw and i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_seq_cst: ; RV32I-LABEL: atomicrmw_and_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_seq_cst: ; RV64I-LABEL: atomicrmw_and_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b seq_cst %1 = atomicrmw and i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_monotonic: ; RV32I-LABEL: atomicrmw_nand_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a0) ; RV32IA-NEXT: lr.w a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB130_1 ; RV32IA-NEXT: bnez a3, .LBB130_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_monotonic: ; RV64I-LABEL: atomicrmw_nand_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a0) ; RV64IA-NEXT: lr.w a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB130_1 ; RV64IA-NEXT: bnez a3, .LBB130_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b monotonic %1 = atomicrmw nand i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_acquire: ; RV32I-LABEL: atomicrmw_nand_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_acquire: ; RV32IA-LABEL: atomicrmw_nand_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB131_1 ; RV32IA-NEXT: bnez a3, .LBB131_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_acquire: ; RV64I-LABEL: atomicrmw_nand_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_acquire: ; RV64IA-LABEL: atomicrmw_nand_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB131_1 ; RV64IA-NEXT: bnez a3, .LBB131_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b acquire %1 = atomicrmw nand i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_release: ; RV32I-LABEL: atomicrmw_nand_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_release: ; RV32IA-LABEL: atomicrmw_nand_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a0) ; RV32IA-NEXT: lr.w a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB132_1 ; RV32IA-NEXT: bnez a3, .LBB132_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_release: ; RV64I-LABEL: atomicrmw_nand_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_release: ; RV64IA-LABEL: atomicrmw_nand_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a0) ; RV64IA-NEXT: lr.w a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB132_1 ; RV64IA-NEXT: bnez a3, .LBB132_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b release %1 = atomicrmw nand i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB133_1 ; RV32IA-NEXT: bnez a3, .LBB133_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB133_1 ; RV64IA-NEXT: bnez a3, .LBB133_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b acq_rel %1 = atomicrmw nand i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB134_1 ; RV32IA-NEXT: bnez a3, .LBB134_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB134_1 ; RV64IA-NEXT: bnez a3, .LBB134_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b seq_cst %1 = atomicrmw nand i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_monotonic: ; RV32I-LABEL: atomicrmw_or_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_monotonic: ; RV32IA-LABEL: atomicrmw_or_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w a0, a1, (a0) ; RV32IA-NEXT: amoor.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_monotonic: ; RV64I-LABEL: atomicrmw_or_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_monotonic: ; RV64IA-LABEL: atomicrmw_or_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w a0, a1, (a0) ; RV64IA-NEXT: amoor.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b monotonic %1 = atomicrmw or i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_acquire: ; RV32I-LABEL: atomicrmw_or_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_acquire: ; RV32IA-LABEL: atomicrmw_or_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_acquire: ; RV64I-LABEL: atomicrmw_or_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_acquire: ; RV64IA-LABEL: atomicrmw_or_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b acquire %1 = atomicrmw or i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_release: ; RV32I-LABEL: atomicrmw_or_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_release: ; RV32IA-LABEL: atomicrmw_or_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_release: ; RV64I-LABEL: atomicrmw_or_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_release: ; RV64IA-LABEL: atomicrmw_or_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b release %1 = atomicrmw or i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_acq_rel: ; RV32I-LABEL: atomicrmw_or_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_acq_rel: ; RV64I-LABEL: atomicrmw_or_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b acq_rel %1 = atomicrmw or i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_seq_cst: ; RV32I-LABEL: atomicrmw_or_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_seq_cst: ; RV64I-LABEL: atomicrmw_or_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b seq_cst %1 = atomicrmw or i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_monotonic: ; RV32I-LABEL: atomicrmw_xor_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w a0, a1, (a0) ; RV32IA-NEXT: amoxor.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_monotonic: ; RV64I-LABEL: atomicrmw_xor_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w a0, a1, (a0) ; RV64IA-NEXT: amoxor.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b monotonic %1 = atomicrmw xor i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_acquire: ; RV32I-LABEL: atomicrmw_xor_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_acquire: ; RV32IA-LABEL: atomicrmw_xor_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_acquire: ; RV64I-LABEL: atomicrmw_xor_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_acquire: ; RV64IA-LABEL: atomicrmw_xor_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b acquire %1 = atomicrmw xor i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_release: ; RV32I-LABEL: atomicrmw_xor_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_release: ; RV32IA-LABEL: atomicrmw_xor_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_release: ; RV64I-LABEL: atomicrmw_xor_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_release: ; RV64IA-LABEL: atomicrmw_xor_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b release %1 = atomicrmw xor i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b acq_rel %1 = atomicrmw xor i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b seq_cst %1 = atomicrmw xor i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_monotonic: ; RV32I-LABEL: atomicrmw_max_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB145_2 ; RV32I-NEXT: j .LBB145_2
; RV32I-NEXT: .LBB145_1: # %atomicrmw.start ; RV32I-NEXT: .LBB145_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB145_4 ; RV32I-NEXT: bnez a0, .LBB145_4
; RV32I-NEXT: .LBB145_2: # %atomicrmw.start ; RV32I-NEXT: .LBB145_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB145_1 ; RV32I-NEXT: blt s1, a3, .LBB145_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB145_1 ; RV32I-NEXT: j .LBB145_1
; RV32I-NEXT: .LBB145_4: # %atomicrmw.end ; RV32I-NEXT: .LBB145_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_monotonic: ; RV32IA-LABEL: atomicrmw_max_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w a0, a1, (a0) ; RV32IA-NEXT: amomax.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB145_4 ; RV64I-NEXT: bnez a0, .LBB145_4
; RV64I-NEXT: .LBB145_2: # %atomicrmw.start ; RV64I-NEXT: .LBB145_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB145_1 ; RV64I-NEXT: blt s1, a0, .LBB145_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB145_1 ; RV64I-NEXT: j .LBB145_1
; RV64I-NEXT: .LBB145_4: # %atomicrmw.end ; RV64I-NEXT: .LBB145_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic: ; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w a0, a1, (a0) ; RV64IA-NEXT: amomax.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b monotonic %1 = atomicrmw max i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acquire: ; RV32I-LABEL: atomicrmw_max_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB146_2 ; RV32I-NEXT: j .LBB146_2
; RV32I-NEXT: .LBB146_1: # %atomicrmw.start ; RV32I-NEXT: .LBB146_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB146_4 ; RV32I-NEXT: bnez a0, .LBB146_4
; RV32I-NEXT: .LBB146_2: # %atomicrmw.start ; RV32I-NEXT: .LBB146_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB146_1 ; RV32I-NEXT: blt s1, a3, .LBB146_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB146_1 ; RV32I-NEXT: j .LBB146_1
; RV32I-NEXT: .LBB146_4: # %atomicrmw.end ; RV32I-NEXT: .LBB146_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acquire: ; RV32IA-LABEL: atomicrmw_max_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acquire: ; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB146_4 ; RV64I-NEXT: bnez a0, .LBB146_4
; RV64I-NEXT: .LBB146_2: # %atomicrmw.start ; RV64I-NEXT: .LBB146_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB146_1 ; RV64I-NEXT: blt s1, a0, .LBB146_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB146_1 ; RV64I-NEXT: j .LBB146_1
; RV64I-NEXT: .LBB146_4: # %atomicrmw.end ; RV64I-NEXT: .LBB146_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acquire: ; RV64IA-LABEL: atomicrmw_max_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acquire %1 = atomicrmw max i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_release: ; RV32I-LABEL: atomicrmw_max_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB147_2 ; RV32I-NEXT: j .LBB147_2
; RV32I-NEXT: .LBB147_1: # %atomicrmw.start ; RV32I-NEXT: .LBB147_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB147_4 ; RV32I-NEXT: bnez a0, .LBB147_4
; RV32I-NEXT: .LBB147_2: # %atomicrmw.start ; RV32I-NEXT: .LBB147_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB147_1 ; RV32I-NEXT: blt s1, a3, .LBB147_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB147_1 ; RV32I-NEXT: j .LBB147_1
; RV32I-NEXT: .LBB147_4: # %atomicrmw.end ; RV32I-NEXT: .LBB147_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_release: ; RV32IA-LABEL: atomicrmw_max_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_release: ; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB147_4 ; RV64I-NEXT: bnez a0, .LBB147_4
; RV64I-NEXT: .LBB147_2: # %atomicrmw.start ; RV64I-NEXT: .LBB147_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB147_1 ; RV64I-NEXT: blt s1, a0, .LBB147_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB147_1 ; RV64I-NEXT: j .LBB147_1
; RV64I-NEXT: .LBB147_4: # %atomicrmw.end ; RV64I-NEXT: .LBB147_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_release: ; RV64IA-LABEL: atomicrmw_max_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b release %1 = atomicrmw max i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acq_rel: ; RV32I-LABEL: atomicrmw_max_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB148_2 ; RV32I-NEXT: j .LBB148_2
; RV32I-NEXT: .LBB148_1: # %atomicrmw.start ; RV32I-NEXT: .LBB148_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB148_4 ; RV32I-NEXT: bnez a0, .LBB148_4
; RV32I-NEXT: .LBB148_2: # %atomicrmw.start ; RV32I-NEXT: .LBB148_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB148_1 ; RV32I-NEXT: blt s1, a3, .LBB148_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB148_1 ; RV32I-NEXT: j .LBB148_1
; RV32I-NEXT: .LBB148_4: # %atomicrmw.end ; RV32I-NEXT: .LBB148_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acq_rel: ; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB148_4 ; RV64I-NEXT: bnez a0, .LBB148_4
; RV64I-NEXT: .LBB148_2: # %atomicrmw.start ; RV64I-NEXT: .LBB148_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB148_1 ; RV64I-NEXT: blt s1, a0, .LBB148_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB148_1 ; RV64I-NEXT: j .LBB148_1
; RV64I-NEXT: .LBB148_4: # %atomicrmw.end ; RV64I-NEXT: .LBB148_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acq_rel %1 = atomicrmw max i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_seq_cst: ; RV32I-LABEL: atomicrmw_max_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB149_2 ; RV32I-NEXT: j .LBB149_2
; RV32I-NEXT: .LBB149_1: # %atomicrmw.start ; RV32I-NEXT: .LBB149_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB149_4 ; RV32I-NEXT: bnez a0, .LBB149_4
; RV32I-NEXT: .LBB149_2: # %atomicrmw.start ; RV32I-NEXT: .LBB149_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB149_1 ; RV32I-NEXT: blt s1, a3, .LBB149_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB149_1 ; RV32I-NEXT: j .LBB149_1
; RV32I-NEXT: .LBB149_4: # %atomicrmw.end ; RV32I-NEXT: .LBB149_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_seq_cst: ; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB149_4 ; RV64I-NEXT: bnez a0, .LBB149_4
; RV64I-NEXT: .LBB149_2: # %atomicrmw.start ; RV64I-NEXT: .LBB149_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB149_1 ; RV64I-NEXT: blt s1, a0, .LBB149_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB149_1 ; RV64I-NEXT: j .LBB149_1
; RV64I-NEXT: .LBB149_4: # %atomicrmw.end ; RV64I-NEXT: .LBB149_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b seq_cst %1 = atomicrmw max i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_monotonic: ; RV32I-LABEL: atomicrmw_min_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB150_2 ; RV32I-NEXT: j .LBB150_2
; RV32I-NEXT: .LBB150_1: # %atomicrmw.start ; RV32I-NEXT: .LBB150_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB150_4 ; RV32I-NEXT: bnez a0, .LBB150_4
; RV32I-NEXT: .LBB150_2: # %atomicrmw.start ; RV32I-NEXT: .LBB150_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB150_1 ; RV32I-NEXT: bge s1, a3, .LBB150_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB150_1 ; RV32I-NEXT: j .LBB150_1
; RV32I-NEXT: .LBB150_4: # %atomicrmw.end ; RV32I-NEXT: .LBB150_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_monotonic: ; RV32IA-LABEL: atomicrmw_min_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w a0, a1, (a0) ; RV32IA-NEXT: amomin.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB150_4 ; RV64I-NEXT: bnez a0, .LBB150_4
; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB150_1 ; RV64I-NEXT: bge s1, a0, .LBB150_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: j .LBB150_1
; RV64I-NEXT: .LBB150_4: # %atomicrmw.end ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic: ; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w a0, a1, (a0) ; RV64IA-NEXT: amomin.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b monotonic %1 = atomicrmw min i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acquire: ; RV32I-LABEL: atomicrmw_min_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB151_2 ; RV32I-NEXT: j .LBB151_2
; RV32I-NEXT: .LBB151_1: # %atomicrmw.start ; RV32I-NEXT: .LBB151_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB151_4 ; RV32I-NEXT: bnez a0, .LBB151_4
; RV32I-NEXT: .LBB151_2: # %atomicrmw.start ; RV32I-NEXT: .LBB151_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB151_1 ; RV32I-NEXT: bge s1, a3, .LBB151_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB151_1 ; RV32I-NEXT: j .LBB151_1
; RV32I-NEXT: .LBB151_4: # %atomicrmw.end ; RV32I-NEXT: .LBB151_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acquire: ; RV32IA-LABEL: atomicrmw_min_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acquire: ; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB151_4 ; RV64I-NEXT: bnez a0, .LBB151_4
; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB151_1 ; RV64I-NEXT: bge s1, a0, .LBB151_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: j .LBB151_1
; RV64I-NEXT: .LBB151_4: # %atomicrmw.end ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acquire: ; RV64IA-LABEL: atomicrmw_min_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acquire %1 = atomicrmw min i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_release: ; RV32I-LABEL: atomicrmw_min_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB152_2 ; RV32I-NEXT: j .LBB152_2
; RV32I-NEXT: .LBB152_1: # %atomicrmw.start ; RV32I-NEXT: .LBB152_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB152_4 ; RV32I-NEXT: bnez a0, .LBB152_4
; RV32I-NEXT: .LBB152_2: # %atomicrmw.start ; RV32I-NEXT: .LBB152_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB152_1 ; RV32I-NEXT: bge s1, a3, .LBB152_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB152_1 ; RV32I-NEXT: j .LBB152_1
; RV32I-NEXT: .LBB152_4: # %atomicrmw.end ; RV32I-NEXT: .LBB152_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_release: ; RV32IA-LABEL: atomicrmw_min_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_release: ; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB152_4 ; RV64I-NEXT: bnez a0, .LBB152_4
; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB152_1 ; RV64I-NEXT: bge s1, a0, .LBB152_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: j .LBB152_1
; RV64I-NEXT: .LBB152_4: # %atomicrmw.end ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_release: ; RV64IA-LABEL: atomicrmw_min_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b release %1 = atomicrmw min i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acq_rel: ; RV32I-LABEL: atomicrmw_min_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB153_2 ; RV32I-NEXT: j .LBB153_2
; RV32I-NEXT: .LBB153_1: # %atomicrmw.start ; RV32I-NEXT: .LBB153_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB153_4 ; RV32I-NEXT: bnez a0, .LBB153_4
; RV32I-NEXT: .LBB153_2: # %atomicrmw.start ; RV32I-NEXT: .LBB153_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB153_1 ; RV32I-NEXT: bge s1, a3, .LBB153_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB153_1 ; RV32I-NEXT: j .LBB153_1
; RV32I-NEXT: .LBB153_4: # %atomicrmw.end ; RV32I-NEXT: .LBB153_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acq_rel: ; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB153_4 ; RV64I-NEXT: bnez a0, .LBB153_4
; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB153_1 ; RV64I-NEXT: bge s1, a0, .LBB153_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: j .LBB153_1
; RV64I-NEXT: .LBB153_4: # %atomicrmw.end ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acq_rel %1 = atomicrmw min i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_seq_cst: ; RV32I-LABEL: atomicrmw_min_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB154_2 ; RV32I-NEXT: j .LBB154_2
; RV32I-NEXT: .LBB154_1: # %atomicrmw.start ; RV32I-NEXT: .LBB154_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB154_4 ; RV32I-NEXT: bnez a0, .LBB154_4
; RV32I-NEXT: .LBB154_2: # %atomicrmw.start ; RV32I-NEXT: .LBB154_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB154_1 ; RV32I-NEXT: bge s1, a3, .LBB154_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB154_1 ; RV32I-NEXT: j .LBB154_1
; RV32I-NEXT: .LBB154_4: # %atomicrmw.end ; RV32I-NEXT: .LBB154_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_seq_cst: ; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB154_4 ; RV64I-NEXT: bnez a0, .LBB154_4
; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB154_1 ; RV64I-NEXT: bge s1, a0, .LBB154_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: j .LBB154_1
; RV64I-NEXT: .LBB154_4: # %atomicrmw.end ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b seq_cst %1 = atomicrmw min i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_monotonic: ; RV32I-LABEL: atomicrmw_umax_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB155_2 ; RV32I-NEXT: j .LBB155_2
; RV32I-NEXT: .LBB155_1: # %atomicrmw.start ; RV32I-NEXT: .LBB155_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB155_4 ; RV32I-NEXT: bnez a0, .LBB155_4
; RV32I-NEXT: .LBB155_2: # %atomicrmw.start ; RV32I-NEXT: .LBB155_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB155_1 ; RV32I-NEXT: bltu s1, a3, .LBB155_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB155_1 ; RV32I-NEXT: j .LBB155_1
; RV32I-NEXT: .LBB155_4: # %atomicrmw.end ; RV32I-NEXT: .LBB155_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB155_4 ; RV64I-NEXT: bnez a0, .LBB155_4
; RV64I-NEXT: .LBB155_2: # %atomicrmw.start ; RV64I-NEXT: .LBB155_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB155_1 ; RV64I-NEXT: bltu s1, a0, .LBB155_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB155_1 ; RV64I-NEXT: j .LBB155_1
; RV64I-NEXT: .LBB155_4: # %atomicrmw.end ; RV64I-NEXT: .LBB155_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b monotonic %1 = atomicrmw umax i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acquire: ; RV32I-LABEL: atomicrmw_umax_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB156_2 ; RV32I-NEXT: j .LBB156_2
; RV32I-NEXT: .LBB156_1: # %atomicrmw.start ; RV32I-NEXT: .LBB156_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB156_4 ; RV32I-NEXT: bnez a0, .LBB156_4
; RV32I-NEXT: .LBB156_2: # %atomicrmw.start ; RV32I-NEXT: .LBB156_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB156_1 ; RV32I-NEXT: bltu s1, a3, .LBB156_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB156_1 ; RV32I-NEXT: j .LBB156_1
; RV32I-NEXT: .LBB156_4: # %atomicrmw.end ; RV32I-NEXT: .LBB156_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acquire: ; RV32IA-LABEL: atomicrmw_umax_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acquire: ; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB156_4 ; RV64I-NEXT: bnez a0, .LBB156_4
; RV64I-NEXT: .LBB156_2: # %atomicrmw.start ; RV64I-NEXT: .LBB156_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB156_1 ; RV64I-NEXT: bltu s1, a0, .LBB156_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB156_1 ; RV64I-NEXT: j .LBB156_1
; RV64I-NEXT: .LBB156_4: # %atomicrmw.end ; RV64I-NEXT: .LBB156_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acquire: ; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acquire %1 = atomicrmw umax i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_release: ; RV32I-LABEL: atomicrmw_umax_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB157_2 ; RV32I-NEXT: j .LBB157_2
; RV32I-NEXT: .LBB157_1: # %atomicrmw.start ; RV32I-NEXT: .LBB157_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB157_4 ; RV32I-NEXT: bnez a0, .LBB157_4
; RV32I-NEXT: .LBB157_2: # %atomicrmw.start ; RV32I-NEXT: .LBB157_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB157_1 ; RV32I-NEXT: bltu s1, a3, .LBB157_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB157_1 ; RV32I-NEXT: j .LBB157_1
; RV32I-NEXT: .LBB157_4: # %atomicrmw.end ; RV32I-NEXT: .LBB157_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_release: ; RV32IA-LABEL: atomicrmw_umax_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_release: ; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB157_4 ; RV64I-NEXT: bnez a0, .LBB157_4
; RV64I-NEXT: .LBB157_2: # %atomicrmw.start ; RV64I-NEXT: .LBB157_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB157_1 ; RV64I-NEXT: bltu s1, a0, .LBB157_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB157_1 ; RV64I-NEXT: j .LBB157_1
; RV64I-NEXT: .LBB157_4: # %atomicrmw.end ; RV64I-NEXT: .LBB157_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_release: ; RV64IA-LABEL: atomicrmw_umax_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b release %1 = atomicrmw umax i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB158_2 ; RV32I-NEXT: j .LBB158_2
; RV32I-NEXT: .LBB158_1: # %atomicrmw.start ; RV32I-NEXT: .LBB158_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB158_4 ; RV32I-NEXT: bnez a0, .LBB158_4
; RV32I-NEXT: .LBB158_2: # %atomicrmw.start ; RV32I-NEXT: .LBB158_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB158_1 ; RV32I-NEXT: bltu s1, a3, .LBB158_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB158_1 ; RV32I-NEXT: j .LBB158_1
; RV32I-NEXT: .LBB158_4: # %atomicrmw.end ; RV32I-NEXT: .LBB158_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB158_4 ; RV64I-NEXT: bnez a0, .LBB158_4
; RV64I-NEXT: .LBB158_2: # %atomicrmw.start ; RV64I-NEXT: .LBB158_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB158_1 ; RV64I-NEXT: bltu s1, a0, .LBB158_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB158_1 ; RV64I-NEXT: j .LBB158_1
; RV64I-NEXT: .LBB158_4: # %atomicrmw.end ; RV64I-NEXT: .LBB158_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acq_rel %1 = atomicrmw umax i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB159_2 ; RV32I-NEXT: j .LBB159_2
; RV32I-NEXT: .LBB159_1: # %atomicrmw.start ; RV32I-NEXT: .LBB159_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB159_4 ; RV32I-NEXT: bnez a0, .LBB159_4
; RV32I-NEXT: .LBB159_2: # %atomicrmw.start ; RV32I-NEXT: .LBB159_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB159_1 ; RV32I-NEXT: bltu s1, a3, .LBB159_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB159_1 ; RV32I-NEXT: j .LBB159_1
; RV32I-NEXT: .LBB159_4: # %atomicrmw.end ; RV32I-NEXT: .LBB159_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB159_4 ; RV64I-NEXT: bnez a0, .LBB159_4
; RV64I-NEXT: .LBB159_2: # %atomicrmw.start ; RV64I-NEXT: .LBB159_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB159_1 ; RV64I-NEXT: bltu s1, a0, .LBB159_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB159_1 ; RV64I-NEXT: j .LBB159_1
; RV64I-NEXT: .LBB159_4: # %atomicrmw.end ; RV64I-NEXT: .LBB159_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b seq_cst %1 = atomicrmw umax i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_monotonic: ; RV32I-LABEL: atomicrmw_umin_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB160_2 ; RV32I-NEXT: j .LBB160_2
; RV32I-NEXT: .LBB160_1: # %atomicrmw.start ; RV32I-NEXT: .LBB160_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB160_4 ; RV32I-NEXT: bnez a0, .LBB160_4
; RV32I-NEXT: .LBB160_2: # %atomicrmw.start ; RV32I-NEXT: .LBB160_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB160_1 ; RV32I-NEXT: bgeu s1, a3, .LBB160_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB160_1 ; RV32I-NEXT: j .LBB160_1
; RV32I-NEXT: .LBB160_4: # %atomicrmw.end ; RV32I-NEXT: .LBB160_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w a0, a1, (a0) ; RV32IA-NEXT: amominu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB160_4 ; RV64I-NEXT: bnez a0, .LBB160_4
; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB160_1 ; RV64I-NEXT: bgeu s1, a0, .LBB160_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: j .LBB160_1
; RV64I-NEXT: .LBB160_4: # %atomicrmw.end ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w a0, a1, (a0) ; RV64IA-NEXT: amominu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b monotonic %1 = atomicrmw umin i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acquire: ; RV32I-LABEL: atomicrmw_umin_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB161_2 ; RV32I-NEXT: j .LBB161_2
; RV32I-NEXT: .LBB161_1: # %atomicrmw.start ; RV32I-NEXT: .LBB161_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB161_4 ; RV32I-NEXT: bnez a0, .LBB161_4
; RV32I-NEXT: .LBB161_2: # %atomicrmw.start ; RV32I-NEXT: .LBB161_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB161_1 ; RV32I-NEXT: bgeu s1, a3, .LBB161_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB161_1 ; RV32I-NEXT: j .LBB161_1
; RV32I-NEXT: .LBB161_4: # %atomicrmw.end ; RV32I-NEXT: .LBB161_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acquire: ; RV32IA-LABEL: atomicrmw_umin_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acquire: ; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB161_4 ; RV64I-NEXT: bnez a0, .LBB161_4
; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB161_1 ; RV64I-NEXT: bgeu s1, a0, .LBB161_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: j .LBB161_1
; RV64I-NEXT: .LBB161_4: # %atomicrmw.end ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acquire: ; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acquire %1 = atomicrmw umin i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_release: ; RV32I-LABEL: atomicrmw_umin_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB162_2 ; RV32I-NEXT: j .LBB162_2
; RV32I-NEXT: .LBB162_1: # %atomicrmw.start ; RV32I-NEXT: .LBB162_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB162_4 ; RV32I-NEXT: bnez a0, .LBB162_4
; RV32I-NEXT: .LBB162_2: # %atomicrmw.start ; RV32I-NEXT: .LBB162_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB162_1 ; RV32I-NEXT: bgeu s1, a3, .LBB162_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB162_1 ; RV32I-NEXT: j .LBB162_1
; RV32I-NEXT: .LBB162_4: # %atomicrmw.end ; RV32I-NEXT: .LBB162_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_release: ; RV32IA-LABEL: atomicrmw_umin_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_release: ; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB162_4 ; RV64I-NEXT: bnez a0, .LBB162_4
; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB162_1 ; RV64I-NEXT: bgeu s1, a0, .LBB162_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: j .LBB162_1
; RV64I-NEXT: .LBB162_4: # %atomicrmw.end ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_release: ; RV64IA-LABEL: atomicrmw_umin_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b release %1 = atomicrmw umin i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB163_2 ; RV32I-NEXT: j .LBB163_2
; RV32I-NEXT: .LBB163_1: # %atomicrmw.start ; RV32I-NEXT: .LBB163_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB163_4 ; RV32I-NEXT: bnez a0, .LBB163_4
; RV32I-NEXT: .LBB163_2: # %atomicrmw.start ; RV32I-NEXT: .LBB163_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB163_1 ; RV32I-NEXT: bgeu s1, a3, .LBB163_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB163_1 ; RV32I-NEXT: j .LBB163_1
; RV32I-NEXT: .LBB163_4: # %atomicrmw.end ; RV32I-NEXT: .LBB163_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB163_4 ; RV64I-NEXT: bnez a0, .LBB163_4
; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB163_1 ; RV64I-NEXT: bgeu s1, a0, .LBB163_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: j .LBB163_1
; RV64I-NEXT: .LBB163_4: # %atomicrmw.end ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acq_rel %1 = atomicrmw umin i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB164_2 ; RV32I-NEXT: j .LBB164_2
; RV32I-NEXT: .LBB164_1: # %atomicrmw.start ; RV32I-NEXT: .LBB164_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB164_4 ; RV32I-NEXT: bnez a0, .LBB164_4
; RV32I-NEXT: .LBB164_2: # %atomicrmw.start ; RV32I-NEXT: .LBB164_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB164_1 ; RV32I-NEXT: bgeu s1, a3, .LBB164_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB164_1 ; RV32I-NEXT: j .LBB164_1
; RV32I-NEXT: .LBB164_4: # %atomicrmw.end ; RV32I-NEXT: .LBB164_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB164_4 ; RV64I-NEXT: bnez a0, .LBB164_4
; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB164_1 ; RV64I-NEXT: bgeu s1, a0, .LBB164_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: j .LBB164_1
; RV64I-NEXT: .LBB164_4: # %atomicrmw.end ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b seq_cst %1 = atomicrmw umin i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d a0, a1, (a0) ; RV64IA-NEXT: amoswap.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b monotonic %1 = atomicrmw xchg i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_acquire: ; RV32I-LABEL: atomicrmw_xchg_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_acquire: ; RV64I-LABEL: atomicrmw_xchg_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b acquire %1 = atomicrmw xchg i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_release: ; RV32I-LABEL: atomicrmw_xchg_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_release: ; RV32IA-LABEL: atomicrmw_xchg_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_release: ; RV64I-LABEL: atomicrmw_xchg_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_release: ; RV64IA-LABEL: atomicrmw_xchg_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b release %1 = atomicrmw xchg i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b acq_rel %1 = atomicrmw xchg i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b seq_cst %1 = atomicrmw xchg i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_monotonic: ; RV32I-LABEL: atomicrmw_add_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_monotonic: ; RV32IA-LABEL: atomicrmw_add_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_monotonic: ; RV64I-LABEL: atomicrmw_add_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_monotonic: ; RV64IA-LABEL: atomicrmw_add_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b monotonic %1 = atomicrmw add i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_acquire: ; RV32I-LABEL: atomicrmw_add_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_acquire: ; RV32IA-LABEL: atomicrmw_add_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_acquire: ; RV64I-LABEL: atomicrmw_add_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_acquire: ; RV64IA-LABEL: atomicrmw_add_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b acquire %1 = atomicrmw add i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_release: ; RV32I-LABEL: atomicrmw_add_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_release: ; RV32IA-LABEL: atomicrmw_add_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_release: ; RV64I-LABEL: atomicrmw_add_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_release: ; RV64IA-LABEL: atomicrmw_add_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b release %1 = atomicrmw add i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_acq_rel: ; RV32I-LABEL: atomicrmw_add_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_acq_rel: ; RV64I-LABEL: atomicrmw_add_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b acq_rel %1 = atomicrmw add i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_seq_cst: ; RV32I-LABEL: atomicrmw_add_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_seq_cst: ; RV64I-LABEL: atomicrmw_add_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b seq_cst %1 = atomicrmw add i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_monotonic: ; RV32I-LABEL: atomicrmw_sub_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_monotonic: ; RV64I-LABEL: atomicrmw_sub_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b monotonic %1 = atomicrmw sub i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_acquire: ; RV32I-LABEL: atomicrmw_sub_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_acquire: ; RV32IA-LABEL: atomicrmw_sub_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_acquire: ; RV64I-LABEL: atomicrmw_sub_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_acquire: ; RV64IA-LABEL: atomicrmw_sub_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b acquire %1 = atomicrmw sub i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_release: ; RV32I-LABEL: atomicrmw_sub_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_release: ; RV32IA-LABEL: atomicrmw_sub_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_release: ; RV64I-LABEL: atomicrmw_sub_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_release: ; RV64IA-LABEL: atomicrmw_sub_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b release %1 = atomicrmw sub i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b acq_rel %1 = atomicrmw sub i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b seq_cst %1 = atomicrmw sub i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_monotonic: ; RV32I-LABEL: atomicrmw_and_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_monotonic: ; RV32IA-LABEL: atomicrmw_and_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_monotonic: ; RV64I-LABEL: atomicrmw_and_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_monotonic: ; RV64IA-LABEL: atomicrmw_and_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d a0, a1, (a0) ; RV64IA-NEXT: amoand.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b monotonic %1 = atomicrmw and i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_acquire: ; RV32I-LABEL: atomicrmw_and_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_acquire: ; RV32IA-LABEL: atomicrmw_and_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_acquire: ; RV64I-LABEL: atomicrmw_and_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_acquire: ; RV64IA-LABEL: atomicrmw_and_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b acquire %1 = atomicrmw and i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_release: ; RV32I-LABEL: atomicrmw_and_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_release: ; RV32IA-LABEL: atomicrmw_and_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_release: ; RV64I-LABEL: atomicrmw_and_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_release: ; RV64IA-LABEL: atomicrmw_and_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b release %1 = atomicrmw and i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_acq_rel: ; RV32I-LABEL: atomicrmw_and_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_acq_rel: ; RV64I-LABEL: atomicrmw_and_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b acq_rel %1 = atomicrmw and i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_seq_cst: ; RV32I-LABEL: atomicrmw_and_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_seq_cst: ; RV64I-LABEL: atomicrmw_and_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b seq_cst %1 = atomicrmw and i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_monotonic: ; RV32I-LABEL: atomicrmw_nand_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_monotonic: ; RV64I-LABEL: atomicrmw_nand_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a2, (a0) ; RV64IA-NEXT: lr.d a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d a3, a3, (a0) ; RV64IA-NEXT: sc.d a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB185_1 ; RV64IA-NEXT: bnez a3, .LBB185_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b monotonic %1 = atomicrmw nand i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_acquire: ; RV32I-LABEL: atomicrmw_nand_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_acquire: ; RV32IA-LABEL: atomicrmw_nand_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_acquire: ; RV64I-LABEL: atomicrmw_nand_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_acquire: ; RV64IA-LABEL: atomicrmw_nand_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a2, (a0) ; RV64IA-NEXT: lr.d.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d a3, a3, (a0) ; RV64IA-NEXT: sc.d a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB186_1 ; RV64IA-NEXT: bnez a3, .LBB186_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b acquire %1 = atomicrmw nand i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_release: ; RV32I-LABEL: atomicrmw_nand_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_release: ; RV32IA-LABEL: atomicrmw_nand_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_release: ; RV64I-LABEL: atomicrmw_nand_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_release: ; RV64IA-LABEL: atomicrmw_nand_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a2, (a0) ; RV64IA-NEXT: lr.d a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.rl a3, a3, (a0) ; RV64IA-NEXT: sc.d.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB187_1 ; RV64IA-NEXT: bnez a3, .LBB187_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b release %1 = atomicrmw nand i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a2, (a0) ; RV64IA-NEXT: lr.d.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.rl a3, a3, (a0) ; RV64IA-NEXT: sc.d.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB188_1 ; RV64IA-NEXT: bnez a3, .LBB188_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b acq_rel %1 = atomicrmw nand i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: lr.d.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.d.aqrl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB189_1 ; RV64IA-NEXT: bnez a3, .LBB189_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b seq_cst %1 = atomicrmw nand i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_monotonic: ; RV32I-LABEL: atomicrmw_or_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_monotonic: ; RV32IA-LABEL: atomicrmw_or_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_monotonic: ; RV64I-LABEL: atomicrmw_or_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_monotonic: ; RV64IA-LABEL: atomicrmw_or_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d a0, a1, (a0) ; RV64IA-NEXT: amoor.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b monotonic %1 = atomicrmw or i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_acquire: ; RV32I-LABEL: atomicrmw_or_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_acquire: ; RV32IA-LABEL: atomicrmw_or_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_acquire: ; RV64I-LABEL: atomicrmw_or_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_acquire: ; RV64IA-LABEL: atomicrmw_or_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b acquire %1 = atomicrmw or i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_release: ; RV32I-LABEL: atomicrmw_or_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_release: ; RV32IA-LABEL: atomicrmw_or_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_release: ; RV64I-LABEL: atomicrmw_or_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_release: ; RV64IA-LABEL: atomicrmw_or_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b release %1 = atomicrmw or i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_acq_rel: ; RV32I-LABEL: atomicrmw_or_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_acq_rel: ; RV64I-LABEL: atomicrmw_or_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b acq_rel %1 = atomicrmw or i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_seq_cst: ; RV32I-LABEL: atomicrmw_or_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_seq_cst: ; RV64I-LABEL: atomicrmw_or_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b seq_cst %1 = atomicrmw or i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_monotonic: ; RV32I-LABEL: atomicrmw_xor_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_monotonic: ; RV64I-LABEL: atomicrmw_xor_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d a0, a1, (a0) ; RV64IA-NEXT: amoxor.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b monotonic %1 = atomicrmw xor i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_acquire: ; RV32I-LABEL: atomicrmw_xor_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_acquire: ; RV32IA-LABEL: atomicrmw_xor_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_acquire: ; RV64I-LABEL: atomicrmw_xor_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_acquire: ; RV64IA-LABEL: atomicrmw_xor_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b acquire %1 = atomicrmw xor i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_release: ; RV32I-LABEL: atomicrmw_xor_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_release: ; RV32IA-LABEL: atomicrmw_xor_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_release: ; RV64I-LABEL: atomicrmw_xor_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_release: ; RV64IA-LABEL: atomicrmw_xor_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b release %1 = atomicrmw xor i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b acq_rel %1 = atomicrmw xor i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b seq_cst %1 = atomicrmw xor i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_monotonic: ; RV32I-LABEL: atomicrmw_max_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB200_2 ; RV32I-NEXT: j .LBB200_2
; RV32I-NEXT: .LBB200_1: # %atomicrmw.start ; RV32I-NEXT: .LBB200_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB200_7 ; RV32I-NEXT: bnez a0, .LBB200_7
; RV32I-NEXT: .LBB200_2: # %atomicrmw.start ; RV32I-NEXT: .LBB200_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB200_4 ; RV32I-NEXT: beq a5, s1, .LBB200_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB200_1 ; RV32I-NEXT: j .LBB200_1
; RV32I-NEXT: .LBB200_7: # %atomicrmw.end ; RV32I-NEXT: .LBB200_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_monotonic: ; RV32IA-LABEL: atomicrmw_max_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB200_2 ; RV32IA-NEXT: j .LBB200_2
; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB200_7 ; RV32IA-NEXT: bnez a0, .LBB200_7
; RV32IA-NEXT: .LBB200_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB200_4 ; RV32IA-NEXT: beq a5, s1, .LBB200_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB200_1 ; RV32IA-NEXT: j .LBB200_1
; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_monotonic: ; RV64I-LABEL: atomicrmw_max_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB200_2 ; RV64I-NEXT: j .LBB200_2
; RV64I-NEXT: .LBB200_1: # %atomicrmw.start ; RV64I-NEXT: .LBB200_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB200_4 ; RV64I-NEXT: bnez a0, .LBB200_4
; RV64I-NEXT: .LBB200_2: # %atomicrmw.start ; RV64I-NEXT: .LBB200_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB200_1 ; RV64I-NEXT: blt s1, a3, .LBB200_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB200_1 ; RV64I-NEXT: j .LBB200_1
; RV64I-NEXT: .LBB200_4: # %atomicrmw.end ; RV64I-NEXT: .LBB200_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_monotonic: ; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d a0, a1, (a0) ; RV64IA-NEXT: amomax.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b monotonic %1 = atomicrmw max i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acquire: ; RV32I-LABEL: atomicrmw_max_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB201_2 ; RV32I-NEXT: j .LBB201_2
; RV32I-NEXT: .LBB201_1: # %atomicrmw.start ; RV32I-NEXT: .LBB201_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB201_7 ; RV32I-NEXT: bnez a0, .LBB201_7
; RV32I-NEXT: .LBB201_2: # %atomicrmw.start ; RV32I-NEXT: .LBB201_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB201_4 ; RV32I-NEXT: beq a5, s1, .LBB201_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB201_1 ; RV32I-NEXT: j .LBB201_1
; RV32I-NEXT: .LBB201_7: # %atomicrmw.end ; RV32I-NEXT: .LBB201_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acquire: ; RV32IA-LABEL: atomicrmw_max_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB201_2 ; RV32IA-NEXT: j .LBB201_2
; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB201_7 ; RV32IA-NEXT: bnez a0, .LBB201_7
; RV32IA-NEXT: .LBB201_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB201_4 ; RV32IA-NEXT: beq a5, s1, .LBB201_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB201_1 ; RV32IA-NEXT: j .LBB201_1
; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acquire: ; RV64I-LABEL: atomicrmw_max_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB201_2 ; RV64I-NEXT: j .LBB201_2
; RV64I-NEXT: .LBB201_1: # %atomicrmw.start ; RV64I-NEXT: .LBB201_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB201_4 ; RV64I-NEXT: bnez a0, .LBB201_4
; RV64I-NEXT: .LBB201_2: # %atomicrmw.start ; RV64I-NEXT: .LBB201_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB201_1 ; RV64I-NEXT: blt s1, a3, .LBB201_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB201_1 ; RV64I-NEXT: j .LBB201_1
; RV64I-NEXT: .LBB201_4: # %atomicrmw.end ; RV64I-NEXT: .LBB201_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acquire: ; RV64IA-LABEL: atomicrmw_max_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acquire %1 = atomicrmw max i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_release: ; RV32I-LABEL: atomicrmw_max_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB202_2 ; RV32I-NEXT: j .LBB202_2
; RV32I-NEXT: .LBB202_1: # %atomicrmw.start ; RV32I-NEXT: .LBB202_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB202_7 ; RV32I-NEXT: bnez a0, .LBB202_7
; RV32I-NEXT: .LBB202_2: # %atomicrmw.start ; RV32I-NEXT: .LBB202_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB202_4 ; RV32I-NEXT: beq a5, s1, .LBB202_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB202_1 ; RV32I-NEXT: j .LBB202_1
; RV32I-NEXT: .LBB202_7: # %atomicrmw.end ; RV32I-NEXT: .LBB202_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_release: ; RV32IA-LABEL: atomicrmw_max_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB202_2 ; RV32IA-NEXT: j .LBB202_2
; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB202_7 ; RV32IA-NEXT: bnez a0, .LBB202_7
; RV32IA-NEXT: .LBB202_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB202_4 ; RV32IA-NEXT: beq a5, s1, .LBB202_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB202_1 ; RV32IA-NEXT: j .LBB202_1
; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_release: ; RV64I-LABEL: atomicrmw_max_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB202_2 ; RV64I-NEXT: j .LBB202_2
; RV64I-NEXT: .LBB202_1: # %atomicrmw.start ; RV64I-NEXT: .LBB202_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB202_4 ; RV64I-NEXT: bnez a0, .LBB202_4
; RV64I-NEXT: .LBB202_2: # %atomicrmw.start ; RV64I-NEXT: .LBB202_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB202_1 ; RV64I-NEXT: blt s1, a3, .LBB202_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB202_1 ; RV64I-NEXT: j .LBB202_1
; RV64I-NEXT: .LBB202_4: # %atomicrmw.end ; RV64I-NEXT: .LBB202_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_release: ; RV64IA-LABEL: atomicrmw_max_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b release %1 = atomicrmw max i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acq_rel: ; RV32I-LABEL: atomicrmw_max_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB203_2 ; RV32I-NEXT: j .LBB203_2
; RV32I-NEXT: .LBB203_1: # %atomicrmw.start ; RV32I-NEXT: .LBB203_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB203_7 ; RV32I-NEXT: bnez a0, .LBB203_7
; RV32I-NEXT: .LBB203_2: # %atomicrmw.start ; RV32I-NEXT: .LBB203_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB203_4 ; RV32I-NEXT: beq a5, s1, .LBB203_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB203_1 ; RV32I-NEXT: j .LBB203_1
; RV32I-NEXT: .LBB203_7: # %atomicrmw.end ; RV32I-NEXT: .LBB203_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB203_2 ; RV32IA-NEXT: j .LBB203_2
; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB203_7 ; RV32IA-NEXT: bnez a0, .LBB203_7
; RV32IA-NEXT: .LBB203_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB203_4 ; RV32IA-NEXT: beq a5, s1, .LBB203_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB203_1 ; RV32IA-NEXT: j .LBB203_1
; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acq_rel: ; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB203_2 ; RV64I-NEXT: j .LBB203_2
; RV64I-NEXT: .LBB203_1: # %atomicrmw.start ; RV64I-NEXT: .LBB203_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB203_4 ; RV64I-NEXT: bnez a0, .LBB203_4
; RV64I-NEXT: .LBB203_2: # %atomicrmw.start ; RV64I-NEXT: .LBB203_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB203_1 ; RV64I-NEXT: blt s1, a3, .LBB203_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB203_1 ; RV64I-NEXT: j .LBB203_1
; RV64I-NEXT: .LBB203_4: # %atomicrmw.end ; RV64I-NEXT: .LBB203_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acq_rel %1 = atomicrmw max i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_seq_cst: ; RV32I-LABEL: atomicrmw_max_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB204_2 ; RV32I-NEXT: j .LBB204_2
; RV32I-NEXT: .LBB204_1: # %atomicrmw.start ; RV32I-NEXT: .LBB204_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB204_7 ; RV32I-NEXT: bnez a0, .LBB204_7
; RV32I-NEXT: .LBB204_2: # %atomicrmw.start ; RV32I-NEXT: .LBB204_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB204_4 ; RV32I-NEXT: beq a5, s1, .LBB204_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB204_1 ; RV32I-NEXT: j .LBB204_1
; RV32I-NEXT: .LBB204_7: # %atomicrmw.end ; RV32I-NEXT: .LBB204_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB204_2 ; RV32IA-NEXT: j .LBB204_2
; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB204_7 ; RV32IA-NEXT: bnez a0, .LBB204_7
; RV32IA-NEXT: .LBB204_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB204_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB204_4 ; RV32IA-NEXT: beq a5, s1, .LBB204_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB204_1 ; RV32IA-NEXT: j .LBB204_1
; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_seq_cst: ; RV64I-LABEL: atomicrmw_max_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB204_2 ; RV64I-NEXT: j .LBB204_2
; RV64I-NEXT: .LBB204_1: # %atomicrmw.start ; RV64I-NEXT: .LBB204_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB204_4 ; RV64I-NEXT: bnez a0, .LBB204_4
; RV64I-NEXT: .LBB204_2: # %atomicrmw.start ; RV64I-NEXT: .LBB204_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB204_1 ; RV64I-NEXT: blt s1, a3, .LBB204_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB204_1 ; RV64I-NEXT: j .LBB204_1
; RV64I-NEXT: .LBB204_4: # %atomicrmw.end ; RV64I-NEXT: .LBB204_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b seq_cst %1 = atomicrmw max i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_monotonic: ; RV32I-LABEL: atomicrmw_min_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB205_2 ; RV32I-NEXT: j .LBB205_2
; RV32I-NEXT: .LBB205_1: # %atomicrmw.start ; RV32I-NEXT: .LBB205_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB205_7 ; RV32I-NEXT: bnez a0, .LBB205_7
; RV32I-NEXT: .LBB205_2: # %atomicrmw.start ; RV32I-NEXT: .LBB205_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB205_4 ; RV32I-NEXT: beq a5, s1, .LBB205_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB205_1 ; RV32I-NEXT: j .LBB205_1
; RV32I-NEXT: .LBB205_7: # %atomicrmw.end ; RV32I-NEXT: .LBB205_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_monotonic: ; RV32IA-LABEL: atomicrmw_min_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB205_2 ; RV32IA-NEXT: j .LBB205_2
; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB205_7 ; RV32IA-NEXT: bnez a0, .LBB205_7
; RV32IA-NEXT: .LBB205_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB205_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB205_4 ; RV32IA-NEXT: beq a5, s1, .LBB205_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB205_1 ; RV32IA-NEXT: j .LBB205_1
; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_monotonic: ; RV64I-LABEL: atomicrmw_min_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB205_2 ; RV64I-NEXT: j .LBB205_2
; RV64I-NEXT: .LBB205_1: # %atomicrmw.start ; RV64I-NEXT: .LBB205_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB205_4 ; RV64I-NEXT: bnez a0, .LBB205_4
; RV64I-NEXT: .LBB205_2: # %atomicrmw.start ; RV64I-NEXT: .LBB205_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB205_1 ; RV64I-NEXT: bge s1, a3, .LBB205_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB205_1 ; RV64I-NEXT: j .LBB205_1
; RV64I-NEXT: .LBB205_4: # %atomicrmw.end ; RV64I-NEXT: .LBB205_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_monotonic: ; RV64IA-LABEL: atomicrmw_min_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d a0, a1, (a0) ; RV64IA-NEXT: amomin.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b monotonic %1 = atomicrmw min i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_acquire: ; RV32I-LABEL: atomicrmw_min_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB206_2 ; RV32I-NEXT: j .LBB206_2
; RV32I-NEXT: .LBB206_1: # %atomicrmw.start ; RV32I-NEXT: .LBB206_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB206_7 ; RV32I-NEXT: bnez a0, .LBB206_7
; RV32I-NEXT: .LBB206_2: # %atomicrmw.start ; RV32I-NEXT: .LBB206_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB206_4 ; RV32I-NEXT: beq a5, s1, .LBB206_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB206_1 ; RV32I-NEXT: j .LBB206_1
; RV32I-NEXT: .LBB206_7: # %atomicrmw.end ; RV32I-NEXT: .LBB206_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_acquire: ; RV32IA-LABEL: atomicrmw_min_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB206_2 ; RV32IA-NEXT: j .LBB206_2
; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB206_7 ; RV32IA-NEXT: bnez a0, .LBB206_7
; RV32IA-NEXT: .LBB206_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB206_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB206_4 ; RV32IA-NEXT: beq a5, s1, .LBB206_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB206_1 ; RV32IA-NEXT: j .LBB206_1
; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_acquire: ; RV64I-LABEL: atomicrmw_min_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB206_2 ; RV64I-NEXT: j .LBB206_2
; RV64I-NEXT: .LBB206_1: # %atomicrmw.start ; RV64I-NEXT: .LBB206_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB206_4 ; RV64I-NEXT: bnez a0, .LBB206_4
; RV64I-NEXT: .LBB206_2: # %atomicrmw.start ; RV64I-NEXT: .LBB206_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB206_1 ; RV64I-NEXT: bge s1, a3, .LBB206_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB206_1 ; RV64I-NEXT: j .LBB206_1
; RV64I-NEXT: .LBB206_4: # %atomicrmw.end ; RV64I-NEXT: .LBB206_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_acquire: ; RV64IA-LABEL: atomicrmw_min_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b acquire %1 = atomicrmw min i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_release: ; RV32I-LABEL: atomicrmw_min_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB207_2 ; RV32I-NEXT: j .LBB207_2
; RV32I-NEXT: .LBB207_1: # %atomicrmw.start ; RV32I-NEXT: .LBB207_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB207_7 ; RV32I-NEXT: bnez a0, .LBB207_7
; RV32I-NEXT: .LBB207_2: # %atomicrmw.start ; RV32I-NEXT: .LBB207_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB207_4 ; RV32I-NEXT: beq a5, s1, .LBB207_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB207_1 ; RV32I-NEXT: j .LBB207_1
; RV32I-NEXT: .LBB207_7: # %atomicrmw.end ; RV32I-NEXT: .LBB207_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_release: ; RV32IA-LABEL: atomicrmw_min_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB207_2 ; RV32IA-NEXT: j .LBB207_2
; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB207_7 ; RV32IA-NEXT: bnez a0, .LBB207_7
; RV32IA-NEXT: .LBB207_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB207_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB207_4 ; RV32IA-NEXT: beq a5, s1, .LBB207_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB207_1 ; RV32IA-NEXT: j .LBB207_1
; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_release: ; RV64I-LABEL: atomicrmw_min_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB207_2 ; RV64I-NEXT: j .LBB207_2
; RV64I-NEXT: .LBB207_1: # %atomicrmw.start ; RV64I-NEXT: .LBB207_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB207_4 ; RV64I-NEXT: bnez a0, .LBB207_4
; RV64I-NEXT: .LBB207_2: # %atomicrmw.start ; RV64I-NEXT: .LBB207_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB207_1 ; RV64I-NEXT: bge s1, a3, .LBB207_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB207_1 ; RV64I-NEXT: j .LBB207_1
; RV64I-NEXT: .LBB207_4: # %atomicrmw.end ; RV64I-NEXT: .LBB207_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_release: ; RV64IA-LABEL: atomicrmw_min_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b release %1 = atomicrmw min i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_acq_rel: ; RV32I-LABEL: atomicrmw_min_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB208_2 ; RV32I-NEXT: j .LBB208_2
; RV32I-NEXT: .LBB208_1: # %atomicrmw.start ; RV32I-NEXT: .LBB208_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB208_7 ; RV32I-NEXT: bnez a0, .LBB208_7
; RV32I-NEXT: .LBB208_2: # %atomicrmw.start ; RV32I-NEXT: .LBB208_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB208_4 ; RV32I-NEXT: beq a5, s1, .LBB208_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB208_1 ; RV32I-NEXT: j .LBB208_1
; RV32I-NEXT: .LBB208_7: # %atomicrmw.end ; RV32I-NEXT: .LBB208_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB208_2 ; RV32IA-NEXT: j .LBB208_2
; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB208_7 ; RV32IA-NEXT: bnez a0, .LBB208_7
; RV32IA-NEXT: .LBB208_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB208_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB208_4 ; RV32IA-NEXT: beq a5, s1, .LBB208_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB208_1 ; RV32IA-NEXT: j .LBB208_1
; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_acq_rel: ; RV64I-LABEL: atomicrmw_min_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB208_2 ; RV64I-NEXT: j .LBB208_2
; RV64I-NEXT: .LBB208_1: # %atomicrmw.start ; RV64I-NEXT: .LBB208_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB208_4 ; RV64I-NEXT: bnez a0, .LBB208_4
; RV64I-NEXT: .LBB208_2: # %atomicrmw.start ; RV64I-NEXT: .LBB208_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB208_1 ; RV64I-NEXT: bge s1, a3, .LBB208_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB208_1 ; RV64I-NEXT: j .LBB208_1
; RV64I-NEXT: .LBB208_4: # %atomicrmw.end ; RV64I-NEXT: .LBB208_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b acq_rel %1 = atomicrmw min i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i64_seq_cst: ; RV32I-LABEL: atomicrmw_min_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB209_2 ; RV32I-NEXT: j .LBB209_2
; RV32I-NEXT: .LBB209_1: # %atomicrmw.start ; RV32I-NEXT: .LBB209_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB209_7 ; RV32I-NEXT: bnez a0, .LBB209_7
; RV32I-NEXT: .LBB209_2: # %atomicrmw.start ; RV32I-NEXT: .LBB209_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB209_4 ; RV32I-NEXT: beq a5, s1, .LBB209_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB209_1 ; RV32I-NEXT: j .LBB209_1
; RV32I-NEXT: .LBB209_7: # %atomicrmw.end ; RV32I-NEXT: .LBB209_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB209_2 ; RV32IA-NEXT: j .LBB209_2
; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB209_7 ; RV32IA-NEXT: bnez a0, .LBB209_7
; RV32IA-NEXT: .LBB209_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB209_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB209_4 ; RV32IA-NEXT: beq a5, s1, .LBB209_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB209_1 ; RV32IA-NEXT: j .LBB209_1
; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i64_seq_cst: ; RV64I-LABEL: atomicrmw_min_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB209_2 ; RV64I-NEXT: j .LBB209_2
; RV64I-NEXT: .LBB209_1: # %atomicrmw.start ; RV64I-NEXT: .LBB209_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB209_4 ; RV64I-NEXT: bnez a0, .LBB209_4
; RV64I-NEXT: .LBB209_2: # %atomicrmw.start ; RV64I-NEXT: .LBB209_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB209_1 ; RV64I-NEXT: bge s1, a3, .LBB209_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB209_1 ; RV64I-NEXT: j .LBB209_1
; RV64I-NEXT: .LBB209_4: # %atomicrmw.end ; RV64I-NEXT: .LBB209_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i64* %a, i64 %b seq_cst %1 = atomicrmw min i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_monotonic: ; RV32I-LABEL: atomicrmw_umax_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB210_2 ; RV32I-NEXT: j .LBB210_2
; RV32I-NEXT: .LBB210_1: # %atomicrmw.start ; RV32I-NEXT: .LBB210_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB210_7 ; RV32I-NEXT: bnez a0, .LBB210_7
; RV32I-NEXT: .LBB210_2: # %atomicrmw.start ; RV32I-NEXT: .LBB210_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB210_4 ; RV32I-NEXT: beq a5, s1, .LBB210_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB210_1 ; RV32I-NEXT: j .LBB210_1
; RV32I-NEXT: .LBB210_7: # %atomicrmw.end ; RV32I-NEXT: .LBB210_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB210_2 ; RV32IA-NEXT: j .LBB210_2
; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB210_7 ; RV32IA-NEXT: bnez a0, .LBB210_7
; RV32IA-NEXT: .LBB210_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB210_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB210_4 ; RV32IA-NEXT: beq a5, s1, .LBB210_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB210_1 ; RV32IA-NEXT: j .LBB210_1
; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_monotonic: ; RV64I-LABEL: atomicrmw_umax_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB210_2 ; RV64I-NEXT: j .LBB210_2
; RV64I-NEXT: .LBB210_1: # %atomicrmw.start ; RV64I-NEXT: .LBB210_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB210_4 ; RV64I-NEXT: bnez a0, .LBB210_4
; RV64I-NEXT: .LBB210_2: # %atomicrmw.start ; RV64I-NEXT: .LBB210_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB210_1 ; RV64I-NEXT: bltu s1, a3, .LBB210_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB210_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB210_1 ; RV64I-NEXT: j .LBB210_1
; RV64I-NEXT: .LBB210_4: # %atomicrmw.end ; RV64I-NEXT: .LBB210_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b monotonic %1 = atomicrmw umax i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_acquire: ; RV32I-LABEL: atomicrmw_umax_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB211_2 ; RV32I-NEXT: j .LBB211_2
; RV32I-NEXT: .LBB211_1: # %atomicrmw.start ; RV32I-NEXT: .LBB211_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB211_7 ; RV32I-NEXT: bnez a0, .LBB211_7
; RV32I-NEXT: .LBB211_2: # %atomicrmw.start ; RV32I-NEXT: .LBB211_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB211_4 ; RV32I-NEXT: beq a5, s1, .LBB211_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB211_1 ; RV32I-NEXT: j .LBB211_1
; RV32I-NEXT: .LBB211_7: # %atomicrmw.end ; RV32I-NEXT: .LBB211_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_acquire: ; RV32IA-LABEL: atomicrmw_umax_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB211_2 ; RV32IA-NEXT: j .LBB211_2
; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB211_7 ; RV32IA-NEXT: bnez a0, .LBB211_7
; RV32IA-NEXT: .LBB211_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB211_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB211_4 ; RV32IA-NEXT: beq a5, s1, .LBB211_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB211_1 ; RV32IA-NEXT: j .LBB211_1
; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_acquire: ; RV64I-LABEL: atomicrmw_umax_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB211_2 ; RV64I-NEXT: j .LBB211_2
; RV64I-NEXT: .LBB211_1: # %atomicrmw.start ; RV64I-NEXT: .LBB211_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB211_4 ; RV64I-NEXT: bnez a0, .LBB211_4
; RV64I-NEXT: .LBB211_2: # %atomicrmw.start ; RV64I-NEXT: .LBB211_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB211_1 ; RV64I-NEXT: bltu s1, a3, .LBB211_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB211_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB211_1 ; RV64I-NEXT: j .LBB211_1
; RV64I-NEXT: .LBB211_4: # %atomicrmw.end ; RV64I-NEXT: .LBB211_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_acquire: ; RV64IA-LABEL: atomicrmw_umax_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b acquire %1 = atomicrmw umax i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_release: ; RV32I-LABEL: atomicrmw_umax_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB212_2 ; RV32I-NEXT: j .LBB212_2
; RV32I-NEXT: .LBB212_1: # %atomicrmw.start ; RV32I-NEXT: .LBB212_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB212_7 ; RV32I-NEXT: bnez a0, .LBB212_7
; RV32I-NEXT: .LBB212_2: # %atomicrmw.start ; RV32I-NEXT: .LBB212_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB212_4 ; RV32I-NEXT: beq a5, s1, .LBB212_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB212_1 ; RV32I-NEXT: j .LBB212_1
; RV32I-NEXT: .LBB212_7: # %atomicrmw.end ; RV32I-NEXT: .LBB212_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_release: ; RV32IA-LABEL: atomicrmw_umax_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB212_2 ; RV32IA-NEXT: j .LBB212_2
; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB212_7 ; RV32IA-NEXT: bnez a0, .LBB212_7
; RV32IA-NEXT: .LBB212_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB212_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB212_4 ; RV32IA-NEXT: beq a5, s1, .LBB212_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB212_1 ; RV32IA-NEXT: j .LBB212_1
; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_release: ; RV64I-LABEL: atomicrmw_umax_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB212_2 ; RV64I-NEXT: j .LBB212_2
; RV64I-NEXT: .LBB212_1: # %atomicrmw.start ; RV64I-NEXT: .LBB212_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB212_4 ; RV64I-NEXT: bnez a0, .LBB212_4
; RV64I-NEXT: .LBB212_2: # %atomicrmw.start ; RV64I-NEXT: .LBB212_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB212_1 ; RV64I-NEXT: bltu s1, a3, .LBB212_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB212_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB212_1 ; RV64I-NEXT: j .LBB212_1
; RV64I-NEXT: .LBB212_4: # %atomicrmw.end ; RV64I-NEXT: .LBB212_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_release: ; RV64IA-LABEL: atomicrmw_umax_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b release %1 = atomicrmw umax i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB213_2 ; RV32I-NEXT: j .LBB213_2
; RV32I-NEXT: .LBB213_1: # %atomicrmw.start ; RV32I-NEXT: .LBB213_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB213_7 ; RV32I-NEXT: bnez a0, .LBB213_7
; RV32I-NEXT: .LBB213_2: # %atomicrmw.start ; RV32I-NEXT: .LBB213_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB213_4 ; RV32I-NEXT: beq a5, s1, .LBB213_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB213_1 ; RV32I-NEXT: j .LBB213_1
; RV32I-NEXT: .LBB213_7: # %atomicrmw.end ; RV32I-NEXT: .LBB213_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB213_2 ; RV32IA-NEXT: j .LBB213_2
; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB213_7 ; RV32IA-NEXT: bnez a0, .LBB213_7
; RV32IA-NEXT: .LBB213_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB213_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB213_4 ; RV32IA-NEXT: beq a5, s1, .LBB213_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB213_1 ; RV32IA-NEXT: j .LBB213_1
; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB213_2 ; RV64I-NEXT: j .LBB213_2
; RV64I-NEXT: .LBB213_1: # %atomicrmw.start ; RV64I-NEXT: .LBB213_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB213_4 ; RV64I-NEXT: bnez a0, .LBB213_4
; RV64I-NEXT: .LBB213_2: # %atomicrmw.start ; RV64I-NEXT: .LBB213_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB213_1 ; RV64I-NEXT: bltu s1, a3, .LBB213_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB213_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB213_1 ; RV64I-NEXT: j .LBB213_1
; RV64I-NEXT: .LBB213_4: # %atomicrmw.end ; RV64I-NEXT: .LBB213_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b acq_rel %1 = atomicrmw umax i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i64_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB214_2 ; RV32I-NEXT: j .LBB214_2
; RV32I-NEXT: .LBB214_1: # %atomicrmw.start ; RV32I-NEXT: .LBB214_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB214_7 ; RV32I-NEXT: bnez a0, .LBB214_7
; RV32I-NEXT: .LBB214_2: # %atomicrmw.start ; RV32I-NEXT: .LBB214_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB214_4 ; RV32I-NEXT: beq a5, s1, .LBB214_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB214_1 ; RV32I-NEXT: j .LBB214_1
; RV32I-NEXT: .LBB214_7: # %atomicrmw.end ; RV32I-NEXT: .LBB214_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB214_2 ; RV32IA-NEXT: j .LBB214_2
; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB214_7 ; RV32IA-NEXT: bnez a0, .LBB214_7
; RV32IA-NEXT: .LBB214_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB214_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB214_4 ; RV32IA-NEXT: beq a5, s1, .LBB214_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB214_1 ; RV32IA-NEXT: j .LBB214_1
; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i64_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB214_2 ; RV64I-NEXT: j .LBB214_2
; RV64I-NEXT: .LBB214_1: # %atomicrmw.start ; RV64I-NEXT: .LBB214_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB214_4 ; RV64I-NEXT: bnez a0, .LBB214_4
; RV64I-NEXT: .LBB214_2: # %atomicrmw.start ; RV64I-NEXT: .LBB214_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB214_1 ; RV64I-NEXT: bltu s1, a3, .LBB214_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB214_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB214_1 ; RV64I-NEXT: j .LBB214_1
; RV64I-NEXT: .LBB214_4: # %atomicrmw.end ; RV64I-NEXT: .LBB214_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i64* %a, i64 %b seq_cst %1 = atomicrmw umax i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_monotonic: ; RV32I-LABEL: atomicrmw_umin_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB215_2 ; RV32I-NEXT: j .LBB215_2
; RV32I-NEXT: .LBB215_1: # %atomicrmw.start ; RV32I-NEXT: .LBB215_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB215_7 ; RV32I-NEXT: bnez a0, .LBB215_7
; RV32I-NEXT: .LBB215_2: # %atomicrmw.start ; RV32I-NEXT: .LBB215_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB215_4 ; RV32I-NEXT: beq a5, s1, .LBB215_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB215_1 ; RV32I-NEXT: j .LBB215_1
; RV32I-NEXT: .LBB215_7: # %atomicrmw.end ; RV32I-NEXT: .LBB215_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB215_2 ; RV32IA-NEXT: j .LBB215_2
; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB215_7 ; RV32IA-NEXT: bnez a0, .LBB215_7
; RV32IA-NEXT: .LBB215_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB215_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB215_4 ; RV32IA-NEXT: beq a5, s1, .LBB215_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB215_1 ; RV32IA-NEXT: j .LBB215_1
; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_monotonic: ; RV64I-LABEL: atomicrmw_umin_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB215_2 ; RV64I-NEXT: j .LBB215_2
; RV64I-NEXT: .LBB215_1: # %atomicrmw.start ; RV64I-NEXT: .LBB215_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB215_4 ; RV64I-NEXT: bnez a0, .LBB215_4
; RV64I-NEXT: .LBB215_2: # %atomicrmw.start ; RV64I-NEXT: .LBB215_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB215_1 ; RV64I-NEXT: bgeu s1, a3, .LBB215_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB215_1 ; RV64I-NEXT: j .LBB215_1
; RV64I-NEXT: .LBB215_4: # %atomicrmw.end ; RV64I-NEXT: .LBB215_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d a0, a1, (a0) ; RV64IA-NEXT: amominu.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b monotonic %1 = atomicrmw umin i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_acquire: ; RV32I-LABEL: atomicrmw_umin_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB216_2 ; RV32I-NEXT: j .LBB216_2
; RV32I-NEXT: .LBB216_1: # %atomicrmw.start ; RV32I-NEXT: .LBB216_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB216_7 ; RV32I-NEXT: bnez a0, .LBB216_7
; RV32I-NEXT: .LBB216_2: # %atomicrmw.start ; RV32I-NEXT: .LBB216_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB216_4 ; RV32I-NEXT: beq a5, s1, .LBB216_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB216_1 ; RV32I-NEXT: j .LBB216_1
; RV32I-NEXT: .LBB216_7: # %atomicrmw.end ; RV32I-NEXT: .LBB216_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_acquire: ; RV32IA-LABEL: atomicrmw_umin_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB216_2 ; RV32IA-NEXT: j .LBB216_2
; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB216_7 ; RV32IA-NEXT: bnez a0, .LBB216_7
; RV32IA-NEXT: .LBB216_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB216_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB216_4 ; RV32IA-NEXT: beq a5, s1, .LBB216_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB216_1 ; RV32IA-NEXT: j .LBB216_1
; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_acquire: ; RV64I-LABEL: atomicrmw_umin_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB216_2 ; RV64I-NEXT: j .LBB216_2
; RV64I-NEXT: .LBB216_1: # %atomicrmw.start ; RV64I-NEXT: .LBB216_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB216_4 ; RV64I-NEXT: bnez a0, .LBB216_4
; RV64I-NEXT: .LBB216_2: # %atomicrmw.start ; RV64I-NEXT: .LBB216_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB216_1 ; RV64I-NEXT: bgeu s1, a3, .LBB216_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB216_1 ; RV64I-NEXT: j .LBB216_1
; RV64I-NEXT: .LBB216_4: # %atomicrmw.end ; RV64I-NEXT: .LBB216_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_acquire: ; RV64IA-LABEL: atomicrmw_umin_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aq a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b acquire %1 = atomicrmw umin i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_release: ; RV32I-LABEL: atomicrmw_umin_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB217_2 ; RV32I-NEXT: j .LBB217_2
; RV32I-NEXT: .LBB217_1: # %atomicrmw.start ; RV32I-NEXT: .LBB217_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB217_7 ; RV32I-NEXT: bnez a0, .LBB217_7
; RV32I-NEXT: .LBB217_2: # %atomicrmw.start ; RV32I-NEXT: .LBB217_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB217_4 ; RV32I-NEXT: beq a5, s1, .LBB217_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB217_1 ; RV32I-NEXT: j .LBB217_1
; RV32I-NEXT: .LBB217_7: # %atomicrmw.end ; RV32I-NEXT: .LBB217_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_release: ; RV32IA-LABEL: atomicrmw_umin_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB217_2 ; RV32IA-NEXT: j .LBB217_2
; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB217_7 ; RV32IA-NEXT: bnez a0, .LBB217_7
; RV32IA-NEXT: .LBB217_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB217_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB217_4 ; RV32IA-NEXT: beq a5, s1, .LBB217_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB217_1 ; RV32IA-NEXT: j .LBB217_1
; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_release: ; RV64I-LABEL: atomicrmw_umin_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB217_2 ; RV64I-NEXT: j .LBB217_2
; RV64I-NEXT: .LBB217_1: # %atomicrmw.start ; RV64I-NEXT: .LBB217_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB217_4 ; RV64I-NEXT: bnez a0, .LBB217_4
; RV64I-NEXT: .LBB217_2: # %atomicrmw.start ; RV64I-NEXT: .LBB217_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB217_1 ; RV64I-NEXT: bgeu s1, a3, .LBB217_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB217_1 ; RV64I-NEXT: j .LBB217_1
; RV64I-NEXT: .LBB217_4: # %atomicrmw.end ; RV64I-NEXT: .LBB217_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_release: ; RV64IA-LABEL: atomicrmw_umin_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.rl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b release %1 = atomicrmw umin i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB218_2 ; RV32I-NEXT: j .LBB218_2
; RV32I-NEXT: .LBB218_1: # %atomicrmw.start ; RV32I-NEXT: .LBB218_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB218_7 ; RV32I-NEXT: bnez a0, .LBB218_7
; RV32I-NEXT: .LBB218_2: # %atomicrmw.start ; RV32I-NEXT: .LBB218_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB218_4 ; RV32I-NEXT: beq a5, s1, .LBB218_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB218_1 ; RV32I-NEXT: j .LBB218_1
; RV32I-NEXT: .LBB218_7: # %atomicrmw.end ; RV32I-NEXT: .LBB218_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB218_2 ; RV32IA-NEXT: j .LBB218_2
; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB218_7 ; RV32IA-NEXT: bnez a0, .LBB218_7
; RV32IA-NEXT: .LBB218_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB218_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB218_4 ; RV32IA-NEXT: beq a5, s1, .LBB218_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB218_1 ; RV32IA-NEXT: j .LBB218_1
; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB218_2 ; RV64I-NEXT: j .LBB218_2
; RV64I-NEXT: .LBB218_1: # %atomicrmw.start ; RV64I-NEXT: .LBB218_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB218_4 ; RV64I-NEXT: bnez a0, .LBB218_4
; RV64I-NEXT: .LBB218_2: # %atomicrmw.start ; RV64I-NEXT: .LBB218_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB218_1 ; RV64I-NEXT: bgeu s1, a3, .LBB218_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB218_1 ; RV64I-NEXT: j .LBB218_1
; RV64I-NEXT: .LBB218_4: # %atomicrmw.end ; RV64I-NEXT: .LBB218_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b acq_rel %1 = atomicrmw umin i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i64_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB219_2 ; RV32I-NEXT: j .LBB219_2
; RV32I-NEXT: .LBB219_1: # %atomicrmw.start ; RV32I-NEXT: .LBB219_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB219_7 ; RV32I-NEXT: bnez a0, .LBB219_7
; RV32I-NEXT: .LBB219_2: # %atomicrmw.start ; RV32I-NEXT: .LBB219_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB219_4 ; RV32I-NEXT: beq a5, s1, .LBB219_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB219_1 ; RV32I-NEXT: j .LBB219_1
; RV32I-NEXT: .LBB219_7: # %atomicrmw.end ; RV32I-NEXT: .LBB219_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB219_2 ; RV32IA-NEXT: j .LBB219_2
; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB219_7 ; RV32IA-NEXT: bnez a0, .LBB219_7
; RV32IA-NEXT: .LBB219_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB219_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB219_4 ; RV32IA-NEXT: beq a5, s1, .LBB219_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB219_1 ; RV32IA-NEXT: j .LBB219_1
; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB219_2 ; RV64I-NEXT: j .LBB219_2
; RV64I-NEXT: .LBB219_1: # %atomicrmw.start ; RV64I-NEXT: .LBB219_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB219_4 ; RV64I-NEXT: bnez a0, .LBB219_4
; RV64I-NEXT: .LBB219_2: # %atomicrmw.start ; RV64I-NEXT: .LBB219_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB219_1 ; RV64I-NEXT: bgeu s1, a3, .LBB219_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB219_1 ; RV64I-NEXT: j .LBB219_1
; RV64I-NEXT: .LBB219_4: # %atomicrmw.end ; RV64I-NEXT: .LBB219_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i64* %a, i64 %b seq_cst %1 = atomicrmw umin i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; RV32I-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a) %tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp ret i64 %tmp
} }
define i8 @test_cttz_i8(i8 %a) nounwind { define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8: ; RV32I-LABEL: test_cttz_i8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a0, 255 ; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2 ; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8 ; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end ; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 false) %tmp = call i8 @llvm.cttz.i8(i8 %a, i1 false)
ret i8 %tmp ret i8 %tmp
} }
define i16 @test_cttz_i16(i16 %a) nounwind { define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16: ; RV32I-LABEL: test_cttz_i16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1 ; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_2 ; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB4_3 ; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16 ; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end ; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 false) %tmp = call i16 @llvm.cttz.i16(i16 %a, i1 false)
ret i16 %tmp ret i16 %tmp
} }
define i32 @test_cttz_i32(i32 %a) nounwind { define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32: ; RV32I-LABEL: test_cttz_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB5_2 ; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB5_3 ; RV32I-NEXT: j .LBB5_3
; RV32I-NEXT: .LBB5_2: ; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end ; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false) %tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %tmp ret i32 %tmp
} }
define i32 @test_ctlz_i32(i32 %a) nounwind { define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctlz_i32: ; RV32I-LABEL: test_ctlz_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB6_2 ; RV32I-NEXT: beqz a0, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
Show All 15 Lines
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB6_3 ; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end ; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %tmp ret i32 %tmp
} }
define i64 @test_cttz_i64(i64 %a) nounwind { define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64: ; RV32I-LABEL: test_cttz_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB7_2 ; RV32I-NEXT: bnez s4, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB7_3: ; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp) ; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false) %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %tmp ret i64 %tmp
} }
define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind { define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8_zero_undef: ; RV32I-LABEL: test_cttz_i8_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true) %tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
ret i8 %tmp ret i8 %tmp
} }
define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind { define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16_zero_undef: ; RV32I-LABEL: test_cttz_i16_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true) %tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
ret i16 %tmp ret i16 %tmp
} }
define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32_zero_undef: ; RV32I-LABEL: test_cttz_i32_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 true) %tmp = call i32 @llvm.cttz.i32(i32 %a, i1 true)
ret i32 %tmp ret i32 %tmp
} }
define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64_zero_undef: ; RV32I-LABEL: test_cttz_i64_zero_undef:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB11_2 ; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp) ; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true) %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true)
ret i64 %tmp ret i64 %tmp
} }
define i32 @test_ctpop_i32(i32 %a) nounwind { define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctpop_i32: ; RV32I-LABEL: test_ctpop_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/byval.ll

Show All 15 Linesentry:
ret i32 %1 ret i32 %1
} }
define void @caller() nounwind { define void @caller() nounwind {
; RV32I-LABEL: caller: ; RV32I-LABEL: caller:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(foo) ; RV32I-NEXT: lui a0, %hi(foo)
; RV32I-NEXT: lw a1, %lo(foo)(a0) ; RV32I-NEXT: lw a1, %lo(foo)(a0)
; RV32I-NEXT: sw a1, 12(sp) ; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a0, a0, %lo(foo) ; RV32I-NEXT: addi a0, a0, %lo(foo)
; RV32I-NEXT: lw a1, 12(a0) ; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: sw a1, 24(sp) ; RV32I-NEXT: sw a1, 24(sp)
; RV32I-NEXT: lw a1, 8(a0) ; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: sw a1, 20(sp) ; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: addi a0, sp, 12 ; RV32I-NEXT: addi a0, sp, 12
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%call = call i32 @callee(%struct.Foo* byval(%struct.Foo) @foo) %call = call i32 @callee(%struct.Foo* byval(%struct.Foo) @foo)
ret void ret void
} }

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
; LP64-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64-NEXT: fsw ft2, %lo(var+8)(a0)
; LP64-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64-NEXT: fsw ft1, %lo(var+4)(a0)
; LP64-NEXT: fsw ft0, %lo(var)(a0) ; LP64-NEXT: fsw ft0, %lo(var)(a0)
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32F-LABEL: callee: ; ILP32F-LABEL: callee:
; ILP32F: # %bb.0: ; ILP32F: # %bb.0:
; ILP32F-NEXT: addi sp, sp, -48 ; ILP32F-NEXT: addi sp, sp, -48
; ILP32F-NEXT: fsw fs0, 44(sp) ; ILP32F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs1, 40(sp) ; ILP32F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs2, 36(sp) ; ILP32F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs3, 32(sp) ; ILP32F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs4, 28(sp) ; ILP32F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs5, 24(sp) ; ILP32F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs6, 20(sp) ; ILP32F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs7, 16(sp) ; ILP32F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs8, 12(sp) ; ILP32F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs9, 8(sp) ; ILP32F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs10, 4(sp) ; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 0(sp) ; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui a0, %hi(var) ; ILP32F-NEXT: lui a0, %hi(var)
; ILP32F-NEXT: flw ft0, %lo(var)(a0) ; ILP32F-NEXT: flw ft0, %lo(var)(a0)
; ILP32F-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32F-NEXT: flw ft1, %lo(var+4)(a0)
; ILP32F-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: flw ft2, %lo(var+8)(a0)
; ILP32F-NEXT: flw ft3, %lo(var+12)(a0) ; ILP32F-NEXT: flw ft3, %lo(var+12)(a0)
; ILP32F-NEXT: addi a1, a0, %lo(var) ; ILP32F-NEXT: addi a1, a0, %lo(var)
; ILP32F-NEXT: flw ft4, 16(a1) ; ILP32F-NEXT: flw ft4, 16(a1)
; ILP32F-NEXT: flw ft5, 20(a1) ; ILP32F-NEXT: flw ft5, 20(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; ILP32F-NEXT: fsw ft7, 28(a1) ; ILP32F-NEXT: fsw ft7, 28(a1)
; ILP32F-NEXT: fsw ft6, 24(a1) ; ILP32F-NEXT: fsw ft6, 24(a1)
; ILP32F-NEXT: fsw ft5, 20(a1) ; ILP32F-NEXT: fsw ft5, 20(a1)
; ILP32F-NEXT: fsw ft4, 16(a1) ; ILP32F-NEXT: fsw ft4, 16(a1)
; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0)
; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0)
; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0) ; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0)
; ILP32F-NEXT: fsw ft0, %lo(var)(a0) ; ILP32F-NEXT: fsw ft0, %lo(var)(a0)
; ILP32F-NEXT: flw fs11, 0(sp) ; ILP32F-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs10, 4(sp) ; ILP32F-NEXT: flw fs10, 4(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs9, 8(sp) ; ILP32F-NEXT: flw fs9, 8(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs8, 12(sp) ; ILP32F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs7, 16(sp) ; ILP32F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs6, 20(sp) ; ILP32F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs5, 24(sp) ; ILP32F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs4, 28(sp) ; ILP32F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs3, 32(sp) ; ILP32F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 36(sp) ; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 40(sp) ; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs0, 44(sp) ; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: addi sp, sp, 48 ; ILP32F-NEXT: addi sp, sp, 48
; ILP32F-NEXT: ret ; ILP32F-NEXT: ret
; ;
; LP64F-LABEL: callee: ; LP64F-LABEL: callee:
; LP64F: # %bb.0: ; LP64F: # %bb.0:
; LP64F-NEXT: addi sp, sp, -48 ; LP64F-NEXT: addi sp, sp, -48
; LP64F-NEXT: fsw fs0, 44(sp) ; LP64F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs1, 40(sp) ; LP64F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs2, 36(sp) ; LP64F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs3, 32(sp) ; LP64F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs4, 28(sp) ; LP64F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs5, 24(sp) ; LP64F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs6, 20(sp) ; LP64F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs7, 16(sp) ; LP64F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs8, 12(sp) ; LP64F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs9, 8(sp) ; LP64F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs10, 4(sp) ; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 0(sp) ; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui a0, %hi(var) ; LP64F-NEXT: lui a0, %hi(var)
; LP64F-NEXT: flw ft0, %lo(var)(a0) ; LP64F-NEXT: flw ft0, %lo(var)(a0)
; LP64F-NEXT: flw ft1, %lo(var+4)(a0) ; LP64F-NEXT: flw ft1, %lo(var+4)(a0)
; LP64F-NEXT: flw ft2, %lo(var+8)(a0) ; LP64F-NEXT: flw ft2, %lo(var+8)(a0)
; LP64F-NEXT: flw ft3, %lo(var+12)(a0) ; LP64F-NEXT: flw ft3, %lo(var+12)(a0)
; LP64F-NEXT: addi a1, a0, %lo(var) ; LP64F-NEXT: addi a1, a0, %lo(var)
; LP64F-NEXT: flw ft4, 16(a1) ; LP64F-NEXT: flw ft4, 16(a1)
; LP64F-NEXT: flw ft5, 20(a1) ; LP64F-NEXT: flw ft5, 20(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; LP64F-NEXT: fsw ft7, 28(a1) ; LP64F-NEXT: fsw ft7, 28(a1)
; LP64F-NEXT: fsw ft6, 24(a1) ; LP64F-NEXT: fsw ft6, 24(a1)
; LP64F-NEXT: fsw ft5, 20(a1) ; LP64F-NEXT: fsw ft5, 20(a1)
; LP64F-NEXT: fsw ft4, 16(a1) ; LP64F-NEXT: fsw ft4, 16(a1)
; LP64F-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64F-NEXT: fsw ft3, %lo(var+12)(a0)
; LP64F-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64F-NEXT: fsw ft2, %lo(var+8)(a0)
; LP64F-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64F-NEXT: fsw ft1, %lo(var+4)(a0)
; LP64F-NEXT: fsw ft0, %lo(var)(a0) ; LP64F-NEXT: fsw ft0, %lo(var)(a0)
; LP64F-NEXT: flw fs11, 0(sp) ; LP64F-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs10, 4(sp) ; LP64F-NEXT: flw fs10, 4(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs9, 8(sp) ; LP64F-NEXT: flw fs9, 8(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs8, 12(sp) ; LP64F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs7, 16(sp) ; LP64F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs6, 20(sp) ; LP64F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs5, 24(sp) ; LP64F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs4, 28(sp) ; LP64F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs3, 32(sp) ; LP64F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 36(sp) ; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 40(sp) ; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs0, 44(sp) ; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: addi sp, sp, 48 ; LP64F-NEXT: addi sp, sp, 48
; LP64F-NEXT: ret ; LP64F-NEXT: ret
; ;
; ILP32D-LABEL: callee: ; ILP32D-LABEL: callee:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
; ILP32D-NEXT: addi sp, sp, -96 ; ILP32D-NEXT: addi sp, sp, -96
; ILP32D-NEXT: fsd fs0, 88(sp) ; ILP32D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs1, 80(sp) ; ILP32D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs2, 72(sp) ; ILP32D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs3, 64(sp) ; ILP32D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs4, 56(sp) ; ILP32D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs5, 48(sp) ; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 40(sp) ; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 32(sp) ; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 24(sp) ; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 16(sp) ; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 8(sp) ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var) ; ILP32D-NEXT: lui a0, %hi(var)
; ILP32D-NEXT: flw ft0, %lo(var)(a0) ; ILP32D-NEXT: flw ft0, %lo(var)(a0)
; ILP32D-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32D-NEXT: flw ft1, %lo(var+4)(a0)
; ILP32D-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: flw ft2, %lo(var+8)(a0)
; ILP32D-NEXT: flw ft3, %lo(var+12)(a0) ; ILP32D-NEXT: flw ft3, %lo(var+12)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var) ; ILP32D-NEXT: addi a1, a0, %lo(var)
; ILP32D-NEXT: flw ft4, 16(a1) ; ILP32D-NEXT: flw ft4, 16(a1)
; ILP32D-NEXT: flw ft5, 20(a1) ; ILP32D-NEXT: flw ft5, 20(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; ILP32D-NEXT: fsw ft7, 28(a1) ; ILP32D-NEXT: fsw ft7, 28(a1)
; ILP32D-NEXT: fsw ft6, 24(a1) ; ILP32D-NEXT: fsw ft6, 24(a1)
; ILP32D-NEXT: fsw ft5, 20(a1) ; ILP32D-NEXT: fsw ft5, 20(a1)
; ILP32D-NEXT: fsw ft4, 16(a1) ; ILP32D-NEXT: fsw ft4, 16(a1)
; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0)
; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0)
; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0) ; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0)
; ILP32D-NEXT: fsw ft0, %lo(var)(a0) ; ILP32D-NEXT: fsw ft0, %lo(var)(a0)
; ILP32D-NEXT: fld fs11, 0(sp) ; ILP32D-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs10, 8(sp) ; ILP32D-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs9, 16(sp) ; ILP32D-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs8, 24(sp) ; ILP32D-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 32(sp) ; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 40(sp) ; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 48(sp) ; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 56(sp) ; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 64(sp) ; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs0, 88(sp) ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 96 ; ILP32D-NEXT: addi sp, sp, 96
; ILP32D-NEXT: ret ; ILP32D-NEXT: ret
; ;
; LP64D-LABEL: callee: ; LP64D-LABEL: callee:
; LP64D: # %bb.0: ; LP64D: # %bb.0:
; LP64D-NEXT: addi sp, sp, -96 ; LP64D-NEXT: addi sp, sp, -96
; LP64D-NEXT: fsd fs0, 88(sp) ; LP64D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs1, 80(sp) ; LP64D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs2, 72(sp) ; LP64D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs3, 64(sp) ; LP64D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs4, 56(sp) ; LP64D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs5, 48(sp) ; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 40(sp) ; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 32(sp) ; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 24(sp) ; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 16(sp) ; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 8(sp) ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var) ; LP64D-NEXT: lui a0, %hi(var)
; LP64D-NEXT: flw ft0, %lo(var)(a0) ; LP64D-NEXT: flw ft0, %lo(var)(a0)
; LP64D-NEXT: flw ft1, %lo(var+4)(a0) ; LP64D-NEXT: flw ft1, %lo(var+4)(a0)
; LP64D-NEXT: flw ft2, %lo(var+8)(a0) ; LP64D-NEXT: flw ft2, %lo(var+8)(a0)
; LP64D-NEXT: flw ft3, %lo(var+12)(a0) ; LP64D-NEXT: flw ft3, %lo(var+12)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var) ; LP64D-NEXT: addi a1, a0, %lo(var)
; LP64D-NEXT: flw ft4, 16(a1) ; LP64D-NEXT: flw ft4, 16(a1)
; LP64D-NEXT: flw ft5, 20(a1) ; LP64D-NEXT: flw ft5, 20(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; LP64D-NEXT: fsw ft7, 28(a1) ; LP64D-NEXT: fsw ft7, 28(a1)
; LP64D-NEXT: fsw ft6, 24(a1) ; LP64D-NEXT: fsw ft6, 24(a1)
; LP64D-NEXT: fsw ft5, 20(a1) ; LP64D-NEXT: fsw ft5, 20(a1)
; LP64D-NEXT: fsw ft4, 16(a1) ; LP64D-NEXT: fsw ft4, 16(a1)
; LP64D-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64D-NEXT: fsw ft3, %lo(var+12)(a0)
; LP64D-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64D-NEXT: fsw ft2, %lo(var+8)(a0)
; LP64D-NEXT: fsw ft1, %lo(var+4)(a0) ; LP64D-NEXT: fsw ft1, %lo(var+4)(a0)
; LP64D-NEXT: fsw ft0, %lo(var)(a0) ; LP64D-NEXT: fsw ft0, %lo(var)(a0)
; LP64D-NEXT: fld fs11, 0(sp) ; LP64D-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs10, 8(sp) ; LP64D-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs9, 16(sp) ; LP64D-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs8, 24(sp) ; LP64D-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 32(sp) ; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 40(sp) ; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 48(sp) ; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 56(sp) ; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 64(sp) ; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 88(sp) ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: addi sp, sp, 96 ; LP64D-NEXT: addi sp, sp, 96
; LP64D-NEXT: ret ; LP64D-NEXT: ret
%val = load [32 x float], [32 x float]* @var %val = load [32 x float], [32 x float]* @var
store volatile [32 x float] %val, [32 x float]* @var store volatile [32 x float] %val, [32 x float]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
; ;
; For the soft float ABIs, no floating point registers are preserved, and ; For the soft float ABIs, no floating point registers are preserved, and
; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs, ; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs,
; fs0-fs11 are preserved across calls. ; fs0-fs11 are preserved across calls.
define void @caller() nounwind { define void @caller() nounwind {
; ILP32-LABEL: caller: ; ILP32-LABEL: caller:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: addi sp, sp, -144 ; ILP32-NEXT: addi sp, sp, -144
; ILP32-NEXT: sw ra, 140(sp) ; ILP32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 136(sp) ; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 132(sp) ; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var) ; ILP32-NEXT: lui s0, %hi(var)
; ILP32-NEXT: flw ft0, %lo(var)(s0) ; ILP32-NEXT: flw ft0, %lo(var)(s0)
; ILP32-NEXT: fsw ft0, 128(sp) ; ILP32-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32-NEXT: flw ft0, %lo(var+4)(s0)
; ILP32-NEXT: fsw ft0, 124(sp) ; ILP32-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32-NEXT: flw ft0, %lo(var+8)(s0)
; ILP32-NEXT: fsw ft0, 120(sp) ; ILP32-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32-NEXT: flw ft0, %lo(var+12)(s0)
; ILP32-NEXT: fsw ft0, 116(sp) ; ILP32-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: addi s1, s0, %lo(var)
; ILP32-NEXT: flw ft0, 16(s1) ; ILP32-NEXT: flw ft0, 16(s1)
; ILP32-NEXT: fsw ft0, 112(sp) ; ILP32-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 20(s1) ; ILP32-NEXT: flw ft0, 20(s1)
; ILP32-NEXT: fsw ft0, 108(sp) ; ILP32-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 24(s1) ; ILP32-NEXT: flw ft0, 24(s1)
; ILP32-NEXT: fsw ft0, 104(sp) ; ILP32-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 28(s1) ; ILP32-NEXT: flw ft0, 28(s1)
; ILP32-NEXT: fsw ft0, 100(sp) ; ILP32-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 32(s1) ; ILP32-NEXT: flw ft0, 32(s1)
; ILP32-NEXT: fsw ft0, 96(sp) ; ILP32-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 36(s1) ; ILP32-NEXT: flw ft0, 36(s1)
; ILP32-NEXT: fsw ft0, 92(sp) ; ILP32-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 40(s1) ; ILP32-NEXT: flw ft0, 40(s1)
; ILP32-NEXT: fsw ft0, 88(sp) ; ILP32-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 44(s1) ; ILP32-NEXT: flw ft0, 44(s1)
; ILP32-NEXT: fsw ft0, 84(sp) ; ILP32-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 48(s1) ; ILP32-NEXT: flw ft0, 48(s1)
; ILP32-NEXT: fsw ft0, 80(sp) ; ILP32-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 52(s1) ; ILP32-NEXT: flw ft0, 52(s1)
; ILP32-NEXT: fsw ft0, 76(sp) ; ILP32-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 56(s1) ; ILP32-NEXT: flw ft0, 56(s1)
; ILP32-NEXT: fsw ft0, 72(sp) ; ILP32-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 60(s1) ; ILP32-NEXT: flw ft0, 60(s1)
; ILP32-NEXT: fsw ft0, 68(sp) ; ILP32-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 64(s1) ; ILP32-NEXT: flw ft0, 64(s1)
; ILP32-NEXT: fsw ft0, 64(sp) ; ILP32-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 68(s1) ; ILP32-NEXT: flw ft0, 68(s1)
; ILP32-NEXT: fsw ft0, 60(sp) ; ILP32-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 72(s1) ; ILP32-NEXT: flw ft0, 72(s1)
; ILP32-NEXT: fsw ft0, 56(sp) ; ILP32-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 76(s1) ; ILP32-NEXT: flw ft0, 76(s1)
; ILP32-NEXT: fsw ft0, 52(sp) ; ILP32-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 80(s1) ; ILP32-NEXT: flw ft0, 80(s1)
; ILP32-NEXT: fsw ft0, 48(sp) ; ILP32-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 84(s1) ; ILP32-NEXT: flw ft0, 84(s1)
; ILP32-NEXT: fsw ft0, 44(sp) ; ILP32-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 88(s1) ; ILP32-NEXT: flw ft0, 88(s1)
; ILP32-NEXT: fsw ft0, 40(sp) ; ILP32-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 92(s1) ; ILP32-NEXT: flw ft0, 92(s1)
; ILP32-NEXT: fsw ft0, 36(sp) ; ILP32-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 96(s1) ; ILP32-NEXT: flw ft0, 96(s1)
; ILP32-NEXT: fsw ft0, 32(sp) ; ILP32-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 100(s1) ; ILP32-NEXT: flw ft0, 100(s1)
; ILP32-NEXT: fsw ft0, 28(sp) ; ILP32-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 104(s1) ; ILP32-NEXT: flw ft0, 104(s1)
; ILP32-NEXT: fsw ft0, 24(sp) ; ILP32-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 108(s1) ; ILP32-NEXT: flw ft0, 108(s1)
; ILP32-NEXT: fsw ft0, 20(sp) ; ILP32-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 112(s1) ; ILP32-NEXT: flw ft0, 112(s1)
; ILP32-NEXT: fsw ft0, 16(sp) ; ILP32-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 116(s1) ; ILP32-NEXT: flw ft0, 116(s1)
; ILP32-NEXT: fsw ft0, 12(sp) ; ILP32-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 120(s1) ; ILP32-NEXT: flw ft0, 120(s1)
; ILP32-NEXT: fsw ft0, 8(sp) ; ILP32-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 124(s1) ; ILP32-NEXT: flw ft0, 124(s1)
; ILP32-NEXT: fsw ft0, 4(sp) ; ILP32-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; ILP32-NEXT: call callee ; ILP32-NEXT: call callee
; ILP32-NEXT: flw ft0, 4(sp) ; ILP32-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 124(s1) ; ILP32-NEXT: fsw ft0, 124(s1)
; ILP32-NEXT: flw ft0, 8(sp) ; ILP32-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 120(s1) ; ILP32-NEXT: fsw ft0, 120(s1)
; ILP32-NEXT: flw ft0, 12(sp) ; ILP32-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 116(s1) ; ILP32-NEXT: fsw ft0, 116(s1)
; ILP32-NEXT: flw ft0, 16(sp) ; ILP32-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 112(s1) ; ILP32-NEXT: fsw ft0, 112(s1)
; ILP32-NEXT: flw ft0, 20(sp) ; ILP32-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 108(s1) ; ILP32-NEXT: fsw ft0, 108(s1)
; ILP32-NEXT: flw ft0, 24(sp) ; ILP32-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 104(s1) ; ILP32-NEXT: fsw ft0, 104(s1)
; ILP32-NEXT: flw ft0, 28(sp) ; ILP32-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 100(s1) ; ILP32-NEXT: fsw ft0, 100(s1)
; ILP32-NEXT: flw ft0, 32(sp) ; ILP32-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 96(s1) ; ILP32-NEXT: fsw ft0, 96(s1)
; ILP32-NEXT: flw ft0, 36(sp) ; ILP32-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 92(s1) ; ILP32-NEXT: fsw ft0, 92(s1)
; ILP32-NEXT: flw ft0, 40(sp) ; ILP32-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 88(s1) ; ILP32-NEXT: fsw ft0, 88(s1)
; ILP32-NEXT: flw ft0, 44(sp) ; ILP32-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 84(s1) ; ILP32-NEXT: fsw ft0, 84(s1)
; ILP32-NEXT: flw ft0, 48(sp) ; ILP32-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 80(s1) ; ILP32-NEXT: fsw ft0, 80(s1)
; ILP32-NEXT: flw ft0, 52(sp) ; ILP32-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 76(s1) ; ILP32-NEXT: fsw ft0, 76(s1)
; ILP32-NEXT: flw ft0, 56(sp) ; ILP32-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 72(s1) ; ILP32-NEXT: fsw ft0, 72(s1)
; ILP32-NEXT: flw ft0, 60(sp) ; ILP32-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 68(s1) ; ILP32-NEXT: fsw ft0, 68(s1)
; ILP32-NEXT: flw ft0, 64(sp) ; ILP32-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 64(s1) ; ILP32-NEXT: fsw ft0, 64(s1)
; ILP32-NEXT: flw ft0, 68(sp) ; ILP32-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 60(s1) ; ILP32-NEXT: fsw ft0, 60(s1)
; ILP32-NEXT: flw ft0, 72(sp) ; ILP32-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 56(s1) ; ILP32-NEXT: fsw ft0, 56(s1)
; ILP32-NEXT: flw ft0, 76(sp) ; ILP32-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 52(s1) ; ILP32-NEXT: fsw ft0, 52(s1)
; ILP32-NEXT: flw ft0, 80(sp) ; ILP32-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 48(s1) ; ILP32-NEXT: fsw ft0, 48(s1)
; ILP32-NEXT: flw ft0, 84(sp) ; ILP32-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 44(s1) ; ILP32-NEXT: fsw ft0, 44(s1)
; ILP32-NEXT: flw ft0, 88(sp) ; ILP32-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 40(s1) ; ILP32-NEXT: fsw ft0, 40(s1)
; ILP32-NEXT: flw ft0, 92(sp) ; ILP32-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 36(s1) ; ILP32-NEXT: fsw ft0, 36(s1)
; ILP32-NEXT: flw ft0, 96(sp) ; ILP32-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 32(s1) ; ILP32-NEXT: fsw ft0, 32(s1)
; ILP32-NEXT: flw ft0, 100(sp) ; ILP32-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 28(s1) ; ILP32-NEXT: fsw ft0, 28(s1)
; ILP32-NEXT: flw ft0, 104(sp) ; ILP32-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 24(s1) ; ILP32-NEXT: fsw ft0, 24(s1)
; ILP32-NEXT: flw ft0, 108(sp) ; ILP32-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 20(s1) ; ILP32-NEXT: fsw ft0, 20(s1)
; ILP32-NEXT: flw ft0, 112(sp) ; ILP32-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 16(s1) ; ILP32-NEXT: fsw ft0, 16(s1)
; ILP32-NEXT: flw ft0, 116(sp) ; ILP32-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32-NEXT: fsw ft0, %lo(var+12)(s0)
; ILP32-NEXT: flw ft0, 120(sp) ; ILP32-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32-NEXT: fsw ft0, %lo(var+8)(s0)
; ILP32-NEXT: flw ft0, 124(sp) ; ILP32-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32-NEXT: fsw ft0, %lo(var+4)(s0)
; ILP32-NEXT: flw ft0, 128(sp) ; ILP32-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, %lo(var)(s0) ; ILP32-NEXT: fsw ft0, %lo(var)(s0)
; ILP32-NEXT: lw s1, 132(sp) ; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 136(sp) ; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw ra, 140(sp) ; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 144 ; ILP32-NEXT: addi sp, sp, 144
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: caller: ; LP64-LABEL: caller:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: addi sp, sp, -160 ; LP64-NEXT: addi sp, sp, -160
; LP64-NEXT: sd ra, 152(sp) ; LP64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s0, 144(sp) ; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 136(sp) ; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var) ; LP64-NEXT: lui s0, %hi(var)
; LP64-NEXT: flw ft0, %lo(var)(s0) ; LP64-NEXT: flw ft0, %lo(var)(s0)
; LP64-NEXT: fsw ft0, 132(sp) ; LP64-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+4)(s0) ; LP64-NEXT: flw ft0, %lo(var+4)(s0)
; LP64-NEXT: fsw ft0, 128(sp) ; LP64-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+8)(s0) ; LP64-NEXT: flw ft0, %lo(var+8)(s0)
; LP64-NEXT: fsw ft0, 124(sp) ; LP64-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, %lo(var+12)(s0) ; LP64-NEXT: flw ft0, %lo(var+12)(s0)
; LP64-NEXT: fsw ft0, 120(sp) ; LP64-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: addi s1, s0, %lo(var)
; LP64-NEXT: flw ft0, 16(s1) ; LP64-NEXT: flw ft0, 16(s1)
; LP64-NEXT: fsw ft0, 116(sp) ; LP64-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 20(s1) ; LP64-NEXT: flw ft0, 20(s1)
; LP64-NEXT: fsw ft0, 112(sp) ; LP64-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 24(s1) ; LP64-NEXT: flw ft0, 24(s1)
; LP64-NEXT: fsw ft0, 108(sp) ; LP64-NEXT: fsw ft0, 108(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 28(s1) ; LP64-NEXT: flw ft0, 28(s1)
; LP64-NEXT: fsw ft0, 104(sp) ; LP64-NEXT: fsw ft0, 104(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 32(s1) ; LP64-NEXT: flw ft0, 32(s1)
; LP64-NEXT: fsw ft0, 100(sp) ; LP64-NEXT: fsw ft0, 100(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 36(s1) ; LP64-NEXT: flw ft0, 36(s1)
; LP64-NEXT: fsw ft0, 96(sp) ; LP64-NEXT: fsw ft0, 96(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 40(s1) ; LP64-NEXT: flw ft0, 40(s1)
; LP64-NEXT: fsw ft0, 92(sp) ; LP64-NEXT: fsw ft0, 92(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 44(s1) ; LP64-NEXT: flw ft0, 44(s1)
; LP64-NEXT: fsw ft0, 88(sp) ; LP64-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 48(s1) ; LP64-NEXT: flw ft0, 48(s1)
; LP64-NEXT: fsw ft0, 84(sp) ; LP64-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 52(s1) ; LP64-NEXT: flw ft0, 52(s1)
; LP64-NEXT: fsw ft0, 80(sp) ; LP64-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 56(s1) ; LP64-NEXT: flw ft0, 56(s1)
; LP64-NEXT: fsw ft0, 76(sp) ; LP64-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 60(s1) ; LP64-NEXT: flw ft0, 60(s1)
; LP64-NEXT: fsw ft0, 72(sp) ; LP64-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 64(s1) ; LP64-NEXT: flw ft0, 64(s1)
; LP64-NEXT: fsw ft0, 68(sp) ; LP64-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 68(s1) ; LP64-NEXT: flw ft0, 68(s1)
; LP64-NEXT: fsw ft0, 64(sp) ; LP64-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 72(s1) ; LP64-NEXT: flw ft0, 72(s1)
; LP64-NEXT: fsw ft0, 60(sp) ; LP64-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 76(s1) ; LP64-NEXT: flw ft0, 76(s1)
; LP64-NEXT: fsw ft0, 56(sp) ; LP64-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 80(s1) ; LP64-NEXT: flw ft0, 80(s1)
; LP64-NEXT: fsw ft0, 52(sp) ; LP64-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 84(s1) ; LP64-NEXT: flw ft0, 84(s1)
; LP64-NEXT: fsw ft0, 48(sp) ; LP64-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 88(s1) ; LP64-NEXT: flw ft0, 88(s1)
; LP64-NEXT: fsw ft0, 44(sp) ; LP64-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 92(s1) ; LP64-NEXT: flw ft0, 92(s1)
; LP64-NEXT: fsw ft0, 40(sp) ; LP64-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 96(s1) ; LP64-NEXT: flw ft0, 96(s1)
; LP64-NEXT: fsw ft0, 36(sp) ; LP64-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 100(s1) ; LP64-NEXT: flw ft0, 100(s1)
; LP64-NEXT: fsw ft0, 32(sp) ; LP64-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 104(s1) ; LP64-NEXT: flw ft0, 104(s1)
; LP64-NEXT: fsw ft0, 28(sp) ; LP64-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 108(s1) ; LP64-NEXT: flw ft0, 108(s1)
; LP64-NEXT: fsw ft0, 24(sp) ; LP64-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 112(s1) ; LP64-NEXT: flw ft0, 112(s1)
; LP64-NEXT: fsw ft0, 20(sp) ; LP64-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 116(s1) ; LP64-NEXT: flw ft0, 116(s1)
; LP64-NEXT: fsw ft0, 16(sp) ; LP64-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 120(s1) ; LP64-NEXT: flw ft0, 120(s1)
; LP64-NEXT: fsw ft0, 12(sp) ; LP64-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 124(s1) ; LP64-NEXT: flw ft0, 124(s1)
; LP64-NEXT: fsw ft0, 8(sp) ; LP64-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; LP64-NEXT: call callee ; LP64-NEXT: call callee
; LP64-NEXT: flw ft0, 8(sp) ; LP64-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 124(s1) ; LP64-NEXT: fsw ft0, 124(s1)
; LP64-NEXT: flw ft0, 12(sp) ; LP64-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 120(s1) ; LP64-NEXT: fsw ft0, 120(s1)
; LP64-NEXT: flw ft0, 16(sp) ; LP64-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 116(s1) ; LP64-NEXT: fsw ft0, 116(s1)
; LP64-NEXT: flw ft0, 20(sp) ; LP64-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 112(s1) ; LP64-NEXT: fsw ft0, 112(s1)
; LP64-NEXT: flw ft0, 24(sp) ; LP64-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 108(s1) ; LP64-NEXT: fsw ft0, 108(s1)
; LP64-NEXT: flw ft0, 28(sp) ; LP64-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 104(s1) ; LP64-NEXT: fsw ft0, 104(s1)
; LP64-NEXT: flw ft0, 32(sp) ; LP64-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 100(s1) ; LP64-NEXT: fsw ft0, 100(s1)
; LP64-NEXT: flw ft0, 36(sp) ; LP64-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 96(s1) ; LP64-NEXT: fsw ft0, 96(s1)
; LP64-NEXT: flw ft0, 40(sp) ; LP64-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 92(s1) ; LP64-NEXT: fsw ft0, 92(s1)
; LP64-NEXT: flw ft0, 44(sp) ; LP64-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 88(s1) ; LP64-NEXT: fsw ft0, 88(s1)
; LP64-NEXT: flw ft0, 48(sp) ; LP64-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 84(s1) ; LP64-NEXT: fsw ft0, 84(s1)
; LP64-NEXT: flw ft0, 52(sp) ; LP64-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 80(s1) ; LP64-NEXT: fsw ft0, 80(s1)
; LP64-NEXT: flw ft0, 56(sp) ; LP64-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 76(s1) ; LP64-NEXT: fsw ft0, 76(s1)
; LP64-NEXT: flw ft0, 60(sp) ; LP64-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 72(s1) ; LP64-NEXT: fsw ft0, 72(s1)
; LP64-NEXT: flw ft0, 64(sp) ; LP64-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 68(s1) ; LP64-NEXT: fsw ft0, 68(s1)
; LP64-NEXT: flw ft0, 68(sp) ; LP64-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 64(s1) ; LP64-NEXT: fsw ft0, 64(s1)
; LP64-NEXT: flw ft0, 72(sp) ; LP64-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 60(s1) ; LP64-NEXT: fsw ft0, 60(s1)
; LP64-NEXT: flw ft0, 76(sp) ; LP64-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 56(s1) ; LP64-NEXT: fsw ft0, 56(s1)
; LP64-NEXT: flw ft0, 80(sp) ; LP64-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 52(s1) ; LP64-NEXT: fsw ft0, 52(s1)
; LP64-NEXT: flw ft0, 84(sp) ; LP64-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 48(s1) ; LP64-NEXT: fsw ft0, 48(s1)
; LP64-NEXT: flw ft0, 88(sp) ; LP64-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 44(s1) ; LP64-NEXT: fsw ft0, 44(s1)
; LP64-NEXT: flw ft0, 92(sp) ; LP64-NEXT: flw ft0, 92(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 40(s1) ; LP64-NEXT: fsw ft0, 40(s1)
; LP64-NEXT: flw ft0, 96(sp) ; LP64-NEXT: flw ft0, 96(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 36(s1) ; LP64-NEXT: fsw ft0, 36(s1)
; LP64-NEXT: flw ft0, 100(sp) ; LP64-NEXT: flw ft0, 100(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 32(s1) ; LP64-NEXT: fsw ft0, 32(s1)
; LP64-NEXT: flw ft0, 104(sp) ; LP64-NEXT: flw ft0, 104(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 28(s1) ; LP64-NEXT: fsw ft0, 28(s1)
; LP64-NEXT: flw ft0, 108(sp) ; LP64-NEXT: flw ft0, 108(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 24(s1) ; LP64-NEXT: fsw ft0, 24(s1)
; LP64-NEXT: flw ft0, 112(sp) ; LP64-NEXT: flw ft0, 112(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 20(s1) ; LP64-NEXT: fsw ft0, 20(s1)
; LP64-NEXT: flw ft0, 116(sp) ; LP64-NEXT: flw ft0, 116(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 16(s1) ; LP64-NEXT: fsw ft0, 16(s1)
; LP64-NEXT: flw ft0, 120(sp) ; LP64-NEXT: flw ft0, 120(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64-NEXT: fsw ft0, %lo(var+12)(s0)
; LP64-NEXT: flw ft0, 124(sp) ; LP64-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64-NEXT: fsw ft0, %lo(var+8)(s0)
; LP64-NEXT: flw ft0, 128(sp) ; LP64-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64-NEXT: fsw ft0, %lo(var+4)(s0)
; LP64-NEXT: flw ft0, 132(sp) ; LP64-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, %lo(var)(s0) ; LP64-NEXT: fsw ft0, %lo(var)(s0)
; LP64-NEXT: ld s1, 136(sp) ; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 144(sp) ; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64-NEXT: ld ra, 152(sp) ; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64-NEXT: addi sp, sp, 160 ; LP64-NEXT: addi sp, sp, 160
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32F-LABEL: caller: ; ILP32F-LABEL: caller:
; ILP32F: # %bb.0: ; ILP32F: # %bb.0:
; ILP32F-NEXT: addi sp, sp, -144 ; ILP32F-NEXT: addi sp, sp, -144
; ILP32F-NEXT: sw ra, 140(sp) ; ILP32F-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; ILP32F-NEXT: sw s0, 136(sp) ; ILP32F-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; ILP32F-NEXT: sw s1, 132(sp) ; ILP32F-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs0, 128(sp) ; ILP32F-NEXT: fsw fs0, 128(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs1, 124(sp) ; ILP32F-NEXT: fsw fs1, 124(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs2, 120(sp) ; ILP32F-NEXT: fsw fs2, 120(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs3, 116(sp) ; ILP32F-NEXT: fsw fs3, 116(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs4, 112(sp) ; ILP32F-NEXT: fsw fs4, 112(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs5, 108(sp) ; ILP32F-NEXT: fsw fs5, 108(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs6, 104(sp) ; ILP32F-NEXT: fsw fs6, 104(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs7, 100(sp) ; ILP32F-NEXT: fsw fs7, 100(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs8, 96(sp) ; ILP32F-NEXT: fsw fs8, 96(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs9, 92(sp) ; ILP32F-NEXT: fsw fs9, 92(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs10, 88(sp) ; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 84(sp) ; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui s0, %hi(var) ; ILP32F-NEXT: lui s0, %hi(var)
; ILP32F-NEXT: flw ft0, %lo(var)(s0) ; ILP32F-NEXT: flw ft0, %lo(var)(s0)
; ILP32F-NEXT: fsw ft0, 80(sp) ; ILP32F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: flw ft0, %lo(var+4)(s0)
; ILP32F-NEXT: fsw ft0, 76(sp) ; ILP32F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32F-NEXT: flw ft0, %lo(var+8)(s0)
; ILP32F-NEXT: fsw ft0, 72(sp) ; ILP32F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32F-NEXT: flw ft0, %lo(var+12)(s0)
; ILP32F-NEXT: fsw ft0, 68(sp) ; ILP32F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; ILP32F-NEXT: addi s1, s0, %lo(var) ; ILP32F-NEXT: addi s1, s0, %lo(var)
; ILP32F-NEXT: flw ft0, 16(s1) ; ILP32F-NEXT: flw ft0, 16(s1)
; ILP32F-NEXT: fsw ft0, 64(sp) ; ILP32F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 20(s1) ; ILP32F-NEXT: flw ft0, 20(s1)
; ILP32F-NEXT: fsw ft0, 60(sp) ; ILP32F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 24(s1) ; ILP32F-NEXT: flw ft0, 24(s1)
; ILP32F-NEXT: fsw ft0, 56(sp) ; ILP32F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 28(s1) ; ILP32F-NEXT: flw ft0, 28(s1)
; ILP32F-NEXT: fsw ft0, 52(sp) ; ILP32F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 32(s1) ; ILP32F-NEXT: flw ft0, 32(s1)
; ILP32F-NEXT: fsw ft0, 48(sp) ; ILP32F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 36(s1) ; ILP32F-NEXT: flw ft0, 36(s1)
; ILP32F-NEXT: fsw ft0, 44(sp) ; ILP32F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 40(s1) ; ILP32F-NEXT: flw ft0, 40(s1)
; ILP32F-NEXT: fsw ft0, 40(sp) ; ILP32F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 44(s1) ; ILP32F-NEXT: flw ft0, 44(s1)
; ILP32F-NEXT: fsw ft0, 36(sp) ; ILP32F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 48(s1) ; ILP32F-NEXT: flw ft0, 48(s1)
; ILP32F-NEXT: fsw ft0, 32(sp) ; ILP32F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 52(s1) ; ILP32F-NEXT: flw ft0, 52(s1)
; ILP32F-NEXT: fsw ft0, 28(sp) ; ILP32F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 56(s1) ; ILP32F-NEXT: flw ft0, 56(s1)
; ILP32F-NEXT: fsw ft0, 24(sp) ; ILP32F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 60(s1) ; ILP32F-NEXT: flw ft0, 60(s1)
; ILP32F-NEXT: fsw ft0, 20(sp) ; ILP32F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 64(s1) ; ILP32F-NEXT: flw ft0, 64(s1)
; ILP32F-NEXT: fsw ft0, 16(sp) ; ILP32F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 68(s1) ; ILP32F-NEXT: flw ft0, 68(s1)
; ILP32F-NEXT: fsw ft0, 12(sp) ; ILP32F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 72(s1) ; ILP32F-NEXT: flw ft0, 72(s1)
; ILP32F-NEXT: fsw ft0, 8(sp) ; ILP32F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw ft0, 76(s1) ; ILP32F-NEXT: flw ft0, 76(s1)
; ILP32F-NEXT: fsw ft0, 4(sp) ; ILP32F-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: flw fs8, 80(s1) ; ILP32F-NEXT: flw fs8, 80(s1)
; ILP32F-NEXT: flw fs9, 84(s1) ; ILP32F-NEXT: flw fs9, 84(s1)
; ILP32F-NEXT: flw fs10, 88(s1) ; ILP32F-NEXT: flw fs10, 88(s1)
; ILP32F-NEXT: flw fs11, 92(s1) ; ILP32F-NEXT: flw fs11, 92(s1)
; ILP32F-NEXT: flw fs0, 96(s1) ; ILP32F-NEXT: flw fs0, 96(s1)
; ILP32F-NEXT: flw fs1, 100(s1) ; ILP32F-NEXT: flw fs1, 100(s1)
; ILP32F-NEXT: flw fs2, 104(s1) ; ILP32F-NEXT: flw fs2, 104(s1)
; ILP32F-NEXT: flw fs3, 108(s1) ; ILP32F-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; ILP32F-NEXT: fsw fs3, 108(s1) ; ILP32F-NEXT: fsw fs3, 108(s1)
; ILP32F-NEXT: fsw fs2, 104(s1) ; ILP32F-NEXT: fsw fs2, 104(s1)
; ILP32F-NEXT: fsw fs1, 100(s1) ; ILP32F-NEXT: fsw fs1, 100(s1)
; ILP32F-NEXT: fsw fs0, 96(s1) ; ILP32F-NEXT: fsw fs0, 96(s1)
; ILP32F-NEXT: fsw fs11, 92(s1) ; ILP32F-NEXT: fsw fs11, 92(s1)
; ILP32F-NEXT: fsw fs10, 88(s1) ; ILP32F-NEXT: fsw fs10, 88(s1)
; ILP32F-NEXT: fsw fs9, 84(s1) ; ILP32F-NEXT: fsw fs9, 84(s1)
; ILP32F-NEXT: fsw fs8, 80(s1) ; ILP32F-NEXT: fsw fs8, 80(s1)
; ILP32F-NEXT: flw ft0, 4(sp) ; ILP32F-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 76(s1) ; ILP32F-NEXT: fsw ft0, 76(s1)
; ILP32F-NEXT: flw ft0, 8(sp) ; ILP32F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 72(s1) ; ILP32F-NEXT: fsw ft0, 72(s1)
; ILP32F-NEXT: flw ft0, 12(sp) ; ILP32F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 68(s1) ; ILP32F-NEXT: fsw ft0, 68(s1)
; ILP32F-NEXT: flw ft0, 16(sp) ; ILP32F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 64(s1) ; ILP32F-NEXT: fsw ft0, 64(s1)
; ILP32F-NEXT: flw ft0, 20(sp) ; ILP32F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 60(s1) ; ILP32F-NEXT: fsw ft0, 60(s1)
; ILP32F-NEXT: flw ft0, 24(sp) ; ILP32F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 56(s1) ; ILP32F-NEXT: fsw ft0, 56(s1)
; ILP32F-NEXT: flw ft0, 28(sp) ; ILP32F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 52(s1) ; ILP32F-NEXT: fsw ft0, 52(s1)
; ILP32F-NEXT: flw ft0, 32(sp) ; ILP32F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 48(s1) ; ILP32F-NEXT: fsw ft0, 48(s1)
; ILP32F-NEXT: flw ft0, 36(sp) ; ILP32F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 44(s1) ; ILP32F-NEXT: fsw ft0, 44(s1)
; ILP32F-NEXT: flw ft0, 40(sp) ; ILP32F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 40(s1) ; ILP32F-NEXT: fsw ft0, 40(s1)
; ILP32F-NEXT: flw ft0, 44(sp) ; ILP32F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 36(s1) ; ILP32F-NEXT: fsw ft0, 36(s1)
; ILP32F-NEXT: flw ft0, 48(sp) ; ILP32F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 32(s1) ; ILP32F-NEXT: fsw ft0, 32(s1)
; ILP32F-NEXT: flw ft0, 52(sp) ; ILP32F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 28(s1) ; ILP32F-NEXT: fsw ft0, 28(s1)
; ILP32F-NEXT: flw ft0, 56(sp) ; ILP32F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 24(s1) ; ILP32F-NEXT: fsw ft0, 24(s1)
; ILP32F-NEXT: flw ft0, 60(sp) ; ILP32F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 20(s1) ; ILP32F-NEXT: fsw ft0, 20(s1)
; ILP32F-NEXT: flw ft0, 64(sp) ; ILP32F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, 16(s1) ; ILP32F-NEXT: fsw ft0, 16(s1)
; ILP32F-NEXT: flw ft0, 68(sp) ; ILP32F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32F-NEXT: fsw ft0, %lo(var+12)(s0)
; ILP32F-NEXT: flw ft0, 72(sp) ; ILP32F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32F-NEXT: fsw ft0, %lo(var+8)(s0)
; ILP32F-NEXT: flw ft0, 76(sp) ; ILP32F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0)
; ILP32F-NEXT: flw ft0, 80(sp) ; ILP32F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
; ILP32F-NEXT: fsw ft0, %lo(var)(s0) ; ILP32F-NEXT: fsw ft0, %lo(var)(s0)
; ILP32F-NEXT: flw fs11, 84(sp) ; ILP32F-NEXT: flw fs11, 84(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs10, 88(sp) ; ILP32F-NEXT: flw fs10, 88(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs9, 92(sp) ; ILP32F-NEXT: flw fs9, 92(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs8, 96(sp) ; ILP32F-NEXT: flw fs8, 96(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs7, 100(sp) ; ILP32F-NEXT: flw fs7, 100(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs6, 104(sp) ; ILP32F-NEXT: flw fs6, 104(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs5, 108(sp) ; ILP32F-NEXT: flw fs5, 108(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs4, 112(sp) ; ILP32F-NEXT: flw fs4, 112(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs3, 116(sp) ; ILP32F-NEXT: flw fs3, 116(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 120(sp) ; ILP32F-NEXT: flw fs2, 120(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 124(sp) ; ILP32F-NEXT: flw fs1, 124(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs0, 128(sp) ; ILP32F-NEXT: flw fs0, 128(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s1, 132(sp) ; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s0, 136(sp) ; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw ra, 140(sp) ; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32F-NEXT: addi sp, sp, 144 ; ILP32F-NEXT: addi sp, sp, 144
; ILP32F-NEXT: ret ; ILP32F-NEXT: ret
; ;
; LP64F-LABEL: caller: ; LP64F-LABEL: caller:
; LP64F: # %bb.0: ; LP64F: # %bb.0:
; LP64F-NEXT: addi sp, sp, -160 ; LP64F-NEXT: addi sp, sp, -160
; LP64F-NEXT: sd ra, 152(sp) ; LP64F-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; LP64F-NEXT: sd s0, 144(sp) ; LP64F-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; LP64F-NEXT: sd s1, 136(sp) ; LP64F-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; LP64F-NEXT: fsw fs0, 132(sp) ; LP64F-NEXT: fsw fs0, 132(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs1, 128(sp) ; LP64F-NEXT: fsw fs1, 128(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs2, 124(sp) ; LP64F-NEXT: fsw fs2, 124(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs3, 120(sp) ; LP64F-NEXT: fsw fs3, 120(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs4, 116(sp) ; LP64F-NEXT: fsw fs4, 116(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs5, 112(sp) ; LP64F-NEXT: fsw fs5, 112(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs6, 108(sp) ; LP64F-NEXT: fsw fs6, 108(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs7, 104(sp) ; LP64F-NEXT: fsw fs7, 104(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs8, 100(sp) ; LP64F-NEXT: fsw fs8, 100(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs9, 96(sp) ; LP64F-NEXT: fsw fs9, 96(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs10, 92(sp) ; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 88(sp) ; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui s0, %hi(var) ; LP64F-NEXT: lui s0, %hi(var)
; LP64F-NEXT: flw ft0, %lo(var)(s0) ; LP64F-NEXT: flw ft0, %lo(var)(s0)
; LP64F-NEXT: fsw ft0, 84(sp) ; LP64F-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+4)(s0) ; LP64F-NEXT: flw ft0, %lo(var+4)(s0)
; LP64F-NEXT: fsw ft0, 80(sp) ; LP64F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+8)(s0) ; LP64F-NEXT: flw ft0, %lo(var+8)(s0)
; LP64F-NEXT: fsw ft0, 76(sp) ; LP64F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, %lo(var+12)(s0) ; LP64F-NEXT: flw ft0, %lo(var+12)(s0)
; LP64F-NEXT: fsw ft0, 72(sp) ; LP64F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; LP64F-NEXT: addi s1, s0, %lo(var) ; LP64F-NEXT: addi s1, s0, %lo(var)
; LP64F-NEXT: flw ft0, 16(s1) ; LP64F-NEXT: flw ft0, 16(s1)
; LP64F-NEXT: fsw ft0, 68(sp) ; LP64F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 20(s1) ; LP64F-NEXT: flw ft0, 20(s1)
; LP64F-NEXT: fsw ft0, 64(sp) ; LP64F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 24(s1) ; LP64F-NEXT: flw ft0, 24(s1)
; LP64F-NEXT: fsw ft0, 60(sp) ; LP64F-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 28(s1) ; LP64F-NEXT: flw ft0, 28(s1)
; LP64F-NEXT: fsw ft0, 56(sp) ; LP64F-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 32(s1) ; LP64F-NEXT: flw ft0, 32(s1)
; LP64F-NEXT: fsw ft0, 52(sp) ; LP64F-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 36(s1) ; LP64F-NEXT: flw ft0, 36(s1)
; LP64F-NEXT: fsw ft0, 48(sp) ; LP64F-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 40(s1) ; LP64F-NEXT: flw ft0, 40(s1)
; LP64F-NEXT: fsw ft0, 44(sp) ; LP64F-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 44(s1) ; LP64F-NEXT: flw ft0, 44(s1)
; LP64F-NEXT: fsw ft0, 40(sp) ; LP64F-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 48(s1) ; LP64F-NEXT: flw ft0, 48(s1)
; LP64F-NEXT: fsw ft0, 36(sp) ; LP64F-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 52(s1) ; LP64F-NEXT: flw ft0, 52(s1)
; LP64F-NEXT: fsw ft0, 32(sp) ; LP64F-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 56(s1) ; LP64F-NEXT: flw ft0, 56(s1)
; LP64F-NEXT: fsw ft0, 28(sp) ; LP64F-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 60(s1) ; LP64F-NEXT: flw ft0, 60(s1)
; LP64F-NEXT: fsw ft0, 24(sp) ; LP64F-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 64(s1) ; LP64F-NEXT: flw ft0, 64(s1)
; LP64F-NEXT: fsw ft0, 20(sp) ; LP64F-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 68(s1) ; LP64F-NEXT: flw ft0, 68(s1)
; LP64F-NEXT: fsw ft0, 16(sp) ; LP64F-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 72(s1) ; LP64F-NEXT: flw ft0, 72(s1)
; LP64F-NEXT: fsw ft0, 12(sp) ; LP64F-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw ft0, 76(s1) ; LP64F-NEXT: flw ft0, 76(s1)
; LP64F-NEXT: fsw ft0, 8(sp) ; LP64F-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; LP64F-NEXT: flw fs8, 80(s1) ; LP64F-NEXT: flw fs8, 80(s1)
; LP64F-NEXT: flw fs9, 84(s1) ; LP64F-NEXT: flw fs9, 84(s1)
; LP64F-NEXT: flw fs10, 88(s1) ; LP64F-NEXT: flw fs10, 88(s1)
; LP64F-NEXT: flw fs11, 92(s1) ; LP64F-NEXT: flw fs11, 92(s1)
; LP64F-NEXT: flw fs0, 96(s1) ; LP64F-NEXT: flw fs0, 96(s1)
; LP64F-NEXT: flw fs1, 100(s1) ; LP64F-NEXT: flw fs1, 100(s1)
; LP64F-NEXT: flw fs2, 104(s1) ; LP64F-NEXT: flw fs2, 104(s1)
; LP64F-NEXT: flw fs3, 108(s1) ; LP64F-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; LP64F-NEXT: fsw fs3, 108(s1) ; LP64F-NEXT: fsw fs3, 108(s1)
; LP64F-NEXT: fsw fs2, 104(s1) ; LP64F-NEXT: fsw fs2, 104(s1)
; LP64F-NEXT: fsw fs1, 100(s1) ; LP64F-NEXT: fsw fs1, 100(s1)
; LP64F-NEXT: fsw fs0, 96(s1) ; LP64F-NEXT: fsw fs0, 96(s1)
; LP64F-NEXT: fsw fs11, 92(s1) ; LP64F-NEXT: fsw fs11, 92(s1)
; LP64F-NEXT: fsw fs10, 88(s1) ; LP64F-NEXT: fsw fs10, 88(s1)
; LP64F-NEXT: fsw fs9, 84(s1) ; LP64F-NEXT: fsw fs9, 84(s1)
; LP64F-NEXT: fsw fs8, 80(s1) ; LP64F-NEXT: fsw fs8, 80(s1)
; LP64F-NEXT: flw ft0, 8(sp) ; LP64F-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 76(s1) ; LP64F-NEXT: fsw ft0, 76(s1)
; LP64F-NEXT: flw ft0, 12(sp) ; LP64F-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 72(s1) ; LP64F-NEXT: fsw ft0, 72(s1)
; LP64F-NEXT: flw ft0, 16(sp) ; LP64F-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 68(s1) ; LP64F-NEXT: fsw ft0, 68(s1)
; LP64F-NEXT: flw ft0, 20(sp) ; LP64F-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 64(s1) ; LP64F-NEXT: fsw ft0, 64(s1)
; LP64F-NEXT: flw ft0, 24(sp) ; LP64F-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 60(s1) ; LP64F-NEXT: fsw ft0, 60(s1)
; LP64F-NEXT: flw ft0, 28(sp) ; LP64F-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 56(s1) ; LP64F-NEXT: fsw ft0, 56(s1)
; LP64F-NEXT: flw ft0, 32(sp) ; LP64F-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 52(s1) ; LP64F-NEXT: fsw ft0, 52(s1)
; LP64F-NEXT: flw ft0, 36(sp) ; LP64F-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 48(s1) ; LP64F-NEXT: fsw ft0, 48(s1)
; LP64F-NEXT: flw ft0, 40(sp) ; LP64F-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 44(s1) ; LP64F-NEXT: fsw ft0, 44(s1)
; LP64F-NEXT: flw ft0, 44(sp) ; LP64F-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 40(s1) ; LP64F-NEXT: fsw ft0, 40(s1)
; LP64F-NEXT: flw ft0, 48(sp) ; LP64F-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 36(s1) ; LP64F-NEXT: fsw ft0, 36(s1)
; LP64F-NEXT: flw ft0, 52(sp) ; LP64F-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 32(s1) ; LP64F-NEXT: fsw ft0, 32(s1)
; LP64F-NEXT: flw ft0, 56(sp) ; LP64F-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 28(s1) ; LP64F-NEXT: fsw ft0, 28(s1)
; LP64F-NEXT: flw ft0, 60(sp) ; LP64F-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 24(s1) ; LP64F-NEXT: fsw ft0, 24(s1)
; LP64F-NEXT: flw ft0, 64(sp) ; LP64F-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 20(s1) ; LP64F-NEXT: fsw ft0, 20(s1)
; LP64F-NEXT: flw ft0, 68(sp) ; LP64F-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, 16(s1) ; LP64F-NEXT: fsw ft0, 16(s1)
; LP64F-NEXT: flw ft0, 72(sp) ; LP64F-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64F-NEXT: fsw ft0, %lo(var+12)(s0)
; LP64F-NEXT: flw ft0, 76(sp) ; LP64F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64F-NEXT: fsw ft0, %lo(var+8)(s0)
; LP64F-NEXT: flw ft0, 80(sp) ; LP64F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64F-NEXT: fsw ft0, %lo(var+4)(s0)
; LP64F-NEXT: flw ft0, 84(sp) ; LP64F-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
; LP64F-NEXT: fsw ft0, %lo(var)(s0) ; LP64F-NEXT: fsw ft0, %lo(var)(s0)
; LP64F-NEXT: flw fs11, 88(sp) ; LP64F-NEXT: flw fs11, 88(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs10, 92(sp) ; LP64F-NEXT: flw fs10, 92(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs9, 96(sp) ; LP64F-NEXT: flw fs9, 96(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs8, 100(sp) ; LP64F-NEXT: flw fs8, 100(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs7, 104(sp) ; LP64F-NEXT: flw fs7, 104(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs6, 108(sp) ; LP64F-NEXT: flw fs6, 108(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs5, 112(sp) ; LP64F-NEXT: flw fs5, 112(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs4, 116(sp) ; LP64F-NEXT: flw fs4, 116(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs3, 120(sp) ; LP64F-NEXT: flw fs3, 120(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 124(sp) ; LP64F-NEXT: flw fs2, 124(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 128(sp) ; LP64F-NEXT: flw fs1, 128(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs0, 132(sp) ; LP64F-NEXT: flw fs0, 132(sp) # 4-byte Folded Reload
; LP64F-NEXT: ld s1, 136(sp) ; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld s0, 144(sp) ; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; LP64F-NEXT: ld ra, 152(sp) ; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; LP64F-NEXT: addi sp, sp, 160 ; LP64F-NEXT: addi sp, sp, 160
; LP64F-NEXT: ret ; LP64F-NEXT: ret
; ;
; ILP32D-LABEL: caller: ; ILP32D-LABEL: caller:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
; ILP32D-NEXT: addi sp, sp, -192 ; ILP32D-NEXT: addi sp, sp, -192
; ILP32D-NEXT: sw ra, 188(sp) ; ILP32D-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s0, 184(sp) ; ILP32D-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s1, 180(sp) ; ILP32D-NEXT: sw s1, 180(sp) # 4-byte Folded Spill
; ILP32D-NEXT: fsd fs0, 168(sp) ; ILP32D-NEXT: fsd fs0, 168(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs1, 160(sp) ; ILP32D-NEXT: fsd fs1, 160(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs2, 152(sp) ; ILP32D-NEXT: fsd fs2, 152(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs3, 144(sp) ; ILP32D-NEXT: fsd fs3, 144(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs4, 136(sp) ; ILP32D-NEXT: fsd fs4, 136(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs5, 128(sp) ; ILP32D-NEXT: fsd fs5, 128(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 120(sp) ; ILP32D-NEXT: fsd fs6, 120(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 112(sp) ; ILP32D-NEXT: fsd fs7, 112(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 104(sp) ; ILP32D-NEXT: fsd fs8, 104(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 96(sp) ; ILP32D-NEXT: fsd fs9, 96(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 88(sp) ; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 80(sp) ; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var) ; ILP32D-NEXT: lui s0, %hi(var)
; ILP32D-NEXT: flw ft0, %lo(var)(s0) ; ILP32D-NEXT: flw ft0, %lo(var)(s0)
; ILP32D-NEXT: fsw ft0, 76(sp) ; ILP32D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: flw ft0, %lo(var+4)(s0)
; ILP32D-NEXT: fsw ft0, 72(sp) ; ILP32D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+8)(s0) ; ILP32D-NEXT: flw ft0, %lo(var+8)(s0)
; ILP32D-NEXT: fsw ft0, 68(sp) ; ILP32D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32D-NEXT: flw ft0, %lo(var+12)(s0)
; ILP32D-NEXT: fsw ft0, 64(sp) ; ILP32D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: addi s1, s0, %lo(var)
; ILP32D-NEXT: flw ft0, 16(s1) ; ILP32D-NEXT: flw ft0, 16(s1)
; ILP32D-NEXT: fsw ft0, 60(sp) ; ILP32D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 20(s1) ; ILP32D-NEXT: flw ft0, 20(s1)
; ILP32D-NEXT: fsw ft0, 56(sp) ; ILP32D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 24(s1) ; ILP32D-NEXT: flw ft0, 24(s1)
; ILP32D-NEXT: fsw ft0, 52(sp) ; ILP32D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 28(s1) ; ILP32D-NEXT: flw ft0, 28(s1)
; ILP32D-NEXT: fsw ft0, 48(sp) ; ILP32D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 32(s1) ; ILP32D-NEXT: flw ft0, 32(s1)
; ILP32D-NEXT: fsw ft0, 44(sp) ; ILP32D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 36(s1) ; ILP32D-NEXT: flw ft0, 36(s1)
; ILP32D-NEXT: fsw ft0, 40(sp) ; ILP32D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 40(s1) ; ILP32D-NEXT: flw ft0, 40(s1)
; ILP32D-NEXT: fsw ft0, 36(sp) ; ILP32D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 44(s1) ; ILP32D-NEXT: flw ft0, 44(s1)
; ILP32D-NEXT: fsw ft0, 32(sp) ; ILP32D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 48(s1) ; ILP32D-NEXT: flw ft0, 48(s1)
; ILP32D-NEXT: fsw ft0, 28(sp) ; ILP32D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 52(s1) ; ILP32D-NEXT: flw ft0, 52(s1)
; ILP32D-NEXT: fsw ft0, 24(sp) ; ILP32D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 56(s1) ; ILP32D-NEXT: flw ft0, 56(s1)
; ILP32D-NEXT: fsw ft0, 20(sp) ; ILP32D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 60(s1) ; ILP32D-NEXT: flw ft0, 60(s1)
; ILP32D-NEXT: fsw ft0, 16(sp) ; ILP32D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 64(s1) ; ILP32D-NEXT: flw ft0, 64(s1)
; ILP32D-NEXT: fsw ft0, 12(sp) ; ILP32D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 68(s1) ; ILP32D-NEXT: flw ft0, 68(s1)
; ILP32D-NEXT: fsw ft0, 8(sp) ; ILP32D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 72(s1) ; ILP32D-NEXT: flw ft0, 72(s1)
; ILP32D-NEXT: fsw ft0, 4(sp) ; ILP32D-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw ft0, 76(s1) ; ILP32D-NEXT: flw ft0, 76(s1)
; ILP32D-NEXT: fsw ft0, 0(sp) ; ILP32D-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill
; ILP32D-NEXT: flw fs8, 80(s1) ; ILP32D-NEXT: flw fs8, 80(s1)
; ILP32D-NEXT: flw fs9, 84(s1) ; ILP32D-NEXT: flw fs9, 84(s1)
; ILP32D-NEXT: flw fs10, 88(s1) ; ILP32D-NEXT: flw fs10, 88(s1)
; ILP32D-NEXT: flw fs11, 92(s1) ; ILP32D-NEXT: flw fs11, 92(s1)
; ILP32D-NEXT: flw fs0, 96(s1) ; ILP32D-NEXT: flw fs0, 96(s1)
; ILP32D-NEXT: flw fs1, 100(s1) ; ILP32D-NEXT: flw fs1, 100(s1)
; ILP32D-NEXT: flw fs2, 104(s1) ; ILP32D-NEXT: flw fs2, 104(s1)
; ILP32D-NEXT: flw fs3, 108(s1) ; ILP32D-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; ILP32D-NEXT: fsw fs3, 108(s1) ; ILP32D-NEXT: fsw fs3, 108(s1)
; ILP32D-NEXT: fsw fs2, 104(s1) ; ILP32D-NEXT: fsw fs2, 104(s1)
; ILP32D-NEXT: fsw fs1, 100(s1) ; ILP32D-NEXT: fsw fs1, 100(s1)
; ILP32D-NEXT: fsw fs0, 96(s1) ; ILP32D-NEXT: fsw fs0, 96(s1)
; ILP32D-NEXT: fsw fs11, 92(s1) ; ILP32D-NEXT: fsw fs11, 92(s1)
; ILP32D-NEXT: fsw fs10, 88(s1) ; ILP32D-NEXT: fsw fs10, 88(s1)
; ILP32D-NEXT: fsw fs9, 84(s1) ; ILP32D-NEXT: fsw fs9, 84(s1)
; ILP32D-NEXT: fsw fs8, 80(s1) ; ILP32D-NEXT: fsw fs8, 80(s1)
; ILP32D-NEXT: flw ft0, 0(sp) ; ILP32D-NEXT: flw ft0, 0(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 76(s1) ; ILP32D-NEXT: fsw ft0, 76(s1)
; ILP32D-NEXT: flw ft0, 4(sp) ; ILP32D-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 72(s1) ; ILP32D-NEXT: fsw ft0, 72(s1)
; ILP32D-NEXT: flw ft0, 8(sp) ; ILP32D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 68(s1) ; ILP32D-NEXT: fsw ft0, 68(s1)
; ILP32D-NEXT: flw ft0, 12(sp) ; ILP32D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 64(s1) ; ILP32D-NEXT: fsw ft0, 64(s1)
; ILP32D-NEXT: flw ft0, 16(sp) ; ILP32D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 60(s1) ; ILP32D-NEXT: fsw ft0, 60(s1)
; ILP32D-NEXT: flw ft0, 20(sp) ; ILP32D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 56(s1) ; ILP32D-NEXT: fsw ft0, 56(s1)
; ILP32D-NEXT: flw ft0, 24(sp) ; ILP32D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 52(s1) ; ILP32D-NEXT: fsw ft0, 52(s1)
; ILP32D-NEXT: flw ft0, 28(sp) ; ILP32D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 48(s1) ; ILP32D-NEXT: fsw ft0, 48(s1)
; ILP32D-NEXT: flw ft0, 32(sp) ; ILP32D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 44(s1) ; ILP32D-NEXT: fsw ft0, 44(s1)
; ILP32D-NEXT: flw ft0, 36(sp) ; ILP32D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 40(s1) ; ILP32D-NEXT: fsw ft0, 40(s1)
; ILP32D-NEXT: flw ft0, 40(sp) ; ILP32D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 36(s1) ; ILP32D-NEXT: fsw ft0, 36(s1)
; ILP32D-NEXT: flw ft0, 44(sp) ; ILP32D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 32(s1) ; ILP32D-NEXT: fsw ft0, 32(s1)
; ILP32D-NEXT: flw ft0, 48(sp) ; ILP32D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 28(s1) ; ILP32D-NEXT: fsw ft0, 28(s1)
; ILP32D-NEXT: flw ft0, 52(sp) ; ILP32D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 24(s1) ; ILP32D-NEXT: fsw ft0, 24(s1)
; ILP32D-NEXT: flw ft0, 56(sp) ; ILP32D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 20(s1) ; ILP32D-NEXT: fsw ft0, 20(s1)
; ILP32D-NEXT: flw ft0, 60(sp) ; ILP32D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, 16(s1) ; ILP32D-NEXT: fsw ft0, 16(s1)
; ILP32D-NEXT: flw ft0, 64(sp) ; ILP32D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+12)(s0) ; ILP32D-NEXT: fsw ft0, %lo(var+12)(s0)
; ILP32D-NEXT: flw ft0, 68(sp) ; ILP32D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fsw ft0, %lo(var+8)(s0)
; ILP32D-NEXT: flw ft0, 72(sp) ; ILP32D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0)
; ILP32D-NEXT: flw ft0, 76(sp) ; ILP32D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; ILP32D-NEXT: fsw ft0, %lo(var)(s0) ; ILP32D-NEXT: fsw ft0, %lo(var)(s0)
; ILP32D-NEXT: fld fs11, 80(sp) ; ILP32D-NEXT: fld fs11, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs10, 88(sp) ; ILP32D-NEXT: fld fs10, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs9, 96(sp) ; ILP32D-NEXT: fld fs9, 96(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs8, 104(sp) ; ILP32D-NEXT: fld fs8, 104(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 112(sp) ; ILP32D-NEXT: fld fs7, 112(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 120(sp) ; ILP32D-NEXT: fld fs6, 120(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 128(sp) ; ILP32D-NEXT: fld fs5, 128(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 136(sp) ; ILP32D-NEXT: fld fs4, 136(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 144(sp) ; ILP32D-NEXT: fld fs3, 144(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 152(sp) ; ILP32D-NEXT: fld fs2, 152(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 160(sp) ; ILP32D-NEXT: fld fs1, 160(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs0, 168(sp) ; ILP32D-NEXT: fld fs0, 168(sp) # 8-byte Folded Reload
; ILP32D-NEXT: lw s1, 180(sp) ; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 184(sp) ; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw ra, 188(sp) ; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 192 ; ILP32D-NEXT: addi sp, sp, 192
; ILP32D-NEXT: ret ; ILP32D-NEXT: ret
; ;
; LP64D-LABEL: caller: ; LP64D-LABEL: caller:
; LP64D: # %bb.0: ; LP64D: # %bb.0:
; LP64D-NEXT: addi sp, sp, -208 ; LP64D-NEXT: addi sp, sp, -208
; LP64D-NEXT: sd ra, 200(sp) ; LP64D-NEXT: sd ra, 200(sp) # 8-byte Folded Spill
; LP64D-NEXT: sd s0, 192(sp) ; LP64D-NEXT: sd s0, 192(sp) # 8-byte Folded Spill
; LP64D-NEXT: sd s1, 184(sp) ; LP64D-NEXT: sd s1, 184(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs0, 176(sp) ; LP64D-NEXT: fsd fs0, 176(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs1, 168(sp) ; LP64D-NEXT: fsd fs1, 168(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs2, 160(sp) ; LP64D-NEXT: fsd fs2, 160(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs3, 152(sp) ; LP64D-NEXT: fsd fs3, 152(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs4, 144(sp) ; LP64D-NEXT: fsd fs4, 144(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs5, 136(sp) ; LP64D-NEXT: fsd fs5, 136(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 128(sp) ; LP64D-NEXT: fsd fs6, 128(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 120(sp) ; LP64D-NEXT: fsd fs7, 120(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 112(sp) ; LP64D-NEXT: fsd fs8, 112(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 104(sp) ; LP64D-NEXT: fsd fs9, 104(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 96(sp) ; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 88(sp) ; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var) ; LP64D-NEXT: lui s0, %hi(var)
; LP64D-NEXT: flw ft0, %lo(var)(s0) ; LP64D-NEXT: flw ft0, %lo(var)(s0)
; LP64D-NEXT: fsw ft0, 84(sp) ; LP64D-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+4)(s0) ; LP64D-NEXT: flw ft0, %lo(var+4)(s0)
; LP64D-NEXT: fsw ft0, 80(sp) ; LP64D-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+8)(s0) ; LP64D-NEXT: flw ft0, %lo(var+8)(s0)
; LP64D-NEXT: fsw ft0, 76(sp) ; LP64D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, %lo(var+12)(s0) ; LP64D-NEXT: flw ft0, %lo(var+12)(s0)
; LP64D-NEXT: fsw ft0, 72(sp) ; LP64D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: addi s1, s0, %lo(var)
; LP64D-NEXT: flw ft0, 16(s1) ; LP64D-NEXT: flw ft0, 16(s1)
; LP64D-NEXT: fsw ft0, 68(sp) ; LP64D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 20(s1) ; LP64D-NEXT: flw ft0, 20(s1)
; LP64D-NEXT: fsw ft0, 64(sp) ; LP64D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 24(s1) ; LP64D-NEXT: flw ft0, 24(s1)
; LP64D-NEXT: fsw ft0, 60(sp) ; LP64D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 28(s1) ; LP64D-NEXT: flw ft0, 28(s1)
; LP64D-NEXT: fsw ft0, 56(sp) ; LP64D-NEXT: fsw ft0, 56(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 32(s1) ; LP64D-NEXT: flw ft0, 32(s1)
; LP64D-NEXT: fsw ft0, 52(sp) ; LP64D-NEXT: fsw ft0, 52(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 36(s1) ; LP64D-NEXT: flw ft0, 36(s1)
; LP64D-NEXT: fsw ft0, 48(sp) ; LP64D-NEXT: fsw ft0, 48(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 40(s1) ; LP64D-NEXT: flw ft0, 40(s1)
; LP64D-NEXT: fsw ft0, 44(sp) ; LP64D-NEXT: fsw ft0, 44(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 44(s1) ; LP64D-NEXT: flw ft0, 44(s1)
; LP64D-NEXT: fsw ft0, 40(sp) ; LP64D-NEXT: fsw ft0, 40(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 48(s1) ; LP64D-NEXT: flw ft0, 48(s1)
; LP64D-NEXT: fsw ft0, 36(sp) ; LP64D-NEXT: fsw ft0, 36(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 52(s1) ; LP64D-NEXT: flw ft0, 52(s1)
; LP64D-NEXT: fsw ft0, 32(sp) ; LP64D-NEXT: fsw ft0, 32(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 56(s1) ; LP64D-NEXT: flw ft0, 56(s1)
; LP64D-NEXT: fsw ft0, 28(sp) ; LP64D-NEXT: fsw ft0, 28(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 60(s1) ; LP64D-NEXT: flw ft0, 60(s1)
; LP64D-NEXT: fsw ft0, 24(sp) ; LP64D-NEXT: fsw ft0, 24(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 64(s1) ; LP64D-NEXT: flw ft0, 64(s1)
; LP64D-NEXT: fsw ft0, 20(sp) ; LP64D-NEXT: fsw ft0, 20(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 68(s1) ; LP64D-NEXT: flw ft0, 68(s1)
; LP64D-NEXT: fsw ft0, 16(sp) ; LP64D-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 72(s1) ; LP64D-NEXT: flw ft0, 72(s1)
; LP64D-NEXT: fsw ft0, 12(sp) ; LP64D-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw ft0, 76(s1) ; LP64D-NEXT: flw ft0, 76(s1)
; LP64D-NEXT: fsw ft0, 8(sp) ; LP64D-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; LP64D-NEXT: flw fs8, 80(s1) ; LP64D-NEXT: flw fs8, 80(s1)
; LP64D-NEXT: flw fs9, 84(s1) ; LP64D-NEXT: flw fs9, 84(s1)
; LP64D-NEXT: flw fs10, 88(s1) ; LP64D-NEXT: flw fs10, 88(s1)
; LP64D-NEXT: flw fs11, 92(s1) ; LP64D-NEXT: flw fs11, 92(s1)
; LP64D-NEXT: flw fs0, 96(s1) ; LP64D-NEXT: flw fs0, 96(s1)
; LP64D-NEXT: flw fs1, 100(s1) ; LP64D-NEXT: flw fs1, 100(s1)
; LP64D-NEXT: flw fs2, 104(s1) ; LP64D-NEXT: flw fs2, 104(s1)
; LP64D-NEXT: flw fs3, 108(s1) ; LP64D-NEXT: flw fs3, 108(s1)
Show All 9 Lines
; LP64D-NEXT: fsw fs3, 108(s1) ; LP64D-NEXT: fsw fs3, 108(s1)
; LP64D-NEXT: fsw fs2, 104(s1) ; LP64D-NEXT: fsw fs2, 104(s1)
; LP64D-NEXT: fsw fs1, 100(s1) ; LP64D-NEXT: fsw fs1, 100(s1)
; LP64D-NEXT: fsw fs0, 96(s1) ; LP64D-NEXT: fsw fs0, 96(s1)
; LP64D-NEXT: fsw fs11, 92(s1) ; LP64D-NEXT: fsw fs11, 92(s1)
; LP64D-NEXT: fsw fs10, 88(s1) ; LP64D-NEXT: fsw fs10, 88(s1)
; LP64D-NEXT: fsw fs9, 84(s1) ; LP64D-NEXT: fsw fs9, 84(s1)
; LP64D-NEXT: fsw fs8, 80(s1) ; LP64D-NEXT: fsw fs8, 80(s1)
; LP64D-NEXT: flw ft0, 8(sp) ; LP64D-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 76(s1) ; LP64D-NEXT: fsw ft0, 76(s1)
; LP64D-NEXT: flw ft0, 12(sp) ; LP64D-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 72(s1) ; LP64D-NEXT: fsw ft0, 72(s1)
; LP64D-NEXT: flw ft0, 16(sp) ; LP64D-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 68(s1) ; LP64D-NEXT: fsw ft0, 68(s1)
; LP64D-NEXT: flw ft0, 20(sp) ; LP64D-NEXT: flw ft0, 20(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 64(s1) ; LP64D-NEXT: fsw ft0, 64(s1)
; LP64D-NEXT: flw ft0, 24(sp) ; LP64D-NEXT: flw ft0, 24(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 60(s1) ; LP64D-NEXT: fsw ft0, 60(s1)
; LP64D-NEXT: flw ft0, 28(sp) ; LP64D-NEXT: flw ft0, 28(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 56(s1) ; LP64D-NEXT: fsw ft0, 56(s1)
; LP64D-NEXT: flw ft0, 32(sp) ; LP64D-NEXT: flw ft0, 32(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 52(s1) ; LP64D-NEXT: fsw ft0, 52(s1)
; LP64D-NEXT: flw ft0, 36(sp) ; LP64D-NEXT: flw ft0, 36(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 48(s1) ; LP64D-NEXT: fsw ft0, 48(s1)
; LP64D-NEXT: flw ft0, 40(sp) ; LP64D-NEXT: flw ft0, 40(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 44(s1) ; LP64D-NEXT: fsw ft0, 44(s1)
; LP64D-NEXT: flw ft0, 44(sp) ; LP64D-NEXT: flw ft0, 44(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 40(s1) ; LP64D-NEXT: fsw ft0, 40(s1)
; LP64D-NEXT: flw ft0, 48(sp) ; LP64D-NEXT: flw ft0, 48(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 36(s1) ; LP64D-NEXT: fsw ft0, 36(s1)
; LP64D-NEXT: flw ft0, 52(sp) ; LP64D-NEXT: flw ft0, 52(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 32(s1) ; LP64D-NEXT: fsw ft0, 32(s1)
; LP64D-NEXT: flw ft0, 56(sp) ; LP64D-NEXT: flw ft0, 56(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 28(s1) ; LP64D-NEXT: fsw ft0, 28(s1)
; LP64D-NEXT: flw ft0, 60(sp) ; LP64D-NEXT: flw ft0, 60(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 24(s1) ; LP64D-NEXT: fsw ft0, 24(s1)
; LP64D-NEXT: flw ft0, 64(sp) ; LP64D-NEXT: flw ft0, 64(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 20(s1) ; LP64D-NEXT: fsw ft0, 20(s1)
; LP64D-NEXT: flw ft0, 68(sp) ; LP64D-NEXT: flw ft0, 68(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, 16(s1) ; LP64D-NEXT: fsw ft0, 16(s1)
; LP64D-NEXT: flw ft0, 72(sp) ; LP64D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+12)(s0) ; LP64D-NEXT: fsw ft0, %lo(var+12)(s0)
; LP64D-NEXT: flw ft0, 76(sp) ; LP64D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+8)(s0) ; LP64D-NEXT: fsw ft0, %lo(var+8)(s0)
; LP64D-NEXT: flw ft0, 80(sp) ; LP64D-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64D-NEXT: fsw ft0, %lo(var+4)(s0)
; LP64D-NEXT: flw ft0, 84(sp) ; LP64D-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload
; LP64D-NEXT: fsw ft0, %lo(var)(s0) ; LP64D-NEXT: fsw ft0, %lo(var)(s0)
; LP64D-NEXT: fld fs11, 88(sp) ; LP64D-NEXT: fld fs11, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs10, 96(sp) ; LP64D-NEXT: fld fs10, 96(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs9, 104(sp) ; LP64D-NEXT: fld fs9, 104(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs8, 112(sp) ; LP64D-NEXT: fld fs8, 112(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 120(sp) ; LP64D-NEXT: fld fs7, 120(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 128(sp) ; LP64D-NEXT: fld fs6, 128(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 136(sp) ; LP64D-NEXT: fld fs5, 136(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 144(sp) ; LP64D-NEXT: fld fs4, 144(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 152(sp) ; LP64D-NEXT: fld fs3, 152(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 160(sp) ; LP64D-NEXT: fld fs2, 160(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 168(sp) ; LP64D-NEXT: fld fs1, 168(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 176(sp) ; LP64D-NEXT: fld fs0, 176(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 184(sp) ; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 192(sp) ; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld ra, 200(sp) ; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload
; LP64D-NEXT: addi sp, sp, 208 ; LP64D-NEXT: addi sp, sp, 208
; LP64D-NEXT: ret ; LP64D-NEXT: ret
%val = load [32 x float], [32 x float]* @var %val = load [32 x float], [32 x float]* @var
call void @callee() call void @callee()
store volatile [32 x float] %val, [32 x float]* @var store volatile [32 x float] %val, [32 x float]* @var
ret void ret void
} }

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

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; LP64-NEXT: fsd ft2, 16(a1) ; LP64-NEXT: fsd ft2, 16(a1)
; LP64-NEXT: fsd ft1, %lo(var+8)(a0) ; LP64-NEXT: fsd ft1, %lo(var+8)(a0)
; LP64-NEXT: fsd ft0, %lo(var)(a0) ; LP64-NEXT: fsd ft0, %lo(var)(a0)
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32D-LABEL: callee: ; ILP32D-LABEL: callee:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
; ILP32D-NEXT: addi sp, sp, -96 ; ILP32D-NEXT: addi sp, sp, -96
; ILP32D-NEXT: fsd fs0, 88(sp) ; ILP32D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs1, 80(sp) ; ILP32D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs2, 72(sp) ; ILP32D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs3, 64(sp) ; ILP32D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs4, 56(sp) ; ILP32D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs5, 48(sp) ; ILP32D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 40(sp) ; ILP32D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 32(sp) ; ILP32D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 24(sp) ; ILP32D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 16(sp) ; ILP32D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 8(sp) ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var) ; ILP32D-NEXT: lui a0, %hi(var)
; ILP32D-NEXT: fld ft0, %lo(var)(a0) ; ILP32D-NEXT: fld ft0, %lo(var)(a0)
; ILP32D-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32D-NEXT: fld ft1, %lo(var+8)(a0)
; ILP32D-NEXT: addi a1, a0, %lo(var) ; ILP32D-NEXT: addi a1, a0, %lo(var)
; ILP32D-NEXT: fld ft2, 16(a1) ; ILP32D-NEXT: fld ft2, 16(a1)
; ILP32D-NEXT: fld ft3, 24(a1) ; ILP32D-NEXT: fld ft3, 24(a1)
; ILP32D-NEXT: fld ft4, 32(a1) ; ILP32D-NEXT: fld ft4, 32(a1)
; ILP32D-NEXT: fld ft5, 40(a1) ; ILP32D-NEXT: fld ft5, 40(a1)
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; ILP32D-NEXT: fsd ft7, 56(a1) ; ILP32D-NEXT: fsd ft7, 56(a1)
; ILP32D-NEXT: fsd ft6, 48(a1) ; ILP32D-NEXT: fsd ft6, 48(a1)
; ILP32D-NEXT: fsd ft5, 40(a1) ; ILP32D-NEXT: fsd ft5, 40(a1)
; ILP32D-NEXT: fsd ft4, 32(a1) ; ILP32D-NEXT: fsd ft4, 32(a1)
; ILP32D-NEXT: fsd ft3, 24(a1) ; ILP32D-NEXT: fsd ft3, 24(a1)
; ILP32D-NEXT: fsd ft2, 16(a1) ; ILP32D-NEXT: fsd ft2, 16(a1)
; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0) ; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0)
; ILP32D-NEXT: fsd ft0, %lo(var)(a0) ; ILP32D-NEXT: fsd ft0, %lo(var)(a0)
; ILP32D-NEXT: fld fs11, 0(sp) ; ILP32D-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs10, 8(sp) ; ILP32D-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs9, 16(sp) ; ILP32D-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs8, 24(sp) ; ILP32D-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 32(sp) ; ILP32D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 40(sp) ; ILP32D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 48(sp) ; ILP32D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 56(sp) ; ILP32D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 64(sp) ; ILP32D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs0, 88(sp) ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 96 ; ILP32D-NEXT: addi sp, sp, 96
; ILP32D-NEXT: ret ; ILP32D-NEXT: ret
; ;
; LP64D-LABEL: callee: ; LP64D-LABEL: callee:
; LP64D: # %bb.0: ; LP64D: # %bb.0:
; LP64D-NEXT: addi sp, sp, -96 ; LP64D-NEXT: addi sp, sp, -96
; LP64D-NEXT: fsd fs0, 88(sp) ; LP64D-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs1, 80(sp) ; LP64D-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs2, 72(sp) ; LP64D-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs3, 64(sp) ; LP64D-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs4, 56(sp) ; LP64D-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs5, 48(sp) ; LP64D-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 40(sp) ; LP64D-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 32(sp) ; LP64D-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 24(sp) ; LP64D-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 16(sp) ; LP64D-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 8(sp) ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var) ; LP64D-NEXT: lui a0, %hi(var)
; LP64D-NEXT: fld ft0, %lo(var)(a0) ; LP64D-NEXT: fld ft0, %lo(var)(a0)
; LP64D-NEXT: fld ft1, %lo(var+8)(a0) ; LP64D-NEXT: fld ft1, %lo(var+8)(a0)
; LP64D-NEXT: addi a1, a0, %lo(var) ; LP64D-NEXT: addi a1, a0, %lo(var)
; LP64D-NEXT: fld ft2, 16(a1) ; LP64D-NEXT: fld ft2, 16(a1)
; LP64D-NEXT: fld ft3, 24(a1) ; LP64D-NEXT: fld ft3, 24(a1)
; LP64D-NEXT: fld ft4, 32(a1) ; LP64D-NEXT: fld ft4, 32(a1)
; LP64D-NEXT: fld ft5, 40(a1) ; LP64D-NEXT: fld ft5, 40(a1)
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; LP64D-NEXT: fsd ft7, 56(a1) ; LP64D-NEXT: fsd ft7, 56(a1)
; LP64D-NEXT: fsd ft6, 48(a1) ; LP64D-NEXT: fsd ft6, 48(a1)
; LP64D-NEXT: fsd ft5, 40(a1) ; LP64D-NEXT: fsd ft5, 40(a1)
; LP64D-NEXT: fsd ft4, 32(a1) ; LP64D-NEXT: fsd ft4, 32(a1)
; LP64D-NEXT: fsd ft3, 24(a1) ; LP64D-NEXT: fsd ft3, 24(a1)
; LP64D-NEXT: fsd ft2, 16(a1) ; LP64D-NEXT: fsd ft2, 16(a1)
; LP64D-NEXT: fsd ft1, %lo(var+8)(a0) ; LP64D-NEXT: fsd ft1, %lo(var+8)(a0)
; LP64D-NEXT: fsd ft0, %lo(var)(a0) ; LP64D-NEXT: fsd ft0, %lo(var)(a0)
; LP64D-NEXT: fld fs11, 0(sp) ; LP64D-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs10, 8(sp) ; LP64D-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs9, 16(sp) ; LP64D-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs8, 24(sp) ; LP64D-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 32(sp) ; LP64D-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 40(sp) ; LP64D-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 48(sp) ; LP64D-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 56(sp) ; LP64D-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 64(sp) ; LP64D-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 88(sp) ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: addi sp, sp, 96 ; LP64D-NEXT: addi sp, sp, 96
; LP64D-NEXT: ret ; LP64D-NEXT: ret
%val = load [32 x double], [32 x double]* @var %val = load [32 x double], [32 x double]* @var
store volatile [32 x double] %val, [32 x double]* @var store volatile [32 x double] %val, [32 x double]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
; ;
; For the soft float ABIs, no floating point registers are preserved, and ; For the soft float ABIs, no floating point registers are preserved, and
; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs, ; codegen will use only ft0 in the body of caller. For the 'f' and 'd ABIs,
; fs0-fs11 are preserved across calls. ; fs0-fs11 are preserved across calls.
define void @caller() nounwind { define void @caller() nounwind {
; ILP32-LABEL: caller: ; ILP32-LABEL: caller:
; ILP32: # %bb.0: ; ILP32: # %bb.0:
; ILP32-NEXT: addi sp, sp, -272 ; ILP32-NEXT: addi sp, sp, -272
; ILP32-NEXT: sw ra, 268(sp) ; ILP32-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 264(sp) ; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s1, 260(sp) ; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var) ; ILP32-NEXT: lui s0, %hi(var)
; ILP32-NEXT: fld ft0, %lo(var)(s0) ; ILP32-NEXT: fld ft0, %lo(var)(s0)
; ILP32-NEXT: fsd ft0, 248(sp) ; ILP32-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32-NEXT: fld ft0, %lo(var+8)(s0)
; ILP32-NEXT: fsd ft0, 240(sp) ; ILP32-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill
; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: addi s1, s0, %lo(var)
; ILP32-NEXT: fld ft0, 16(s1) ; ILP32-NEXT: fld ft0, 16(s1)
; ILP32-NEXT: fsd ft0, 232(sp) ; ILP32-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 24(s1) ; ILP32-NEXT: fld ft0, 24(s1)
; ILP32-NEXT: fsd ft0, 224(sp) ; ILP32-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 32(s1) ; ILP32-NEXT: fld ft0, 32(s1)
; ILP32-NEXT: fsd ft0, 216(sp) ; ILP32-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 40(s1) ; ILP32-NEXT: fld ft0, 40(s1)
; ILP32-NEXT: fsd ft0, 208(sp) ; ILP32-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 48(s1) ; ILP32-NEXT: fld ft0, 48(s1)
; ILP32-NEXT: fsd ft0, 200(sp) ; ILP32-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 56(s1) ; ILP32-NEXT: fld ft0, 56(s1)
; ILP32-NEXT: fsd ft0, 192(sp) ; ILP32-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 64(s1) ; ILP32-NEXT: fld ft0, 64(s1)
; ILP32-NEXT: fsd ft0, 184(sp) ; ILP32-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 72(s1) ; ILP32-NEXT: fld ft0, 72(s1)
; ILP32-NEXT: fsd ft0, 176(sp) ; ILP32-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 80(s1) ; ILP32-NEXT: fld ft0, 80(s1)
; ILP32-NEXT: fsd ft0, 168(sp) ; ILP32-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 88(s1) ; ILP32-NEXT: fld ft0, 88(s1)
; ILP32-NEXT: fsd ft0, 160(sp) ; ILP32-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 96(s1) ; ILP32-NEXT: fld ft0, 96(s1)
; ILP32-NEXT: fsd ft0, 152(sp) ; ILP32-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 104(s1) ; ILP32-NEXT: fld ft0, 104(s1)
; ILP32-NEXT: fsd ft0, 144(sp) ; ILP32-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 112(s1) ; ILP32-NEXT: fld ft0, 112(s1)
; ILP32-NEXT: fsd ft0, 136(sp) ; ILP32-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 120(s1) ; ILP32-NEXT: fld ft0, 120(s1)
; ILP32-NEXT: fsd ft0, 128(sp) ; ILP32-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 128(s1) ; ILP32-NEXT: fld ft0, 128(s1)
; ILP32-NEXT: fsd ft0, 120(sp) ; ILP32-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 136(s1) ; ILP32-NEXT: fld ft0, 136(s1)
; ILP32-NEXT: fsd ft0, 112(sp) ; ILP32-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 144(s1) ; ILP32-NEXT: fld ft0, 144(s1)
; ILP32-NEXT: fsd ft0, 104(sp) ; ILP32-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 152(s1) ; ILP32-NEXT: fld ft0, 152(s1)
; ILP32-NEXT: fsd ft0, 96(sp) ; ILP32-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 160(s1) ; ILP32-NEXT: fld ft0, 160(s1)
; ILP32-NEXT: fsd ft0, 88(sp) ; ILP32-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 168(s1) ; ILP32-NEXT: fld ft0, 168(s1)
; ILP32-NEXT: fsd ft0, 80(sp) ; ILP32-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 176(s1) ; ILP32-NEXT: fld ft0, 176(s1)
; ILP32-NEXT: fsd ft0, 72(sp) ; ILP32-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 184(s1) ; ILP32-NEXT: fld ft0, 184(s1)
; ILP32-NEXT: fsd ft0, 64(sp) ; ILP32-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 192(s1) ; ILP32-NEXT: fld ft0, 192(s1)
; ILP32-NEXT: fsd ft0, 56(sp) ; ILP32-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 200(s1) ; ILP32-NEXT: fld ft0, 200(s1)
; ILP32-NEXT: fsd ft0, 48(sp) ; ILP32-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 208(s1) ; ILP32-NEXT: fld ft0, 208(s1)
; ILP32-NEXT: fsd ft0, 40(sp) ; ILP32-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 216(s1) ; ILP32-NEXT: fld ft0, 216(s1)
; ILP32-NEXT: fsd ft0, 32(sp) ; ILP32-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 224(s1) ; ILP32-NEXT: fld ft0, 224(s1)
; ILP32-NEXT: fsd ft0, 24(sp) ; ILP32-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 232(s1) ; ILP32-NEXT: fld ft0, 232(s1)
; ILP32-NEXT: fsd ft0, 16(sp) ; ILP32-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 240(s1) ; ILP32-NEXT: fld ft0, 240(s1)
; ILP32-NEXT: fsd ft0, 8(sp) ; ILP32-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 248(s1) ; ILP32-NEXT: fld ft0, 248(s1)
; ILP32-NEXT: fsd ft0, 0(sp) ; ILP32-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; ILP32-NEXT: call callee ; ILP32-NEXT: call callee
; ILP32-NEXT: fld ft0, 0(sp) ; ILP32-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 248(s1) ; ILP32-NEXT: fsd ft0, 248(s1)
; ILP32-NEXT: fld ft0, 8(sp) ; ILP32-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 240(s1) ; ILP32-NEXT: fsd ft0, 240(s1)
; ILP32-NEXT: fld ft0, 16(sp) ; ILP32-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 232(s1) ; ILP32-NEXT: fsd ft0, 232(s1)
; ILP32-NEXT: fld ft0, 24(sp) ; ILP32-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 224(s1) ; ILP32-NEXT: fsd ft0, 224(s1)
; ILP32-NEXT: fld ft0, 32(sp) ; ILP32-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 216(s1) ; ILP32-NEXT: fsd ft0, 216(s1)
; ILP32-NEXT: fld ft0, 40(sp) ; ILP32-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 208(s1) ; ILP32-NEXT: fsd ft0, 208(s1)
; ILP32-NEXT: fld ft0, 48(sp) ; ILP32-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 200(s1) ; ILP32-NEXT: fsd ft0, 200(s1)
; ILP32-NEXT: fld ft0, 56(sp) ; ILP32-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 192(s1) ; ILP32-NEXT: fsd ft0, 192(s1)
; ILP32-NEXT: fld ft0, 64(sp) ; ILP32-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 184(s1) ; ILP32-NEXT: fsd ft0, 184(s1)
; ILP32-NEXT: fld ft0, 72(sp) ; ILP32-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 176(s1) ; ILP32-NEXT: fsd ft0, 176(s1)
; ILP32-NEXT: fld ft0, 80(sp) ; ILP32-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 168(s1) ; ILP32-NEXT: fsd ft0, 168(s1)
; ILP32-NEXT: fld ft0, 88(sp) ; ILP32-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 160(s1) ; ILP32-NEXT: fsd ft0, 160(s1)
; ILP32-NEXT: fld ft0, 96(sp) ; ILP32-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 152(s1) ; ILP32-NEXT: fsd ft0, 152(s1)
; ILP32-NEXT: fld ft0, 104(sp) ; ILP32-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 144(s1) ; ILP32-NEXT: fsd ft0, 144(s1)
; ILP32-NEXT: fld ft0, 112(sp) ; ILP32-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 136(s1) ; ILP32-NEXT: fsd ft0, 136(s1)
; ILP32-NEXT: fld ft0, 120(sp) ; ILP32-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 128(s1) ; ILP32-NEXT: fsd ft0, 128(s1)
; ILP32-NEXT: fld ft0, 128(sp) ; ILP32-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 120(s1) ; ILP32-NEXT: fsd ft0, 120(s1)
; ILP32-NEXT: fld ft0, 136(sp) ; ILP32-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 112(s1) ; ILP32-NEXT: fsd ft0, 112(s1)
; ILP32-NEXT: fld ft0, 144(sp) ; ILP32-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 104(s1) ; ILP32-NEXT: fsd ft0, 104(s1)
; ILP32-NEXT: fld ft0, 152(sp) ; ILP32-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 96(s1) ; ILP32-NEXT: fsd ft0, 96(s1)
; ILP32-NEXT: fld ft0, 160(sp) ; ILP32-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 88(s1) ; ILP32-NEXT: fsd ft0, 88(s1)
; ILP32-NEXT: fld ft0, 168(sp) ; ILP32-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 80(s1) ; ILP32-NEXT: fsd ft0, 80(s1)
; ILP32-NEXT: fld ft0, 176(sp) ; ILP32-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 72(s1) ; ILP32-NEXT: fsd ft0, 72(s1)
; ILP32-NEXT: fld ft0, 184(sp) ; ILP32-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 64(s1) ; ILP32-NEXT: fsd ft0, 64(s1)
; ILP32-NEXT: fld ft0, 192(sp) ; ILP32-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 56(s1) ; ILP32-NEXT: fsd ft0, 56(s1)
; ILP32-NEXT: fld ft0, 200(sp) ; ILP32-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 48(s1) ; ILP32-NEXT: fsd ft0, 48(s1)
; ILP32-NEXT: fld ft0, 208(sp) ; ILP32-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 40(s1) ; ILP32-NEXT: fsd ft0, 40(s1)
; ILP32-NEXT: fld ft0, 216(sp) ; ILP32-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 32(s1) ; ILP32-NEXT: fsd ft0, 32(s1)
; ILP32-NEXT: fld ft0, 224(sp) ; ILP32-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 24(s1) ; ILP32-NEXT: fsd ft0, 24(s1)
; ILP32-NEXT: fld ft0, 232(sp) ; ILP32-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 16(s1) ; ILP32-NEXT: fsd ft0, 16(s1)
; ILP32-NEXT: fld ft0, 240(sp) ; ILP32-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32-NEXT: fsd ft0, %lo(var+8)(s0)
; ILP32-NEXT: fld ft0, 248(sp) ; ILP32-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, %lo(var)(s0) ; ILP32-NEXT: fsd ft0, %lo(var)(s0)
; ILP32-NEXT: lw s1, 260(sp) ; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 264(sp) ; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw ra, 268(sp) ; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 272 ; ILP32-NEXT: addi sp, sp, 272
; ILP32-NEXT: ret ; ILP32-NEXT: ret
; ;
; LP64-LABEL: caller: ; LP64-LABEL: caller:
; LP64: # %bb.0: ; LP64: # %bb.0:
; LP64-NEXT: addi sp, sp, -288 ; LP64-NEXT: addi sp, sp, -288
; LP64-NEXT: sd ra, 280(sp) ; LP64-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s0, 272(sp) ; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; LP64-NEXT: sd s1, 264(sp) ; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var) ; LP64-NEXT: lui s0, %hi(var)
; LP64-NEXT: fld ft0, %lo(var)(s0) ; LP64-NEXT: fld ft0, %lo(var)(s0)
; LP64-NEXT: fsd ft0, 256(sp) ; LP64-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, %lo(var+8)(s0) ; LP64-NEXT: fld ft0, %lo(var+8)(s0)
; LP64-NEXT: fsd ft0, 248(sp) ; LP64-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: addi s1, s0, %lo(var)
; LP64-NEXT: fld ft0, 16(s1) ; LP64-NEXT: fld ft0, 16(s1)
; LP64-NEXT: fsd ft0, 240(sp) ; LP64-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 24(s1) ; LP64-NEXT: fld ft0, 24(s1)
; LP64-NEXT: fsd ft0, 232(sp) ; LP64-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 32(s1) ; LP64-NEXT: fld ft0, 32(s1)
; LP64-NEXT: fsd ft0, 224(sp) ; LP64-NEXT: fsd ft0, 224(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 40(s1) ; LP64-NEXT: fld ft0, 40(s1)
; LP64-NEXT: fsd ft0, 216(sp) ; LP64-NEXT: fsd ft0, 216(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 48(s1) ; LP64-NEXT: fld ft0, 48(s1)
; LP64-NEXT: fsd ft0, 208(sp) ; LP64-NEXT: fsd ft0, 208(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 56(s1) ; LP64-NEXT: fld ft0, 56(s1)
; LP64-NEXT: fsd ft0, 200(sp) ; LP64-NEXT: fsd ft0, 200(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 64(s1) ; LP64-NEXT: fld ft0, 64(s1)
; LP64-NEXT: fsd ft0, 192(sp) ; LP64-NEXT: fsd ft0, 192(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 72(s1) ; LP64-NEXT: fld ft0, 72(s1)
; LP64-NEXT: fsd ft0, 184(sp) ; LP64-NEXT: fsd ft0, 184(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 80(s1) ; LP64-NEXT: fld ft0, 80(s1)
; LP64-NEXT: fsd ft0, 176(sp) ; LP64-NEXT: fsd ft0, 176(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 88(s1) ; LP64-NEXT: fld ft0, 88(s1)
; LP64-NEXT: fsd ft0, 168(sp) ; LP64-NEXT: fsd ft0, 168(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 96(s1) ; LP64-NEXT: fld ft0, 96(s1)
; LP64-NEXT: fsd ft0, 160(sp) ; LP64-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 104(s1) ; LP64-NEXT: fld ft0, 104(s1)
; LP64-NEXT: fsd ft0, 152(sp) ; LP64-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 112(s1) ; LP64-NEXT: fld ft0, 112(s1)
; LP64-NEXT: fsd ft0, 144(sp) ; LP64-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 120(s1) ; LP64-NEXT: fld ft0, 120(s1)
; LP64-NEXT: fsd ft0, 136(sp) ; LP64-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 128(s1) ; LP64-NEXT: fld ft0, 128(s1)
; LP64-NEXT: fsd ft0, 128(sp) ; LP64-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 136(s1) ; LP64-NEXT: fld ft0, 136(s1)
; LP64-NEXT: fsd ft0, 120(sp) ; LP64-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 144(s1) ; LP64-NEXT: fld ft0, 144(s1)
; LP64-NEXT: fsd ft0, 112(sp) ; LP64-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 152(s1) ; LP64-NEXT: fld ft0, 152(s1)
; LP64-NEXT: fsd ft0, 104(sp) ; LP64-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 160(s1) ; LP64-NEXT: fld ft0, 160(s1)
; LP64-NEXT: fsd ft0, 96(sp) ; LP64-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 168(s1) ; LP64-NEXT: fld ft0, 168(s1)
; LP64-NEXT: fsd ft0, 88(sp) ; LP64-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 176(s1) ; LP64-NEXT: fld ft0, 176(s1)
; LP64-NEXT: fsd ft0, 80(sp) ; LP64-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 184(s1) ; LP64-NEXT: fld ft0, 184(s1)
; LP64-NEXT: fsd ft0, 72(sp) ; LP64-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 192(s1) ; LP64-NEXT: fld ft0, 192(s1)
; LP64-NEXT: fsd ft0, 64(sp) ; LP64-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 200(s1) ; LP64-NEXT: fld ft0, 200(s1)
; LP64-NEXT: fsd ft0, 56(sp) ; LP64-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 208(s1) ; LP64-NEXT: fld ft0, 208(s1)
; LP64-NEXT: fsd ft0, 48(sp) ; LP64-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 216(s1) ; LP64-NEXT: fld ft0, 216(s1)
; LP64-NEXT: fsd ft0, 40(sp) ; LP64-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 224(s1) ; LP64-NEXT: fld ft0, 224(s1)
; LP64-NEXT: fsd ft0, 32(sp) ; LP64-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 232(s1) ; LP64-NEXT: fld ft0, 232(s1)
; LP64-NEXT: fsd ft0, 24(sp) ; LP64-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 240(s1) ; LP64-NEXT: fld ft0, 240(s1)
; LP64-NEXT: fsd ft0, 16(sp) ; LP64-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 248(s1) ; LP64-NEXT: fld ft0, 248(s1)
; LP64-NEXT: fsd ft0, 8(sp) ; LP64-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; LP64-NEXT: call callee ; LP64-NEXT: call callee
; LP64-NEXT: fld ft0, 8(sp) ; LP64-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 248(s1) ; LP64-NEXT: fsd ft0, 248(s1)
; LP64-NEXT: fld ft0, 16(sp) ; LP64-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 240(s1) ; LP64-NEXT: fsd ft0, 240(s1)
; LP64-NEXT: fld ft0, 24(sp) ; LP64-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 232(s1) ; LP64-NEXT: fsd ft0, 232(s1)
; LP64-NEXT: fld ft0, 32(sp) ; LP64-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 224(s1) ; LP64-NEXT: fsd ft0, 224(s1)
; LP64-NEXT: fld ft0, 40(sp) ; LP64-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 216(s1) ; LP64-NEXT: fsd ft0, 216(s1)
; LP64-NEXT: fld ft0, 48(sp) ; LP64-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 208(s1) ; LP64-NEXT: fsd ft0, 208(s1)
; LP64-NEXT: fld ft0, 56(sp) ; LP64-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 200(s1) ; LP64-NEXT: fsd ft0, 200(s1)
; LP64-NEXT: fld ft0, 64(sp) ; LP64-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 192(s1) ; LP64-NEXT: fsd ft0, 192(s1)
; LP64-NEXT: fld ft0, 72(sp) ; LP64-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 184(s1) ; LP64-NEXT: fsd ft0, 184(s1)
; LP64-NEXT: fld ft0, 80(sp) ; LP64-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 176(s1) ; LP64-NEXT: fsd ft0, 176(s1)
; LP64-NEXT: fld ft0, 88(sp) ; LP64-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 168(s1) ; LP64-NEXT: fsd ft0, 168(s1)
; LP64-NEXT: fld ft0, 96(sp) ; LP64-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 160(s1) ; LP64-NEXT: fsd ft0, 160(s1)
; LP64-NEXT: fld ft0, 104(sp) ; LP64-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 152(s1) ; LP64-NEXT: fsd ft0, 152(s1)
; LP64-NEXT: fld ft0, 112(sp) ; LP64-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 144(s1) ; LP64-NEXT: fsd ft0, 144(s1)
; LP64-NEXT: fld ft0, 120(sp) ; LP64-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 136(s1) ; LP64-NEXT: fsd ft0, 136(s1)
; LP64-NEXT: fld ft0, 128(sp) ; LP64-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 128(s1) ; LP64-NEXT: fsd ft0, 128(s1)
; LP64-NEXT: fld ft0, 136(sp) ; LP64-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 120(s1) ; LP64-NEXT: fsd ft0, 120(s1)
; LP64-NEXT: fld ft0, 144(sp) ; LP64-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 112(s1) ; LP64-NEXT: fsd ft0, 112(s1)
; LP64-NEXT: fld ft0, 152(sp) ; LP64-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 104(s1) ; LP64-NEXT: fsd ft0, 104(s1)
; LP64-NEXT: fld ft0, 160(sp) ; LP64-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 96(s1) ; LP64-NEXT: fsd ft0, 96(s1)
; LP64-NEXT: fld ft0, 168(sp) ; LP64-NEXT: fld ft0, 168(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 88(s1) ; LP64-NEXT: fsd ft0, 88(s1)
; LP64-NEXT: fld ft0, 176(sp) ; LP64-NEXT: fld ft0, 176(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 80(s1) ; LP64-NEXT: fsd ft0, 80(s1)
; LP64-NEXT: fld ft0, 184(sp) ; LP64-NEXT: fld ft0, 184(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 72(s1) ; LP64-NEXT: fsd ft0, 72(s1)
; LP64-NEXT: fld ft0, 192(sp) ; LP64-NEXT: fld ft0, 192(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 64(s1) ; LP64-NEXT: fsd ft0, 64(s1)
; LP64-NEXT: fld ft0, 200(sp) ; LP64-NEXT: fld ft0, 200(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 56(s1) ; LP64-NEXT: fsd ft0, 56(s1)
; LP64-NEXT: fld ft0, 208(sp) ; LP64-NEXT: fld ft0, 208(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 48(s1) ; LP64-NEXT: fsd ft0, 48(s1)
; LP64-NEXT: fld ft0, 216(sp) ; LP64-NEXT: fld ft0, 216(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 40(s1) ; LP64-NEXT: fsd ft0, 40(s1)
; LP64-NEXT: fld ft0, 224(sp) ; LP64-NEXT: fld ft0, 224(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 32(s1) ; LP64-NEXT: fsd ft0, 32(s1)
; LP64-NEXT: fld ft0, 232(sp) ; LP64-NEXT: fld ft0, 232(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 24(s1) ; LP64-NEXT: fsd ft0, 24(s1)
; LP64-NEXT: fld ft0, 240(sp) ; LP64-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 16(s1) ; LP64-NEXT: fsd ft0, 16(s1)
; LP64-NEXT: fld ft0, 248(sp) ; LP64-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64-NEXT: fsd ft0, %lo(var+8)(s0)
; LP64-NEXT: fld ft0, 256(sp) ; LP64-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, %lo(var)(s0) ; LP64-NEXT: fsd ft0, %lo(var)(s0)
; LP64-NEXT: ld s1, 264(sp) ; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; LP64-NEXT: ld s0, 272(sp) ; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64-NEXT: ld ra, 280(sp) ; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64-NEXT: addi sp, sp, 288 ; LP64-NEXT: addi sp, sp, 288
; LP64-NEXT: ret ; LP64-NEXT: ret
; ;
; ILP32D-LABEL: caller: ; ILP32D-LABEL: caller:
; ILP32D: # %bb.0: ; ILP32D: # %bb.0:
; ILP32D-NEXT: addi sp, sp, -272 ; ILP32D-NEXT: addi sp, sp, -272
; ILP32D-NEXT: sw ra, 268(sp) ; ILP32D-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s0, 264(sp) ; ILP32D-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s1, 260(sp) ; ILP32D-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
; ILP32D-NEXT: fsd fs0, 248(sp) ; ILP32D-NEXT: fsd fs0, 248(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs1, 240(sp) ; ILP32D-NEXT: fsd fs1, 240(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs2, 232(sp) ; ILP32D-NEXT: fsd fs2, 232(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs3, 224(sp) ; ILP32D-NEXT: fsd fs3, 224(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs4, 216(sp) ; ILP32D-NEXT: fsd fs4, 216(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs5, 208(sp) ; ILP32D-NEXT: fsd fs5, 208(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs6, 200(sp) ; ILP32D-NEXT: fsd fs6, 200(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs7, 192(sp) ; ILP32D-NEXT: fsd fs7, 192(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs8, 184(sp) ; ILP32D-NEXT: fsd fs8, 184(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs9, 176(sp) ; ILP32D-NEXT: fsd fs9, 176(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs10, 168(sp) ; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 160(sp) ; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var) ; ILP32D-NEXT: lui s0, %hi(var)
; ILP32D-NEXT: fld ft0, %lo(var)(s0) ; ILP32D-NEXT: fld ft0, %lo(var)(s0)
; ILP32D-NEXT: fsd ft0, 152(sp) ; ILP32D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fld ft0, %lo(var+8)(s0)
; ILP32D-NEXT: fsd ft0, 144(sp) ; ILP32D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: addi s1, s0, %lo(var)
; ILP32D-NEXT: fld ft0, 16(s1) ; ILP32D-NEXT: fld ft0, 16(s1)
; ILP32D-NEXT: fsd ft0, 136(sp) ; ILP32D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 24(s1) ; ILP32D-NEXT: fld ft0, 24(s1)
; ILP32D-NEXT: fsd ft0, 128(sp) ; ILP32D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 32(s1) ; ILP32D-NEXT: fld ft0, 32(s1)
; ILP32D-NEXT: fsd ft0, 120(sp) ; ILP32D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 40(s1) ; ILP32D-NEXT: fld ft0, 40(s1)
; ILP32D-NEXT: fsd ft0, 112(sp) ; ILP32D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 48(s1) ; ILP32D-NEXT: fld ft0, 48(s1)
; ILP32D-NEXT: fsd ft0, 104(sp) ; ILP32D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 56(s1) ; ILP32D-NEXT: fld ft0, 56(s1)
; ILP32D-NEXT: fsd ft0, 96(sp) ; ILP32D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 64(s1) ; ILP32D-NEXT: fld ft0, 64(s1)
; ILP32D-NEXT: fsd ft0, 88(sp) ; ILP32D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 72(s1) ; ILP32D-NEXT: fld ft0, 72(s1)
; ILP32D-NEXT: fsd ft0, 80(sp) ; ILP32D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 80(s1) ; ILP32D-NEXT: fld ft0, 80(s1)
; ILP32D-NEXT: fsd ft0, 72(sp) ; ILP32D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 88(s1) ; ILP32D-NEXT: fld ft0, 88(s1)
; ILP32D-NEXT: fsd ft0, 64(sp) ; ILP32D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 96(s1) ; ILP32D-NEXT: fld ft0, 96(s1)
; ILP32D-NEXT: fsd ft0, 56(sp) ; ILP32D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 104(s1) ; ILP32D-NEXT: fld ft0, 104(s1)
; ILP32D-NEXT: fsd ft0, 48(sp) ; ILP32D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 112(s1) ; ILP32D-NEXT: fld ft0, 112(s1)
; ILP32D-NEXT: fsd ft0, 40(sp) ; ILP32D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 120(s1) ; ILP32D-NEXT: fld ft0, 120(s1)
; ILP32D-NEXT: fsd ft0, 32(sp) ; ILP32D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 128(s1) ; ILP32D-NEXT: fld ft0, 128(s1)
; ILP32D-NEXT: fsd ft0, 24(sp) ; ILP32D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 136(s1) ; ILP32D-NEXT: fld ft0, 136(s1)
; ILP32D-NEXT: fsd ft0, 16(sp) ; ILP32D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 144(s1) ; ILP32D-NEXT: fld ft0, 144(s1)
; ILP32D-NEXT: fsd ft0, 8(sp) ; ILP32D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld ft0, 152(s1) ; ILP32D-NEXT: fld ft0, 152(s1)
; ILP32D-NEXT: fsd ft0, 0(sp) ; ILP32D-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fld fs8, 160(s1) ; ILP32D-NEXT: fld fs8, 160(s1)
; ILP32D-NEXT: fld fs9, 168(s1) ; ILP32D-NEXT: fld fs9, 168(s1)
; ILP32D-NEXT: fld fs10, 176(s1) ; ILP32D-NEXT: fld fs10, 176(s1)
; ILP32D-NEXT: fld fs11, 184(s1) ; ILP32D-NEXT: fld fs11, 184(s1)
; ILP32D-NEXT: fld fs0, 192(s1) ; ILP32D-NEXT: fld fs0, 192(s1)
; ILP32D-NEXT: fld fs1, 200(s1) ; ILP32D-NEXT: fld fs1, 200(s1)
; ILP32D-NEXT: fld fs2, 208(s1) ; ILP32D-NEXT: fld fs2, 208(s1)
; ILP32D-NEXT: fld fs3, 216(s1) ; ILP32D-NEXT: fld fs3, 216(s1)
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; ILP32D-NEXT: fsd fs3, 216(s1) ; ILP32D-NEXT: fsd fs3, 216(s1)
; ILP32D-NEXT: fsd fs2, 208(s1) ; ILP32D-NEXT: fsd fs2, 208(s1)
; ILP32D-NEXT: fsd fs1, 200(s1) ; ILP32D-NEXT: fsd fs1, 200(s1)
; ILP32D-NEXT: fsd fs0, 192(s1) ; ILP32D-NEXT: fsd fs0, 192(s1)
; ILP32D-NEXT: fsd fs11, 184(s1) ; ILP32D-NEXT: fsd fs11, 184(s1)
; ILP32D-NEXT: fsd fs10, 176(s1) ; ILP32D-NEXT: fsd fs10, 176(s1)
; ILP32D-NEXT: fsd fs9, 168(s1) ; ILP32D-NEXT: fsd fs9, 168(s1)
; ILP32D-NEXT: fsd fs8, 160(s1) ; ILP32D-NEXT: fsd fs8, 160(s1)
; ILP32D-NEXT: fld ft0, 0(sp) ; ILP32D-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 152(s1) ; ILP32D-NEXT: fsd ft0, 152(s1)
; ILP32D-NEXT: fld ft0, 8(sp) ; ILP32D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 144(s1) ; ILP32D-NEXT: fsd ft0, 144(s1)
; ILP32D-NEXT: fld ft0, 16(sp) ; ILP32D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 136(s1) ; ILP32D-NEXT: fsd ft0, 136(s1)
; ILP32D-NEXT: fld ft0, 24(sp) ; ILP32D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 128(s1) ; ILP32D-NEXT: fsd ft0, 128(s1)
; ILP32D-NEXT: fld ft0, 32(sp) ; ILP32D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 120(s1) ; ILP32D-NEXT: fsd ft0, 120(s1)
; ILP32D-NEXT: fld ft0, 40(sp) ; ILP32D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 112(s1) ; ILP32D-NEXT: fsd ft0, 112(s1)
; ILP32D-NEXT: fld ft0, 48(sp) ; ILP32D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 104(s1) ; ILP32D-NEXT: fsd ft0, 104(s1)
; ILP32D-NEXT: fld ft0, 56(sp) ; ILP32D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 96(s1) ; ILP32D-NEXT: fsd ft0, 96(s1)
; ILP32D-NEXT: fld ft0, 64(sp) ; ILP32D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 88(s1) ; ILP32D-NEXT: fsd ft0, 88(s1)
; ILP32D-NEXT: fld ft0, 72(sp) ; ILP32D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 80(s1) ; ILP32D-NEXT: fsd ft0, 80(s1)
; ILP32D-NEXT: fld ft0, 80(sp) ; ILP32D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 72(s1) ; ILP32D-NEXT: fsd ft0, 72(s1)
; ILP32D-NEXT: fld ft0, 88(sp) ; ILP32D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 64(s1) ; ILP32D-NEXT: fsd ft0, 64(s1)
; ILP32D-NEXT: fld ft0, 96(sp) ; ILP32D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 56(s1) ; ILP32D-NEXT: fsd ft0, 56(s1)
; ILP32D-NEXT: fld ft0, 104(sp) ; ILP32D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 48(s1) ; ILP32D-NEXT: fsd ft0, 48(s1)
; ILP32D-NEXT: fld ft0, 112(sp) ; ILP32D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 40(s1) ; ILP32D-NEXT: fsd ft0, 40(s1)
; ILP32D-NEXT: fld ft0, 120(sp) ; ILP32D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 32(s1) ; ILP32D-NEXT: fsd ft0, 32(s1)
; ILP32D-NEXT: fld ft0, 128(sp) ; ILP32D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 24(s1) ; ILP32D-NEXT: fsd ft0, 24(s1)
; ILP32D-NEXT: fld ft0, 136(sp) ; ILP32D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, 16(s1) ; ILP32D-NEXT: fsd ft0, 16(s1)
; ILP32D-NEXT: fld ft0, 144(sp) ; ILP32D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0)
; ILP32D-NEXT: fld ft0, 152(sp) ; ILP32D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fsd ft0, %lo(var)(s0) ; ILP32D-NEXT: fsd ft0, %lo(var)(s0)
; ILP32D-NEXT: fld fs11, 160(sp) ; ILP32D-NEXT: fld fs11, 160(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs10, 168(sp) ; ILP32D-NEXT: fld fs10, 168(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs9, 176(sp) ; ILP32D-NEXT: fld fs9, 176(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs8, 184(sp) ; ILP32D-NEXT: fld fs8, 184(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs7, 192(sp) ; ILP32D-NEXT: fld fs7, 192(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs6, 200(sp) ; ILP32D-NEXT: fld fs6, 200(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs5, 208(sp) ; ILP32D-NEXT: fld fs5, 208(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs4, 216(sp) ; ILP32D-NEXT: fld fs4, 216(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs3, 224(sp) ; ILP32D-NEXT: fld fs3, 224(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 232(sp) ; ILP32D-NEXT: fld fs2, 232(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 240(sp) ; ILP32D-NEXT: fld fs1, 240(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs0, 248(sp) ; ILP32D-NEXT: fld fs0, 248(sp) # 8-byte Folded Reload
; ILP32D-NEXT: lw s1, 260(sp) ; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 264(sp) ; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw ra, 268(sp) ; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 272 ; ILP32D-NEXT: addi sp, sp, 272
; ILP32D-NEXT: ret ; ILP32D-NEXT: ret
; ;
; LP64D-LABEL: caller: ; LP64D-LABEL: caller:
; LP64D: # %bb.0: ; LP64D: # %bb.0:
; LP64D-NEXT: addi sp, sp, -288 ; LP64D-NEXT: addi sp, sp, -288
; LP64D-NEXT: sd ra, 280(sp) ; LP64D-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
; LP64D-NEXT: sd s0, 272(sp) ; LP64D-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; LP64D-NEXT: sd s1, 264(sp) ; LP64D-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs0, 256(sp) ; LP64D-NEXT: fsd fs0, 256(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs1, 248(sp) ; LP64D-NEXT: fsd fs1, 248(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs2, 240(sp) ; LP64D-NEXT: fsd fs2, 240(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs3, 232(sp) ; LP64D-NEXT: fsd fs3, 232(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs4, 224(sp) ; LP64D-NEXT: fsd fs4, 224(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs5, 216(sp) ; LP64D-NEXT: fsd fs5, 216(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs6, 208(sp) ; LP64D-NEXT: fsd fs6, 208(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs7, 200(sp) ; LP64D-NEXT: fsd fs7, 200(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs8, 192(sp) ; LP64D-NEXT: fsd fs8, 192(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs9, 184(sp) ; LP64D-NEXT: fsd fs9, 184(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs10, 176(sp) ; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 168(sp) ; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var) ; LP64D-NEXT: lui s0, %hi(var)
; LP64D-NEXT: fld ft0, %lo(var)(s0) ; LP64D-NEXT: fld ft0, %lo(var)(s0)
; LP64D-NEXT: fsd ft0, 160(sp) ; LP64D-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, %lo(var+8)(s0) ; LP64D-NEXT: fld ft0, %lo(var+8)(s0)
; LP64D-NEXT: fsd ft0, 152(sp) ; LP64D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill
; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: addi s1, s0, %lo(var)
; LP64D-NEXT: fld ft0, 16(s1) ; LP64D-NEXT: fld ft0, 16(s1)
; LP64D-NEXT: fsd ft0, 144(sp) ; LP64D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 24(s1) ; LP64D-NEXT: fld ft0, 24(s1)
; LP64D-NEXT: fsd ft0, 136(sp) ; LP64D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 32(s1) ; LP64D-NEXT: fld ft0, 32(s1)
; LP64D-NEXT: fsd ft0, 128(sp) ; LP64D-NEXT: fsd ft0, 128(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 40(s1) ; LP64D-NEXT: fld ft0, 40(s1)
; LP64D-NEXT: fsd ft0, 120(sp) ; LP64D-NEXT: fsd ft0, 120(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 48(s1) ; LP64D-NEXT: fld ft0, 48(s1)
; LP64D-NEXT: fsd ft0, 112(sp) ; LP64D-NEXT: fsd ft0, 112(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 56(s1) ; LP64D-NEXT: fld ft0, 56(s1)
; LP64D-NEXT: fsd ft0, 104(sp) ; LP64D-NEXT: fsd ft0, 104(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 64(s1) ; LP64D-NEXT: fld ft0, 64(s1)
; LP64D-NEXT: fsd ft0, 96(sp) ; LP64D-NEXT: fsd ft0, 96(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 72(s1) ; LP64D-NEXT: fld ft0, 72(s1)
; LP64D-NEXT: fsd ft0, 88(sp) ; LP64D-NEXT: fsd ft0, 88(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 80(s1) ; LP64D-NEXT: fld ft0, 80(s1)
; LP64D-NEXT: fsd ft0, 80(sp) ; LP64D-NEXT: fsd ft0, 80(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 88(s1) ; LP64D-NEXT: fld ft0, 88(s1)
; LP64D-NEXT: fsd ft0, 72(sp) ; LP64D-NEXT: fsd ft0, 72(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 96(s1) ; LP64D-NEXT: fld ft0, 96(s1)
; LP64D-NEXT: fsd ft0, 64(sp) ; LP64D-NEXT: fsd ft0, 64(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 104(s1) ; LP64D-NEXT: fld ft0, 104(s1)
; LP64D-NEXT: fsd ft0, 56(sp) ; LP64D-NEXT: fsd ft0, 56(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 112(s1) ; LP64D-NEXT: fld ft0, 112(s1)
; LP64D-NEXT: fsd ft0, 48(sp) ; LP64D-NEXT: fsd ft0, 48(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 120(s1) ; LP64D-NEXT: fld ft0, 120(s1)
; LP64D-NEXT: fsd ft0, 40(sp) ; LP64D-NEXT: fsd ft0, 40(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 128(s1) ; LP64D-NEXT: fld ft0, 128(s1)
; LP64D-NEXT: fsd ft0, 32(sp) ; LP64D-NEXT: fsd ft0, 32(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 136(s1) ; LP64D-NEXT: fld ft0, 136(s1)
; LP64D-NEXT: fsd ft0, 24(sp) ; LP64D-NEXT: fsd ft0, 24(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 144(s1) ; LP64D-NEXT: fld ft0, 144(s1)
; LP64D-NEXT: fsd ft0, 16(sp) ; LP64D-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld ft0, 152(s1) ; LP64D-NEXT: fld ft0, 152(s1)
; LP64D-NEXT: fsd ft0, 8(sp) ; LP64D-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fld fs8, 160(s1) ; LP64D-NEXT: fld fs8, 160(s1)
; LP64D-NEXT: fld fs9, 168(s1) ; LP64D-NEXT: fld fs9, 168(s1)
; LP64D-NEXT: fld fs10, 176(s1) ; LP64D-NEXT: fld fs10, 176(s1)
; LP64D-NEXT: fld fs11, 184(s1) ; LP64D-NEXT: fld fs11, 184(s1)
; LP64D-NEXT: fld fs0, 192(s1) ; LP64D-NEXT: fld fs0, 192(s1)
; LP64D-NEXT: fld fs1, 200(s1) ; LP64D-NEXT: fld fs1, 200(s1)
; LP64D-NEXT: fld fs2, 208(s1) ; LP64D-NEXT: fld fs2, 208(s1)
; LP64D-NEXT: fld fs3, 216(s1) ; LP64D-NEXT: fld fs3, 216(s1)
Show All 9 Lines
; LP64D-NEXT: fsd fs3, 216(s1) ; LP64D-NEXT: fsd fs3, 216(s1)
; LP64D-NEXT: fsd fs2, 208(s1) ; LP64D-NEXT: fsd fs2, 208(s1)
; LP64D-NEXT: fsd fs1, 200(s1) ; LP64D-NEXT: fsd fs1, 200(s1)
; LP64D-NEXT: fsd fs0, 192(s1) ; LP64D-NEXT: fsd fs0, 192(s1)
; LP64D-NEXT: fsd fs11, 184(s1) ; LP64D-NEXT: fsd fs11, 184(s1)
; LP64D-NEXT: fsd fs10, 176(s1) ; LP64D-NEXT: fsd fs10, 176(s1)
; LP64D-NEXT: fsd fs9, 168(s1) ; LP64D-NEXT: fsd fs9, 168(s1)
; LP64D-NEXT: fsd fs8, 160(s1) ; LP64D-NEXT: fsd fs8, 160(s1)
; LP64D-NEXT: fld ft0, 8(sp) ; LP64D-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 152(s1) ; LP64D-NEXT: fsd ft0, 152(s1)
; LP64D-NEXT: fld ft0, 16(sp) ; LP64D-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 144(s1) ; LP64D-NEXT: fsd ft0, 144(s1)
; LP64D-NEXT: fld ft0, 24(sp) ; LP64D-NEXT: fld ft0, 24(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 136(s1) ; LP64D-NEXT: fsd ft0, 136(s1)
; LP64D-NEXT: fld ft0, 32(sp) ; LP64D-NEXT: fld ft0, 32(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 128(s1) ; LP64D-NEXT: fsd ft0, 128(s1)
; LP64D-NEXT: fld ft0, 40(sp) ; LP64D-NEXT: fld ft0, 40(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 120(s1) ; LP64D-NEXT: fsd ft0, 120(s1)
; LP64D-NEXT: fld ft0, 48(sp) ; LP64D-NEXT: fld ft0, 48(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 112(s1) ; LP64D-NEXT: fsd ft0, 112(s1)
; LP64D-NEXT: fld ft0, 56(sp) ; LP64D-NEXT: fld ft0, 56(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 104(s1) ; LP64D-NEXT: fsd ft0, 104(s1)
; LP64D-NEXT: fld ft0, 64(sp) ; LP64D-NEXT: fld ft0, 64(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 96(s1) ; LP64D-NEXT: fsd ft0, 96(s1)
; LP64D-NEXT: fld ft0, 72(sp) ; LP64D-NEXT: fld ft0, 72(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 88(s1) ; LP64D-NEXT: fsd ft0, 88(s1)
; LP64D-NEXT: fld ft0, 80(sp) ; LP64D-NEXT: fld ft0, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 80(s1) ; LP64D-NEXT: fsd ft0, 80(s1)
; LP64D-NEXT: fld ft0, 88(sp) ; LP64D-NEXT: fld ft0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 72(s1) ; LP64D-NEXT: fsd ft0, 72(s1)
; LP64D-NEXT: fld ft0, 96(sp) ; LP64D-NEXT: fld ft0, 96(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 64(s1) ; LP64D-NEXT: fsd ft0, 64(s1)
; LP64D-NEXT: fld ft0, 104(sp) ; LP64D-NEXT: fld ft0, 104(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 56(s1) ; LP64D-NEXT: fsd ft0, 56(s1)
; LP64D-NEXT: fld ft0, 112(sp) ; LP64D-NEXT: fld ft0, 112(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 48(s1) ; LP64D-NEXT: fsd ft0, 48(s1)
; LP64D-NEXT: fld ft0, 120(sp) ; LP64D-NEXT: fld ft0, 120(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 40(s1) ; LP64D-NEXT: fsd ft0, 40(s1)
; LP64D-NEXT: fld ft0, 128(sp) ; LP64D-NEXT: fld ft0, 128(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 32(s1) ; LP64D-NEXT: fsd ft0, 32(s1)
; LP64D-NEXT: fld ft0, 136(sp) ; LP64D-NEXT: fld ft0, 136(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 24(s1) ; LP64D-NEXT: fsd ft0, 24(s1)
; LP64D-NEXT: fld ft0, 144(sp) ; LP64D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, 16(s1) ; LP64D-NEXT: fsd ft0, 16(s1)
; LP64D-NEXT: fld ft0, 152(sp) ; LP64D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64D-NEXT: fsd ft0, %lo(var+8)(s0)
; LP64D-NEXT: fld ft0, 160(sp) ; LP64D-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload
; LP64D-NEXT: fsd ft0, %lo(var)(s0) ; LP64D-NEXT: fsd ft0, %lo(var)(s0)
; LP64D-NEXT: fld fs11, 168(sp) ; LP64D-NEXT: fld fs11, 168(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs10, 176(sp) ; LP64D-NEXT: fld fs10, 176(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs9, 184(sp) ; LP64D-NEXT: fld fs9, 184(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs8, 192(sp) ; LP64D-NEXT: fld fs8, 192(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs7, 200(sp) ; LP64D-NEXT: fld fs7, 200(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs6, 208(sp) ; LP64D-NEXT: fld fs6, 208(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs5, 216(sp) ; LP64D-NEXT: fld fs5, 216(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs4, 224(sp) ; LP64D-NEXT: fld fs4, 224(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs3, 232(sp) ; LP64D-NEXT: fld fs3, 232(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 240(sp) ; LP64D-NEXT: fld fs2, 240(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 248(sp) ; LP64D-NEXT: fld fs1, 248(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs0, 256(sp) ; LP64D-NEXT: fld fs0, 256(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s1, 264(sp) ; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld s0, 272(sp) ; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; LP64D-NEXT: ld ra, 280(sp) ; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; LP64D-NEXT: addi sp, sp, 288 ; LP64D-NEXT: addi sp, sp, 288
; LP64D-NEXT: ret ; LP64D-NEXT: ret
%val = load [32 x double], [32 x double]* @var %val = load [32 x double], [32 x double]* @var
call void @callee() call void @callee()
store volatile [32 x double] %val, [32 x double]* @var store volatile [32 x double] %val, [32 x double]* @var
ret void ret void
} }

llvm/test/CodeGen/RISCV/callee-saved-gprs.ll

Show All 23 Lines
; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns ; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
; something appropriate. ; something appropriate.
define void @callee() nounwind { define void @callee() nounwind {
; RV32I-LABEL: callee: ; RV32I-LABEL: callee:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80 ; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp) ; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 72(sp) ; RV32I-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 68(sp) ; RV32I-NEXT: sw s1, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 64(sp) ; RV32I-NEXT: sw s2, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 60(sp) ; RV32I-NEXT: sw s3, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 56(sp) ; RV32I-NEXT: sw s4, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 52(sp) ; RV32I-NEXT: sw s5, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 48(sp) ; RV32I-NEXT: sw s6, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 44(sp) ; RV32I-NEXT: sw s7, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 40(sp) ; RV32I-NEXT: sw s8, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 36(sp) ; RV32I-NEXT: sw s9, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 32(sp) ; RV32I-NEXT: sw s10, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 28(sp) ; RV32I-NEXT: sw s11, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a7, %hi(var) ; RV32I-NEXT: lui a7, %hi(var)
; RV32I-NEXT: lw a0, %lo(var)(a7) ; RV32I-NEXT: lw a0, %lo(var)(a7)
; RV32I-NEXT: sw a0, 24(sp) ; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+4)(a7) ; RV32I-NEXT: lw a0, %lo(var+4)(a7)
; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+8)(a7) ; RV32I-NEXT: lw a0, %lo(var+8)(a7)
; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+12)(a7) ; RV32I-NEXT: lw a0, %lo(var+12)(a7)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a5, a7, %lo(var) ; RV32I-NEXT: addi a5, a7, %lo(var)
; RV32I-NEXT: lw a0, 16(a5) ; RV32I-NEXT: lw a0, 16(a5)
; RV32I-NEXT: sw a0, 8(sp) ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 20(a5) ; RV32I-NEXT: lw a0, 20(a5)
; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw t4, 24(a5) ; RV32I-NEXT: lw t4, 24(a5)
; RV32I-NEXT: lw t5, 28(a5) ; RV32I-NEXT: lw t5, 28(a5)
; RV32I-NEXT: lw t6, 32(a5) ; RV32I-NEXT: lw t6, 32(a5)
; RV32I-NEXT: lw s2, 36(a5) ; RV32I-NEXT: lw s2, 36(a5)
; RV32I-NEXT: lw s3, 40(a5) ; RV32I-NEXT: lw s3, 40(a5)
; RV32I-NEXT: lw s4, 44(a5) ; RV32I-NEXT: lw s4, 44(a5)
; RV32I-NEXT: lw s5, 48(a5) ; RV32I-NEXT: lw s5, 48(a5)
; RV32I-NEXT: lw s6, 52(a5) ; RV32I-NEXT: lw s6, 52(a5)
Show All 36 Lines
; RV32I-NEXT: sw s6, 52(a5) ; RV32I-NEXT: sw s6, 52(a5)
; RV32I-NEXT: sw s5, 48(a5) ; RV32I-NEXT: sw s5, 48(a5)
; RV32I-NEXT: sw s4, 44(a5) ; RV32I-NEXT: sw s4, 44(a5)
; RV32I-NEXT: sw s3, 40(a5) ; RV32I-NEXT: sw s3, 40(a5)
; RV32I-NEXT: sw s2, 36(a5) ; RV32I-NEXT: sw s2, 36(a5)
; RV32I-NEXT: sw t6, 32(a5) ; RV32I-NEXT: sw t6, 32(a5)
; RV32I-NEXT: sw t5, 28(a5) ; RV32I-NEXT: sw t5, 28(a5)
; RV32I-NEXT: sw t4, 24(a5) ; RV32I-NEXT: sw t4, 24(a5)
; RV32I-NEXT: lw a0, 4(sp) ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 20(a5) ; RV32I-NEXT: sw a0, 20(a5)
; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 16(a5) ; RV32I-NEXT: sw a0, 16(a5)
; RV32I-NEXT: lw a0, 12(sp) ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+12)(a7) ; RV32I-NEXT: sw a0, %lo(var+12)(a7)
; RV32I-NEXT: lw a0, 16(sp) ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+8)(a7) ; RV32I-NEXT: sw a0, %lo(var+8)(a7)
; RV32I-NEXT: lw a0, 20(sp) ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+4)(a7) ; RV32I-NEXT: sw a0, %lo(var+4)(a7)
; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var)(a7) ; RV32I-NEXT: sw a0, %lo(var)(a7)
; RV32I-NEXT: lw s11, 28(sp) ; RV32I-NEXT: lw s11, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 32(sp) ; RV32I-NEXT: lw s10, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 36(sp) ; RV32I-NEXT: lw s9, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 40(sp) ; RV32I-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 44(sp) ; RV32I-NEXT: lw s7, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 48(sp) ; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 52(sp) ; RV32I-NEXT: lw s5, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 56(sp) ; RV32I-NEXT: lw s4, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 60(sp) ; RV32I-NEXT: lw s3, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 64(sp) ; RV32I-NEXT: lw s2, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 68(sp) ; RV32I-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 72(sp) ; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 76(sp) ; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 80 ; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-WITH-FP-LABEL: callee: ; RV32I-WITH-FP-LABEL: callee:
; RV32I-WITH-FP: # %bb.0: ; RV32I-WITH-FP: # %bb.0:
; RV32I-WITH-FP-NEXT: addi sp, sp, -80 ; RV32I-WITH-FP-NEXT: addi sp, sp, -80
; RV32I-WITH-FP-NEXT: sw ra, 76(sp) ; RV32I-WITH-FP-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s0, 72(sp) ; RV32I-WITH-FP-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s1, 68(sp) ; RV32I-WITH-FP-NEXT: sw s1, 68(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s2, 64(sp) ; RV32I-WITH-FP-NEXT: sw s2, 64(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s3, 60(sp) ; RV32I-WITH-FP-NEXT: sw s3, 60(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s4, 56(sp) ; RV32I-WITH-FP-NEXT: sw s4, 56(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s5, 52(sp) ; RV32I-WITH-FP-NEXT: sw s5, 52(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s6, 48(sp) ; RV32I-WITH-FP-NEXT: sw s6, 48(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s7, 44(sp) ; RV32I-WITH-FP-NEXT: sw s7, 44(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s8, 40(sp) ; RV32I-WITH-FP-NEXT: sw s8, 40(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s9, 36(sp) ; RV32I-WITH-FP-NEXT: sw s9, 36(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s10, 32(sp) ; RV32I-WITH-FP-NEXT: sw s10, 32(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s11, 28(sp) ; RV32I-WITH-FP-NEXT: sw s11, 28(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi s0, sp, 80 ; RV32I-WITH-FP-NEXT: addi s0, sp, 80
; RV32I-WITH-FP-NEXT: lui a7, %hi(var) ; RV32I-WITH-FP-NEXT: lui a7, %hi(var)
; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(a7) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(a7)
; RV32I-WITH-FP-NEXT: sw a0, -56(s0) ; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7)
; RV32I-WITH-FP-NEXT: sw a0, -60(s0) ; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7)
; RV32I-WITH-FP-NEXT: sw a0, -64(s0) ; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7)
; RV32I-WITH-FP-NEXT: sw a0, -68(s0) ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var) ; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var)
; RV32I-WITH-FP-NEXT: lw a0, 16(a5) ; RV32I-WITH-FP-NEXT: lw a0, 16(a5)
; RV32I-WITH-FP-NEXT: sw a0, -72(s0) ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 20(a5) ; RV32I-WITH-FP-NEXT: lw a0, 20(a5)
; RV32I-WITH-FP-NEXT: sw a0, -76(s0) ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 24(a5) ; RV32I-WITH-FP-NEXT: lw a0, 24(a5)
; RV32I-WITH-FP-NEXT: sw a0, -80(s0) ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw t5, 28(a5) ; RV32I-WITH-FP-NEXT: lw t5, 28(a5)
; RV32I-WITH-FP-NEXT: lw t6, 32(a5) ; RV32I-WITH-FP-NEXT: lw t6, 32(a5)
; RV32I-WITH-FP-NEXT: lw s2, 36(a5) ; RV32I-WITH-FP-NEXT: lw s2, 36(a5)
; RV32I-WITH-FP-NEXT: lw s3, 40(a5) ; RV32I-WITH-FP-NEXT: lw s3, 40(a5)
; RV32I-WITH-FP-NEXT: lw s4, 44(a5) ; RV32I-WITH-FP-NEXT: lw s4, 44(a5)
; RV32I-WITH-FP-NEXT: lw s5, 48(a5) ; RV32I-WITH-FP-NEXT: lw s5, 48(a5)
; RV32I-WITH-FP-NEXT: lw s6, 52(a5) ; RV32I-WITH-FP-NEXT: lw s6, 52(a5)
; RV32I-WITH-FP-NEXT: lw s7, 56(a5) ; RV32I-WITH-FP-NEXT: lw s7, 56(a5)
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; RV32I-WITH-FP-NEXT: sw s7, 56(a5) ; RV32I-WITH-FP-NEXT: sw s7, 56(a5)
; RV32I-WITH-FP-NEXT: sw s6, 52(a5) ; RV32I-WITH-FP-NEXT: sw s6, 52(a5)
; RV32I-WITH-FP-NEXT: sw s5, 48(a5) ; RV32I-WITH-FP-NEXT: sw s5, 48(a5)
; RV32I-WITH-FP-NEXT: sw s4, 44(a5) ; RV32I-WITH-FP-NEXT: sw s4, 44(a5)
; RV32I-WITH-FP-NEXT: sw s3, 40(a5) ; RV32I-WITH-FP-NEXT: sw s3, 40(a5)
; RV32I-WITH-FP-NEXT: sw s2, 36(a5) ; RV32I-WITH-FP-NEXT: sw s2, 36(a5)
; RV32I-WITH-FP-NEXT: sw t6, 32(a5) ; RV32I-WITH-FP-NEXT: sw t6, 32(a5)
; RV32I-WITH-FP-NEXT: sw t5, 28(a5) ; RV32I-WITH-FP-NEXT: sw t5, 28(a5)
; RV32I-WITH-FP-NEXT: lw a0, -80(s0) ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 24(a5) ; RV32I-WITH-FP-NEXT: sw a0, 24(a5)
; RV32I-WITH-FP-NEXT: lw a0, -76(s0) ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 20(a5) ; RV32I-WITH-FP-NEXT: sw a0, 20(a5)
; RV32I-WITH-FP-NEXT: lw a0, -72(s0) ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 16(a5) ; RV32I-WITH-FP-NEXT: sw a0, 16(a5)
; RV32I-WITH-FP-NEXT: lw a0, -68(s0) ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7)
; RV32I-WITH-FP-NEXT: lw a0, -64(s0) ; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7)
; RV32I-WITH-FP-NEXT: lw a0, -60(s0) ; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7)
; RV32I-WITH-FP-NEXT: lw a0, -56(s0) ; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(a7) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(a7)
; RV32I-WITH-FP-NEXT: lw s11, 28(sp) ; RV32I-WITH-FP-NEXT: lw s11, 28(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s10, 32(sp) ; RV32I-WITH-FP-NEXT: lw s10, 32(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s9, 36(sp) ; RV32I-WITH-FP-NEXT: lw s9, 36(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s8, 40(sp) ; RV32I-WITH-FP-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s7, 44(sp) ; RV32I-WITH-FP-NEXT: lw s7, 44(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s6, 48(sp) ; RV32I-WITH-FP-NEXT: lw s6, 48(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s5, 52(sp) ; RV32I-WITH-FP-NEXT: lw s5, 52(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s4, 56(sp) ; RV32I-WITH-FP-NEXT: lw s4, 56(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s3, 60(sp) ; RV32I-WITH-FP-NEXT: lw s3, 60(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s2, 64(sp) ; RV32I-WITH-FP-NEXT: lw s2, 64(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s1, 68(sp) ; RV32I-WITH-FP-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 72(sp) ; RV32I-WITH-FP-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw ra, 76(sp) ; RV32I-WITH-FP-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: addi sp, sp, 80 ; RV32I-WITH-FP-NEXT: addi sp, sp, 80
; RV32I-WITH-FP-NEXT: ret ; RV32I-WITH-FP-NEXT: ret
; ;
; RV64I-LABEL: callee: ; RV64I-LABEL: callee:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -160 ; RV64I-NEXT: addi sp, sp, -160
; RV64I-NEXT: sd ra, 152(sp) ; RV64I-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 144(sp) ; RV64I-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 136(sp) ; RV64I-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 128(sp) ; RV64I-NEXT: sd s2, 128(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 120(sp) ; RV64I-NEXT: sd s3, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 112(sp) ; RV64I-NEXT: sd s4, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 104(sp) ; RV64I-NEXT: sd s5, 104(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 96(sp) ; RV64I-NEXT: sd s6, 96(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 88(sp) ; RV64I-NEXT: sd s7, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 80(sp) ; RV64I-NEXT: sd s8, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 72(sp) ; RV64I-NEXT: sd s9, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s10, 64(sp) ; RV64I-NEXT: sd s10, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s11, 56(sp) ; RV64I-NEXT: sd s11, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a7, %hi(var) ; RV64I-NEXT: lui a7, %hi(var)
; RV64I-NEXT: lw a0, %lo(var)(a7) ; RV64I-NEXT: lw a0, %lo(var)(a7)
; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+4)(a7) ; RV64I-NEXT: lw a0, %lo(var+4)(a7)
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+8)(a7) ; RV64I-NEXT: lw a0, %lo(var+8)(a7)
; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+12)(a7) ; RV64I-NEXT: lw a0, %lo(var+12)(a7)
; RV64I-NEXT: sd a0, 24(sp) ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a5, a7, %lo(var) ; RV64I-NEXT: addi a5, a7, %lo(var)
; RV64I-NEXT: lw a0, 16(a5) ; RV64I-NEXT: lw a0, 16(a5)
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 20(a5) ; RV64I-NEXT: lw a0, 20(a5)
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw t4, 24(a5) ; RV64I-NEXT: lw t4, 24(a5)
; RV64I-NEXT: lw t5, 28(a5) ; RV64I-NEXT: lw t5, 28(a5)
; RV64I-NEXT: lw t6, 32(a5) ; RV64I-NEXT: lw t6, 32(a5)
; RV64I-NEXT: lw s2, 36(a5) ; RV64I-NEXT: lw s2, 36(a5)
; RV64I-NEXT: lw s3, 40(a5) ; RV64I-NEXT: lw s3, 40(a5)
; RV64I-NEXT: lw s4, 44(a5) ; RV64I-NEXT: lw s4, 44(a5)
; RV64I-NEXT: lw s5, 48(a5) ; RV64I-NEXT: lw s5, 48(a5)
; RV64I-NEXT: lw s6, 52(a5) ; RV64I-NEXT: lw s6, 52(a5)
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; RV64I-NEXT: sw s6, 52(a5) ; RV64I-NEXT: sw s6, 52(a5)
; RV64I-NEXT: sw s5, 48(a5) ; RV64I-NEXT: sw s5, 48(a5)
; RV64I-NEXT: sw s4, 44(a5) ; RV64I-NEXT: sw s4, 44(a5)
; RV64I-NEXT: sw s3, 40(a5) ; RV64I-NEXT: sw s3, 40(a5)
; RV64I-NEXT: sw s2, 36(a5) ; RV64I-NEXT: sw s2, 36(a5)
; RV64I-NEXT: sw t6, 32(a5) ; RV64I-NEXT: sw t6, 32(a5)
; RV64I-NEXT: sw t5, 28(a5) ; RV64I-NEXT: sw t5, 28(a5)
; RV64I-NEXT: sw t4, 24(a5) ; RV64I-NEXT: sw t4, 24(a5)
; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 20(a5) ; RV64I-NEXT: sw a0, 20(a5)
; RV64I-NEXT: ld a0, 16(sp) ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 16(a5) ; RV64I-NEXT: sw a0, 16(a5)
; RV64I-NEXT: ld a0, 24(sp) ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+12)(a7) ; RV64I-NEXT: sw a0, %lo(var+12)(a7)
; RV64I-NEXT: ld a0, 32(sp) ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+8)(a7) ; RV64I-NEXT: sw a0, %lo(var+8)(a7)
; RV64I-NEXT: ld a0, 40(sp) ; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+4)(a7) ; RV64I-NEXT: sw a0, %lo(var+4)(a7)
; RV64I-NEXT: ld a0, 48(sp) ; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var)(a7) ; RV64I-NEXT: sw a0, %lo(var)(a7)
; RV64I-NEXT: ld s11, 56(sp) ; RV64I-NEXT: ld s11, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s10, 64(sp) ; RV64I-NEXT: ld s10, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s9, 72(sp) ; RV64I-NEXT: ld s9, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 80(sp) ; RV64I-NEXT: ld s8, 80(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 88(sp) ; RV64I-NEXT: ld s7, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 96(sp) ; RV64I-NEXT: ld s6, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 104(sp) ; RV64I-NEXT: ld s5, 104(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 112(sp) ; RV64I-NEXT: ld s4, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 120(sp) ; RV64I-NEXT: ld s3, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 128(sp) ; RV64I-NEXT: ld s2, 128(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 136(sp) ; RV64I-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 144(sp) ; RV64I-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 152(sp) ; RV64I-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 160 ; RV64I-NEXT: addi sp, sp, 160
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64I-WITH-FP-LABEL: callee: ; RV64I-WITH-FP-LABEL: callee:
; RV64I-WITH-FP: # %bb.0: ; RV64I-WITH-FP: # %bb.0:
; RV64I-WITH-FP-NEXT: addi sp, sp, -160 ; RV64I-WITH-FP-NEXT: addi sp, sp, -160
; RV64I-WITH-FP-NEXT: sd ra, 152(sp) ; RV64I-WITH-FP-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s0, 144(sp) ; RV64I-WITH-FP-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s1, 136(sp) ; RV64I-WITH-FP-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s2, 128(sp) ; RV64I-WITH-FP-NEXT: sd s2, 128(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s3, 120(sp) ; RV64I-WITH-FP-NEXT: sd s3, 120(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s4, 112(sp) ; RV64I-WITH-FP-NEXT: sd s4, 112(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s5, 104(sp) ; RV64I-WITH-FP-NEXT: sd s5, 104(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s6, 96(sp) ; RV64I-WITH-FP-NEXT: sd s6, 96(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s7, 88(sp) ; RV64I-WITH-FP-NEXT: sd s7, 88(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s8, 80(sp) ; RV64I-WITH-FP-NEXT: sd s8, 80(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s9, 72(sp) ; RV64I-WITH-FP-NEXT: sd s9, 72(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s10, 64(sp) ; RV64I-WITH-FP-NEXT: sd s10, 64(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s11, 56(sp) ; RV64I-WITH-FP-NEXT: sd s11, 56(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi s0, sp, 160 ; RV64I-WITH-FP-NEXT: addi s0, sp, 160
; RV64I-WITH-FP-NEXT: lui a7, %hi(var) ; RV64I-WITH-FP-NEXT: lui a7, %hi(var)
; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(a7) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(a7)
; RV64I-WITH-FP-NEXT: sd a0, -112(s0) ; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7)
; RV64I-WITH-FP-NEXT: sd a0, -120(s0) ; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7)
; RV64I-WITH-FP-NEXT: sd a0, -128(s0) ; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7)
; RV64I-WITH-FP-NEXT: sd a0, -136(s0) ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var) ; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var)
; RV64I-WITH-FP-NEXT: lw a0, 16(a5) ; RV64I-WITH-FP-NEXT: lw a0, 16(a5)
; RV64I-WITH-FP-NEXT: sd a0, -144(s0) ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 20(a5) ; RV64I-WITH-FP-NEXT: lw a0, 20(a5)
; RV64I-WITH-FP-NEXT: sd a0, -152(s0) ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 24(a5) ; RV64I-WITH-FP-NEXT: lw a0, 24(a5)
; RV64I-WITH-FP-NEXT: sd a0, -160(s0) ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw t5, 28(a5) ; RV64I-WITH-FP-NEXT: lw t5, 28(a5)
; RV64I-WITH-FP-NEXT: lw t6, 32(a5) ; RV64I-WITH-FP-NEXT: lw t6, 32(a5)
; RV64I-WITH-FP-NEXT: lw s2, 36(a5) ; RV64I-WITH-FP-NEXT: lw s2, 36(a5)
; RV64I-WITH-FP-NEXT: lw s3, 40(a5) ; RV64I-WITH-FP-NEXT: lw s3, 40(a5)
; RV64I-WITH-FP-NEXT: lw s4, 44(a5) ; RV64I-WITH-FP-NEXT: lw s4, 44(a5)
; RV64I-WITH-FP-NEXT: lw s5, 48(a5) ; RV64I-WITH-FP-NEXT: lw s5, 48(a5)
; RV64I-WITH-FP-NEXT: lw s6, 52(a5) ; RV64I-WITH-FP-NEXT: lw s6, 52(a5)
; RV64I-WITH-FP-NEXT: lw s7, 56(a5) ; RV64I-WITH-FP-NEXT: lw s7, 56(a5)
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; RV64I-WITH-FP-NEXT: sw s7, 56(a5) ; RV64I-WITH-FP-NEXT: sw s7, 56(a5)
; RV64I-WITH-FP-NEXT: sw s6, 52(a5) ; RV64I-WITH-FP-NEXT: sw s6, 52(a5)
; RV64I-WITH-FP-NEXT: sw s5, 48(a5) ; RV64I-WITH-FP-NEXT: sw s5, 48(a5)
; RV64I-WITH-FP-NEXT: sw s4, 44(a5) ; RV64I-WITH-FP-NEXT: sw s4, 44(a5)
; RV64I-WITH-FP-NEXT: sw s3, 40(a5) ; RV64I-WITH-FP-NEXT: sw s3, 40(a5)
; RV64I-WITH-FP-NEXT: sw s2, 36(a5) ; RV64I-WITH-FP-NEXT: sw s2, 36(a5)
; RV64I-WITH-FP-NEXT: sw t6, 32(a5) ; RV64I-WITH-FP-NEXT: sw t6, 32(a5)
; RV64I-WITH-FP-NEXT: sw t5, 28(a5) ; RV64I-WITH-FP-NEXT: sw t5, 28(a5)
; RV64I-WITH-FP-NEXT: ld a0, -160(s0) ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 24(a5) ; RV64I-WITH-FP-NEXT: sw a0, 24(a5)
; RV64I-WITH-FP-NEXT: ld a0, -152(s0) ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 20(a5) ; RV64I-WITH-FP-NEXT: sw a0, 20(a5)
; RV64I-WITH-FP-NEXT: ld a0, -144(s0) ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 16(a5) ; RV64I-WITH-FP-NEXT: sw a0, 16(a5)
; RV64I-WITH-FP-NEXT: ld a0, -136(s0) ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7)
; RV64I-WITH-FP-NEXT: ld a0, -128(s0) ; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7)
; RV64I-WITH-FP-NEXT: ld a0, -120(s0) ; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7)
; RV64I-WITH-FP-NEXT: ld a0, -112(s0) ; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(a7) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(a7)
; RV64I-WITH-FP-NEXT: ld s11, 56(sp) ; RV64I-WITH-FP-NEXT: ld s11, 56(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s10, 64(sp) ; RV64I-WITH-FP-NEXT: ld s10, 64(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s9, 72(sp) ; RV64I-WITH-FP-NEXT: ld s9, 72(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s8, 80(sp) ; RV64I-WITH-FP-NEXT: ld s8, 80(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s7, 88(sp) ; RV64I-WITH-FP-NEXT: ld s7, 88(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s6, 96(sp) ; RV64I-WITH-FP-NEXT: ld s6, 96(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s5, 104(sp) ; RV64I-WITH-FP-NEXT: ld s5, 104(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s4, 112(sp) ; RV64I-WITH-FP-NEXT: ld s4, 112(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s3, 120(sp) ; RV64I-WITH-FP-NEXT: ld s3, 120(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s2, 128(sp) ; RV64I-WITH-FP-NEXT: ld s2, 128(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s1, 136(sp) ; RV64I-WITH-FP-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 144(sp) ; RV64I-WITH-FP-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld ra, 152(sp) ; RV64I-WITH-FP-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: addi sp, sp, 160 ; RV64I-WITH-FP-NEXT: addi sp, sp, 160
; RV64I-WITH-FP-NEXT: ret ; RV64I-WITH-FP-NEXT: ret
%val = load [32 x i32], [32 x i32]* @var %val = load [32 x i32], [32 x i32]* @var
store volatile [32 x i32] %val, [32 x i32]* @var store volatile [32 x i32] %val, [32 x i32]* @var
ret void ret void
} }
; This function tests that RISCVRegisterInfo::getCallPreservedMask returns ; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
; something appropriate. ; something appropriate.
define void @caller() nounwind { define void @caller() nounwind {
; RV32I-LABEL: caller: ; RV32I-LABEL: caller:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -144 ; RV32I-NEXT: addi sp, sp, -144
; RV32I-NEXT: sw ra, 140(sp) ; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 136(sp) ; RV32I-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 132(sp) ; RV32I-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 128(sp) ; RV32I-NEXT: sw s2, 128(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 124(sp) ; RV32I-NEXT: sw s3, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 120(sp) ; RV32I-NEXT: sw s4, 120(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 116(sp) ; RV32I-NEXT: sw s5, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 112(sp) ; RV32I-NEXT: sw s6, 112(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 108(sp) ; RV32I-NEXT: sw s7, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 104(sp) ; RV32I-NEXT: sw s8, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 100(sp) ; RV32I-NEXT: sw s9, 100(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 96(sp) ; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 92(sp) ; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s0, %hi(var) ; RV32I-NEXT: lui s0, %hi(var)
; RV32I-NEXT: lw a0, %lo(var)(s0) ; RV32I-NEXT: lw a0, %lo(var)(s0)
; RV32I-NEXT: sw a0, 88(sp) ; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+4)(s0) ; RV32I-NEXT: lw a0, %lo(var+4)(s0)
; RV32I-NEXT: sw a0, 84(sp) ; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+8)(s0) ; RV32I-NEXT: lw a0, %lo(var+8)(s0)
; RV32I-NEXT: sw a0, 80(sp) ; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+12)(s0) ; RV32I-NEXT: lw a0, %lo(var+12)(s0)
; RV32I-NEXT: sw a0, 76(sp) ; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s1, s0, %lo(var) ; RV32I-NEXT: addi s1, s0, %lo(var)
; RV32I-NEXT: lw a0, 16(s1) ; RV32I-NEXT: lw a0, 16(s1)
; RV32I-NEXT: sw a0, 72(sp) ; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 20(s1) ; RV32I-NEXT: lw a0, 20(s1)
; RV32I-NEXT: sw a0, 68(sp) ; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 24(s1) ; RV32I-NEXT: lw a0, 24(s1)
; RV32I-NEXT: sw a0, 64(sp) ; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 28(s1) ; RV32I-NEXT: lw a0, 28(s1)
; RV32I-NEXT: sw a0, 60(sp) ; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 32(s1) ; RV32I-NEXT: lw a0, 32(s1)
; RV32I-NEXT: sw a0, 56(sp) ; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 36(s1) ; RV32I-NEXT: lw a0, 36(s1)
; RV32I-NEXT: sw a0, 52(sp) ; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 40(s1) ; RV32I-NEXT: lw a0, 40(s1)
; RV32I-NEXT: sw a0, 48(sp) ; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 44(s1) ; RV32I-NEXT: lw a0, 44(s1)
; RV32I-NEXT: sw a0, 44(sp) ; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 48(s1) ; RV32I-NEXT: lw a0, 48(s1)
; RV32I-NEXT: sw a0, 40(sp) ; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 52(s1) ; RV32I-NEXT: lw a0, 52(s1)
; RV32I-NEXT: sw a0, 36(sp) ; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 56(s1) ; RV32I-NEXT: lw a0, 56(s1)
; RV32I-NEXT: sw a0, 32(sp) ; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 60(s1) ; RV32I-NEXT: lw a0, 60(s1)
; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 64(s1) ; RV32I-NEXT: lw a0, 64(s1)
; RV32I-NEXT: sw a0, 24(sp) ; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 68(s1) ; RV32I-NEXT: lw a0, 68(s1)
; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 72(s1) ; RV32I-NEXT: lw a0, 72(s1)
; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 76(s1) ; RV32I-NEXT: lw a0, 76(s1)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 80(s1) ; RV32I-NEXT: lw a0, 80(s1)
; RV32I-NEXT: sw a0, 8(sp) ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 84(s1) ; RV32I-NEXT: lw a0, 84(s1)
; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s4, 88(s1) ; RV32I-NEXT: lw s4, 88(s1)
; RV32I-NEXT: lw s5, 92(s1) ; RV32I-NEXT: lw s5, 92(s1)
; RV32I-NEXT: lw s6, 96(s1) ; RV32I-NEXT: lw s6, 96(s1)
; RV32I-NEXT: lw s7, 100(s1) ; RV32I-NEXT: lw s7, 100(s1)
; RV32I-NEXT: lw s8, 104(s1) ; RV32I-NEXT: lw s8, 104(s1)
; RV32I-NEXT: lw s9, 108(s1) ; RV32I-NEXT: lw s9, 108(s1)
; RV32I-NEXT: lw s10, 112(s1) ; RV32I-NEXT: lw s10, 112(s1)
; RV32I-NEXT: lw s11, 116(s1) ; RV32I-NEXT: lw s11, 116(s1)
; RV32I-NEXT: lw s2, 120(s1) ; RV32I-NEXT: lw s2, 120(s1)
; RV32I-NEXT: lw s3, 124(s1) ; RV32I-NEXT: lw s3, 124(s1)
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee
; RV32I-NEXT: sw s3, 124(s1) ; RV32I-NEXT: sw s3, 124(s1)
; RV32I-NEXT: sw s2, 120(s1) ; RV32I-NEXT: sw s2, 120(s1)
; RV32I-NEXT: sw s11, 116(s1) ; RV32I-NEXT: sw s11, 116(s1)
; RV32I-NEXT: sw s10, 112(s1) ; RV32I-NEXT: sw s10, 112(s1)
; RV32I-NEXT: sw s9, 108(s1) ; RV32I-NEXT: sw s9, 108(s1)
; RV32I-NEXT: sw s8, 104(s1) ; RV32I-NEXT: sw s8, 104(s1)
; RV32I-NEXT: sw s7, 100(s1) ; RV32I-NEXT: sw s7, 100(s1)
; RV32I-NEXT: sw s6, 96(s1) ; RV32I-NEXT: sw s6, 96(s1)
; RV32I-NEXT: sw s5, 92(s1) ; RV32I-NEXT: sw s5, 92(s1)
; RV32I-NEXT: sw s4, 88(s1) ; RV32I-NEXT: sw s4, 88(s1)
; RV32I-NEXT: lw a0, 4(sp) ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 84(s1) ; RV32I-NEXT: sw a0, 84(s1)
; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 80(s1) ; RV32I-NEXT: sw a0, 80(s1)
; RV32I-NEXT: lw a0, 12(sp) ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 76(s1) ; RV32I-NEXT: sw a0, 76(s1)
; RV32I-NEXT: lw a0, 16(sp) ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 72(s1) ; RV32I-NEXT: sw a0, 72(s1)
; RV32I-NEXT: lw a0, 20(sp) ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 68(s1) ; RV32I-NEXT: sw a0, 68(s1)
; RV32I-NEXT: lw a0, 24(sp) ; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 64(s1) ; RV32I-NEXT: sw a0, 64(s1)
; RV32I-NEXT: lw a0, 28(sp) ; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 60(s1) ; RV32I-NEXT: sw a0, 60(s1)
; RV32I-NEXT: lw a0, 32(sp) ; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 56(s1) ; RV32I-NEXT: sw a0, 56(s1)
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 52(s1) ; RV32I-NEXT: sw a0, 52(s1)
; RV32I-NEXT: lw a0, 40(sp) ; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 48(s1) ; RV32I-NEXT: sw a0, 48(s1)
; RV32I-NEXT: lw a0, 44(sp) ; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 44(s1) ; RV32I-NEXT: sw a0, 44(s1)
; RV32I-NEXT: lw a0, 48(sp) ; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 40(s1) ; RV32I-NEXT: sw a0, 40(s1)
; RV32I-NEXT: lw a0, 52(sp) ; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 36(s1) ; RV32I-NEXT: sw a0, 36(s1)
; RV32I-NEXT: lw a0, 56(sp) ; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 32(s1) ; RV32I-NEXT: sw a0, 32(s1)
; RV32I-NEXT: lw a0, 60(sp) ; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 28(s1) ; RV32I-NEXT: sw a0, 28(s1)
; RV32I-NEXT: lw a0, 64(sp) ; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 24(s1) ; RV32I-NEXT: sw a0, 24(s1)
; RV32I-NEXT: lw a0, 68(sp) ; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 20(s1) ; RV32I-NEXT: sw a0, 20(s1)
; RV32I-NEXT: lw a0, 72(sp) ; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 16(s1) ; RV32I-NEXT: sw a0, 16(s1)
; RV32I-NEXT: lw a0, 76(sp) ; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+12)(s0) ; RV32I-NEXT: sw a0, %lo(var+12)(s0)
; RV32I-NEXT: lw a0, 80(sp) ; RV32I-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+8)(s0) ; RV32I-NEXT: sw a0, %lo(var+8)(s0)
; RV32I-NEXT: lw a0, 84(sp) ; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+4)(s0) ; RV32I-NEXT: sw a0, %lo(var+4)(s0)
; RV32I-NEXT: lw a0, 88(sp) ; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var)(s0) ; RV32I-NEXT: sw a0, %lo(var)(s0)
; RV32I-NEXT: lw s11, 92(sp) ; RV32I-NEXT: lw s11, 92(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 96(sp) ; RV32I-NEXT: lw s10, 96(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 100(sp) ; RV32I-NEXT: lw s9, 100(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 104(sp) ; RV32I-NEXT: lw s8, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 108(sp) ; RV32I-NEXT: lw s7, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 112(sp) ; RV32I-NEXT: lw s6, 112(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 116(sp) ; RV32I-NEXT: lw s5, 116(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 120(sp) ; RV32I-NEXT: lw s4, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 124(sp) ; RV32I-NEXT: lw s3, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 128(sp) ; RV32I-NEXT: lw s2, 128(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 132(sp) ; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 136(sp) ; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 140(sp) ; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 144 ; RV32I-NEXT: addi sp, sp, 144
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-WITH-FP-LABEL: caller: ; RV32I-WITH-FP-LABEL: caller:
; RV32I-WITH-FP: # %bb.0: ; RV32I-WITH-FP: # %bb.0:
; RV32I-WITH-FP-NEXT: addi sp, sp, -144 ; RV32I-WITH-FP-NEXT: addi sp, sp, -144
; RV32I-WITH-FP-NEXT: sw ra, 140(sp) ; RV32I-WITH-FP-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s0, 136(sp) ; RV32I-WITH-FP-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s1, 132(sp) ; RV32I-WITH-FP-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s2, 128(sp) ; RV32I-WITH-FP-NEXT: sw s2, 128(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s3, 124(sp) ; RV32I-WITH-FP-NEXT: sw s3, 124(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s4, 120(sp) ; RV32I-WITH-FP-NEXT: sw s4, 120(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s5, 116(sp) ; RV32I-WITH-FP-NEXT: sw s5, 116(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s6, 112(sp) ; RV32I-WITH-FP-NEXT: sw s6, 112(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s7, 108(sp) ; RV32I-WITH-FP-NEXT: sw s7, 108(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s8, 104(sp) ; RV32I-WITH-FP-NEXT: sw s8, 104(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s9, 100(sp) ; RV32I-WITH-FP-NEXT: sw s9, 100(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s10, 96(sp) ; RV32I-WITH-FP-NEXT: sw s10, 96(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s11, 92(sp) ; RV32I-WITH-FP-NEXT: sw s11, 92(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi s0, sp, 144 ; RV32I-WITH-FP-NEXT: addi s0, sp, 144
; RV32I-WITH-FP-NEXT: lui s6, %hi(var) ; RV32I-WITH-FP-NEXT: lui s6, %hi(var)
; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s6)
; RV32I-WITH-FP-NEXT: sw a0, -56(s0) ; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
; RV32I-WITH-FP-NEXT: sw a0, -60(s0) ; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
; RV32I-WITH-FP-NEXT: sw a0, -64(s0) ; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
; RV32I-WITH-FP-NEXT: sw a0, -68(s0) ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi s1, s6, %lo(var) ; RV32I-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV32I-WITH-FP-NEXT: lw a0, 16(s1) ; RV32I-WITH-FP-NEXT: lw a0, 16(s1)
; RV32I-WITH-FP-NEXT: sw a0, -72(s0) ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 20(s1) ; RV32I-WITH-FP-NEXT: lw a0, 20(s1)
; RV32I-WITH-FP-NEXT: sw a0, -76(s0) ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 24(s1) ; RV32I-WITH-FP-NEXT: lw a0, 24(s1)
; RV32I-WITH-FP-NEXT: sw a0, -80(s0) ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 28(s1) ; RV32I-WITH-FP-NEXT: lw a0, 28(s1)
; RV32I-WITH-FP-NEXT: sw a0, -84(s0) ; RV32I-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 32(s1) ; RV32I-WITH-FP-NEXT: lw a0, 32(s1)
; RV32I-WITH-FP-NEXT: sw a0, -88(s0) ; RV32I-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 36(s1) ; RV32I-WITH-FP-NEXT: lw a0, 36(s1)
; RV32I-WITH-FP-NEXT: sw a0, -92(s0) ; RV32I-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 40(s1) ; RV32I-WITH-FP-NEXT: lw a0, 40(s1)
; RV32I-WITH-FP-NEXT: sw a0, -96(s0) ; RV32I-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 44(s1) ; RV32I-WITH-FP-NEXT: lw a0, 44(s1)
; RV32I-WITH-FP-NEXT: sw a0, -100(s0) ; RV32I-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 48(s1) ; RV32I-WITH-FP-NEXT: lw a0, 48(s1)
; RV32I-WITH-FP-NEXT: sw a0, -104(s0) ; RV32I-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 52(s1) ; RV32I-WITH-FP-NEXT: lw a0, 52(s1)
; RV32I-WITH-FP-NEXT: sw a0, -108(s0) ; RV32I-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 56(s1) ; RV32I-WITH-FP-NEXT: lw a0, 56(s1)
; RV32I-WITH-FP-NEXT: sw a0, -112(s0) ; RV32I-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 60(s1) ; RV32I-WITH-FP-NEXT: lw a0, 60(s1)
; RV32I-WITH-FP-NEXT: sw a0, -116(s0) ; RV32I-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 64(s1) ; RV32I-WITH-FP-NEXT: lw a0, 64(s1)
; RV32I-WITH-FP-NEXT: sw a0, -120(s0) ; RV32I-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 68(s1) ; RV32I-WITH-FP-NEXT: lw a0, 68(s1)
; RV32I-WITH-FP-NEXT: sw a0, -124(s0) ; RV32I-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 72(s1) ; RV32I-WITH-FP-NEXT: lw a0, 72(s1)
; RV32I-WITH-FP-NEXT: sw a0, -128(s0) ; RV32I-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 76(s1) ; RV32I-WITH-FP-NEXT: lw a0, 76(s1)
; RV32I-WITH-FP-NEXT: sw a0, -132(s0) ; RV32I-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 80(s1) ; RV32I-WITH-FP-NEXT: lw a0, 80(s1)
; RV32I-WITH-FP-NEXT: sw a0, -136(s0) ; RV32I-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 84(s1) ; RV32I-WITH-FP-NEXT: lw a0, 84(s1)
; RV32I-WITH-FP-NEXT: sw a0, -140(s0) ; RV32I-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 88(s1) ; RV32I-WITH-FP-NEXT: lw a0, 88(s1)
; RV32I-WITH-FP-NEXT: sw a0, -144(s0) ; RV32I-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw s8, 92(s1) ; RV32I-WITH-FP-NEXT: lw s8, 92(s1)
; RV32I-WITH-FP-NEXT: lw s9, 96(s1) ; RV32I-WITH-FP-NEXT: lw s9, 96(s1)
; RV32I-WITH-FP-NEXT: lw s10, 100(s1) ; RV32I-WITH-FP-NEXT: lw s10, 100(s1)
; RV32I-WITH-FP-NEXT: lw s11, 104(s1) ; RV32I-WITH-FP-NEXT: lw s11, 104(s1)
; RV32I-WITH-FP-NEXT: lw s2, 108(s1) ; RV32I-WITH-FP-NEXT: lw s2, 108(s1)
; RV32I-WITH-FP-NEXT: lw s3, 112(s1) ; RV32I-WITH-FP-NEXT: lw s3, 112(s1)
; RV32I-WITH-FP-NEXT: lw s4, 116(s1) ; RV32I-WITH-FP-NEXT: lw s4, 116(s1)
; RV32I-WITH-FP-NEXT: lw s5, 120(s1) ; RV32I-WITH-FP-NEXT: lw s5, 120(s1)
; RV32I-WITH-FP-NEXT: lw s7, 124(s1) ; RV32I-WITH-FP-NEXT: lw s7, 124(s1)
; RV32I-WITH-FP-NEXT: call callee ; RV32I-WITH-FP-NEXT: call callee
; RV32I-WITH-FP-NEXT: sw s7, 124(s1) ; RV32I-WITH-FP-NEXT: sw s7, 124(s1)
; RV32I-WITH-FP-NEXT: sw s5, 120(s1) ; RV32I-WITH-FP-NEXT: sw s5, 120(s1)
; RV32I-WITH-FP-NEXT: sw s4, 116(s1) ; RV32I-WITH-FP-NEXT: sw s4, 116(s1)
; RV32I-WITH-FP-NEXT: sw s3, 112(s1) ; RV32I-WITH-FP-NEXT: sw s3, 112(s1)
; RV32I-WITH-FP-NEXT: sw s2, 108(s1) ; RV32I-WITH-FP-NEXT: sw s2, 108(s1)
; RV32I-WITH-FP-NEXT: sw s11, 104(s1) ; RV32I-WITH-FP-NEXT: sw s11, 104(s1)
; RV32I-WITH-FP-NEXT: sw s10, 100(s1) ; RV32I-WITH-FP-NEXT: sw s10, 100(s1)
; RV32I-WITH-FP-NEXT: sw s9, 96(s1) ; RV32I-WITH-FP-NEXT: sw s9, 96(s1)
; RV32I-WITH-FP-NEXT: sw s8, 92(s1) ; RV32I-WITH-FP-NEXT: sw s8, 92(s1)
; RV32I-WITH-FP-NEXT: lw a0, -144(s0) ; RV32I-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 88(s1) ; RV32I-WITH-FP-NEXT: sw a0, 88(s1)
; RV32I-WITH-FP-NEXT: lw a0, -140(s0) ; RV32I-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 84(s1) ; RV32I-WITH-FP-NEXT: sw a0, 84(s1)
; RV32I-WITH-FP-NEXT: lw a0, -136(s0) ; RV32I-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 80(s1) ; RV32I-WITH-FP-NEXT: sw a0, 80(s1)
; RV32I-WITH-FP-NEXT: lw a0, -132(s0) ; RV32I-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 76(s1) ; RV32I-WITH-FP-NEXT: sw a0, 76(s1)
; RV32I-WITH-FP-NEXT: lw a0, -128(s0) ; RV32I-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 72(s1) ; RV32I-WITH-FP-NEXT: sw a0, 72(s1)
; RV32I-WITH-FP-NEXT: lw a0, -124(s0) ; RV32I-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 68(s1) ; RV32I-WITH-FP-NEXT: sw a0, 68(s1)
; RV32I-WITH-FP-NEXT: lw a0, -120(s0) ; RV32I-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 64(s1) ; RV32I-WITH-FP-NEXT: sw a0, 64(s1)
; RV32I-WITH-FP-NEXT: lw a0, -116(s0) ; RV32I-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 60(s1) ; RV32I-WITH-FP-NEXT: sw a0, 60(s1)
; RV32I-WITH-FP-NEXT: lw a0, -112(s0) ; RV32I-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 56(s1) ; RV32I-WITH-FP-NEXT: sw a0, 56(s1)
; RV32I-WITH-FP-NEXT: lw a0, -108(s0) ; RV32I-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 52(s1) ; RV32I-WITH-FP-NEXT: sw a0, 52(s1)
; RV32I-WITH-FP-NEXT: lw a0, -104(s0) ; RV32I-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 48(s1) ; RV32I-WITH-FP-NEXT: sw a0, 48(s1)
; RV32I-WITH-FP-NEXT: lw a0, -100(s0) ; RV32I-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 44(s1) ; RV32I-WITH-FP-NEXT: sw a0, 44(s1)
; RV32I-WITH-FP-NEXT: lw a0, -96(s0) ; RV32I-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 40(s1) ; RV32I-WITH-FP-NEXT: sw a0, 40(s1)
; RV32I-WITH-FP-NEXT: lw a0, -92(s0) ; RV32I-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 36(s1) ; RV32I-WITH-FP-NEXT: sw a0, 36(s1)
; RV32I-WITH-FP-NEXT: lw a0, -88(s0) ; RV32I-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 32(s1) ; RV32I-WITH-FP-NEXT: sw a0, 32(s1)
; RV32I-WITH-FP-NEXT: lw a0, -84(s0) ; RV32I-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 28(s1) ; RV32I-WITH-FP-NEXT: sw a0, 28(s1)
; RV32I-WITH-FP-NEXT: lw a0, -80(s0) ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 24(s1) ; RV32I-WITH-FP-NEXT: sw a0, 24(s1)
; RV32I-WITH-FP-NEXT: lw a0, -76(s0) ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 20(s1) ; RV32I-WITH-FP-NEXT: sw a0, 20(s1)
; RV32I-WITH-FP-NEXT: lw a0, -72(s0) ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 16(s1) ; RV32I-WITH-FP-NEXT: sw a0, 16(s1)
; RV32I-WITH-FP-NEXT: lw a0, -68(s0) ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
; RV32I-WITH-FP-NEXT: lw a0, -64(s0) ; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
; RV32I-WITH-FP-NEXT: lw a0, -60(s0) ; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
; RV32I-WITH-FP-NEXT: lw a0, -56(s0) ; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s6)
; RV32I-WITH-FP-NEXT: lw s11, 92(sp) ; RV32I-WITH-FP-NEXT: lw s11, 92(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s10, 96(sp) ; RV32I-WITH-FP-NEXT: lw s10, 96(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s9, 100(sp) ; RV32I-WITH-FP-NEXT: lw s9, 100(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s8, 104(sp) ; RV32I-WITH-FP-NEXT: lw s8, 104(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s7, 108(sp) ; RV32I-WITH-FP-NEXT: lw s7, 108(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s6, 112(sp) ; RV32I-WITH-FP-NEXT: lw s6, 112(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s5, 116(sp) ; RV32I-WITH-FP-NEXT: lw s5, 116(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s4, 120(sp) ; RV32I-WITH-FP-NEXT: lw s4, 120(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s3, 124(sp) ; RV32I-WITH-FP-NEXT: lw s3, 124(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s2, 128(sp) ; RV32I-WITH-FP-NEXT: lw s2, 128(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s1, 132(sp) ; RV32I-WITH-FP-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 136(sp) ; RV32I-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw ra, 140(sp) ; RV32I-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: addi sp, sp, 144 ; RV32I-WITH-FP-NEXT: addi sp, sp, 144
; RV32I-WITH-FP-NEXT: ret ; RV32I-WITH-FP-NEXT: ret
; ;
; RV64I-LABEL: caller: ; RV64I-LABEL: caller:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -288 ; RV64I-NEXT: addi sp, sp, -288
; RV64I-NEXT: sd ra, 280(sp) ; RV64I-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 272(sp) ; RV64I-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 264(sp) ; RV64I-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 256(sp) ; RV64I-NEXT: sd s2, 256(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 248(sp) ; RV64I-NEXT: sd s3, 248(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 240(sp) ; RV64I-NEXT: sd s4, 240(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 232(sp) ; RV64I-NEXT: sd s5, 232(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 224(sp) ; RV64I-NEXT: sd s6, 224(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 216(sp) ; RV64I-NEXT: sd s7, 216(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 208(sp) ; RV64I-NEXT: sd s8, 208(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 200(sp) ; RV64I-NEXT: sd s9, 200(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s10, 192(sp) ; RV64I-NEXT: sd s10, 192(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s11, 184(sp) ; RV64I-NEXT: sd s11, 184(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui s0, %hi(var) ; RV64I-NEXT: lui s0, %hi(var)
; RV64I-NEXT: lw a0, %lo(var)(s0) ; RV64I-NEXT: lw a0, %lo(var)(s0)
; RV64I-NEXT: sd a0, 176(sp) ; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+4)(s0) ; RV64I-NEXT: lw a0, %lo(var+4)(s0)
; RV64I-NEXT: sd a0, 168(sp) ; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+8)(s0) ; RV64I-NEXT: lw a0, %lo(var+8)(s0)
; RV64I-NEXT: sd a0, 160(sp) ; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+12)(s0) ; RV64I-NEXT: lw a0, %lo(var+12)(s0)
; RV64I-NEXT: sd a0, 152(sp) ; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s1, s0, %lo(var) ; RV64I-NEXT: addi s1, s0, %lo(var)
; RV64I-NEXT: lw a0, 16(s1) ; RV64I-NEXT: lw a0, 16(s1)
; RV64I-NEXT: sd a0, 144(sp) ; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 20(s1) ; RV64I-NEXT: lw a0, 20(s1)
; RV64I-NEXT: sd a0, 136(sp) ; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 24(s1) ; RV64I-NEXT: lw a0, 24(s1)
; RV64I-NEXT: sd a0, 128(sp) ; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 28(s1) ; RV64I-NEXT: lw a0, 28(s1)
; RV64I-NEXT: sd a0, 120(sp) ; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 32(s1) ; RV64I-NEXT: lw a0, 32(s1)
; RV64I-NEXT: sd a0, 112(sp) ; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 36(s1) ; RV64I-NEXT: lw a0, 36(s1)
; RV64I-NEXT: sd a0, 104(sp) ; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 40(s1) ; RV64I-NEXT: lw a0, 40(s1)
; RV64I-NEXT: sd a0, 96(sp) ; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 44(s1) ; RV64I-NEXT: lw a0, 44(s1)
; RV64I-NEXT: sd a0, 88(sp) ; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 48(s1) ; RV64I-NEXT: lw a0, 48(s1)
; RV64I-NEXT: sd a0, 80(sp) ; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 52(s1) ; RV64I-NEXT: lw a0, 52(s1)
; RV64I-NEXT: sd a0, 72(sp) ; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 56(s1) ; RV64I-NEXT: lw a0, 56(s1)
; RV64I-NEXT: sd a0, 64(sp) ; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 60(s1) ; RV64I-NEXT: lw a0, 60(s1)
; RV64I-NEXT: sd a0, 56(sp) ; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 64(s1) ; RV64I-NEXT: lw a0, 64(s1)
; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 68(s1) ; RV64I-NEXT: lw a0, 68(s1)
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 72(s1) ; RV64I-NEXT: lw a0, 72(s1)
; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 76(s1) ; RV64I-NEXT: lw a0, 76(s1)
; RV64I-NEXT: sd a0, 24(sp) ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 80(s1) ; RV64I-NEXT: lw a0, 80(s1)
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 84(s1) ; RV64I-NEXT: lw a0, 84(s1)
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw s4, 88(s1) ; RV64I-NEXT: lw s4, 88(s1)
; RV64I-NEXT: lw s5, 92(s1) ; RV64I-NEXT: lw s5, 92(s1)
; RV64I-NEXT: lw s6, 96(s1) ; RV64I-NEXT: lw s6, 96(s1)
; RV64I-NEXT: lw s7, 100(s1) ; RV64I-NEXT: lw s7, 100(s1)
; RV64I-NEXT: lw s8, 104(s1) ; RV64I-NEXT: lw s8, 104(s1)
; RV64I-NEXT: lw s9, 108(s1) ; RV64I-NEXT: lw s9, 108(s1)
; RV64I-NEXT: lw s10, 112(s1) ; RV64I-NEXT: lw s10, 112(s1)
; RV64I-NEXT: lw s11, 116(s1) ; RV64I-NEXT: lw s11, 116(s1)
; RV64I-NEXT: lw s2, 120(s1) ; RV64I-NEXT: lw s2, 120(s1)
; RV64I-NEXT: lw s3, 124(s1) ; RV64I-NEXT: lw s3, 124(s1)
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee
; RV64I-NEXT: sw s3, 124(s1) ; RV64I-NEXT: sw s3, 124(s1)
; RV64I-NEXT: sw s2, 120(s1) ; RV64I-NEXT: sw s2, 120(s1)
; RV64I-NEXT: sw s11, 116(s1) ; RV64I-NEXT: sw s11, 116(s1)
; RV64I-NEXT: sw s10, 112(s1) ; RV64I-NEXT: sw s10, 112(s1)
; RV64I-NEXT: sw s9, 108(s1) ; RV64I-NEXT: sw s9, 108(s1)
; RV64I-NEXT: sw s8, 104(s1) ; RV64I-NEXT: sw s8, 104(s1)
; RV64I-NEXT: sw s7, 100(s1) ; RV64I-NEXT: sw s7, 100(s1)
; RV64I-NEXT: sw s6, 96(s1) ; RV64I-NEXT: sw s6, 96(s1)
; RV64I-NEXT: sw s5, 92(s1) ; RV64I-NEXT: sw s5, 92(s1)
; RV64I-NEXT: sw s4, 88(s1) ; RV64I-NEXT: sw s4, 88(s1)
; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 84(s1) ; RV64I-NEXT: sw a0, 84(s1)
; RV64I-NEXT: ld a0, 16(sp) ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 80(s1) ; RV64I-NEXT: sw a0, 80(s1)
; RV64I-NEXT: ld a0, 24(sp) ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 76(s1) ; RV64I-NEXT: sw a0, 76(s1)
; RV64I-NEXT: ld a0, 32(sp) ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 72(s1) ; RV64I-NEXT: sw a0, 72(s1)
; RV64I-NEXT: ld a0, 40(sp) ; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 68(s1) ; RV64I-NEXT: sw a0, 68(s1)
; RV64I-NEXT: ld a0, 48(sp) ; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 64(s1) ; RV64I-NEXT: sw a0, 64(s1)
; RV64I-NEXT: ld a0, 56(sp) ; RV64I-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 60(s1) ; RV64I-NEXT: sw a0, 60(s1)
; RV64I-NEXT: ld a0, 64(sp) ; RV64I-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 56(s1) ; RV64I-NEXT: sw a0, 56(s1)
; RV64I-NEXT: ld a0, 72(sp) ; RV64I-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 52(s1) ; RV64I-NEXT: sw a0, 52(s1)
; RV64I-NEXT: ld a0, 80(sp) ; RV64I-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 48(s1) ; RV64I-NEXT: sw a0, 48(s1)
; RV64I-NEXT: ld a0, 88(sp) ; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 44(s1) ; RV64I-NEXT: sw a0, 44(s1)
; RV64I-NEXT: ld a0, 96(sp) ; RV64I-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 40(s1) ; RV64I-NEXT: sw a0, 40(s1)
; RV64I-NEXT: ld a0, 104(sp) ; RV64I-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 36(s1) ; RV64I-NEXT: sw a0, 36(s1)
; RV64I-NEXT: ld a0, 112(sp) ; RV64I-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 32(s1) ; RV64I-NEXT: sw a0, 32(s1)
; RV64I-NEXT: ld a0, 120(sp) ; RV64I-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 28(s1) ; RV64I-NEXT: sw a0, 28(s1)
; RV64I-NEXT: ld a0, 128(sp) ; RV64I-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 24(s1) ; RV64I-NEXT: sw a0, 24(s1)
; RV64I-NEXT: ld a0, 136(sp) ; RV64I-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 20(s1) ; RV64I-NEXT: sw a0, 20(s1)
; RV64I-NEXT: ld a0, 144(sp) ; RV64I-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 16(s1) ; RV64I-NEXT: sw a0, 16(s1)
; RV64I-NEXT: ld a0, 152(sp) ; RV64I-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+12)(s0) ; RV64I-NEXT: sw a0, %lo(var+12)(s0)
; RV64I-NEXT: ld a0, 160(sp) ; RV64I-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+8)(s0) ; RV64I-NEXT: sw a0, %lo(var+8)(s0)
; RV64I-NEXT: ld a0, 168(sp) ; RV64I-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+4)(s0) ; RV64I-NEXT: sw a0, %lo(var+4)(s0)
; RV64I-NEXT: ld a0, 176(sp) ; RV64I-NEXT: ld a0, 176(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var)(s0) ; RV64I-NEXT: sw a0, %lo(var)(s0)
; RV64I-NEXT: ld s11, 184(sp) ; RV64I-NEXT: ld s11, 184(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s10, 192(sp) ; RV64I-NEXT: ld s10, 192(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s9, 200(sp) ; RV64I-NEXT: ld s9, 200(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 208(sp) ; RV64I-NEXT: ld s8, 208(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 216(sp) ; RV64I-NEXT: ld s7, 216(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 224(sp) ; RV64I-NEXT: ld s6, 224(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 232(sp) ; RV64I-NEXT: ld s5, 232(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 240(sp) ; RV64I-NEXT: ld s4, 240(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 248(sp) ; RV64I-NEXT: ld s3, 248(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 256(sp) ; RV64I-NEXT: ld s2, 256(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 264(sp) ; RV64I-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 272(sp) ; RV64I-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 280(sp) ; RV64I-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 288 ; RV64I-NEXT: addi sp, sp, 288
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64I-WITH-FP-LABEL: caller: ; RV64I-WITH-FP-LABEL: caller:
; RV64I-WITH-FP: # %bb.0: ; RV64I-WITH-FP: # %bb.0:
; RV64I-WITH-FP-NEXT: addi sp, sp, -288 ; RV64I-WITH-FP-NEXT: addi sp, sp, -288
; RV64I-WITH-FP-NEXT: sd ra, 280(sp) ; RV64I-WITH-FP-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s0, 272(sp) ; RV64I-WITH-FP-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s1, 264(sp) ; RV64I-WITH-FP-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s2, 256(sp) ; RV64I-WITH-FP-NEXT: sd s2, 256(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s3, 248(sp) ; RV64I-WITH-FP-NEXT: sd s3, 248(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s4, 240(sp) ; RV64I-WITH-FP-NEXT: sd s4, 240(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s5, 232(sp) ; RV64I-WITH-FP-NEXT: sd s5, 232(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s6, 224(sp) ; RV64I-WITH-FP-NEXT: sd s6, 224(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s7, 216(sp) ; RV64I-WITH-FP-NEXT: sd s7, 216(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s8, 208(sp) ; RV64I-WITH-FP-NEXT: sd s8, 208(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s9, 200(sp) ; RV64I-WITH-FP-NEXT: sd s9, 200(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s10, 192(sp) ; RV64I-WITH-FP-NEXT: sd s10, 192(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s11, 184(sp) ; RV64I-WITH-FP-NEXT: sd s11, 184(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi s0, sp, 288 ; RV64I-WITH-FP-NEXT: addi s0, sp, 288
; RV64I-WITH-FP-NEXT: lui s6, %hi(var) ; RV64I-WITH-FP-NEXT: lui s6, %hi(var)
; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s6)
; RV64I-WITH-FP-NEXT: sd a0, -112(s0) ; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
; RV64I-WITH-FP-NEXT: sd a0, -120(s0) ; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
; RV64I-WITH-FP-NEXT: sd a0, -128(s0) ; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
; RV64I-WITH-FP-NEXT: sd a0, -136(s0) ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi s1, s6, %lo(var) ; RV64I-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV64I-WITH-FP-NEXT: lw a0, 16(s1) ; RV64I-WITH-FP-NEXT: lw a0, 16(s1)
; RV64I-WITH-FP-NEXT: sd a0, -144(s0) ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 20(s1) ; RV64I-WITH-FP-NEXT: lw a0, 20(s1)
; RV64I-WITH-FP-NEXT: sd a0, -152(s0) ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 24(s1) ; RV64I-WITH-FP-NEXT: lw a0, 24(s1)
; RV64I-WITH-FP-NEXT: sd a0, -160(s0) ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 28(s1) ; RV64I-WITH-FP-NEXT: lw a0, 28(s1)
; RV64I-WITH-FP-NEXT: sd a0, -168(s0) ; RV64I-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 32(s1) ; RV64I-WITH-FP-NEXT: lw a0, 32(s1)
; RV64I-WITH-FP-NEXT: sd a0, -176(s0) ; RV64I-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 36(s1) ; RV64I-WITH-FP-NEXT: lw a0, 36(s1)
; RV64I-WITH-FP-NEXT: sd a0, -184(s0) ; RV64I-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 40(s1) ; RV64I-WITH-FP-NEXT: lw a0, 40(s1)
; RV64I-WITH-FP-NEXT: sd a0, -192(s0) ; RV64I-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 44(s1) ; RV64I-WITH-FP-NEXT: lw a0, 44(s1)
; RV64I-WITH-FP-NEXT: sd a0, -200(s0) ; RV64I-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 48(s1) ; RV64I-WITH-FP-NEXT: lw a0, 48(s1)
; RV64I-WITH-FP-NEXT: sd a0, -208(s0) ; RV64I-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 52(s1) ; RV64I-WITH-FP-NEXT: lw a0, 52(s1)
; RV64I-WITH-FP-NEXT: sd a0, -216(s0) ; RV64I-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 56(s1) ; RV64I-WITH-FP-NEXT: lw a0, 56(s1)
; RV64I-WITH-FP-NEXT: sd a0, -224(s0) ; RV64I-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 60(s1) ; RV64I-WITH-FP-NEXT: lw a0, 60(s1)
; RV64I-WITH-FP-NEXT: sd a0, -232(s0) ; RV64I-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 64(s1) ; RV64I-WITH-FP-NEXT: lw a0, 64(s1)
; RV64I-WITH-FP-NEXT: sd a0, -240(s0) ; RV64I-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 68(s1) ; RV64I-WITH-FP-NEXT: lw a0, 68(s1)
; RV64I-WITH-FP-NEXT: sd a0, -248(s0) ; RV64I-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 72(s1) ; RV64I-WITH-FP-NEXT: lw a0, 72(s1)
; RV64I-WITH-FP-NEXT: sd a0, -256(s0) ; RV64I-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 76(s1) ; RV64I-WITH-FP-NEXT: lw a0, 76(s1)
; RV64I-WITH-FP-NEXT: sd a0, -264(s0) ; RV64I-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 80(s1) ; RV64I-WITH-FP-NEXT: lw a0, 80(s1)
; RV64I-WITH-FP-NEXT: sd a0, -272(s0) ; RV64I-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 84(s1) ; RV64I-WITH-FP-NEXT: lw a0, 84(s1)
; RV64I-WITH-FP-NEXT: sd a0, -280(s0) ; RV64I-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 88(s1) ; RV64I-WITH-FP-NEXT: lw a0, 88(s1)
; RV64I-WITH-FP-NEXT: sd a0, -288(s0) ; RV64I-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw s8, 92(s1) ; RV64I-WITH-FP-NEXT: lw s8, 92(s1)
; RV64I-WITH-FP-NEXT: lw s9, 96(s1) ; RV64I-WITH-FP-NEXT: lw s9, 96(s1)
; RV64I-WITH-FP-NEXT: lw s10, 100(s1) ; RV64I-WITH-FP-NEXT: lw s10, 100(s1)
; RV64I-WITH-FP-NEXT: lw s11, 104(s1) ; RV64I-WITH-FP-NEXT: lw s11, 104(s1)
; RV64I-WITH-FP-NEXT: lw s2, 108(s1) ; RV64I-WITH-FP-NEXT: lw s2, 108(s1)
; RV64I-WITH-FP-NEXT: lw s3, 112(s1) ; RV64I-WITH-FP-NEXT: lw s3, 112(s1)
; RV64I-WITH-FP-NEXT: lw s4, 116(s1) ; RV64I-WITH-FP-NEXT: lw s4, 116(s1)
; RV64I-WITH-FP-NEXT: lw s5, 120(s1) ; RV64I-WITH-FP-NEXT: lw s5, 120(s1)
; RV64I-WITH-FP-NEXT: lw s7, 124(s1) ; RV64I-WITH-FP-NEXT: lw s7, 124(s1)
; RV64I-WITH-FP-NEXT: call callee ; RV64I-WITH-FP-NEXT: call callee
; RV64I-WITH-FP-NEXT: sw s7, 124(s1) ; RV64I-WITH-FP-NEXT: sw s7, 124(s1)
; RV64I-WITH-FP-NEXT: sw s5, 120(s1) ; RV64I-WITH-FP-NEXT: sw s5, 120(s1)
; RV64I-WITH-FP-NEXT: sw s4, 116(s1) ; RV64I-WITH-FP-NEXT: sw s4, 116(s1)
; RV64I-WITH-FP-NEXT: sw s3, 112(s1) ; RV64I-WITH-FP-NEXT: sw s3, 112(s1)
; RV64I-WITH-FP-NEXT: sw s2, 108(s1) ; RV64I-WITH-FP-NEXT: sw s2, 108(s1)
; RV64I-WITH-FP-NEXT: sw s11, 104(s1) ; RV64I-WITH-FP-NEXT: sw s11, 104(s1)
; RV64I-WITH-FP-NEXT: sw s10, 100(s1) ; RV64I-WITH-FP-NEXT: sw s10, 100(s1)
; RV64I-WITH-FP-NEXT: sw s9, 96(s1) ; RV64I-WITH-FP-NEXT: sw s9, 96(s1)
; RV64I-WITH-FP-NEXT: sw s8, 92(s1) ; RV64I-WITH-FP-NEXT: sw s8, 92(s1)
; RV64I-WITH-FP-NEXT: ld a0, -288(s0) ; RV64I-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 88(s1) ; RV64I-WITH-FP-NEXT: sw a0, 88(s1)
; RV64I-WITH-FP-NEXT: ld a0, -280(s0) ; RV64I-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 84(s1) ; RV64I-WITH-FP-NEXT: sw a0, 84(s1)
; RV64I-WITH-FP-NEXT: ld a0, -272(s0) ; RV64I-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 80(s1) ; RV64I-WITH-FP-NEXT: sw a0, 80(s1)
; RV64I-WITH-FP-NEXT: ld a0, -264(s0) ; RV64I-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 76(s1) ; RV64I-WITH-FP-NEXT: sw a0, 76(s1)
; RV64I-WITH-FP-NEXT: ld a0, -256(s0) ; RV64I-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 72(s1) ; RV64I-WITH-FP-NEXT: sw a0, 72(s1)
; RV64I-WITH-FP-NEXT: ld a0, -248(s0) ; RV64I-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 68(s1) ; RV64I-WITH-FP-NEXT: sw a0, 68(s1)
; RV64I-WITH-FP-NEXT: ld a0, -240(s0) ; RV64I-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 64(s1) ; RV64I-WITH-FP-NEXT: sw a0, 64(s1)
; RV64I-WITH-FP-NEXT: ld a0, -232(s0) ; RV64I-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 60(s1) ; RV64I-WITH-FP-NEXT: sw a0, 60(s1)
; RV64I-WITH-FP-NEXT: ld a0, -224(s0) ; RV64I-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 56(s1) ; RV64I-WITH-FP-NEXT: sw a0, 56(s1)
; RV64I-WITH-FP-NEXT: ld a0, -216(s0) ; RV64I-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 52(s1) ; RV64I-WITH-FP-NEXT: sw a0, 52(s1)
; RV64I-WITH-FP-NEXT: ld a0, -208(s0) ; RV64I-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 48(s1) ; RV64I-WITH-FP-NEXT: sw a0, 48(s1)
; RV64I-WITH-FP-NEXT: ld a0, -200(s0) ; RV64I-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 44(s1) ; RV64I-WITH-FP-NEXT: sw a0, 44(s1)
; RV64I-WITH-FP-NEXT: ld a0, -192(s0) ; RV64I-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 40(s1) ; RV64I-WITH-FP-NEXT: sw a0, 40(s1)
; RV64I-WITH-FP-NEXT: ld a0, -184(s0) ; RV64I-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 36(s1) ; RV64I-WITH-FP-NEXT: sw a0, 36(s1)
; RV64I-WITH-FP-NEXT: ld a0, -176(s0) ; RV64I-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 32(s1) ; RV64I-WITH-FP-NEXT: sw a0, 32(s1)
; RV64I-WITH-FP-NEXT: ld a0, -168(s0) ; RV64I-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 28(s1) ; RV64I-WITH-FP-NEXT: sw a0, 28(s1)
; RV64I-WITH-FP-NEXT: ld a0, -160(s0) ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 24(s1) ; RV64I-WITH-FP-NEXT: sw a0, 24(s1)
; RV64I-WITH-FP-NEXT: ld a0, -152(s0) ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 20(s1) ; RV64I-WITH-FP-NEXT: sw a0, 20(s1)
; RV64I-WITH-FP-NEXT: ld a0, -144(s0) ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 16(s1) ; RV64I-WITH-FP-NEXT: sw a0, 16(s1)
; RV64I-WITH-FP-NEXT: ld a0, -136(s0) ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
; RV64I-WITH-FP-NEXT: ld a0, -128(s0) ; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
; RV64I-WITH-FP-NEXT: ld a0, -120(s0) ; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
; RV64I-WITH-FP-NEXT: ld a0, -112(s0) ; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s6)
; RV64I-WITH-FP-NEXT: ld s11, 184(sp) ; RV64I-WITH-FP-NEXT: ld s11, 184(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s10, 192(sp) ; RV64I-WITH-FP-NEXT: ld s10, 192(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s9, 200(sp) ; RV64I-WITH-FP-NEXT: ld s9, 200(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s8, 208(sp) ; RV64I-WITH-FP-NEXT: ld s8, 208(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s7, 216(sp) ; RV64I-WITH-FP-NEXT: ld s7, 216(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s6, 224(sp) ; RV64I-WITH-FP-NEXT: ld s6, 224(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s5, 232(sp) ; RV64I-WITH-FP-NEXT: ld s5, 232(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s4, 240(sp) ; RV64I-WITH-FP-NEXT: ld s4, 240(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s3, 248(sp) ; RV64I-WITH-FP-NEXT: ld s3, 248(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s2, 256(sp) ; RV64I-WITH-FP-NEXT: ld s2, 256(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s1, 264(sp) ; RV64I-WITH-FP-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 272(sp) ; RV64I-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld ra, 280(sp) ; RV64I-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: addi sp, sp, 288 ; RV64I-WITH-FP-NEXT: addi sp, sp, 288
; RV64I-WITH-FP-NEXT: ret ; RV64I-WITH-FP-NEXT: ret
%val = load [32 x i32], [32 x i32]* @var %val = load [32 x i32], [32 x i32]* @var
call void @callee() call void @callee()
store volatile [32 x i32] %val, [32 x i32]* @var store volatile [32 x i32] %val, [32 x i32]* @var
ret void ret void
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

Show All 15 Lines
; Check that on RV32 ilp32[f], double is passed in a pair of registers. Unlike ; Check that on RV32 ilp32[f], double is passed in a pair of registers. Unlike
; the convention for varargs, this need not be an aligned pair. ; the convention for varargs, this need not be an aligned pair.
define i32 @callee_double_in_regs(i32 %a, double %b) nounwind { define i32 @callee_double_in_regs(i32 %a, double %b) nounwind {
; RV32I-FPELIM-LABEL: callee_double_in_regs: ; RV32I-FPELIM-LABEL: callee_double_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw s0, 8(sp) ; RV32I-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv s0, a0 ; RV32I-FPELIM-NEXT: mv s0, a0
; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2 ; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: call __fixdfsi ; RV32I-FPELIM-NEXT: call __fixdfsi@plt
; RV32I-FPELIM-NEXT: add a0, s0, a0 ; RV32I-FPELIM-NEXT: add a0, s0, a0
; RV32I-FPELIM-NEXT: lw s0, 8(sp) ; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_double_in_regs: ; RV32I-WITHFP-LABEL: callee_double_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s1, 4(sp) ; RV32I-WITHFP-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv s1, a0 ; RV32I-WITHFP-NEXT: mv s1, a0
; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: mv a1, a2 ; RV32I-WITHFP-NEXT: mv a1, a2
; RV32I-WITHFP-NEXT: call __fixdfsi ; RV32I-WITHFP-NEXT: call __fixdfsi@plt
; RV32I-WITHFP-NEXT: add a0, s1, a0 ; RV32I-WITHFP-NEXT: add a0, s1, a0
; RV32I-WITHFP-NEXT: lw s1, 4(sp) ; RV32I-WITHFP-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_fptosi = fptosi double %b to i32 %b_fptosi = fptosi double %b to i32
%1 = add i32 %a, %b_fptosi %1 = add i32 %a, %b_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_regs() nounwind { define i32 @caller_double_in_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_double_in_regs: ; RV32I-FPELIM-LABEL: caller_double_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: lui a2, 262144 ; RV32I-FPELIM-NEXT: lui a2, 262144
; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: call callee_double_in_regs ; RV32I-FPELIM-NEXT: call callee_double_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_double_in_regs: ; RV32I-WITHFP-LABEL: caller_double_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: lui a2, 262144 ; RV32I-WITHFP-NEXT: lui a2, 262144
; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: call callee_double_in_regs ; RV32I-WITHFP-NEXT: call callee_double_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_double_in_regs(i32 1, double 2.0) %1 = call i32 @callee_double_in_regs(i32 1, double 2.0)
ret i32 %1 ret i32 %1
} }
; Check 2x*xlen values are aligned appropriately when passed on the stack ; Check 2x*xlen values are aligned appropriately when passed on the stack
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
Show All 12 Lines
; RV32I-FPELIM-NEXT: add a0, a0, a3 ; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4 ; RV32I-FPELIM-NEXT: add a0, a0, a4
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_aligned_stack: ; RV32I-WITHFP-LABEL: callee_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2) ; RV32I-WITHFP-NEXT: lw a0, 0(a2)
; RV32I-WITHFP-NEXT: lw a1, 20(s0) ; RV32I-WITHFP-NEXT: lw a1, 20(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(s0) ; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0) ; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0) ; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7 ; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2 ; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3 ; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4 ; RV32I-WITHFP-NEXT: add a0, a0, a4
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = bitcast fp128 %c to i128 %1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32 %2 = trunc i128 %1 to i32
%3 = add i32 %2, %g %3 = add i32 %2, %g
%4 = add i32 %3, %h %4 = add i32 %3, %h
%5 = bitcast double %i to i64 %5 = bitcast double %i to i64
%6 = trunc i64 %5 to i32 %6 = trunc i64 %5 to i32
%7 = add i32 %4, %6 %7 = add i32 %4, %6
%8 = add i32 %7, %j %8 = add i32 %7, %j
%9 = extractvalue [2 x i32] %k, 0 %9 = extractvalue [2 x i32] %k, 0
%10 = add i32 %8, %9 %10 = add i32 %8, %9
ret i32 %10 ret i32 %10
} }
define void @caller_aligned_stack() nounwind { define void @caller_aligned_stack() nounwind {
; The double should be 8-byte aligned on the stack, but the two-element array ; The double should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned ; should only be 4-byte aligned
; RV32I-FPELIM-LABEL: caller_aligned_stack: ; RV32I-FPELIM-LABEL: caller_aligned_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64 ; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) ; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 18 ; RV32I-FPELIM-NEXT: addi a0, zero, 18
; RV32I-FPELIM-NEXT: sw a0, 24(sp) ; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 17 ; RV32I-FPELIM-NEXT: addi a0, zero, 17
; RV32I-FPELIM-NEXT: sw a0, 20(sp) ; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 16 ; RV32I-FPELIM-NEXT: addi a0, zero, 16
; RV32I-FPELIM-NEXT: sw a0, 16(sp) ; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: lui a0, 262236 ; RV32I-FPELIM-NEXT: lui a0, 262236
; RV32I-FPELIM-NEXT: addi a0, a0, 655 ; RV32I-FPELIM-NEXT: addi a0, a0, 655
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; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32 ; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12 ; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14 ; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp) ; RV32I-FPELIM-NEXT: sw t0, 32(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_aligned_stack: ; RV32I-WITHFP-LABEL: caller_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp) ; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) ; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64 ; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, zero, 18 ; RV32I-WITHFP-NEXT: addi a0, zero, 18
; RV32I-WITHFP-NEXT: sw a0, 24(sp) ; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 17 ; RV32I-WITHFP-NEXT: addi a0, zero, 17
; RV32I-WITHFP-NEXT: sw a0, 20(sp) ; RV32I-WITHFP-NEXT: sw a0, 20(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 16 ; RV32I-WITHFP-NEXT: addi a0, zero, 16
; RV32I-WITHFP-NEXT: sw a0, 16(sp) ; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: lui a0, 262236 ; RV32I-WITHFP-NEXT: lui a0, 262236
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; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32 ; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12 ; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14 ; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0) ; RV32I-WITHFP-NEXT: sw t0, -32(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11, %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16, i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
[2 x i32] [i32 17, i32 18]) [2 x i32] [i32 17, i32 18])
ret void ret void
} }
define double @callee_small_scalar_ret() nounwind { define double @callee_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_small_scalar_ret: ; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a1, 261888 ; RV32I-FPELIM-NEXT: lui a1, 261888
; RV32I-FPELIM-NEXT: mv a0, zero ; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_small_scalar_ret: ; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a1, 261888 ; RV32I-WITHFP-NEXT: lui a1, 261888
; RV32I-WITHFP-NEXT: mv a0, zero ; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret double 1.0 ret double 1.0
} }
define i64 @caller_small_scalar_ret() nounwind { define i64 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_small_scalar_ret: ; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret ; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_small_scalar_ret: ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: call callee_small_scalar_ret ; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call double @callee_small_scalar_ret() %1 = call double @callee_small_scalar_ret()
%2 = bitcast double %1 to i64 %2 = bitcast double %1 to i64
ret i64 %2 ret i64 %2
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

Show All 27 Lines
; RV32I-FPELIM-LABEL: callee_i64_in_regs: ; RV32I-FPELIM-LABEL: callee_i64_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_i64_in_regs: ; RV32I-WITHFP-LABEL: callee_i64_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_trunc = trunc i64 %b to i32 %b_trunc = trunc i64 %b to i32
%1 = add i32 %a, %b_trunc %1 = add i32 %a, %b_trunc
ret i32 %1 ret i32 %1
} }
define i32 @caller_i64_in_regs() nounwind { define i32 @caller_i64_in_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_i64_in_regs: ; RV32I-FPELIM-LABEL: caller_i64_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: call callee_i64_in_regs ; RV32I-FPELIM-NEXT: call callee_i64_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_i64_in_regs: ; RV32I-WITHFP-LABEL: caller_i64_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: call callee_i64_in_regs ; RV32I-WITHFP-NEXT: call callee_i64_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_i64_in_regs(i32 1, i64 2) %1 = call i32 @callee_i64_in_regs(i32 1, i64 2)
ret i32 %1 ret i32 %1
} }
; Check that the stack is used once the GPRs are exhausted ; Check that the stack is used once the GPRs are exhausted
Show All 16 Lines
; RV32I-FPELIM-NEXT: add a0, a0, a5 ; RV32I-FPELIM-NEXT: add a0, a0, a5
; RV32I-FPELIM-NEXT: add a0, a0, a6 ; RV32I-FPELIM-NEXT: add a0, a0, a6
; RV32I-FPELIM-NEXT: add a0, a0, t0 ; RV32I-FPELIM-NEXT: add a0, a0, t0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_many_scalars: ; RV32I-WITHFP-LABEL: callee_many_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw t0, 4(s0) ; RV32I-WITHFP-NEXT: lw t0, 4(s0)
; RV32I-WITHFP-NEXT: lw t1, 0(s0) ; RV32I-WITHFP-NEXT: lw t1, 0(s0)
; RV32I-WITHFP-NEXT: andi t2, a0, 255 ; RV32I-WITHFP-NEXT: andi t2, a0, 255
; RV32I-WITHFP-NEXT: lui a0, 16 ; RV32I-WITHFP-NEXT: lui a0, 16
; RV32I-WITHFP-NEXT: addi a0, a0, -1 ; RV32I-WITHFP-NEXT: addi a0, a0, -1
; RV32I-WITHFP-NEXT: and a0, a1, a0 ; RV32I-WITHFP-NEXT: and a0, a1, a0
; RV32I-WITHFP-NEXT: add a0, t2, a0 ; RV32I-WITHFP-NEXT: add a0, t2, a0
; RV32I-WITHFP-NEXT: add a0, a0, a2 ; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: xor a1, a4, t1 ; RV32I-WITHFP-NEXT: xor a1, a4, t1
; RV32I-WITHFP-NEXT: xor a2, a3, a7 ; RV32I-WITHFP-NEXT: xor a2, a3, a7
; RV32I-WITHFP-NEXT: or a1, a2, a1 ; RV32I-WITHFP-NEXT: or a1, a2, a1
; RV32I-WITHFP-NEXT: seqz a1, a1 ; RV32I-WITHFP-NEXT: seqz a1, a1
; RV32I-WITHFP-NEXT: add a0, a1, a0 ; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: add a0, a0, a5 ; RV32I-WITHFP-NEXT: add a0, a0, a5
; RV32I-WITHFP-NEXT: add a0, a0, a6 ; RV32I-WITHFP-NEXT: add a0, a0, a6
; RV32I-WITHFP-NEXT: add a0, a0, t0 ; RV32I-WITHFP-NEXT: add a0, a0, t0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%a_ext = zext i8 %a to i32 %a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32 %b_ext = zext i16 %b to i32
%1 = add i32 %a_ext, %b_ext %1 = add i32 %a_ext, %b_ext
%2 = add i32 %1, %c %2 = add i32 %1, %c
%3 = icmp eq i64 %d, %g %3 = icmp eq i64 %d, %g
%4 = zext i1 %3 to i32 %4 = zext i1 %3 to i32
%5 = add i32 %4, %2 %5 = add i32 %4, %2
%6 = add i32 %5, %e %6 = add i32 %5, %e
%7 = add i32 %6, %f %7 = add i32 %6, %f
%8 = add i32 %7, %h %8 = add i32 %7, %h
ret i32 %8 ret i32 %8
} }
define i32 @caller_many_scalars() nounwind { define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM-LABEL: caller_many_scalars: ; RV32I-FPELIM-LABEL: caller_many_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3 ; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4 ; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: addi a5, zero, 5 ; RV32I-FPELIM-NEXT: addi a5, zero, 5
; RV32I-FPELIM-NEXT: addi a6, zero, 6 ; RV32I-FPELIM-NEXT: addi a6, zero, 6
; RV32I-FPELIM-NEXT: addi a7, zero, 7 ; RV32I-FPELIM-NEXT: addi a7, zero, 7
; RV32I-FPELIM-NEXT: sw zero, 0(sp) ; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: mv a4, zero ; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: call callee_many_scalars ; RV32I-FPELIM-NEXT: call callee_many_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_many_scalars: ; RV32I-WITHFP-LABEL: caller_many_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3 ; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4 ; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: addi a5, zero, 5 ; RV32I-WITHFP-NEXT: addi a5, zero, 5
; RV32I-WITHFP-NEXT: addi a6, zero, 6 ; RV32I-WITHFP-NEXT: addi a6, zero, 6
; RV32I-WITHFP-NEXT: addi a7, zero, 7 ; RV32I-WITHFP-NEXT: addi a7, zero, 7
; RV32I-WITHFP-NEXT: sw zero, 0(sp) ; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: mv a4, zero ; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: call callee_many_scalars ; RV32I-WITHFP-NEXT: call callee_many_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8) %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
ret i32 %1 ret i32 %1
} }
; Check that i128 and fp128 are passed indirectly ; Check that i128 and fp128 are passed indirectly
Show All 17 Lines
; RV32I-FPELIM-NEXT: or a0, a1, a0 ; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a2 ; RV32I-FPELIM-NEXT: or a0, a0, a2
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars: ; RV32I-WITHFP-LABEL: callee_large_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a6, 0(a1) ; RV32I-WITHFP-NEXT: lw a6, 0(a1)
; RV32I-WITHFP-NEXT: lw a7, 0(a0) ; RV32I-WITHFP-NEXT: lw a7, 0(a0)
; RV32I-WITHFP-NEXT: lw a4, 4(a1) ; RV32I-WITHFP-NEXT: lw a4, 4(a1)
; RV32I-WITHFP-NEXT: lw a5, 12(a1) ; RV32I-WITHFP-NEXT: lw a5, 12(a1)
; RV32I-WITHFP-NEXT: lw a2, 12(a0) ; RV32I-WITHFP-NEXT: lw a2, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a0) ; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a1, 8(a1) ; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0) ; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a2, a2, a5 ; RV32I-WITHFP-NEXT: xor a2, a2, a5
; RV32I-WITHFP-NEXT: xor a3, a3, a4 ; RV32I-WITHFP-NEXT: xor a3, a3, a4
; RV32I-WITHFP-NEXT: or a2, a3, a2 ; RV32I-WITHFP-NEXT: or a2, a3, a2
; RV32I-WITHFP-NEXT: xor a0, a0, a1 ; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: xor a1, a7, a6 ; RV32I-WITHFP-NEXT: xor a1, a7, a6
; RV32I-WITHFP-NEXT: or a0, a1, a0 ; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a2 ; RV32I-WITHFP-NEXT: or a0, a0, a2
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_bitcast = bitcast fp128 %b to i128 %b_bitcast = bitcast fp128 %b to i128
%1 = icmp eq i128 %a, %b_bitcast %1 = icmp eq i128 %a, %b_bitcast
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @caller_large_scalars() nounwind { define i32 @caller_large_scalars() nounwind {
; RV32I-FPELIM-LABEL: caller_large_scalars: ; RV32I-FPELIM-LABEL: caller_large_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48 ; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp) ; RV32I-FPELIM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: lui a0, 524272 ; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 12(sp) ; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 4(sp) ; RV32I-FPELIM-NEXT: sw zero, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp) ; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: sw zero, 36(sp) ; RV32I-FPELIM-NEXT: sw zero, 36(sp)
; RV32I-FPELIM-NEXT: sw zero, 32(sp) ; RV32I-FPELIM-NEXT: sw zero, 32(sp)
; RV32I-FPELIM-NEXT: sw zero, 28(sp) ; RV32I-FPELIM-NEXT: sw zero, 28(sp)
; RV32I-FPELIM-NEXT: addi a2, zero, 1 ; RV32I-FPELIM-NEXT: addi a2, zero, 1
; RV32I-FPELIM-NEXT: addi a0, sp, 24 ; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: mv a1, sp ; RV32I-FPELIM-NEXT: mv a1, sp
; RV32I-FPELIM-NEXT: sw a2, 24(sp) ; RV32I-FPELIM-NEXT: sw a2, 24(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars ; RV32I-FPELIM-NEXT: call callee_large_scalars
; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_scalars: ; RV32I-WITHFP-LABEL: caller_large_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48 ; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp) ; RV32I-WITHFP-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 40(sp) ; RV32I-WITHFP-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 48 ; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: lui a0, 524272 ; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0) ; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a2, zero, 1 ; RV32I-WITHFP-NEXT: addi a2, zero, 1
; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: addi a1, s0, -48 ; RV32I-WITHFP-NEXT: addi a1, s0, -48
; RV32I-WITHFP-NEXT: sw a2, -24(s0) ; RV32I-WITHFP-NEXT: sw a2, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars ; RV32I-WITHFP-NEXT: call callee_large_scalars
; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 48 ; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000) %1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
ret i32 %1 ret i32 %1
} }
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
Show All 19 Lines
; RV32I-FPELIM-NEXT: or a0, a2, a0 ; RV32I-FPELIM-NEXT: or a0, a2, a0
; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 4(s0) ; RV32I-WITHFP-NEXT: lw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw a6, 0(a0) ; RV32I-WITHFP-NEXT: lw a6, 0(a0)
; RV32I-WITHFP-NEXT: lw t0, 0(a7) ; RV32I-WITHFP-NEXT: lw t0, 0(a7)
; RV32I-WITHFP-NEXT: lw a3, 4(a0) ; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a4, 12(a0) ; RV32I-WITHFP-NEXT: lw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw a5, 12(a7) ; RV32I-WITHFP-NEXT: lw a5, 12(a7)
; RV32I-WITHFP-NEXT: lw a1, 4(a7) ; RV32I-WITHFP-NEXT: lw a1, 4(a7)
; RV32I-WITHFP-NEXT: lw a0, 8(a0) ; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a2, 8(a7) ; RV32I-WITHFP-NEXT: lw a2, 8(a7)
; RV32I-WITHFP-NEXT: xor a4, a5, a4 ; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a1, a1, a3 ; RV32I-WITHFP-NEXT: xor a1, a1, a3
; RV32I-WITHFP-NEXT: or a1, a1, a4 ; RV32I-WITHFP-NEXT: or a1, a1, a4
; RV32I-WITHFP-NEXT: xor a0, a2, a0 ; RV32I-WITHFP-NEXT: xor a0, a2, a0
; RV32I-WITHFP-NEXT: xor a2, t0, a6 ; RV32I-WITHFP-NEXT: xor a2, t0, a6
; RV32I-WITHFP-NEXT: or a0, a2, a0 ; RV32I-WITHFP-NEXT: or a0, a2, a0
; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%j_bitcast = bitcast fp128 %j to i128 %j_bitcast = bitcast fp128 %j to i128
%1 = icmp eq i128 %h, %j_bitcast %1 = icmp eq i128 %h, %j_bitcast
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @caller_large_scalars_exhausted_regs() nounwind { define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs: ; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64 ; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) ; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, sp, 16 ; RV32I-FPELIM-NEXT: addi a0, sp, 16
; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 9 ; RV32I-FPELIM-NEXT: addi a0, zero, 9
; RV32I-FPELIM-NEXT: sw a0, 0(sp) ; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: lui a0, 524272 ; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 28(sp) ; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp) ; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp) ; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp) ; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 52(sp) ; RV32I-FPELIM-NEXT: sw zero, 52(sp)
; RV32I-FPELIM-NEXT: sw zero, 48(sp) ; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp) ; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi t0, zero, 8 ; RV32I-FPELIM-NEXT: addi t0, zero, 8
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3 ; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4 ; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: addi a4, zero, 5 ; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6 ; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7 ; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: addi a7, sp, 40 ; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: sw t0, 40(sp) ; RV32I-FPELIM-NEXT: sw t0, 40(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs: ; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp) ; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) ; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64 ; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, s0, -48 ; RV32I-WITHFP-NEXT: addi a0, s0, -48
; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 9 ; RV32I-WITHFP-NEXT: addi a0, zero, 9
; RV32I-WITHFP-NEXT: sw a0, 0(sp) ; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 524272 ; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0) ; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi t0, zero, 8 ; RV32I-WITHFP-NEXT: addi t0, zero, 8
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3 ; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4 ; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: addi a4, zero, 5 ; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6 ; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7 ; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: addi a7, s0, -24 ; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: sw t0, -24(s0) ; RV32I-WITHFP-NEXT: sw t0, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_large_scalars_exhausted_regs( %1 = call i32 @callee_large_scalars_exhausted_regs(
i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
fp128 0xL00000000000000007FFF000000000000) fp128 0xL00000000000000007FFF000000000000)
ret i32 %1 ret i32 %1
} }
; Ensure that libcalls generated in the middle-end obey the calling convention ; Ensure that libcalls generated in the middle-end obey the calling convention
define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls: ; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv a2, a1 ; RV32I-FPELIM-NEXT: mv a2, a1
; RV32I-FPELIM-NEXT: mv a1, a0 ; RV32I-FPELIM-NEXT: mv a1, a0
; RV32I-FPELIM-NEXT: addi a0, sp, 8 ; RV32I-FPELIM-NEXT: addi a0, sp, 8
; RV32I-FPELIM-NEXT: call __floatditf ; RV32I-FPELIM-NEXT: call __floatditf@plt
; RV32I-FPELIM-NEXT: lw a0, 8(sp) ; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls: ; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32 ; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: mv a2, a1 ; RV32I-WITHFP-NEXT: mv a2, a1
; RV32I-WITHFP-NEXT: mv a1, a0 ; RV32I-WITHFP-NEXT: mv a1, a0
; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: call __floatditf ; RV32I-WITHFP-NEXT: call __floatditf@plt
; RV32I-WITHFP-NEXT: lw a0, -24(s0) ; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = sitofp i64 %a to fp128 %1 = sitofp i64 %a to fp128
%2 = bitcast fp128 %1 to i128 %2 = bitcast fp128 %1 to i128
%3 = trunc i128 %2 to i32 %3 = trunc i128 %2 to i32
ret i32 %3 ret i32 %3
} }
; Check passing of coerced integer arrays ; Check passing of coerced integer arrays
%struct.small = type { i32, i32* } %struct.small = type { i32, i32* }
define i32 @callee_small_coerced_struct([2 x i32] %a.coerce) nounwind { define i32 @callee_small_coerced_struct([2 x i32] %a.coerce) nounwind {
; RV32I-FPELIM-LABEL: callee_small_coerced_struct: ; RV32I-FPELIM-LABEL: callee_small_coerced_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: xor a0, a0, a1 ; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_small_coerced_struct: ; RV32I-WITHFP-LABEL: callee_small_coerced_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: xor a0, a0, a1 ; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = extractvalue [2 x i32] %a.coerce, 0 %1 = extractvalue [2 x i32] %a.coerce, 0
%2 = extractvalue [2 x i32] %a.coerce, 1 %2 = extractvalue [2 x i32] %a.coerce, 1
%3 = icmp eq i32 %1, %2 %3 = icmp eq i32 %1, %2
%4 = zext i1 %3 to i32 %4 = zext i1 %3 to i32
ret i32 %4 ret i32 %4
} }
define i32 @caller_small_coerced_struct() nounwind { define i32 @caller_small_coerced_struct() nounwind {
; RV32I-FPELIM-LABEL: caller_small_coerced_struct: ; RV32I-FPELIM-LABEL: caller_small_coerced_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: call callee_small_coerced_struct ; RV32I-FPELIM-NEXT: call callee_small_coerced_struct
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_small_coerced_struct: ; RV32I-WITHFP-LABEL: caller_small_coerced_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: call callee_small_coerced_struct ; RV32I-WITHFP-NEXT: call callee_small_coerced_struct
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2]) %1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2])
ret i32 %1 ret i32 %1
} }
; Check large struct arguments, which are passed byval ; Check large struct arguments, which are passed byval
%struct.large = type { i32, i32, i32, i32 } %struct.large = type { i32, i32, i32, i32 }
define i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %a) nounwind { define i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %a) nounwind {
; RV32I-FPELIM-LABEL: callee_large_struct: ; RV32I-FPELIM-LABEL: callee_large_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a1, 0(a0) ; RV32I-FPELIM-NEXT: lw a1, 0(a0)
; RV32I-FPELIM-NEXT: lw a0, 12(a0) ; RV32I-FPELIM-NEXT: lw a0, 12(a0)
; RV32I-FPELIM-NEXT: add a0, a1, a0 ; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_struct: ; RV32I-WITHFP-LABEL: callee_large_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a1, 0(a0) ; RV32I-WITHFP-NEXT: lw a1, 0(a0)
; RV32I-WITHFP-NEXT: lw a0, 12(a0) ; RV32I-WITHFP-NEXT: lw a0, 12(a0)
; RV32I-WITHFP-NEXT: add a0, a1, a0 ; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0 %1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3 %2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3
%3 = load i32, i32* %1 %3 = load i32, i32* %1
%4 = load i32, i32* %2 %4 = load i32, i32* %2
%5 = add i32 %3, %4 %5 = add i32 %3, %4
ret i32 %5 ret i32 %5
} }
define i32 @caller_large_struct() nounwind { define i32 @caller_large_struct() nounwind {
; RV32I-FPELIM-LABEL: caller_large_struct: ; RV32I-FPELIM-LABEL: caller_large_struct:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48 ; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp) ; RV32I-FPELIM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp) ; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 28(sp) ; RV32I-FPELIM-NEXT: sw a1, 28(sp)
; RV32I-FPELIM-NEXT: addi a2, zero, 3 ; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: sw a2, 32(sp) ; RV32I-FPELIM-NEXT: sw a2, 32(sp)
; RV32I-FPELIM-NEXT: addi a3, zero, 4 ; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: sw a3, 36(sp) ; RV32I-FPELIM-NEXT: sw a3, 36(sp)
; RV32I-FPELIM-NEXT: sw a0, 8(sp) ; RV32I-FPELIM-NEXT: sw a0, 8(sp)
; RV32I-FPELIM-NEXT: sw a1, 12(sp) ; RV32I-FPELIM-NEXT: sw a1, 12(sp)
; RV32I-FPELIM-NEXT: sw a2, 16(sp) ; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 20(sp) ; RV32I-FPELIM-NEXT: sw a3, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 8 ; RV32I-FPELIM-NEXT: addi a0, sp, 8
; RV32I-FPELIM-NEXT: call callee_large_struct ; RV32I-FPELIM-NEXT: call callee_large_struct
; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_struct: ; RV32I-WITHFP-LABEL: caller_large_struct:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48 ; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp) ; RV32I-WITHFP-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 40(sp) ; RV32I-WITHFP-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 48 ; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0) ; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, -20(s0) ; RV32I-WITHFP-NEXT: sw a1, -20(s0)
; RV32I-WITHFP-NEXT: addi a2, zero, 3 ; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: sw a2, -16(s0) ; RV32I-WITHFP-NEXT: sw a2, -16(s0)
; RV32I-WITHFP-NEXT: addi a3, zero, 4 ; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: sw a3, -12(s0) ; RV32I-WITHFP-NEXT: sw a3, -12(s0)
; RV32I-WITHFP-NEXT: sw a0, -40(s0) ; RV32I-WITHFP-NEXT: sw a0, -40(s0)
; RV32I-WITHFP-NEXT: sw a1, -36(s0) ; RV32I-WITHFP-NEXT: sw a1, -36(s0)
; RV32I-WITHFP-NEXT: sw a2, -32(s0) ; RV32I-WITHFP-NEXT: sw a2, -32(s0)
; RV32I-WITHFP-NEXT: sw a3, -28(s0) ; RV32I-WITHFP-NEXT: sw a3, -28(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -40 ; RV32I-WITHFP-NEXT: addi a0, s0, -40
; RV32I-WITHFP-NEXT: call callee_large_struct ; RV32I-WITHFP-NEXT: call callee_large_struct
; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 48 ; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%ls = alloca %struct.large, align 4 %ls = alloca %struct.large, align 4
%1 = bitcast %struct.large* %ls to i8* %1 = bitcast %struct.large* %ls to i8*
%a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0
store i32 1, i32* %a store i32 1, i32* %a
%b = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 1 %b = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 1
store i32 2, i32* %b store i32 2, i32* %b
Show All 22 Lines
; RV32I-FPELIM-NEXT: add a0, a0, a3 ; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4 ; RV32I-FPELIM-NEXT: add a0, a0, a4
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_aligned_stack: ; RV32I-WITHFP-LABEL: callee_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2) ; RV32I-WITHFP-NEXT: lw a0, 0(a2)
; RV32I-WITHFP-NEXT: lw a1, 20(s0) ; RV32I-WITHFP-NEXT: lw a1, 20(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(s0) ; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0) ; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0) ; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7 ; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2 ; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3 ; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4 ; RV32I-WITHFP-NEXT: add a0, a0, a4
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = bitcast fp128 %c to i128 %1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32 %2 = trunc i128 %1 to i32
%3 = add i32 %2, %g %3 = add i32 %2, %g
%4 = add i32 %3, %h %4 = add i32 %3, %h
%5 = trunc i64 %i to i32 %5 = trunc i64 %i to i32
%6 = add i32 %4, %5 %6 = add i32 %4, %5
%7 = add i32 %6, %j %7 = add i32 %6, %j
%8 = extractvalue [2 x i32] %k, 0 %8 = extractvalue [2 x i32] %k, 0
%9 = add i32 %7, %8 %9 = add i32 %7, %8
ret i32 %9 ret i32 %9
} }
define void @caller_aligned_stack() nounwind { define void @caller_aligned_stack() nounwind {
; The i64 should be 8-byte aligned on the stack, but the two-element array ; The i64 should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned ; should only be 4-byte aligned
; RV32I-FPELIM-LABEL: caller_aligned_stack: ; RV32I-FPELIM-LABEL: caller_aligned_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64 ; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) ; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 19 ; RV32I-FPELIM-NEXT: addi a0, zero, 19
; RV32I-FPELIM-NEXT: sw a0, 24(sp) ; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 18 ; RV32I-FPELIM-NEXT: addi a0, zero, 18
; RV32I-FPELIM-NEXT: sw a0, 20(sp) ; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 17 ; RV32I-FPELIM-NEXT: addi a0, zero, 17
; RV32I-FPELIM-NEXT: sw a0, 16(sp) ; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp) ; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 16 ; RV32I-FPELIM-NEXT: addi a0, zero, 16
Show All 17 Lines
; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32 ; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12 ; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14 ; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp) ; RV32I-FPELIM-NEXT: sw t0, 32(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_aligned_stack: ; RV32I-WITHFP-LABEL: caller_aligned_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64 ; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp) ; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) ; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64 ; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, zero, 19 ; RV32I-WITHFP-NEXT: addi a0, zero, 19
; RV32I-WITHFP-NEXT: sw a0, 24(sp) ; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 18 ; RV32I-WITHFP-NEXT: addi a0, zero, 18
; RV32I-WITHFP-NEXT: sw a0, 20(sp) ; RV32I-WITHFP-NEXT: sw a0, 20(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 17 ; RV32I-WITHFP-NEXT: addi a0, zero, 17
; RV32I-WITHFP-NEXT: sw a0, 16(sp) ; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: sw zero, 12(sp) ; RV32I-WITHFP-NEXT: sw zero, 12(sp)
Show All 18 Lines
; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32 ; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12 ; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14 ; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0) ; RV32I-WITHFP-NEXT: sw t0, -32(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64 ; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11, %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
i64 20000000000, i32 14, i32 15, i64 16, i32 17, i64 20000000000, i32 14, i32 15, i64 16, i32 17,
[2 x i32] [i32 18, i32 19]) [2 x i32] [i32 18, i32 19])
ret void ret void
} }
; Check return of 2x xlen scalars ; Check return of 2x xlen scalars
define i64 @callee_small_scalar_ret() nounwind { define i64 @callee_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_small_scalar_ret: ; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a0, 466866 ; RV32I-FPELIM-NEXT: lui a0, 466866
; RV32I-FPELIM-NEXT: addi a0, a0, 1677 ; RV32I-FPELIM-NEXT: addi a0, a0, 1677
; RV32I-FPELIM-NEXT: addi a1, zero, 287 ; RV32I-FPELIM-NEXT: addi a1, zero, 287
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_small_scalar_ret: ; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 466866 ; RV32I-WITHFP-NEXT: lui a0, 466866
; RV32I-WITHFP-NEXT: addi a0, a0, 1677 ; RV32I-WITHFP-NEXT: addi a0, a0, 1677
; RV32I-WITHFP-NEXT: addi a1, zero, 287 ; RV32I-WITHFP-NEXT: addi a1, zero, 287
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret i64 1234567898765 ret i64 1234567898765
} }
define i32 @caller_small_scalar_ret() nounwind { define i32 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_small_scalar_ret: ; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret ; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
; RV32I-FPELIM-NEXT: lui a2, 56 ; RV32I-FPELIM-NEXT: lui a2, 56
; RV32I-FPELIM-NEXT: addi a2, a2, 580 ; RV32I-FPELIM-NEXT: addi a2, a2, 580
; RV32I-FPELIM-NEXT: xor a1, a1, a2 ; RV32I-FPELIM-NEXT: xor a1, a1, a2
; RV32I-FPELIM-NEXT: lui a2, 200614 ; RV32I-FPELIM-NEXT: lui a2, 200614
; RV32I-FPELIM-NEXT: addi a2, a2, 647 ; RV32I-FPELIM-NEXT: addi a2, a2, 647
; RV32I-FPELIM-NEXT: xor a0, a0, a2 ; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_small_scalar_ret: ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: call callee_small_scalar_ret ; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
; RV32I-WITHFP-NEXT: lui a2, 56 ; RV32I-WITHFP-NEXT: lui a2, 56
; RV32I-WITHFP-NEXT: addi a2, a2, 580 ; RV32I-WITHFP-NEXT: addi a2, a2, 580
; RV32I-WITHFP-NEXT: xor a1, a1, a2 ; RV32I-WITHFP-NEXT: xor a1, a1, a2
; RV32I-WITHFP-NEXT: lui a2, 200614 ; RV32I-WITHFP-NEXT: lui a2, 200614
; RV32I-WITHFP-NEXT: addi a2, a2, 647 ; RV32I-WITHFP-NEXT: addi a2, a2, 647
; RV32I-WITHFP-NEXT: xor a0, a0, a2 ; RV32I-WITHFP-NEXT: xor a0, a0, a2
; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i64 @callee_small_scalar_ret() %1 = call i64 @callee_small_scalar_ret()
%2 = icmp eq i64 987654321234567, %1 %2 = icmp eq i64 987654321234567, %1
%3 = zext i1 %2 to i32 %3 = zext i1 %2 to i32
ret i32 %3 ret i32 %3
} }
; Check return of 2x xlen structs ; Check return of 2x xlen structs
define %struct.small @callee_small_struct_ret() nounwind { define %struct.small @callee_small_struct_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_small_struct_ret: ; RV32I-FPELIM-LABEL: callee_small_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_small_struct_ret: ; RV32I-WITHFP-LABEL: callee_small_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret %struct.small { i32 1, i32* null } ret %struct.small { i32 1, i32* null }
} }
define i32 @caller_small_struct_ret() nounwind { define i32 @caller_small_struct_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_small_struct_ret: ; RV32I-FPELIM-LABEL: caller_small_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: call callee_small_struct_ret ; RV32I-FPELIM-NEXT: call callee_small_struct_ret
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_small_struct_ret: ; RV32I-WITHFP-LABEL: caller_small_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: call callee_small_struct_ret ; RV32I-WITHFP-NEXT: call callee_small_struct_ret
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call %struct.small @callee_small_struct_ret() %1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0 %2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1 %3 = extractvalue %struct.small %1, 1
%4 = ptrtoint i32* %3 to i32 %4 = ptrtoint i32* %3 to i32
%5 = add i32 %2, %4 %5 = add i32 %2, %4
ret i32 %5 ret i32 %5
Show All 9 Lines
; RV32I-FPELIM-NEXT: sw zero, 8(a0) ; RV32I-FPELIM-NEXT: sw zero, 8(a0)
; RV32I-FPELIM-NEXT: sw zero, 4(a0) ; RV32I-FPELIM-NEXT: sw zero, 4(a0)
; RV32I-FPELIM-NEXT: sw zero, 0(a0) ; RV32I-FPELIM-NEXT: sw zero, 0(a0)
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalar_ret: ; RV32I-WITHFP-LABEL: callee_large_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a1, 524272 ; RV32I-WITHFP-NEXT: lui a1, 524272
; RV32I-WITHFP-NEXT: sw a1, 12(a0) ; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: sw zero, 8(a0) ; RV32I-WITHFP-NEXT: sw zero, 8(a0)
; RV32I-WITHFP-NEXT: sw zero, 4(a0) ; RV32I-WITHFP-NEXT: sw zero, 4(a0)
; RV32I-WITHFP-NEXT: sw zero, 0(a0) ; RV32I-WITHFP-NEXT: sw zero, 0(a0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret fp128 0xL00000000000000007FFF000000000000 ret fp128 0xL00000000000000007FFF000000000000
} }
define void @caller_large_scalar_ret() nounwind { define void @caller_large_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_large_scalar_ret: ; RV32I-FPELIM-LABEL: caller_large_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv a0, sp ; RV32I-FPELIM-NEXT: mv a0, sp
; RV32I-FPELIM-NEXT: call callee_large_scalar_ret ; RV32I-FPELIM-NEXT: call callee_large_scalar_ret
; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_scalar_ret: ; RV32I-WITHFP-LABEL: caller_large_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32 ; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -32 ; RV32I-WITHFP-NEXT: addi a0, s0, -32
; RV32I-WITHFP-NEXT: call callee_large_scalar_ret ; RV32I-WITHFP-NEXT: call callee_large_scalar_ret
; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call fp128 @callee_large_scalar_ret() %1 = call fp128 @callee_large_scalar_ret()
ret void ret void
} }
; Check return of >2x xlen structs ; Check return of >2x xlen structs
define void @callee_large_struct_ret(%struct.large* noalias sret(%struct.large) %agg.result) nounwind { define void @callee_large_struct_ret(%struct.large* noalias sret(%struct.large) %agg.result) nounwind {
; RV32I-FPELIM-LABEL: callee_large_struct_ret: ; RV32I-FPELIM-LABEL: callee_large_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi a1, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 1
; RV32I-FPELIM-NEXT: sw a1, 0(a0) ; RV32I-FPELIM-NEXT: sw a1, 0(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 4(a0) ; RV32I-FPELIM-NEXT: sw a1, 4(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 3 ; RV32I-FPELIM-NEXT: addi a1, zero, 3
; RV32I-FPELIM-NEXT: sw a1, 8(a0) ; RV32I-FPELIM-NEXT: sw a1, 8(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 4 ; RV32I-FPELIM-NEXT: addi a1, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 12(a0) ; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_struct_ret: ; RV32I-WITHFP-LABEL: callee_large_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a1, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 1
; RV32I-WITHFP-NEXT: sw a1, 0(a0) ; RV32I-WITHFP-NEXT: sw a1, 0(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, 4(a0) ; RV32I-WITHFP-NEXT: sw a1, 4(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 3 ; RV32I-WITHFP-NEXT: addi a1, zero, 3
; RV32I-WITHFP-NEXT: sw a1, 8(a0) ; RV32I-WITHFP-NEXT: sw a1, 8(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 4 ; RV32I-WITHFP-NEXT: addi a1, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 12(a0) ; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0
store i32 1, i32* %a, align 4 store i32 1, i32* %a, align 4
%b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1 %b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1
store i32 2, i32* %b, align 4 store i32 2, i32* %b, align 4
%c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2 %c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2
store i32 3, i32* %c, align 4 store i32 3, i32* %c, align 4
%d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3 %d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3
store i32 4, i32* %d, align 4 store i32 4, i32* %d, align 4
ret void ret void
} }
define i32 @caller_large_struct_ret() nounwind { define i32 @caller_large_struct_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_large_struct_ret: ; RV32I-FPELIM-LABEL: caller_large_struct_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, sp, 8 ; RV32I-FPELIM-NEXT: addi a0, sp, 8
; RV32I-FPELIM-NEXT: call callee_large_struct_ret ; RV32I-FPELIM-NEXT: call callee_large_struct_ret
; RV32I-FPELIM-NEXT: lw a0, 8(sp) ; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw a1, 20(sp) ; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_large_struct_ret: ; RV32I-WITHFP-LABEL: caller_large_struct_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32 ; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: call callee_large_struct_ret ; RV32I-WITHFP-NEXT: call callee_large_struct_ret
; RV32I-WITHFP-NEXT: lw a0, -24(s0) ; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw a1, -12(s0) ; RV32I-WITHFP-NEXT: lw a1, -12(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = alloca %struct.large %1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1) call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
%3 = load i32, i32* %2 %3 = load i32, i32* %2
%4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3
%5 = load i32, i32* %4 %5 = load i32, i32* %4
%6 = add i32 %3, %5 %6 = add i32 %3, %5
ret i32 %6 ret i32 %6
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll

Show All 10 Lines
; ABIs belong in calling-conv-*-common.ll. This file contains tests that will ; ABIs belong in calling-conv-*-common.ll. This file contains tests that will
; have different output across those ABIs. i.e. where some arguments would be ; have different output across those ABIs. i.e. where some arguments would be
; passed according to the floating point ABI. ; passed according to the floating point ABI.
define i32 @callee_float_in_regs(i32 %a, float %b) nounwind { define i32 @callee_float_in_regs(i32 %a, float %b) nounwind {
; RV32I-FPELIM-LABEL: callee_float_in_regs: ; RV32I-FPELIM-LABEL: callee_float_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw s0, 8(sp) ; RV32I-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv s0, a0 ; RV32I-FPELIM-NEXT: mv s0, a0
; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: call __fixsfsi ; RV32I-FPELIM-NEXT: call __fixsfsi@plt
; RV32I-FPELIM-NEXT: add a0, s0, a0 ; RV32I-FPELIM-NEXT: add a0, s0, a0
; RV32I-FPELIM-NEXT: lw s0, 8(sp) ; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_float_in_regs: ; RV32I-WITHFP-LABEL: callee_float_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s1, 4(sp) ; RV32I-WITHFP-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv s1, a0 ; RV32I-WITHFP-NEXT: mv s1, a0
; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: call __fixsfsi ; RV32I-WITHFP-NEXT: call __fixsfsi@plt
; RV32I-WITHFP-NEXT: add a0, s1, a0 ; RV32I-WITHFP-NEXT: add a0, s1, a0
; RV32I-WITHFP-NEXT: lw s1, 4(sp) ; RV32I-WITHFP-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_fptosi = fptosi float %b to i32 %b_fptosi = fptosi float %b to i32
%1 = add i32 %a, %b_fptosi %1 = add i32 %a, %b_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_regs() nounwind { define i32 @caller_float_in_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_float_in_regs: ; RV32I-FPELIM-LABEL: caller_float_in_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: lui a1, 262144 ; RV32I-FPELIM-NEXT: lui a1, 262144
; RV32I-FPELIM-NEXT: call callee_float_in_regs ; RV32I-FPELIM-NEXT: call callee_float_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_float_in_regs: ; RV32I-WITHFP-LABEL: caller_float_in_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: lui a1, 262144 ; RV32I-WITHFP-NEXT: lui a1, 262144
; RV32I-WITHFP-NEXT: call callee_float_in_regs ; RV32I-WITHFP-NEXT: call callee_float_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_float_in_regs(i32 1, float 2.0) %1 = call i32 @callee_float_in_regs(i32 1, float 2.0)
ret i32 %1 ret i32 %1
} }
define i32 @callee_float_on_stack(i64 %a, i64 %b, i64 %c, i64 %d, float %e) nounwind { define i32 @callee_float_on_stack(i64 %a, i64 %b, i64 %c, i64 %d, float %e) nounwind {
; RV32I-FPELIM-LABEL: callee_float_on_stack: ; RV32I-FPELIM-LABEL: callee_float_on_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 0(sp) ; RV32I-FPELIM-NEXT: lw a0, 0(sp)
; RV32I-FPELIM-NEXT: add a0, a6, a0 ; RV32I-FPELIM-NEXT: add a0, a6, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_float_on_stack: ; RV32I-WITHFP-LABEL: callee_float_on_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(s0) ; RV32I-WITHFP-NEXT: lw a0, 0(s0)
; RV32I-WITHFP-NEXT: add a0, a6, a0 ; RV32I-WITHFP-NEXT: add a0, a6, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = trunc i64 %d to i32 %1 = trunc i64 %d to i32
%2 = bitcast float %e to i32 %2 = bitcast float %e to i32
%3 = add i32 %1, %2 %3 = add i32 %1, %2
ret i32 %3 ret i32 %3
} }
define i32 @caller_float_on_stack() nounwind { define i32 @caller_float_on_stack() nounwind {
; RV32I-FPELIM-LABEL: caller_float_on_stack: ; RV32I-FPELIM-LABEL: caller_float_on_stack:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: lui a1, 264704 ; RV32I-FPELIM-NEXT: lui a1, 264704
; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a2, zero, 2 ; RV32I-FPELIM-NEXT: addi a2, zero, 2
; RV32I-FPELIM-NEXT: addi a4, zero, 3 ; RV32I-FPELIM-NEXT: addi a4, zero, 3
; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 0(sp) ; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: mv a3, zero ; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: mv a5, zero ; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: mv a7, zero ; RV32I-FPELIM-NEXT: mv a7, zero
; RV32I-FPELIM-NEXT: call callee_float_on_stack ; RV32I-FPELIM-NEXT: call callee_float_on_stack
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_float_on_stack: ; RV32I-WITHFP-LABEL: caller_float_on_stack:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a1, 264704 ; RV32I-WITHFP-NEXT: lui a1, 264704
; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a2, zero, 2 ; RV32I-WITHFP-NEXT: addi a2, zero, 2
; RV32I-WITHFP-NEXT: addi a4, zero, 3 ; RV32I-WITHFP-NEXT: addi a4, zero, 3
; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 0(sp) ; RV32I-WITHFP-NEXT: sw a1, 0(sp)
; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: mv a3, zero ; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: mv a5, zero ; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: mv a7, zero ; RV32I-WITHFP-NEXT: mv a7, zero
; RV32I-WITHFP-NEXT: call callee_float_on_stack ; RV32I-WITHFP-NEXT: call callee_float_on_stack
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0) %1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0)
ret i32 %1 ret i32 %1
} }
define float @callee_tiny_scalar_ret() nounwind { define float @callee_tiny_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_tiny_scalar_ret: ; RV32I-FPELIM-LABEL: callee_tiny_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a0, 260096 ; RV32I-FPELIM-NEXT: lui a0, 260096
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_tiny_scalar_ret: ; RV32I-WITHFP-LABEL: callee_tiny_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 260096 ; RV32I-WITHFP-NEXT: lui a0, 260096
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
ret float 1.0 ret float 1.0
} }
define i32 @caller_tiny_scalar_ret() nounwind { define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: caller_tiny_scalar_ret: ; RV32I-FPELIM-LABEL: caller_tiny_scalar_ret:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret ; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret
; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: caller_tiny_scalar_ret: ; RV32I-WITHFP-LABEL: caller_tiny_scalar_ret:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret ; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret
; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%1 = call float @callee_tiny_scalar_ret() %1 = call float @callee_tiny_scalar_ret()
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

Show All 15 Lines; RV32-ILP32D-NEXT: ret
%1 = add i32 %a, %b_fptosi %1 = add i32 %a, %b_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_fpr() nounwind { define i32 @caller_double_in_fpr() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_fpr: ; RV32-ILP32D-LABEL: caller_double_in_fpr:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1 ; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: call callee_double_in_fpr ; RV32-ILP32D-NEXT: call callee_double_in_fpr
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_fpr(i32 1, double 2.0) %1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind { define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs: ; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: lw a0, 0(sp) ; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz ; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a0, a1 ; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%f_fptosi = fptosi double %f to i32 %f_fptosi = fptosi double %f to i32
%1 = add i32 %e, %f_fptosi %1 = add i32 %e, %f_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_fpr_exhausted_gprs() nounwind { define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs: ; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: addi a1, zero, 5 ; RV32-ILP32D-NEXT: addi a1, zero, 5
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI3_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1 ; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: addi a2, zero, 2 ; RV32-ILP32D-NEXT: addi a2, zero, 2
; RV32-ILP32D-NEXT: addi a4, zero, 3 ; RV32-ILP32D-NEXT: addi a4, zero, 3
; RV32-ILP32D-NEXT: addi a6, zero, 4 ; RV32-ILP32D-NEXT: addi a6, zero, 4
; RV32-ILP32D-NEXT: sw a1, 0(sp) ; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero ; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero ; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero ; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs ; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_fpr_exhausted_gprs( %1 = call i32 @callee_double_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0) i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
Show All 14 Lines; RV32-ILP32D-NEXT: ret
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_gpr_exhausted_fprs() nounwind { define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs: ; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI5_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI5_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI5_1)(a0) ; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI5_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI5_2)(a0) ; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI5_2)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI5_3)(a0) ; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI5_3)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI5_4)(a0) ; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI5_4)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI5_5)(a0) ; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI5_5)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI5_6)(a0) ; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI5_6)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0) ; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32D-NEXT: lui a1, 262688 ; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: mv a0, zero ; RV32-ILP32D-NEXT: mv a0, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs ; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_gpr_exhausted_fprs( %1 = call i32 @callee_double_in_gpr_exhausted_fprs(
double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
double 7.0, double 8.0, double 9.0) double 7.0, double 8.0, double 9.0)
ret i32 %1 ret i32 %1
} }
Show All 14 Lines; RV32-ILP32D-NEXT: ret
%1 = add i32 %g, %m_fptosi %1 = add i32 %g, %m_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind { define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a1, 262816 ; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI7_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI7_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI7_1)(a0) ; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI7_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI7_2)(a0) ; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI7_2)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3)
Show All 11 Lines
; RV32-ILP32D-NEXT: addi a4, zero, 5 ; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: addi a6, zero, 7 ; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw a1, 0(sp) ; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero ; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero ; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero ; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs( %1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(
i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0, i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0,
double 9.0, double 10.0, double 11.0, double 12.0, double 13.0) double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
ret i32 %1 ret i32 %1
} }
Show All 11 Lines; RV32-ILP32D-NEXT: ret
%1 = add i32 %g_trunc, %m_fptosi %1 = add i32 %g_trunc, %m_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind { define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs: ; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a0, 262816 ; RV32-ILP32D-NEXT: lui a0, 262816
; RV32-ILP32D-NEXT: sw a0, 4(sp) ; RV32-ILP32D-NEXT: sw a0, 4(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI9_1)(a0) ; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI9_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI9_2)(a0) ; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI9_2)(a0)
Show All 12 Lines
; RV32-ILP32D-NEXT: addi a4, zero, 5 ; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: addi a6, zero, 7 ; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw zero, 0(sp) ; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero ; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero ; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero ; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero ; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs ; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs( %1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(
i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0, i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,
double 9.0, double 10.0, double 11.0, double 12.0, double 13.0) double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
ret i32 %1 ret i32 %1
} }
define double @callee_double_ret() nounwind { define double @callee_double_ret() nounwind {
; RV32-ILP32D-LABEL: callee_double_ret: ; RV32-ILP32D-LABEL: callee_double_ret:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI10_0) ; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI10_0)(a0) ; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI10_0)(a0)
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
ret double 1.0 ret double 1.0
} }
define i32 @caller_double_ret() nounwind { define i32 @caller_double_ret() nounwind {
; RV32-ILP32D-LABEL: caller_double_ret: ; RV32-ILP32D-LABEL: caller_double_ret:
; RV32-ILP32D: # %bb.0: ; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16 ; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) ; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: call callee_double_ret ; RV32-ILP32D-NEXT: call callee_double_ret
; RV32-ILP32D-NEXT: fsd fa0, 0(sp) ; RV32-ILP32D-NEXT: fsd fa0, 0(sp)
; RV32-ILP32D-NEXT: lw a0, 0(sp) ; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: lw ra, 12(sp) ; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16 ; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret ; RV32-ILP32D-NEXT: ret
%1 = call double @callee_double_ret() %1 = call double @callee_double_ret()
%2 = bitcast double %1 to i64 %2 = bitcast double %1 to i64
%3 = trunc i64 %2 to i32 %3 = trunc i64 %2 to i32
ret i32 %3 ret i32 %3
} }

llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll

Show All 18 Lines; RV32-ILP32FD-NEXT: ret
%1 = add i32 %a, %b_fptosi %1 = add i32 %a, %b_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_fpr() nounwind { define i32 @caller_float_in_fpr() nounwind {
; RV32-ILP32FD-LABEL: caller_float_in_fpr: ; RV32-ILP32FD-LABEL: caller_float_in_fpr:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI1_0)(a0) ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1 ; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: call callee_float_in_fpr ; RV32-ILP32FD-NEXT: call callee_float_in_fpr
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_in_fpr(i32 1, float 2.0) %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind { define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs: ; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: lw a0, 0(sp) ; RV32-ILP32FD-NEXT: lw a0, 0(sp)
; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1 ; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%f_fptosi = fptosi float %f to i32 %f_fptosi = fptosi float %f to i32
%1 = add i32 %e, %f_fptosi %1 = add i32 %e, %f_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_fpr_exhausted_gprs() nounwind { define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs: ; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: addi a1, zero, 5 ; RV32-ILP32FD-NEXT: addi a1, zero, 5
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI3_0)(a0) ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1 ; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: addi a2, zero, 2 ; RV32-ILP32FD-NEXT: addi a2, zero, 2
; RV32-ILP32FD-NEXT: addi a4, zero, 3 ; RV32-ILP32FD-NEXT: addi a4, zero, 3
; RV32-ILP32FD-NEXT: addi a6, zero, 4 ; RV32-ILP32FD-NEXT: addi a6, zero, 4
; RV32-ILP32FD-NEXT: sw a1, 0(sp) ; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero ; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero ; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero ; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero ; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs ; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_in_fpr_exhausted_gprs( %1 = call i32 @callee_float_in_fpr_exhausted_gprs(
i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0) i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
ret i32 %1 ret i32 %1
} }
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
Show All 10 Lines; RV32-ILP32FD-NEXT: ret
%1 = add i32 %h_fptosi, %i_fptosi %1 = add i32 %h_fptosi, %i_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_in_gpr_exhausted_fprs() nounwind { define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs: ; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI5_0)(a0) ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI5_0)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_1) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32FD-NEXT: flw fa1, %lo(.LCPI5_1)(a0) ; RV32-ILP32FD-NEXT: flw fa1, %lo(.LCPI5_1)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_2) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32FD-NEXT: flw fa2, %lo(.LCPI5_2)(a0) ; RV32-ILP32FD-NEXT: flw fa2, %lo(.LCPI5_2)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_3) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32FD-NEXT: flw fa3, %lo(.LCPI5_3)(a0) ; RV32-ILP32FD-NEXT: flw fa3, %lo(.LCPI5_3)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_4) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32FD-NEXT: flw fa4, %lo(.LCPI5_4)(a0) ; RV32-ILP32FD-NEXT: flw fa4, %lo(.LCPI5_4)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_5) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32FD-NEXT: flw fa5, %lo(.LCPI5_5)(a0) ; RV32-ILP32FD-NEXT: flw fa5, %lo(.LCPI5_5)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32FD-NEXT: flw fa6, %lo(.LCPI5_6)(a0) ; RV32-ILP32FD-NEXT: flw fa6, %lo(.LCPI5_6)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32FD-NEXT: flw fa7, %lo(.LCPI5_7)(a0) ; RV32-ILP32FD-NEXT: flw fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32FD-NEXT: lui a0, 266496 ; RV32-ILP32FD-NEXT: lui a0, 266496
; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs ; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_in_gpr_exhausted_fprs( %1 = call i32 @callee_float_in_gpr_exhausted_fprs(
float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,
float 7.0, float 8.0, float 9.0) float 7.0, float 8.0, float 9.0)
ret i32 %1 ret i32 %1
} }
Show All 10 Lines; RV32-ILP32FD-NEXT: ret
%1 = add i32 %g_trunc, %m_fptosi %1 = add i32 %g_trunc, %m_fptosi
ret i32 %1 ret i32 %1
} }
define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind { define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs: ; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: lui a1, 267520 ; RV32-ILP32FD-NEXT: lui a1, 267520
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI7_0)(a0) ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI7_0)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_1) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32FD-NEXT: flw fa1, %lo(.LCPI7_1)(a0) ; RV32-ILP32FD-NEXT: flw fa1, %lo(.LCPI7_1)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_2) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32FD-NEXT: flw fa2, %lo(.LCPI7_2)(a0) ; RV32-ILP32FD-NEXT: flw fa2, %lo(.LCPI7_2)(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_3) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_3)
Show All 11 Lines
; RV32-ILP32FD-NEXT: addi a4, zero, 5 ; RV32-ILP32FD-NEXT: addi a4, zero, 5
; RV32-ILP32FD-NEXT: addi a6, zero, 7 ; RV32-ILP32FD-NEXT: addi a6, zero, 7
; RV32-ILP32FD-NEXT: sw a1, 0(sp) ; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero ; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero ; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero ; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero ; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs ; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs( %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0, i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
float 9.0, float 10.0, float 11.0, float 12.0, float 13.0) float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
ret i32 %1 ret i32 %1
} }
define float @callee_float_ret() nounwind { define float @callee_float_ret() nounwind {
; RV32-ILP32FD-LABEL: callee_float_ret: ; RV32-ILP32FD-LABEL: callee_float_ret:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI8_0) ; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI8_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI8_0)(a0) ; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI8_0)(a0)
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
ret float 1.0 ret float 1.0
} }
define i32 @caller_float_ret() nounwind { define i32 @caller_float_ret() nounwind {
; RV32-ILP32FD-LABEL: caller_float_ret: ; RV32-ILP32FD-LABEL: caller_float_ret:
; RV32-ILP32FD: # %bb.0: ; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: call callee_float_ret ; RV32-ILP32FD-NEXT: call callee_float_ret
; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0 ; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0
; RV32-ILP32FD-NEXT: lw ra, 12(sp) ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret ; RV32-ILP32FD-NEXT: ret
%1 = call float @callee_float_ret() %1 = call float @callee_float_ret()
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
; RUN: -verify-machineinstrs < %s \ ; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; This file contains tests that should have identical output for the lp64 and ; This file contains tests that should have identical output for the lp64 and
; lp64f ABIs. It doesn't check codegen when frame pointer elimination is ; lp64f ABIs. It doesn't check codegen when frame pointer elimination is
; disabled, as there is sufficient coverage for this case in other files. ; disabled, as there is sufficient coverage for this case in other files.
define i64 @callee_double_in_regs(i64 %a, double %b) nounwind { define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
; RV64I-LABEL: callee_double_in_regs: ; RV64I-LABEL: callee_double_in_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: call __fixdfdi ; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: add a0, s0, a0 ; RV64I-NEXT: add a0, s0, a0
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_fptosi = fptosi double %b to i64 %b_fptosi = fptosi double %b to i64
%1 = add i64 %a, %b_fptosi %1 = add i64 %a, %b_fptosi
ret i64 %1 ret i64 %1
} }
define i64 @caller_double_in_regs() nounwind { define i64 @caller_double_in_regs() nounwind {
; RV64I-LABEL: caller_double_in_regs: ; RV64I-LABEL: caller_double_in_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: slli a1, a0, 62 ; RV64I-NEXT: slli a1, a0, 62
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: call callee_double_in_regs ; RV64I-NEXT: call callee_double_in_regs
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_double_in_regs(i64 1, double 2.0) %1 = call i64 @callee_double_in_regs(i64 1, double 2.0)
ret i64 %1 ret i64 %1
} }
define double @callee_double_ret() nounwind { define double @callee_double_ret() nounwind {
; RV64I-LABEL: callee_double_ret: ; RV64I-LABEL: callee_double_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1023 ; RV64I-NEXT: addi a0, zero, 1023
; RV64I-NEXT: slli a0, a0, 52 ; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret double 1.0 ret double 1.0
} }
define i64 @caller_double_ret() nounwind { define i64 @caller_double_ret() nounwind {
; RV64I-LABEL: caller_double_ret: ; RV64I-LABEL: caller_double_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_double_ret ; RV64I-NEXT: call callee_double_ret
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call double @callee_double_ret() %1 = call double @callee_double_ret()
%2 = bitcast double %1 to i64 %2 = bitcast double %1 to i64
ret i64 %2 ret i64 %2
} }

llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

Show All 25 Lines; RV64I-NEXT: ret
%1 = add i64 %a, %b_trunc %1 = add i64 %a, %b_trunc
ret i64 %1 ret i64 %1
} }
define i64 @caller_i128_in_regs() nounwind { define i64 @caller_i128_in_regs() nounwind {
; RV64I-LABEL: caller_i128_in_regs: ; RV64I-LABEL: caller_i128_in_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call callee_i128_in_regs ; RV64I-NEXT: call callee_i128_in_regs
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_i128_in_regs(i64 1, i128 2) %1 = call i64 @callee_i128_in_regs(i64 1, i128 2)
ret i64 %1 ret i64 %1
} }
; Check that the stack is used once the GPRs are exhausted ; Check that the stack is used once the GPRs are exhausted
Show All 29 Lines; RV64I-NEXT: ret
%8 = add i32 %7, %h %8 = add i32 %7, %h
ret i32 %8 ret i32 %8
} }
define i32 @caller_many_scalars() nounwind { define i32 @caller_many_scalars() nounwind {
; RV64I-LABEL: caller_many_scalars: ; RV64I-LABEL: caller_many_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 8 ; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a5, zero, 5 ; RV64I-NEXT: addi a5, zero, 5
; RV64I-NEXT: addi a6, zero, 6 ; RV64I-NEXT: addi a6, zero, 6
; RV64I-NEXT: addi a7, zero, 7 ; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd zero, 0(sp) ; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call callee_many_scalars ; RV64I-NEXT: call callee_many_scalars
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8) %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i128 4, i32 5, i32 6, i128 7, i32 8)
ret i32 %1 ret i32 %1
} }
; Check that i256 is passed indirectly. ; Check that i256 is passed indirectly.
Show All 21 Lines; RV64I-NEXT: ret
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars() nounwind { define i64 @caller_large_scalars() nounwind {
; RV64I-LABEL: caller_large_scalars: ; RV64I-LABEL: caller_large_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp) ; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd zero, 16(sp) ; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: addi a0, zero, 2 ; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 0(sp) ; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: sd zero, 48(sp) ; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: addi a0, sp, 32 ; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 32(sp) ; RV64I-NEXT: sd a2, 32(sp)
; RV64I-NEXT: call callee_large_scalars ; RV64I-NEXT: call callee_large_scalars
; RV64I-NEXT: ld ra, 72(sp) ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_large_scalars(i256 1, i256 2) %1 = call i64 @callee_large_scalars(i256 1, i256 2)
ret i64 %1 ret i64 %1
} }
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
Show All 24 Lines; RV64I-NEXT: ret
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars_exhausted_regs() nounwind { define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-LABEL: caller_large_scalars_exhausted_regs: ; RV64I-LABEL: caller_large_scalars_exhausted_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 16 ; RV64I-NEXT: addi a0, sp, 16
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 9 ; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 0(sp) ; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 32(sp) ; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 10 ; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 72(sp) ; RV64I-NEXT: sd zero, 72(sp)
; RV64I-NEXT: sd zero, 64(sp) ; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: addi t0, zero, 8 ; RV64I-NEXT: addi t0, zero, 8
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6 ; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a6, zero, 7 ; RV64I-NEXT: addi a6, zero, 7
; RV64I-NEXT: addi a7, sp, 48 ; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd t0, 48(sp) ; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs ; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_large_scalars_exhausted_regs( %1 = call i64 @callee_large_scalars_exhausted_regs(
i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
i256 10) i256 10)
ret i64 %1 ret i64 %1
} }
; Ensure that libcalls generated in the middle-end obey the calling convention ; Ensure that libcalls generated in the middle-end obey the calling convention
define i64 @caller_mixed_scalar_libcalls(i64 %a) nounwind { define i64 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
; RV64I-LABEL: caller_mixed_scalar_libcalls: ; RV64I-LABEL: caller_mixed_scalar_libcalls:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floatditf ; RV64I-NEXT: call __floatditf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = sitofp i64 %a to fp128 %1 = sitofp i64 %a to fp128
%2 = bitcast fp128 %1 to i128 %2 = bitcast fp128 %1 to i128
%3 = trunc i128 %2 to i64 %3 = trunc i128 %2 to i64
ret i64 %3 ret i64 %3
} }
Show All 13 Lines; RV64I-NEXT: ret
%4 = zext i1 %3 to i64 %4 = zext i1 %3 to i64
ret i64 %4 ret i64 %4
} }
define i64 @caller_small_coerced_struct() nounwind { define i64 @caller_small_coerced_struct() nounwind {
; RV64I-LABEL: caller_small_coerced_struct: ; RV64I-LABEL: caller_small_coerced_struct:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call callee_small_coerced_struct ; RV64I-NEXT: call callee_small_coerced_struct
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_small_coerced_struct([2 x i64] [i64 1, i64 2]) %1 = call i64 @callee_small_coerced_struct([2 x i64] [i64 1, i64 2])
ret i64 %1 ret i64 %1
} }
; Check large struct arguments, which are passed byval ; Check large struct arguments, which are passed byval
Show All 13 Lines; RV64I-NEXT: ret
%5 = add i64 %3, %4 %5 = add i64 %3, %4
ret i64 %5 ret i64 %5
} }
define i64 @caller_large_struct() nounwind { define i64 @caller_large_struct() nounwind {
; RV64I-LABEL: caller_large_struct: ; RV64I-LABEL: caller_large_struct:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp) ; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sd a1, 48(sp) ; RV64I-NEXT: sd a1, 48(sp)
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: sd a2, 56(sp) ; RV64I-NEXT: sd a2, 56(sp)
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: sd a3, 64(sp) ; RV64I-NEXT: sd a3, 64(sp)
; RV64I-NEXT: sd a0, 8(sp) ; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: sd a1, 16(sp) ; RV64I-NEXT: sd a1, 16(sp)
; RV64I-NEXT: sd a2, 24(sp) ; RV64I-NEXT: sd a2, 24(sp)
; RV64I-NEXT: sd a3, 32(sp) ; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: addi a0, sp, 8 ; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct ; RV64I-NEXT: call callee_large_struct
; RV64I-NEXT: ld ra, 72(sp) ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%ls = alloca %struct.large, align 8 %ls = alloca %struct.large, align 8
%1 = bitcast %struct.large* %ls to i8* %1 = bitcast %struct.large* %ls to i8*
%a = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 0 %a = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 0
store i64 1, i64* %a store i64 1, i64* %a
%b = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 1 %b = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 1
store i64 2, i64* %b store i64 2, i64* %b
Show All 34 Lines
} }
define void @caller_aligned_stack() nounwind { define void @caller_aligned_stack() nounwind {
; The i128 should be 16-byte aligned on the stack, but the two-element array ; The i128 should be 16-byte aligned on the stack, but the two-element array
; should only be 8-byte aligned ; should only be 8-byte aligned
; RV64I-LABEL: caller_aligned_stack: ; RV64I-LABEL: caller_aligned_stack:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 12 ; RV64I-NEXT: addi a0, zero, 12
; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: addi a0, zero, 11 ; RV64I-NEXT: addi a0, zero, 11
; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a0, zero, 10 ; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 9 ; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: addi a6, zero, 8 ; RV64I-NEXT: addi a6, zero, 8
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6 ; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a7, zero, 7 ; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd a6, 0(sp) ; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: mv a6, zero ; RV64I-NEXT: mv a6, zero
; RV64I-NEXT: call callee_aligned_stack ; RV64I-NEXT: call callee_aligned_stack
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5, %1 = call i64 @callee_aligned_stack(i64 1, i64 2, i64 3, i64 4, i64 5,
i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12]) i128 6, i64 7, i64 8, i128 9, i64 10, [2 x i64] [i64 11, i64 12])
ret void ret void
} }
; Check return of 2x xlen scalars ; Check return of 2x xlen scalars
define i128 @callee_small_scalar_ret() nounwind { define i128 @callee_small_scalar_ret() nounwind {
; RV64I-LABEL: callee_small_scalar_ret: ; RV64I-LABEL: callee_small_scalar_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i128 -1 ret i128 -1
} }
define i64 @caller_small_scalar_ret() nounwind { define i64 @caller_small_scalar_ret() nounwind {
; RV64I-LABEL: caller_small_scalar_ret: ; RV64I-LABEL: caller_small_scalar_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_small_scalar_ret ; RV64I-NEXT: call callee_small_scalar_ret
; RV64I-NEXT: not a1, a1 ; RV64I-NEXT: not a1, a1
; RV64I-NEXT: xori a0, a0, -2 ; RV64I-NEXT: xori a0, a0, -2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i128 @callee_small_scalar_ret() %1 = call i128 @callee_small_scalar_ret()
%2 = icmp eq i128 -2, %1 %2 = icmp eq i128 -2, %1
%3 = zext i1 %2 to i64 %3 = zext i1 %2 to i64
ret i64 %3 ret i64 %3
} }
; Check return of 2x xlen structs ; Check return of 2x xlen structs
define %struct.small @callee_small_struct_ret() nounwind { define %struct.small @callee_small_struct_ret() nounwind {
; RV64I-LABEL: callee_small_struct_ret: ; RV64I-LABEL: callee_small_struct_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1 ; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret %struct.small { i64 1, i64* null } ret %struct.small { i64 1, i64* null }
} }
define i64 @caller_small_struct_ret() nounwind { define i64 @caller_small_struct_ret() nounwind {
; RV64I-LABEL: caller_small_struct_ret: ; RV64I-LABEL: caller_small_struct_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_small_struct_ret ; RV64I-NEXT: call callee_small_struct_ret
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call %struct.small @callee_small_struct_ret() %1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0 %2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1 %3 = extractvalue %struct.small %1, 1
%4 = ptrtoint i64* %3 to i64 %4 = ptrtoint i64* %3 to i64
%5 = add i64 %2, %4 %5 = add i64 %2, %4
ret i64 %5 ret i64 %5
Show All 14 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
ret i256 -123456789 ret i256 -123456789
} }
define void @caller_large_scalar_ret() nounwind { define void @caller_large_scalar_ret() nounwind {
; RV64I-LABEL: caller_large_scalar_ret: ; RV64I-LABEL: caller_large_scalar_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee_large_scalar_ret ; RV64I-NEXT: call callee_large_scalar_ret
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i256 @callee_large_scalar_ret() %1 = call i256 @callee_large_scalar_ret()
ret void ret void
} }
; Check return of >2x xlen structs ; Check return of >2x xlen structs
Show All 23 Lines; RV64I-NEXT: ret
store i64 4, i64* %d, align 4 store i64 4, i64* %d, align 4
ret void ret void
} }
define i64 @caller_large_struct_ret() nounwind { define i64 @caller_large_struct_ret() nounwind {
; RV64I-LABEL: caller_large_struct_ret: ; RV64I-LABEL: caller_large_struct_ret:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 8 ; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct_ret ; RV64I-NEXT: call callee_large_struct_ret
; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 32(sp) ; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca %struct.large %1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1) call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0
%3 = load i64, i64* %2 %3 = load i64, i64* %2
%4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3
%5 = load i64, i64* %4 %5 = load i64, i64* %4
%6 = add i64 %3, %5 %6 = add i64 %3, %5
ret i64 %6 ret i64 %6
} }

llvm/test/CodeGen/RISCV/calling-conv-lp64.ll

Show All 12 Lines
; passed according to the floating point ABI. ; passed according to the floating point ABI.
; TODO: softened float values can be passed anyext. ; TODO: softened float values can be passed anyext.
define i64 @callee_float_in_regs(i64 %a, float %b) nounwind { define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
; RV64I-FPELIM-LABEL: callee_float_in_regs: ; RV64I-FPELIM-LABEL: callee_float_in_regs:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: sd s0, 0(sp) ; RV64I-FPELIM-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: mv s0, a0 ; RV64I-FPELIM-NEXT: mv s0, a0
; RV64I-FPELIM-NEXT: mv a0, a1 ; RV64I-FPELIM-NEXT: mv a0, a1
; RV64I-FPELIM-NEXT: call __fixsfdi ; RV64I-FPELIM-NEXT: call __fixsfdi@plt
; RV64I-FPELIM-NEXT: add a0, s0, a0 ; RV64I-FPELIM-NEXT: add a0, s0, a0
; RV64I-FPELIM-NEXT: ld s0, 0(sp) ; RV64I-FPELIM-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: ld ra, 8(sp) ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: callee_float_in_regs: ; RV64I-WITHFP-LABEL: callee_float_in_regs:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -32 ; RV64I-WITHFP-NEXT: addi sp, sp, -32
; RV64I-WITHFP-NEXT: sd ra, 24(sp) ; RV64I-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 16(sp) ; RV64I-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s1, 8(sp) ; RV64I-WITHFP-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 32 ; RV64I-WITHFP-NEXT: addi s0, sp, 32
; RV64I-WITHFP-NEXT: mv s1, a0 ; RV64I-WITHFP-NEXT: mv s1, a0
; RV64I-WITHFP-NEXT: mv a0, a1 ; RV64I-WITHFP-NEXT: mv a0, a1
; RV64I-WITHFP-NEXT: call __fixsfdi ; RV64I-WITHFP-NEXT: call __fixsfdi@plt
; RV64I-WITHFP-NEXT: add a0, s1, a0 ; RV64I-WITHFP-NEXT: add a0, s1, a0
; RV64I-WITHFP-NEXT: ld s1, 8(sp) ; RV64I-WITHFP-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld s0, 16(sp) ; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 24(sp) ; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 32 ; RV64I-WITHFP-NEXT: addi sp, sp, 32
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%b_fptosi = fptosi float %b to i64 %b_fptosi = fptosi float %b to i64
%1 = add i64 %a, %b_fptosi %1 = add i64 %a, %b_fptosi
ret i64 %1 ret i64 %1
} }
define i64 @caller_float_in_regs() nounwind { define i64 @caller_float_in_regs() nounwind {
; RV64I-FPELIM-LABEL: caller_float_in_regs: ; RV64I-FPELIM-LABEL: caller_float_in_regs:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: addi a0, zero, 1 ; RV64I-FPELIM-NEXT: addi a0, zero, 1
; RV64I-FPELIM-NEXT: lui a1, 262144 ; RV64I-FPELIM-NEXT: lui a1, 262144
; RV64I-FPELIM-NEXT: call callee_float_in_regs ; RV64I-FPELIM-NEXT: call callee_float_in_regs
; RV64I-FPELIM-NEXT: ld ra, 8(sp) ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: caller_float_in_regs: ; RV64I-WITHFP-LABEL: caller_float_in_regs:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -16 ; RV64I-WITHFP-NEXT: addi sp, sp, -16
; RV64I-WITHFP-NEXT: sd ra, 8(sp) ; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) ; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16 ; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: addi a0, zero, 1 ; RV64I-WITHFP-NEXT: addi a0, zero, 1
; RV64I-WITHFP-NEXT: lui a1, 262144 ; RV64I-WITHFP-NEXT: lui a1, 262144
; RV64I-WITHFP-NEXT: call callee_float_in_regs ; RV64I-WITHFP-NEXT: call callee_float_in_regs
; RV64I-WITHFP-NEXT: ld s0, 0(sp) ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16 ; RV64I-WITHFP-NEXT: addi sp, sp, 16
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%1 = call i64 @callee_float_in_regs(i64 1, float 2.0) %1 = call i64 @callee_float_in_regs(i64 1, float 2.0)
ret i64 %1 ret i64 %1
} }
define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind { define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind {
; RV64I-FPELIM-LABEL: callee_float_on_stack: ; RV64I-FPELIM-LABEL: callee_float_on_stack:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: lw a0, 0(sp) ; RV64I-FPELIM-NEXT: lw a0, 0(sp)
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: callee_float_on_stack: ; RV64I-WITHFP-LABEL: callee_float_on_stack:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -16 ; RV64I-WITHFP-NEXT: addi sp, sp, -16
; RV64I-WITHFP-NEXT: sd ra, 8(sp) ; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) ; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16 ; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: lw a0, 0(s0) ; RV64I-WITHFP-NEXT: lw a0, 0(s0)
; RV64I-WITHFP-NEXT: ld s0, 0(sp) ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16 ; RV64I-WITHFP-NEXT: addi sp, sp, 16
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%1 = trunc i128 %d to i64 %1 = trunc i128 %d to i64
%2 = bitcast float %e to i32 %2 = bitcast float %e to i32
%3 = sext i32 %2 to i64 %3 = sext i32 %2 to i64
%4 = add i64 %1, %3 %4 = add i64 %1, %3
ret i64 %3 ret i64 %3
} }
define i64 @caller_float_on_stack() nounwind { define i64 @caller_float_on_stack() nounwind {
; RV64I-FPELIM-LABEL: caller_float_on_stack: ; RV64I-FPELIM-LABEL: caller_float_on_stack:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: lui a1, 264704 ; RV64I-FPELIM-NEXT: lui a1, 264704
; RV64I-FPELIM-NEXT: addi a0, zero, 1 ; RV64I-FPELIM-NEXT: addi a0, zero, 1
; RV64I-FPELIM-NEXT: addi a2, zero, 2 ; RV64I-FPELIM-NEXT: addi a2, zero, 2
; RV64I-FPELIM-NEXT: addi a4, zero, 3 ; RV64I-FPELIM-NEXT: addi a4, zero, 3
; RV64I-FPELIM-NEXT: addi a6, zero, 4 ; RV64I-FPELIM-NEXT: addi a6, zero, 4
; RV64I-FPELIM-NEXT: sd a1, 0(sp) ; RV64I-FPELIM-NEXT: sd a1, 0(sp)
; RV64I-FPELIM-NEXT: mv a1, zero ; RV64I-FPELIM-NEXT: mv a1, zero
; RV64I-FPELIM-NEXT: mv a3, zero ; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: mv a5, zero ; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: mv a7, zero ; RV64I-FPELIM-NEXT: mv a7, zero
; RV64I-FPELIM-NEXT: call callee_float_on_stack ; RV64I-FPELIM-NEXT: call callee_float_on_stack
; RV64I-FPELIM-NEXT: ld ra, 8(sp) ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: caller_float_on_stack: ; RV64I-WITHFP-LABEL: caller_float_on_stack:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -32 ; RV64I-WITHFP-NEXT: addi sp, sp, -32
; RV64I-WITHFP-NEXT: sd ra, 24(sp) ; RV64I-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 16(sp) ; RV64I-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 32 ; RV64I-WITHFP-NEXT: addi s0, sp, 32
; RV64I-WITHFP-NEXT: lui a1, 264704 ; RV64I-WITHFP-NEXT: lui a1, 264704
; RV64I-WITHFP-NEXT: addi a0, zero, 1 ; RV64I-WITHFP-NEXT: addi a0, zero, 1
; RV64I-WITHFP-NEXT: addi a2, zero, 2 ; RV64I-WITHFP-NEXT: addi a2, zero, 2
; RV64I-WITHFP-NEXT: addi a4, zero, 3 ; RV64I-WITHFP-NEXT: addi a4, zero, 3
; RV64I-WITHFP-NEXT: addi a6, zero, 4 ; RV64I-WITHFP-NEXT: addi a6, zero, 4
; RV64I-WITHFP-NEXT: sd a1, 0(sp) ; RV64I-WITHFP-NEXT: sd a1, 0(sp)
; RV64I-WITHFP-NEXT: mv a1, zero ; RV64I-WITHFP-NEXT: mv a1, zero
; RV64I-WITHFP-NEXT: mv a3, zero ; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: mv a5, zero ; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: mv a7, zero ; RV64I-WITHFP-NEXT: mv a7, zero
; RV64I-WITHFP-NEXT: call callee_float_on_stack ; RV64I-WITHFP-NEXT: call callee_float_on_stack
; RV64I-WITHFP-NEXT: ld s0, 16(sp) ; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 24(sp) ; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 32 ; RV64I-WITHFP-NEXT: addi sp, sp, 32
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0) %1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
ret i64 %1 ret i64 %1
} }
define float @callee_tiny_scalar_ret() nounwind { define float @callee_tiny_scalar_ret() nounwind {
; RV64I-FPELIM-LABEL: callee_tiny_scalar_ret: ; RV64I-FPELIM-LABEL: callee_tiny_scalar_ret:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: lui a0, 260096 ; RV64I-FPELIM-NEXT: lui a0, 260096
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: callee_tiny_scalar_ret: ; RV64I-WITHFP-LABEL: callee_tiny_scalar_ret:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -16 ; RV64I-WITHFP-NEXT: addi sp, sp, -16
; RV64I-WITHFP-NEXT: sd ra, 8(sp) ; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) ; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16 ; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: lui a0, 260096 ; RV64I-WITHFP-NEXT: lui a0, 260096
; RV64I-WITHFP-NEXT: ld s0, 0(sp) ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16 ; RV64I-WITHFP-NEXT: addi sp, sp, 16
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
ret float 1.0 ret float 1.0
} }
; The sign extension of the float return is necessary, as softened floats are ; The sign extension of the float return is necessary, as softened floats are
; passed anyext. ; passed anyext.
define i64 @caller_tiny_scalar_ret() nounwind { define i64 @caller_tiny_scalar_ret() nounwind {
; RV64I-FPELIM-LABEL: caller_tiny_scalar_ret: ; RV64I-FPELIM-LABEL: caller_tiny_scalar_ret:
; RV64I-FPELIM: # %bb.0: ; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16 ; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) ; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret ; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret
; RV64I-FPELIM-NEXT: sext.w a0, a0 ; RV64I-FPELIM-NEXT: sext.w a0, a0
; RV64I-FPELIM-NEXT: ld ra, 8(sp) ; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16 ; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret ; RV64I-FPELIM-NEXT: ret
; ;
; RV64I-WITHFP-LABEL: caller_tiny_scalar_ret: ; RV64I-WITHFP-LABEL: caller_tiny_scalar_ret:
; RV64I-WITHFP: # %bb.0: ; RV64I-WITHFP: # %bb.0:
; RV64I-WITHFP-NEXT: addi sp, sp, -16 ; RV64I-WITHFP-NEXT: addi sp, sp, -16
; RV64I-WITHFP-NEXT: sd ra, 8(sp) ; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) ; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16 ; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret ; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret
; RV64I-WITHFP-NEXT: sext.w a0, a0 ; RV64I-WITHFP-NEXT: sext.w a0, a0
; RV64I-WITHFP-NEXT: ld s0, 0(sp) ; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) ; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16 ; RV64I-WITHFP-NEXT: addi sp, sp, 16
; RV64I-WITHFP-NEXT: ret ; RV64I-WITHFP-NEXT: ret
%1 = call float @callee_tiny_scalar_ret() %1 = call float @callee_tiny_scalar_ret()
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
%3 = sext i32 %2 to i64 %3 = sext i32 %2 to i64
ret i64 %3 ret i64 %3
} }

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

Show All 25 Lines; RV32IF-NEXT: ret
%1 = fadd float %e, %f %1 = fadd float %e, %f
ret float %1 ret float %1
} }
define float @caller_onstack_f32_noop(float %a) nounwind { define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-LABEL: caller_onstack_f32_noop: ; RV32IF-LABEL: caller_onstack_f32_noop:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw a0, 4(sp) ; RV32IF-NEXT: sw a0, 4(sp)
; RV32IF-NEXT: lui a1, 264704 ; RV32IF-NEXT: lui a1, 264704
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: addi a2, zero, 2 ; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: addi a4, zero, 3 ; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: addi a6, zero, 4 ; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: sw a1, 0(sp) ; RV32IF-NEXT: sw a1, 0(sp)
; RV32IF-NEXT: mv a1, zero ; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero ; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero ; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero ; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a) %1 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float 5.0, float %a)
ret float %1 ret float %1
} }
define float @caller_onstack_f32_fadd(float %a, float %b) nounwind { define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-LABEL: caller_onstack_f32_fadd: ; RV32IF-LABEL: caller_onstack_f32_fadd:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft2, ft1, ft0 ; RV32IF-NEXT: fadd.s ft2, ft1, ft0
; RV32IF-NEXT: fsub.s ft0, ft0, ft1 ; RV32IF-NEXT: fsub.s ft0, ft0, ft1
; RV32IF-NEXT: fsw ft0, 4(sp) ; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: addi a2, zero, 2 ; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: addi a4, zero, 3 ; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: addi a6, zero, 4 ; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: fsw ft2, 0(sp) ; RV32IF-NEXT: fsw ft2, 0(sp)
; RV32IF-NEXT: mv a1, zero ; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero ; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero ; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero ; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop ; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = fsub float %b, %a %2 = fsub float %b, %a
%3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2) %3 = call float @onstack_f32_noop(i64 1, i64 2, i64 3, i64 4, float %1, float %2)
ret float %3 ret float %3
} }

llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll

Show All 9 Lines
} }
declare void @receive_uint8(i8 zeroext) declare void @receive_uint8(i8 zeroext)
define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind { define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind {
; RV32I-LABEL: pass_uint8_as_uint8: ; RV32I-LABEL: pass_uint8_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
call void @receive_uint8(i8 zeroext %a) call void @receive_uint8(i8 zeroext %a)
ret void ret void
} }
declare zeroext i8 @return_uint8() declare zeroext i8 @return_uint8()
define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind { define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
; RV32I-LABEL: ret_callresult_uint8_as_uint8: ; RV32I-LABEL: ret_callresult_uint8_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call zeroext i8 @return_uint8() %1 = call zeroext i8 @return_uint8()
ret i8 %1 ret i8 %1
} }
define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind { define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_sint8_ret: ; RV32I-LABEL: uint8_arg_to_sint8_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: ret ; RV32I-NEXT: ret
ret i8 %a ret i8 %a
} }
declare void @receive_sint8(i8 signext) declare void @receive_sint8(i8 signext)
define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind { define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind {
; RV32I-LABEL: pass_uint8_as_sint8: ; RV32I-LABEL: pass_uint8_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
call void @receive_sint8(i8 signext %a) call void @receive_sint8(i8 signext %a)
ret void ret void
} }
define signext i8 @ret_callresult_uint8_as_sint8() nounwind { define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
; RV32I-LABEL: ret_callresult_uint8_as_sint8: ; RV32I-LABEL: ret_callresult_uint8_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call zeroext i8 @return_uint8() %1 = call zeroext i8 @return_uint8()
ret i8 %1 ret i8 %1
} }
define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind { define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_anyint32_ret: ; RV32I-LABEL: uint8_arg_to_anyint32_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = zext i8 %a to i32 %1 = zext i8 %a to i32
ret i32 %1 ret i32 %1
} }
declare void @receive_anyint32(i32 signext) declare void @receive_anyint32(i32 signext)
define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind { define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind {
; RV32I-LABEL: pass_uint8_as_anyint32: ; RV32I-LABEL: pass_uint8_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = zext i8 %a to i32 %1 = zext i8 %a to i32
call void @receive_anyint32(i32 signext %1) call void @receive_anyint32(i32 signext %1)
ret void ret void
} }
define signext i32 @ret_callresult_uint8_as_anyint32() nounwind { define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
; RV32I-LABEL: ret_callresult_uint8_as_anyint32: ; RV32I-LABEL: ret_callresult_uint8_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call zeroext i8 @return_uint8() %1 = call zeroext i8 @return_uint8()
%2 = zext i8 %1 to i32 %2 = zext i8 %1 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind { define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_uint8_ret: ; RV32I-LABEL: sint8_arg_to_uint8_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: ret ; RV32I-NEXT: ret
ret i8 %a ret i8 %a
} }
define void @pass_sint8_as_uint8(i8 signext %a) nounwind { define void @pass_sint8_as_uint8(i8 signext %a) nounwind {
; RV32I-LABEL: pass_sint8_as_uint8: ; RV32I-LABEL: pass_sint8_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
call void @receive_uint8(i8 zeroext %a) call void @receive_uint8(i8 zeroext %a)
ret void ret void
} }
declare signext i8 @return_sint8() declare signext i8 @return_sint8()
define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind { define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
; RV32I-LABEL: ret_callresult_sint8_as_uint8: ; RV32I-LABEL: ret_callresult_sint8_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i8 @return_sint8() %1 = call signext i8 @return_sint8()
ret i8 %1 ret i8 %1
} }
define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind { define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_sint8_ret: ; RV32I-LABEL: sint8_arg_to_sint8_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
ret i8 %a ret i8 %a
} }
define void @pass_sint8_as_sint8(i8 signext %a) nounwind { define void @pass_sint8_as_sint8(i8 signext %a) nounwind {
; RV32I-LABEL: pass_sint8_as_sint8: ; RV32I-LABEL: pass_sint8_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
call void @receive_sint8(i8 signext %a) call void @receive_sint8(i8 signext %a)
ret void ret void
} }
define signext i8 @ret_callresult_sint8_as_sint8() nounwind { define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
; RV32I-LABEL: ret_callresult_sint8_as_sint8: ; RV32I-LABEL: ret_callresult_sint8_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i8 @return_sint8() %1 = call signext i8 @return_sint8()
ret i8 %1 ret i8 %1
} }
define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind { define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_anyint32_ret: ; RV32I-LABEL: sint8_arg_to_anyint32_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = sext i8 %a to i32 %1 = sext i8 %a to i32
ret i32 %1 ret i32 %1
} }
define void @pass_sint8_as_anyint32(i8 signext %a) nounwind { define void @pass_sint8_as_anyint32(i8 signext %a) nounwind {
; RV32I-LABEL: pass_sint8_as_anyint32: ; RV32I-LABEL: pass_sint8_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = sext i8 %a to i32 %1 = sext i8 %a to i32
call void @receive_anyint32(i32 signext %1) call void @receive_anyint32(i32 signext %1)
ret void ret void
} }
define signext i32 @ret_callresult_sint8_as_anyint32() nounwind { define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
; RV32I-LABEL: ret_callresult_sint8_as_anyint32: ; RV32I-LABEL: ret_callresult_sint8_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i8 @return_sint8() %1 = call signext i8 @return_sint8()
%2 = sext i8 %1 to i32 %2 = sext i8 %1 to i32
ret i32 %2 ret i32 %2
} }
define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind { define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_uint8_ret: ; RV32I-LABEL: anyint32_arg_to_uint8_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = trunc i32 %a to i8 %1 = trunc i32 %a to i8
ret i8 %1 ret i8 %1
} }
define void @pass_anyint32_as_uint8(i32 signext %a) nounwind { define void @pass_anyint32_as_uint8(i32 signext %a) nounwind {
; RV32I-LABEL: pass_anyint32_as_uint8: ; RV32I-LABEL: pass_anyint32_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = trunc i32 %a to i8 %1 = trunc i32 %a to i8
call void @receive_uint8(i8 zeroext %1) call void @receive_uint8(i8 zeroext %1)
ret void ret void
} }
declare signext i32 @return_anyint32() declare signext i32 @return_anyint32()
define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind { define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
; RV32I-LABEL: ret_callresult_anyint32_as_uint8: ; RV32I-LABEL: ret_callresult_anyint32_as_uint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i32 @return_anyint32() %1 = call signext i32 @return_anyint32()
%2 = trunc i32 %1 to i8 %2 = trunc i32 %1 to i8
ret i8 %2 ret i8 %2
} }
define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind { define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_sint8_ret: ; RV32I-LABEL: anyint32_arg_to_sint8_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = trunc i32 %a to i8 %1 = trunc i32 %a to i8
ret i8 %1 ret i8 %1
} }
define void @pass_anyint32_as_sint8(i32 signext %a) nounwind { define void @pass_anyint32_as_sint8(i32 signext %a) nounwind {
; RV32I-LABEL: pass_anyint32_as_sint8: ; RV32I-LABEL: pass_anyint32_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = trunc i32 %a to i8 %1 = trunc i32 %a to i8
call void @receive_sint8(i8 signext %1) call void @receive_sint8(i8 signext %1)
ret void ret void
} }
define signext i8 @ret_callresult_anyint32_as_sint8() nounwind { define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
; RV32I-LABEL: ret_callresult_anyint32_as_sint8: ; RV32I-LABEL: ret_callresult_anyint32_as_sint8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i32 @return_anyint32() %1 = call signext i32 @return_anyint32()
%2 = trunc i32 %1 to i8 %2 = trunc i32 %1 to i8
ret i8 %2 ret i8 %2
} }
define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind { define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_anyint32_ret: ; RV32I-LABEL: anyint32_arg_to_anyint32_ret:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
ret i32 %a ret i32 %a
} }
define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind { define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind {
; RV32I-LABEL: pass_anyint32_as_anyint32: ; RV32I-LABEL: pass_anyint32_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
call void @receive_anyint32(i32 signext %a) call void @receive_anyint32(i32 signext %a)
ret void ret void
} }
define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind { define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
; RV32I-LABEL: ret_callresult_anyint32_as_anyint32: ; RV32I-LABEL: ret_callresult_anyint32_as_anyint32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = call signext i32 @return_anyint32() %1 = call signext i32 @return_anyint32()
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/calls.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -relocation-model=pic -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -relocation-model=pic -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-PIC %s ; RUN: | FileCheck -check-prefix=RV32I-PIC %s
declare i32 @external_function(i32) declare i32 @external_function(i32)
define i32 @test_call_external(i32 %a) nounwind { define i32 @test_call_external(i32 %a) nounwind {
; RV32I-LABEL: test_call_external: ; RV32I-LABEL: test_call_external:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call external_function ; RV32I-NEXT: call external_function@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_external: ; RV32I-PIC-LABEL: test_call_external:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: call external_function@plt ; RV32I-PIC-NEXT: call external_function@plt
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 @external_function(i32 %a) %1 = call i32 @external_function(i32 %a)
ret i32 %1 ret i32 %1
} }
declare dso_local i32 @dso_local_function(i32) declare dso_local i32 @dso_local_function(i32)
define i32 @test_call_dso_local(i32 %a) nounwind { define i32 @test_call_dso_local(i32 %a) nounwind {
; RV32I-LABEL: test_call_dso_local: ; RV32I-LABEL: test_call_dso_local:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call dso_local_function ; RV32I-NEXT: call dso_local_function
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_dso_local: ; RV32I-PIC-LABEL: test_call_dso_local:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: call dso_local_function ; RV32I-PIC-NEXT: call dso_local_function
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 @dso_local_function(i32 %a) %1 = call i32 @dso_local_function(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @defined_function(i32 %a) nounwind { define i32 @defined_function(i32 %a) nounwind {
; RV32I-LABEL: defined_function: ; RV32I-LABEL: defined_function:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1 ; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: defined_function: ; RV32I-PIC-LABEL: defined_function:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi a0, a0, 1 ; RV32I-PIC-NEXT: addi a0, a0, 1
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = add i32 %a, 1 %1 = add i32 %a, 1
ret i32 %1 ret i32 %1
} }
define i32 @test_call_defined(i32 %a) nounwind { define i32 @test_call_defined(i32 %a) nounwind {
; RV32I-LABEL: test_call_defined: ; RV32I-LABEL: test_call_defined:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call defined_function ; RV32I-NEXT: call defined_function
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_defined: ; RV32I-PIC-LABEL: test_call_defined:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: call defined_function@plt ; RV32I-PIC-NEXT: call defined_function@plt
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 @defined_function(i32 %a) %1 = call i32 @defined_function(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind { define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
; RV32I-LABEL: test_call_indirect: ; RV32I-LABEL: test_call_indirect:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: jalr a2 ; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_indirect: ; RV32I-PIC-LABEL: test_call_indirect:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: mv a2, a0 ; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a0, a1 ; RV32I-PIC-NEXT: mv a0, a1
; RV32I-PIC-NEXT: jalr a2 ; RV32I-PIC-NEXT: jalr a2
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 %a(i32 %b) %1 = call i32 %a(i32 %b)
ret i32 %1 ret i32 %1
} }
; Ensure that calls to fastcc functions aren't rejected. Such calls may be ; Ensure that calls to fastcc functions aren't rejected. Such calls may be
; introduced when compiling with optimisation. ; introduced when compiling with optimisation.
Show All 11 Lines
%1 = add i32 %a, %b %1 = add i32 %a, %b
ret i32 %1 ret i32 %1
} }
define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: test_call_fastcc: ; RV32I-LABEL: test_call_fastcc:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call fastcc_function ; RV32I-NEXT: call fastcc_function
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_fastcc: ; RV32I-PIC-LABEL: test_call_fastcc:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: sw s0, 8(sp) ; RV32I-PIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: mv s0, a0 ; RV32I-PIC-NEXT: mv s0, a0
; RV32I-PIC-NEXT: call fastcc_function@plt ; RV32I-PIC-NEXT: call fastcc_function@plt
; RV32I-PIC-NEXT: mv a0, s0 ; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw s0, 8(sp) ; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b) %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
ret i32 %a ret i32 %a
} }
declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
define i32 @test_call_external_many_args(i32 %a) nounwind { define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_external_many_args: ; RV32I-LABEL: test_call_external_many_args:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp) ; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0 ; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: call external_many_args ; RV32I-NEXT: call external_many_args@plt
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_external_many_args: ; RV32I-PIC-LABEL: test_call_external_many_args:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: sw s0, 8(sp) ; RV32I-PIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: mv s0, a0 ; RV32I-PIC-NEXT: mv s0, a0
; RV32I-PIC-NEXT: sw a0, 4(sp) ; RV32I-PIC-NEXT: sw a0, 4(sp)
; RV32I-PIC-NEXT: sw a0, 0(sp) ; RV32I-PIC-NEXT: sw a0, 0(sp)
; RV32I-PIC-NEXT: mv a1, a0 ; RV32I-PIC-NEXT: mv a1, a0
; RV32I-PIC-NEXT: mv a2, a0 ; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a3, a0 ; RV32I-PIC-NEXT: mv a3, a0
; RV32I-PIC-NEXT: mv a4, a0 ; RV32I-PIC-NEXT: mv a4, a0
; RV32I-PIC-NEXT: mv a5, a0 ; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0 ; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0 ; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call external_many_args@plt ; RV32I-PIC-NEXT: call external_many_args@plt
; RV32I-PIC-NEXT: mv a0, s0 ; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw s0, 8(sp) ; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a, %1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a) i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %a ret i32 %a
} }
define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind { define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
Show All 11 Lines; RV32I-PIC-NEXT: ret
%added = add i32 %j, 1 %added = add i32 %j, 1
ret i32 %added ret i32 %added
} }
define i32 @test_call_defined_many_args(i32 %a) nounwind { define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_defined_many_args: ; RV32I-LABEL: test_call_defined_many_args:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp) ; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0 ; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: call defined_many_args ; RV32I-NEXT: call defined_many_args
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32I-PIC-LABEL: test_call_defined_many_args: ; RV32I-PIC-LABEL: test_call_defined_many_args:
; RV32I-PIC: # %bb.0: ; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16 ; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) ; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: sw a0, 4(sp) ; RV32I-PIC-NEXT: sw a0, 4(sp)
; RV32I-PIC-NEXT: sw a0, 0(sp) ; RV32I-PIC-NEXT: sw a0, 0(sp)
; RV32I-PIC-NEXT: mv a1, a0 ; RV32I-PIC-NEXT: mv a1, a0
; RV32I-PIC-NEXT: mv a2, a0 ; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a3, a0 ; RV32I-PIC-NEXT: mv a3, a0
; RV32I-PIC-NEXT: mv a4, a0 ; RV32I-PIC-NEXT: mv a4, a0
; RV32I-PIC-NEXT: mv a5, a0 ; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0 ; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0 ; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call defined_many_args@plt ; RV32I-PIC-NEXT: call defined_many_args@plt
; RV32I-PIC-NEXT: lw ra, 12(sp) ; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16 ; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret ; RV32I-PIC-NEXT: ret
%1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a, %1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a) i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/copysign-casts.ll

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Lines; RV64IFDZFH-NEXT: ret
%t = call float @llvm.copysign.f32(float %a, float %c) %t = call float @llvm.copysign.f32(float %a, float %c)
ret float %t ret float %t
} }
define half @fold_demote_h_s(half %a, float %b) nounwind { define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32I-LABEL: fold_demote_h_s: ; RV32I-LABEL: fold_demote_h_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: call __gnu_h2f_ieee ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: and a2, s0, a1 ; RV32I-NEXT: and a2, s0, a1
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: call __gnu_f2h_ieee ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fold_demote_h_s: ; RV64I-LABEL: fold_demote_h_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: call __gnu_h2f_ieee ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: and a2, s0, a1 ; RV64I-NEXT: and a2, s0, a1
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: call __gnu_f2h_ieee ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IF-LABEL: fold_demote_h_s: ; RV32IF-LABEL: fold_demote_h_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 8(sp) ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa1 ; RV32IF-NEXT: fmv.s fs0, fa1
; RV32IF-NEXT: call __gnu_f2h_ieee ; RV32IF-NEXT: call __gnu_f2h_ieee@plt
; RV32IF-NEXT: call __gnu_h2f_ieee ; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: fsgnj.s fa0, fa0, fs0 ; RV32IF-NEXT: fsgnj.s fa0, fa0, fs0
; RV32IF-NEXT: flw fs0, 8(sp) ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IFD-LABEL: fold_demote_h_s: ; RV32IFD-LABEL: fold_demote_h_s:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.s fs0, fa1 ; RV32IFD-NEXT: fmv.s fs0, fa1
; RV32IFD-NEXT: call __gnu_f2h_ieee ; RV32IFD-NEXT: call __gnu_f2h_ieee@plt
; RV32IFD-NEXT: call __gnu_h2f_ieee ; RV32IFD-NEXT: call __gnu_h2f_ieee@plt
; RV32IFD-NEXT: fsgnj.s fa0, fa0, fs0 ; RV32IFD-NEXT: fsgnj.s fa0, fa0, fs0
; RV32IFD-NEXT: fld fs0, 0(sp) ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fold_demote_h_s: ; RV64IFD-LABEL: fold_demote_h_s:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 0(sp) ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.s fs0, fa1 ; RV64IFD-NEXT: fmv.s fs0, fa1
; RV64IFD-NEXT: call __gnu_f2h_ieee ; RV64IFD-NEXT: call __gnu_f2h_ieee@plt
; RV64IFD-NEXT: call __gnu_h2f_ieee ; RV64IFD-NEXT: call __gnu_h2f_ieee@plt
; RV64IFD-NEXT: fsgnj.s fa0, fa0, fs0 ; RV64IFD-NEXT: fsgnj.s fa0, fa0, fs0
; RV64IFD-NEXT: fld fs0, 0(sp) ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_demote_h_s: ; RV32IFZFH-LABEL: fold_demote_h_s:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fcvt.h.s ft0, fa1 ; RV32IFZFH-NEXT: fcvt.h.s ft0, fa1
; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0
; RV32IFZFH-NEXT: ret ; RV32IFZFH-NEXT: ret
Show All 13 Lines; RV64IFDZFH-NEXT: ret
%t = call half @llvm.copysign.f16(half %a, half %c) %t = call half @llvm.copysign.f16(half %a, half %c)
ret half %t ret half %t
} }
define half @fold_demote_h_d(half %a, double %b) nounwind { define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32I-LABEL: fold_demote_h_d: ; RV32I-LABEL: fold_demote_h_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: call __gnu_h2f_ieee ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: and a2, s0, a1 ; RV32I-NEXT: and a2, s0, a1
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: call __gnu_f2h_ieee ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fold_demote_h_d: ; RV64I-LABEL: fold_demote_h_d:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: call __gnu_h2f_ieee ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: and a1, s0, a1 ; RV64I-NEXT: and a1, s0, a1
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IF-LABEL: fold_demote_h_d: ; RV32IF-LABEL: fold_demote_h_d:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a1 ; RV32IF-NEXT: mv s0, a1
; RV32IF-NEXT: call __gnu_f2h_ieee ; RV32IF-NEXT: call __gnu_f2h_ieee@plt
; RV32IF-NEXT: call __gnu_h2f_ieee ; RV32IF-NEXT: call __gnu_h2f_ieee@plt
; RV32IF-NEXT: fmv.w.x ft0, s0 ; RV32IF-NEXT: fmv.w.x ft0, s0
; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0
; RV32IF-NEXT: lw s0, 8(sp) ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IFD-LABEL: fold_demote_h_d: ; RV32IFD-LABEL: fold_demote_h_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa1 ; RV32IFD-NEXT: fmv.d fs0, fa1
; RV32IFD-NEXT: call __gnu_f2h_ieee ; RV32IFD-NEXT: call __gnu_f2h_ieee@plt
; RV32IFD-NEXT: call __gnu_h2f_ieee ; RV32IFD-NEXT: call __gnu_h2f_ieee@plt
; RV32IFD-NEXT: fcvt.s.d ft0, fs0 ; RV32IFD-NEXT: fcvt.s.d ft0, fs0
; RV32IFD-NEXT: fsgnj.s fa0, fa0, ft0 ; RV32IFD-NEXT: fsgnj.s fa0, fa0, ft0
; RV32IFD-NEXT: fld fs0, 0(sp) ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fold_demote_h_d: ; RV64IFD-LABEL: fold_demote_h_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 0(sp) ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa1 ; RV64IFD-NEXT: fmv.d fs0, fa1
; RV64IFD-NEXT: call __gnu_f2h_ieee ; RV64IFD-NEXT: call __gnu_f2h_ieee@plt
; RV64IFD-NEXT: call __gnu_h2f_ieee ; RV64IFD-NEXT: call __gnu_h2f_ieee@plt
; RV64IFD-NEXT: fcvt.s.d ft0, fs0 ; RV64IFD-NEXT: fcvt.s.d ft0, fs0
; RV64IFD-NEXT: fsgnj.s fa0, fa0, ft0 ; RV64IFD-NEXT: fsgnj.s fa0, fa0, ft0
; RV64IFD-NEXT: fld fs0, 0(sp) ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32IFZFH-LABEL: fold_demote_h_d: ; RV32IFZFH-LABEL: fold_demote_h_d:
; RV32IFZFH: # %bb.0: ; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: srli a0, a1, 16 ; RV32IFZFH-NEXT: srli a0, a1, 16
; RV32IFZFH-NEXT: fmv.h.x ft0, a0 ; RV32IFZFH-NEXT: fmv.h.x ft0, a0
; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, ft0
Show All 17 Lines

llvm/test/CodeGen/RISCV/div.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s ; RUN: | FileCheck -check-prefix=RV64IM %s
define i32 @udiv(i32 %a, i32 %b) nounwind { define i32 @udiv(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: udiv: ; RV32I-LABEL: udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: udiv: ; RV32IM-LABEL: udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: divu a0, a0, a1 ; RV32IM-NEXT: divu a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: udiv: ; RV64I-LABEL: udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: udiv: ; RV64IM-LABEL: udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: divuw a0, a0, a1 ; RV64IM-NEXT: divuw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = udiv i32 %a, %b %1 = udiv i32 %a, %b
ret i32 %1 ret i32 %1
} }
define i32 @udiv_constant(i32 %a) nounwind { define i32 @udiv_constant(i32 %a) nounwind {
; RV32I-LABEL: udiv_constant: ; RV32I-LABEL: udiv_constant:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: udiv_constant: ; RV32IM-LABEL: udiv_constant:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 838861 ; RV32IM-NEXT: lui a1, 838861
; RV32IM-NEXT: addi a1, a1, -819 ; RV32IM-NEXT: addi a1, a1, -819
; RV32IM-NEXT: mulhu a0, a0, a1 ; RV32IM-NEXT: mulhu a0, a0, a1
; RV32IM-NEXT: srli a0, a0, 2 ; RV32IM-NEXT: srli a0, a0, 2
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: udiv_constant: ; RV64I-LABEL: udiv_constant:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: udiv_constant: ; RV64IM-LABEL: udiv_constant:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1035469 ; RV64IM-NEXT: lui a1, 1035469
Show All 34 Lines; RV64IM-NEXT: ret
%1 = udiv i32 %a, 8 %1 = udiv i32 %a, 8
ret i32 %1 ret i32 %1
} }
define i64 @udiv64(i64 %a, i64 %b) nounwind { define i64 @udiv64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: udiv64: ; RV32I-LABEL: udiv64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: call __udivdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: udiv64: ; RV32IM-LABEL: udiv64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: call __udivdi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: udiv64: ; RV64I-LABEL: udiv64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: udiv64: ; RV64IM-LABEL: udiv64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: divu a0, a0, a1 ; RV64IM-NEXT: divu a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = udiv i64 %a, %b %1 = udiv i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @udiv64_constant(i64 %a) nounwind { define i64 @udiv64_constant(i64 %a) nounwind {
; RV32I-LABEL: udiv64_constant: ; RV32I-LABEL: udiv64_constant:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: call __udivdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: udiv64_constant: ; RV32IM-LABEL: udiv64_constant:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: addi a2, zero, 5 ; RV32IM-NEXT: addi a2, zero, 5
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: call __udivdi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: udiv64_constant: ; RV64I-LABEL: udiv64_constant:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: udiv64_constant: ; RV64IM-LABEL: udiv64_constant:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 1035469 ; RV64IM-NEXT: lui a1, 1035469
; RV64IM-NEXT: addiw a1, a1, -819 ; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -819 ; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -819 ; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -819 ; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: mulhu a0, a0, a1 ; RV64IM-NEXT: mulhu a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 2 ; RV64IM-NEXT: srli a0, a0, 2
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = udiv i64 %a, 5 %1 = udiv i64 %a, 5
ret i64 %1 ret i64 %1
} }
define i32 @sdiv(i32 %a, i32 %b) nounwind { define i32 @sdiv(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sdiv: ; RV32I-LABEL: sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: sdiv: ; RV32IM-LABEL: sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: div a0, a0, a1 ; RV32IM-NEXT: div a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: sdiv: ; RV64I-LABEL: sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv: ; RV64IM-LABEL: sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: divw a0, a0, a1 ; RV64IM-NEXT: divw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sdiv i32 %a, %b %1 = sdiv i32 %a, %b
ret i32 %1 ret i32 %1
} }
define i32 @sdiv_constant(i32 %a) nounwind { define i32 @sdiv_constant(i32 %a) nounwind {
; RV32I-LABEL: sdiv_constant: ; RV32I-LABEL: sdiv_constant:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: sdiv_constant: ; RV32IM-LABEL: sdiv_constant:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 419430 ; RV32IM-NEXT: lui a1, 419430
; RV32IM-NEXT: addi a1, a1, 1639 ; RV32IM-NEXT: addi a1, a1, 1639
; RV32IM-NEXT: mulh a0, a0, a1 ; RV32IM-NEXT: mulh a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31 ; RV32IM-NEXT: srli a1, a0, 31
; RV32IM-NEXT: srai a0, a0, 1 ; RV32IM-NEXT: srai a0, a0, 1
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: sdiv_constant: ; RV64I-LABEL: sdiv_constant:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv_constant: ; RV64IM-LABEL: sdiv_constant:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 13107 ; RV64IM-NEXT: lui a1, 13107
; RV64IM-NEXT: addiw a1, a1, 819 ; RV64IM-NEXT: addiw a1, a1, 819
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
%1 = sdiv i32 %a, 8 %1 = sdiv i32 %a, 8
ret i32 %1 ret i32 %1
} }
define i64 @sdiv64(i64 %a, i64 %b) nounwind { define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: sdiv64: ; RV32I-LABEL: sdiv64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: call __divdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: sdiv64: ; RV32IM-LABEL: sdiv64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: call __divdi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: sdiv64: ; RV64I-LABEL: sdiv64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv64: ; RV64IM-LABEL: sdiv64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: div a0, a0, a1 ; RV64IM-NEXT: div a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sdiv i64 %a, %b %1 = sdiv i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @sdiv64_constant(i64 %a) nounwind { define i64 @sdiv64_constant(i64 %a) nounwind {
; RV32I-LABEL: sdiv64_constant: ; RV32I-LABEL: sdiv64_constant:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: call __divdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: sdiv64_constant: ; RV32IM-LABEL: sdiv64_constant:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: addi a2, zero, 5 ; RV32IM-NEXT: addi a2, zero, 5
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: call __divdi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_constant: ; RV64I-LABEL: sdiv64_constant:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv64_constant: ; RV64IM-LABEL: sdiv64_constant:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 13107 ; RV64IM-NEXT: lui a1, 13107
; RV64IM-NEXT: addiw a1, a1, 819 ; RV64IM-NEXT: addiw a1, a1, 819
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
Show All 13 Lines
; Although this sdiv has two sexti32 operands, it shouldn't compile to divw on ; Although this sdiv has two sexti32 operands, it shouldn't compile to divw on
; RV64M as that wouldn't produce the correct result for e.g. INT_MIN/-1. ; RV64M as that wouldn't produce the correct result for e.g. INT_MIN/-1.
define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind { define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sdiv64_sext_operands: ; RV32I-LABEL: sdiv64_sext_operands:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srai a3, a2, 31 ; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: call __divdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: sdiv64_sext_operands: ; RV32IM-LABEL: sdiv64_sext_operands:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: mv a2, a1 ; RV32IM-NEXT: mv a2, a1
; RV32IM-NEXT: srai a1, a0, 31 ; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srai a3, a2, 31 ; RV32IM-NEXT: srai a3, a2, 31
; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: call __divdi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_sext_operands: ; RV64I-LABEL: sdiv64_sext_operands:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: sdiv64_sext_operands: ; RV64IM-LABEL: sdiv64_sext_operands:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1 ; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: div a0, a0, a1 ; RV64IM-NEXT: div a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sext i32 %a to i64 %1 = sext i32 %a to i64
%2 = sext i32 %b to i64 %2 = sext i32 %b to i64
%3 = sdiv i64 %1, %2 %3 = sdiv i64 %1, %2
ret i64 %3 ret i64 %3
} }

llvm/test/CodeGen/RISCV/double-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
define void @br_fcmp_false(double %a, double %b) nounwind { define void @br_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD-LABEL: br_fcmp_false:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: bnez a0, .LBB0_2 ; RV32IFD-NEXT: bnez a0, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB0_2: # %if.else ; RV32IFD-NEXT: .LBB0_2: # %if.else
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD-LABEL: br_fcmp_false:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: addi a0, zero, 1 ; RV64IFD-NEXT: addi a0, zero, 1
; RV64IFD-NEXT: bnez a0, .LBB0_2 ; RV64IFD-NEXT: bnez a0, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.then ; RV64IFD-NEXT: # %bb.1: # %if.then
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB0_2: # %if.else ; RV64IFD-NEXT: .LBB0_2: # %if.else
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp false double %a, %b %1 = fcmp false double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
ret void ret void
if.else: if.else:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oeq(double %a, double %b) nounwind { define void @br_fcmp_oeq(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_oeq: ; RV32IFD-LABEL: br_fcmp_oeq:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB1_2 ; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB1_2: # %if.then ; RV32IFD-NEXT: .LBB1_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_oeq: ; RV64IFD-LABEL: br_fcmp_oeq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB1_2 ; RV64IFD-NEXT: bnez a0, .LBB1_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB1_2: # %if.then ; RV64IFD-NEXT: .LBB1_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp oeq double %a, %b %1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: generated code quality for this is very poor due to ; TODO: generated code quality for this is very poor due to
; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires ; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
; expansion. ; expansion.
define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_oeq_alt: ; RV32IFD-LABEL: br_fcmp_oeq_alt:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: beqz a0, .LBB2_2 ; RV32IFD-NEXT: beqz a0, .LBB2_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB2_2: # %if.then ; RV32IFD-NEXT: .LBB2_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_oeq_alt: ; RV64IFD-LABEL: br_fcmp_oeq_alt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: beqz a0, .LBB2_2 ; RV64IFD-NEXT: beqz a0, .LBB2_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB2_2: # %if.then ; RV64IFD-NEXT: .LBB2_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp oeq double %a, %b %1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
if.else: if.else:
ret void ret void
} }
define void @br_fcmp_ogt(double %a, double %b) nounwind { define void @br_fcmp_ogt(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ogt: ; RV32IFD-LABEL: br_fcmp_ogt:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB3_2 ; RV32IFD-NEXT: bnez a0, .LBB3_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB3_2: # %if.then ; RV32IFD-NEXT: .LBB3_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ogt: ; RV64IFD-LABEL: br_fcmp_ogt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB3_2 ; RV64IFD-NEXT: bnez a0, .LBB3_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB3_2: # %if.then ; RV64IFD-NEXT: .LBB3_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ogt double %a, %b %1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oge(double %a, double %b) nounwind { define void @br_fcmp_oge(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_oge: ; RV32IFD-LABEL: br_fcmp_oge:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB4_2 ; RV32IFD-NEXT: bnez a0, .LBB4_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB4_2: # %if.then ; RV32IFD-NEXT: .LBB4_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_oge: ; RV64IFD-LABEL: br_fcmp_oge:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB4_2 ; RV64IFD-NEXT: bnez a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB4_2: # %if.then ; RV64IFD-NEXT: .LBB4_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp oge double %a, %b %1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_olt(double %a, double %b) nounwind { define void @br_fcmp_olt(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_olt: ; RV32IFD-LABEL: br_fcmp_olt:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB5_2 ; RV32IFD-NEXT: bnez a0, .LBB5_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB5_2: # %if.then ; RV32IFD-NEXT: .LBB5_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_olt: ; RV64IFD-LABEL: br_fcmp_olt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB5_2 ; RV64IFD-NEXT: bnez a0, .LBB5_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB5_2: # %if.then ; RV64IFD-NEXT: .LBB5_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp olt double %a, %b %1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ole(double %a, double %b) nounwind { define void @br_fcmp_ole(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ole: ; RV32IFD-LABEL: br_fcmp_ole:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB6_2 ; RV32IFD-NEXT: bnez a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB6_2: # %if.then ; RV32IFD-NEXT: .LBB6_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ole: ; RV64IFD-LABEL: br_fcmp_ole:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB6_2 ; RV64IFD-NEXT: bnez a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB6_2: # %if.then ; RV64IFD-NEXT: .LBB6_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ole double %a, %b %1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.s+sltiu+bne -> feq.s+beq ; TODO: feq.s+sltiu+bne -> feq.s+beq
define void @br_fcmp_one(double %a, double %b) nounwind { define void @br_fcmp_one(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_one: ; RV32IFD-LABEL: br_fcmp_one:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1 ; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1 ; RV32IFD-NEXT: not a1, a1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB7_2 ; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB7_2: # %if.then ; RV32IFD-NEXT: .LBB7_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_one: ; RV64IFD-LABEL: br_fcmp_one:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1 ; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1 ; RV64IFD-NEXT: not a1, a1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB7_2 ; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB7_2: # %if.then ; RV64IFD-NEXT: .LBB7_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp one double %a, %b %1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ord(double %a, double %b) nounwind { define void @br_fcmp_ord(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ord: ; RV32IFD-LABEL: br_fcmp_ord:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB8_2 ; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB8_2: # %if.then ; RV32IFD-NEXT: .LBB8_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ord: ; RV64IFD-LABEL: br_fcmp_ord:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB8_2: # %if.then ; RV64IFD-NEXT: .LBB8_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ord double %a, %b %1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ueq(double %a, double %b) nounwind { define void @br_fcmp_ueq(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ueq: ; RV32IFD-LABEL: br_fcmp_ueq:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: or a0, a0, a1 ; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB9_2 ; RV32IFD-NEXT: bnez a0, .LBB9_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_2: # %if.then ; RV32IFD-NEXT: .LBB9_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ueq: ; RV64IFD-LABEL: br_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: feq.d a2, ft1, ft1 ; RV64IFD-NEXT: feq.d a2, ft1, ft1
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB9_2 ; RV64IFD-NEXT: bnez a0, .LBB9_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB9_2: # %if.then ; RV64IFD-NEXT: .LBB9_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ugt(double %a, double %b) nounwind { define void @br_fcmp_ugt(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ugt: ; RV32IFD-LABEL: br_fcmp_ugt:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB10_2 ; RV32IFD-NEXT: bnez a0, .LBB10_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB10_2: # %if.then ; RV32IFD-NEXT: .LBB10_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ugt: ; RV64IFD-LABEL: br_fcmp_ugt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB10_2 ; RV64IFD-NEXT: bnez a0, .LBB10_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB10_2: # %if.then ; RV64IFD-NEXT: .LBB10_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ugt double %a, %b %1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uge(double %a, double %b) nounwind { define void @br_fcmp_uge(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_uge: ; RV32IFD-LABEL: br_fcmp_uge:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB11_2 ; RV32IFD-NEXT: bnez a0, .LBB11_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB11_2: # %if.then ; RV32IFD-NEXT: .LBB11_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_uge: ; RV64IFD-LABEL: br_fcmp_uge:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB11_2 ; RV64IFD-NEXT: bnez a0, .LBB11_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB11_2: # %if.then ; RV64IFD-NEXT: .LBB11_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp uge double %a, %b %1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ult(double %a, double %b) nounwind { define void @br_fcmp_ult(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ult: ; RV32IFD-LABEL: br_fcmp_ult:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB12_2 ; RV32IFD-NEXT: bnez a0, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB12_2: # %if.then ; RV32IFD-NEXT: .LBB12_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ult: ; RV64IFD-LABEL: br_fcmp_ult:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB12_2 ; RV64IFD-NEXT: bnez a0, .LBB12_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB12_2: # %if.then ; RV64IFD-NEXT: .LBB12_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ult double %a, %b %1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ule(double %a, double %b) nounwind { define void @br_fcmp_ule(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_ule: ; RV32IFD-LABEL: br_fcmp_ule:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB13_2 ; RV32IFD-NEXT: bnez a0, .LBB13_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB13_2: # %if.then ; RV32IFD-NEXT: .LBB13_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ule: ; RV64IFD-LABEL: br_fcmp_ule:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB13_2 ; RV64IFD-NEXT: bnez a0, .LBB13_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB13_2: # %if.then ; RV64IFD-NEXT: .LBB13_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ule double %a, %b %1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_une(double %a, double %b) nounwind { define void @br_fcmp_une(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_une: ; RV32IFD-LABEL: br_fcmp_une:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB14_2 ; RV32IFD-NEXT: bnez a0, .LBB14_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB14_2: # %if.then ; RV32IFD-NEXT: .LBB14_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_une: ; RV64IFD-LABEL: br_fcmp_une:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB14_2 ; RV64IFD-NEXT: bnez a0, .LBB14_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB14_2: # %if.then ; RV64IFD-NEXT: .LBB14_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp une double %a, %b %1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uno(double %a, double %b) nounwind { define void @br_fcmp_uno(double %a, double %b) nounwind {
; TODO: sltiu+bne -> beq ; TODO: sltiu+bne -> beq
; RV32IFD-LABEL: br_fcmp_uno: ; RV32IFD-LABEL: br_fcmp_uno:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0 ; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: bnez a0, .LBB15_2 ; RV32IFD-NEXT: bnez a0, .LBB15_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB15_2: # %if.then ; RV32IFD-NEXT: .LBB15_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_uno: ; RV64IFD-LABEL: br_fcmp_uno:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0 ; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: bnez a0, .LBB15_2 ; RV64IFD-NEXT: bnez a0, .LBB15_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB15_2: # %if.then ; RV64IFD-NEXT: .LBB15_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_true(double %a, double %b) nounwind { define void @br_fcmp_true(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_true: ; RV32IFD-LABEL: br_fcmp_true:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: bnez a0, .LBB16_2 ; RV32IFD-NEXT: bnez a0, .LBB16_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB16_2: # %if.then ; RV32IFD-NEXT: .LBB16_2: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_true: ; RV64IFD-LABEL: br_fcmp_true:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: addi a0, zero, 1 ; RV64IFD-NEXT: addi a0, zero, 1
; RV64IFD-NEXT: bnez a0, .LBB16_2 ; RV64IFD-NEXT: bnez a0, .LBB16_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB16_2: # %if.then ; RV64IFD-NEXT: .LBB16_2: # %if.then
; RV64IFD-NEXT: call abort ; RV64IFD-NEXT: call abort@plt
%1 = fcmp true double %a, %b %1 = fcmp true double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }

llvm/test/CodeGen/RISCV/double-calling-conv.ll

Show All 27 Lines
} }
; TODO: code quality for loading and then passing f64 constants is poor. ; TODO: code quality for loading and then passing f64 constants is poor.
define double @caller_double_inreg() nounwind { define double @caller_double_inreg() nounwind {
; RV32IFD-LABEL: caller_double_inreg: ; RV32IFD-LABEL: caller_double_inreg:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262236 ; RV32IFD-NEXT: lui a0, 262236
; RV32IFD-NEXT: addi a1, a0, 655 ; RV32IFD-NEXT: addi a1, a0, 655
; RV32IFD-NEXT: lui a0, 377487 ; RV32IFD-NEXT: lui a0, 377487
; RV32IFD-NEXT: addi a0, a0, 1475 ; RV32IFD-NEXT: addi a0, a0, 1475
; RV32IFD-NEXT: lui a2, 262364 ; RV32IFD-NEXT: lui a2, 262364
; RV32IFD-NEXT: addi a3, a2, 655 ; RV32IFD-NEXT: addi a3, a2, 655
; RV32IFD-NEXT: mv a2, a0 ; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: call callee_double_inreg ; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = call double @callee_double_inreg(double 2.720000e+00, double 3.720000e+00) %1 = call double @callee_double_inreg(double 2.720000e+00, double 3.720000e+00)
ret double %1 ret double %1
} }
define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind { define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind {
; RV32IFD-LABEL: callee_double_split_reg_stack: ; RV32IFD-LABEL: callee_double_split_reg_stack:
Show All 15 Lines; RV32IFD-NEXT: ret
%1 = fadd double %d, %e %1 = fadd double %d, %e
ret double %1 ret double %1
} }
define double @caller_double_split_reg_stack() nounwind { define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-LABEL: caller_double_split_reg_stack: ; RV32IFD-LABEL: caller_double_split_reg_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510 ; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a2, a0, 327 ; RV32IFD-NEXT: addi a2, a0, 327
; RV32IFD-NEXT: lui a0, 262446 ; RV32IFD-NEXT: lui a0, 262446
; RV32IFD-NEXT: addi a6, a0, 327 ; RV32IFD-NEXT: addi a6, a0, 327
; RV32IFD-NEXT: lui a0, 713032 ; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a5, a0, -1311 ; RV32IFD-NEXT: addi a5, a0, -1311
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a1, zero, 2 ; RV32IFD-NEXT: addi a1, zero, 2
; RV32IFD-NEXT: addi a3, zero, 3 ; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: mv a2, zero ; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: mv a4, zero ; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: mv a7, a5 ; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack ; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72) %1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
ret double %1 ret double %1
} }
define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind { define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind {
; RV32IFD-LABEL: callee_double_stack: ; RV32IFD-LABEL: callee_double_stack:
Show All 10 Lines; RV32IFD-NEXT: ret
%1 = fadd double %e, %f %1 = fadd double %e, %f
ret double %1 ret double %1
} }
define double @caller_double_stack() nounwind { define double @caller_double_stack() nounwind {
; RV32IFD-LABEL: caller_double_stack: ; RV32IFD-LABEL: caller_double_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510 ; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327 ; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 4(sp) ; RV32IFD-NEXT: sw a0, 4(sp)
; RV32IFD-NEXT: lui a0, 713032 ; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a1, a0, -1311 ; RV32IFD-NEXT: addi a1, a0, -1311
; RV32IFD-NEXT: sw a1, 0(sp) ; RV32IFD-NEXT: sw a1, 0(sp)
; RV32IFD-NEXT: lui a0, 262574 ; RV32IFD-NEXT: lui a0, 262574
; RV32IFD-NEXT: addi a0, a0, 327 ; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 12(sp) ; RV32IFD-NEXT: sw a0, 12(sp)
; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a2, zero, 2 ; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: addi a4, zero, 3 ; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: addi a6, zero, 4 ; RV32IFD-NEXT: addi a6, zero, 4
; RV32IFD-NEXT: sw a1, 8(sp) ; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: mv a1, zero ; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: mv a3, zero ; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: mv a5, zero ; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero ; RV32IFD-NEXT: mv a7, zero
; RV32IFD-NEXT: call callee_double_stack ; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
%1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72) %1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-convert.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines; RV64IFD-NEXT: ret
%1 = uitofp i32 %a to double %1 = uitofp i32 %a to double
ret double %1 ret double %1
} }
define i64 @fcvt_l_d(double %a) nounwind { define i64 @fcvt_l_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d: ; RV32IFD-LABEL: fcvt_l_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __fixdfdi ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_l_d: ; RV64IFD-LABEL: fcvt_l_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fptosi double %a to i64 %1 = fptosi double %a to i64
ret i64 %1 ret i64 %1
} }
define i64 @fcvt_lu_d(double %a) nounwind { define i64 @fcvt_lu_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d: ; RV32IFD-LABEL: fcvt_lu_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __fixunsdfdi ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_lu_d: ; RV64IFD-LABEL: fcvt_lu_d:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
Show All 29 Lines; RV64IFD-NEXT: ret
%2 = bitcast double %1 to i64 %2 = bitcast double %1 to i64
ret i64 %2 ret i64 %2
} }
define double @fcvt_d_l(i64 %a) nounwind { define double @fcvt_d_l(i64 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_l: ; RV32IFD-LABEL: fcvt_d_l:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __floatdidf ; RV32IFD-NEXT: call __floatdidf@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_l: ; RV64IFD-LABEL: fcvt_d_l:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.d.l ft0, a0 ; RV64IFD-NEXT: fcvt.d.l ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = sitofp i64 %a to double %1 = sitofp i64 %a to double
ret double %1 ret double %1
} }
define double @fcvt_d_lu(i64 %a) nounwind { define double @fcvt_d_lu(i64 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_lu: ; RV32IFD-LABEL: fcvt_d_lu:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __floatundidf ; RV32IFD-NEXT: call __floatundidf@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_d_lu: ; RV64IFD-LABEL: fcvt_d_lu:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.d.lu ft0, a0 ; RV64IFD-NEXT: fcvt.d.lu ft0, a0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
Show All 34 Lines

llvm/test/CodeGen/RISCV/double-frem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32ID %s ; RUN: | FileCheck -check-prefix=RV32ID %s
define double @frem_f64(double %a, double %b) nounwind { define double @frem_f64(double %a, double %b) nounwind {
; RV32ID-LABEL: frem_f64: ; RV32ID-LABEL: frem_f64:
; RV32ID: # %bb.0: ; RV32ID: # %bb.0:
; RV32ID-NEXT: addi sp, sp, -16 ; RV32ID-NEXT: addi sp, sp, -16
; RV32ID-NEXT: sw ra, 12(sp) ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32ID-NEXT: call fmod ; RV32ID-NEXT: call fmod@plt
; RV32ID-NEXT: lw ra, 12(sp) ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: addi sp, sp, 16
; RV32ID-NEXT: ret ; RV32ID-NEXT: ret
%1 = frem double %a, %b %1 = frem double %a, %b
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-intrinsics.ll

Show All 30 Lines
} }
declare double @llvm.powi.f64(double, i32) declare double @llvm.powi.f64(double, i32)
define double @powi_f64(double %a, i32 %b) nounwind { define double @powi_f64(double %a, i32 %b) nounwind {
; RV32IFD-LABEL: powi_f64: ; RV32IFD-LABEL: powi_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __powidf2 ; RV32IFD-NEXT: call __powidf2@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: powi_f64: ; RV64IFD-LABEL: powi_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sext.w a1, a1 ; RV64IFD-NEXT: sext.w a1, a1
; RV64IFD-NEXT: call __powidf2 ; RV64IFD-NEXT: call __powidf2@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.powi.f64(double %a, i32 %b) %1 = call double @llvm.powi.f64(double %a, i32 %b)
ret double %1 ret double %1
} }
declare double @llvm.sin.f64(double) declare double @llvm.sin.f64(double)
define double @sin_f64(double %a) nounwind { define double @sin_f64(double %a) nounwind {
; RV32IFD-LABEL: sin_f64: ; RV32IFD-LABEL: sin_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: call sin@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: sin_f64: ; RV64IFD-LABEL: sin_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: call sin@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.sin.f64(double %a) %1 = call double @llvm.sin.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.cos.f64(double) declare double @llvm.cos.f64(double)
define double @cos_f64(double %a) nounwind { define double @cos_f64(double %a) nounwind {
; RV32IFD-LABEL: cos_f64: ; RV32IFD-LABEL: cos_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: call cos@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: cos_f64: ; RV64IFD-LABEL: cos_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: call cos@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.cos.f64(double %a) %1 = call double @llvm.cos.f64(double %a)
ret double %1 ret double %1
} }
; The sin+cos combination results in an FSINCOS SelectionDAG node. ; The sin+cos combination results in an FSINCOS SelectionDAG node.
define double @sincos_f64(double %a) nounwind { define double @sincos_f64(double %a) nounwind {
; RV32IFD-LABEL: sincos_f64: ; RV32IFD-LABEL: sincos_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 24(sp) ; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s1, 20(sp) ; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: mv s0, a1 ; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0 ; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: call sin ; RV32IFD-NEXT: call sin@plt
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: mv a0, s1 ; RV32IFD-NEXT: mv a0, s1
; RV32IFD-NEXT: mv a1, s0 ; RV32IFD-NEXT: mv a1, s0
; RV32IFD-NEXT: call cos ; RV32IFD-NEXT: call cos@plt
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw s1, 20(sp) ; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 24(sp) ; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: sincos_f64: ; RV64IFD-LABEL: sincos_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32 ; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sd s0, 16(sp) ; RV64IFD-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: mv s0, a0 ; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: call sin ; RV64IFD-NEXT: call sin@plt
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp) ; RV64IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: mv a0, s0 ; RV64IFD-NEXT: mv a0, s0
; RV64IFD-NEXT: call cos ; RV64IFD-NEXT: call cos@plt
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 8(sp) ; RV64IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s0, 16(sp) ; RV64IFD-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: ld ra, 24(sp) ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32 ; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.sin.f64(double %a) %1 = call double @llvm.sin.f64(double %a)
%2 = call double @llvm.cos.f64(double %a) %2 = call double @llvm.cos.f64(double %a)
%3 = fadd double %1, %2 %3 = fadd double %1, %2
ret double %3 ret double %3
} }
declare double @llvm.pow.f64(double, double) declare double @llvm.pow.f64(double, double)
define double @pow_f64(double %a, double %b) nounwind { define double @pow_f64(double %a, double %b) nounwind {
; RV32IFD-LABEL: pow_f64: ; RV32IFD-LABEL: pow_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call pow ; RV32IFD-NEXT: call pow@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: pow_f64: ; RV64IFD-LABEL: pow_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call pow ; RV64IFD-NEXT: call pow@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.pow.f64(double %a, double %b) %1 = call double @llvm.pow.f64(double %a, double %b)
ret double %1 ret double %1
} }
declare double @llvm.exp.f64(double) declare double @llvm.exp.f64(double)
define double @exp_f64(double %a) nounwind { define double @exp_f64(double %a) nounwind {
; RV32IFD-LABEL: exp_f64: ; RV32IFD-LABEL: exp_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call exp ; RV32IFD-NEXT: call exp@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: exp_f64: ; RV64IFD-LABEL: exp_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call exp ; RV64IFD-NEXT: call exp@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.exp.f64(double %a) %1 = call double @llvm.exp.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.exp2.f64(double) declare double @llvm.exp2.f64(double)
define double @exp2_f64(double %a) nounwind { define double @exp2_f64(double %a) nounwind {
; RV32IFD-LABEL: exp2_f64: ; RV32IFD-LABEL: exp2_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call exp2 ; RV32IFD-NEXT: call exp2@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: exp2_f64: ; RV64IFD-LABEL: exp2_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call exp2 ; RV64IFD-NEXT: call exp2@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.exp2.f64(double %a) %1 = call double @llvm.exp2.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.log.f64(double) declare double @llvm.log.f64(double)
define double @log_f64(double %a) nounwind { define double @log_f64(double %a) nounwind {
; RV32IFD-LABEL: log_f64: ; RV32IFD-LABEL: log_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log ; RV32IFD-NEXT: call log@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: log_f64: ; RV64IFD-LABEL: log_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log ; RV64IFD-NEXT: call log@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.log.f64(double %a) %1 = call double @llvm.log.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.log10.f64(double) declare double @llvm.log10.f64(double)
define double @log10_f64(double %a) nounwind { define double @log10_f64(double %a) nounwind {
; RV32IFD-LABEL: log10_f64: ; RV32IFD-LABEL: log10_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log10 ; RV32IFD-NEXT: call log10@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: log10_f64: ; RV64IFD-LABEL: log10_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log10 ; RV64IFD-NEXT: call log10@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.log10.f64(double %a) %1 = call double @llvm.log10.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.log2.f64(double) declare double @llvm.log2.f64(double)
define double @log2_f64(double %a) nounwind { define double @log2_f64(double %a) nounwind {
; RV32IFD-LABEL: log2_f64: ; RV32IFD-LABEL: log2_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log2 ; RV32IFD-NEXT: call log2@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: log2_f64: ; RV64IFD-LABEL: log2_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log2 ; RV64IFD-NEXT: call log2@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.log2.f64(double %a) %1 = call double @llvm.log2.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.fma.f64(double, double, double) declare double @llvm.fma.f64(double, double, double)
▲ Show 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
} }
declare double @llvm.floor.f64(double) declare double @llvm.floor.f64(double)
define double @floor_f64(double %a) nounwind { define double @floor_f64(double %a) nounwind {
; RV32IFD-LABEL: floor_f64: ; RV32IFD-LABEL: floor_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call floor ; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: floor_f64: ; RV64IFD-LABEL: floor_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call floor ; RV64IFD-NEXT: call floor@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.floor.f64(double %a) %1 = call double @llvm.floor.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.ceil.f64(double) declare double @llvm.ceil.f64(double)
define double @ceil_f64(double %a) nounwind { define double @ceil_f64(double %a) nounwind {
; RV32IFD-LABEL: ceil_f64: ; RV32IFD-LABEL: ceil_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call ceil ; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: ceil_f64: ; RV64IFD-LABEL: ceil_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call ceil ; RV64IFD-NEXT: call ceil@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.ceil.f64(double %a) %1 = call double @llvm.ceil.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.trunc.f64(double) declare double @llvm.trunc.f64(double)
define double @trunc_f64(double %a) nounwind { define double @trunc_f64(double %a) nounwind {
; RV32IFD-LABEL: trunc_f64: ; RV32IFD-LABEL: trunc_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call trunc ; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: trunc_f64: ; RV64IFD-LABEL: trunc_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call trunc ; RV64IFD-NEXT: call trunc@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.trunc.f64(double %a) %1 = call double @llvm.trunc.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.rint.f64(double) declare double @llvm.rint.f64(double)
define double @rint_f64(double %a) nounwind { define double @rint_f64(double %a) nounwind {
; RV32IFD-LABEL: rint_f64: ; RV32IFD-LABEL: rint_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call rint ; RV32IFD-NEXT: call rint@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: rint_f64: ; RV64IFD-LABEL: rint_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call rint ; RV64IFD-NEXT: call rint@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.rint.f64(double %a) %1 = call double @llvm.rint.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.nearbyint.f64(double) declare double @llvm.nearbyint.f64(double)
define double @nearbyint_f64(double %a) nounwind { define double @nearbyint_f64(double %a) nounwind {
; RV32IFD-LABEL: nearbyint_f64: ; RV32IFD-LABEL: nearbyint_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call nearbyint ; RV32IFD-NEXT: call nearbyint@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: nearbyint_f64: ; RV64IFD-LABEL: nearbyint_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call nearbyint ; RV64IFD-NEXT: call nearbyint@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.nearbyint.f64(double %a) %1 = call double @llvm.nearbyint.f64(double %a)
ret double %1 ret double %1
} }
declare double @llvm.round.f64(double) declare double @llvm.round.f64(double)
define double @round_f64(double %a) nounwind { define double @round_f64(double %a) nounwind {
; RV32IFD-LABEL: round_f64: ; RV32IFD-LABEL: round_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call round ; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: round_f64: ; RV64IFD-LABEL: round_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call round ; RV64IFD-NEXT: call round@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.round.f64(double %a) %1 = call double @llvm.round.f64(double %a)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/double-mem.ll

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define double @fld_stack(double %a) nounwind { define double @fld_stack(double %a) nounwind {
; RV32IFD-LABEL: fld_stack: ; RV32IFD-LABEL: fld_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fld_stack: ; RV64IFD-LABEL: fld_stack:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32 ; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp) ; RV64IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: addi a0, sp, 16 ; RV64IFD-NEXT: addi a0, sp, 16
; RV64IFD-NEXT: call notdead ; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: fld ft0, 16(sp) ; RV64IFD-NEXT: fld ft0, 16(sp)
; RV64IFD-NEXT: fld ft1, 8(sp) ; RV64IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 24(sp) ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32 ; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = alloca double, align 8 %1 = alloca double, align 8
%2 = bitcast double* %1 to i8* %2 = bitcast double* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load double, double* %1 %3 = load double, double* %1
%4 = fadd double %3, %a ; force load in to FPR64 %4 = fadd double %3, %a ; force load in to FPR64
ret double %4 ret double %4
} }
define void @fsd_stack(double %a, double %b) nounwind { define void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-LABEL: fsd_stack: ; RV32IFD-LABEL: fsd_stack:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fsd_stack: ; RV64IFD-LABEL: fsd_stack:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) ; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: mv a0, sp ; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead ; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fadd double %a, %b ; force store from FPR64 %1 = fadd double %a, %b ; force store from FPR64
%2 = alloca double, align 8 %2 = alloca double, align 8
store double %1, double* %2 store double %1, double* %2
%3 = bitcast double* %2 to i8* %3 = bitcast double* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
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llvm/test/CodeGen/RISCV/double-previous-failure.ll

Show All 10 Lines
; This previously failed complaining of multiple vreg defs due to an ABI ; This previously failed complaining of multiple vreg defs due to an ABI
; lowering issue. ; lowering issue.
define i32 @main() nounwind { define i32 @main() nounwind {
; RV32IFD-LABEL: main: ; RV32IFD-LABEL: main:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero ; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call test ; RV32IFD-NEXT: call test
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: flt.d a0, ft0, ft1
; RV32IFD-NEXT: not a0, a0 ; RV32IFD-NEXT: not a0, a0
; RV32IFD-NEXT: flt.d a1, ft2, ft0 ; RV32IFD-NEXT: flt.d a1, ft2, ft0
; RV32IFD-NEXT: xori a1, a1, 1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: and a0, a0, a1 ; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB1_2 ; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then ; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort ; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: .LBB1_2: # %if.end ; RV32IFD-NEXT: .LBB1_2: # %if.end
; RV32IFD-NEXT: mv a0, zero ; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call exit ; RV32IFD-NEXT: call exit@plt
entry: entry:
%call = call double @test(double 2.000000e+00) %call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01 %cmp = fcmp olt double %call, 2.400000e-01
%cmp2 = fcmp ogt double %call, 2.600000e-01 %cmp2 = fcmp ogt double %call, 2.600000e-01
%or.cond = or i1 %cmp, %cmp2 %or.cond = or i1 %cmp, %cmp2
br i1 %or.cond, label %if.then, label %if.end br i1 %or.cond, label %if.then, label %if.end
if.then: if.then:
Show All 11 Lines

llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @func(double %d, i32 %n) nounwind { define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func: ; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: beqz a2, .LBB0_2 ; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1 ; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func ; RV32IFD-NEXT: call func
; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: .LBB0_2: # %return ; RV32IFD-NEXT: .LBB0_2: # %return
; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: func: ; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry ; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: slli a2, a1, 32 ; RV64IFD-NEXT: slli a2, a1, 32
; RV64IFD-NEXT: srli a2, a2, 32 ; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2 ; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1 ; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) ; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func ; RV64IFD-NEXT: call func
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 0(sp) ; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: .LBB0_2: # %return ; RV64IFD-NEXT: .LBB0_2: # %return
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 8(sp) ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
entry: entry:
%cmp = icmp eq i32 %n, 0 %cmp = icmp eq i32 %n, 0
br i1 %cmp, label %return, label %if.else br i1 %cmp, label %return, label %if.else
if.else: if.else:
%sub = add i32 %n, -1 %sub = add i32 %n, -1
%call = tail call double @func(double %d, i32 %sub) %call = tail call double @func(double %d, i32 %sub)
%add = fadd double %call, %d %add = fadd double %call, %d
ret double %add ret double %add
return: return:
ret double %d ret double %d
} }

llvm/test/CodeGen/RISCV/exception-pointer-register.ll

Show All 11 Lines
declare void @bar(i1* %p); declare void @bar(i1* %p);
declare dso_local i32 @__gxx_personality_v0(...) declare dso_local i32 @__gxx_personality_v0(...)
define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; RV32I-LABEL: caller: ; RV32I-LABEL: caller:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16 ; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8 ; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12 ; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.1: # %bb2 ; RV32I-NEXT: # %bb.1: # %bb2
; RV32I-NEXT: .Ltmp0: ; RV32I-NEXT: .Ltmp0:
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call bar ; RV32I-NEXT: call bar@plt
; RV32I-NEXT: .Ltmp1: ; RV32I-NEXT: .Ltmp1:
; RV32I-NEXT: j .LBB0_3 ; RV32I-NEXT: j .LBB0_3
; RV32I-NEXT: .LBB0_2: # %bb1 ; RV32I-NEXT: .LBB0_2: # %bb1
; RV32I-NEXT: .Ltmp2: ; RV32I-NEXT: .Ltmp2:
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .Ltmp3: ; RV32I-NEXT: .Ltmp3:
; RV32I-NEXT: .LBB0_3: # %end2 ; RV32I-NEXT: .LBB0_3: # %end2
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %lpad ; RV32I-NEXT: .LBB0_4: # %lpad
; RV32I-NEXT: .Ltmp4: ; RV32I-NEXT: .Ltmp4:
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call _Unwind_Resume ; RV32I-NEXT: call _Unwind_Resume@plt
; ;
; RV64I-LABEL: caller: ; RV64I-LABEL: caller:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32 ; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16 ; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24 ; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a0, .LBB0_2 ; RV64I-NEXT: beqz a0, .LBB0_2
; RV64I-NEXT: # %bb.1: # %bb2 ; RV64I-NEXT: # %bb.1: # %bb2
; RV64I-NEXT: .Ltmp0: ; RV64I-NEXT: .Ltmp0:
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call bar ; RV64I-NEXT: call bar@plt
; RV64I-NEXT: .Ltmp1: ; RV64I-NEXT: .Ltmp1:
; RV64I-NEXT: j .LBB0_3 ; RV64I-NEXT: j .LBB0_3
; RV64I-NEXT: .LBB0_2: # %bb1 ; RV64I-NEXT: .LBB0_2: # %bb1
; RV64I-NEXT: .Ltmp2: ; RV64I-NEXT: .Ltmp2:
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call foo ; RV64I-NEXT: call foo@plt
; RV64I-NEXT: .Ltmp3: ; RV64I-NEXT: .Ltmp3:
; RV64I-NEXT: .LBB0_3: # %end2 ; RV64I-NEXT: .LBB0_3: # %end2
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_4: # %lpad ; RV64I-NEXT: .LBB0_4: # %lpad
; RV64I-NEXT: .Ltmp4: ; RV64I-NEXT: .Ltmp4:
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call _Unwind_Resume ; RV64I-NEXT: call _Unwind_Resume@plt
entry: entry:
%0 = icmp eq i1* %p, null %0 = icmp eq i1* %p, null
br i1 %0, label %bb1, label %bb2 br i1 %0, label %bb1, label %bb2
bb1: bb1:
invoke void @foo(i1* %p) to label %end1 unwind label %lpad invoke void @foo(i1* %p) to label %end1 unwind label %lpad
bb2: bb2:
Show All 24 Lines

llvm/test/CodeGen/RISCV/fastcc-float.ll

Show All 11 Lines
} }
; With the fastcc, arguments will be passed by fa0-fa7 and ft0-ft11. ; With the fastcc, arguments will be passed by fa0-fa7 and ft0-ft11.
; The rest will be pushed on the stack. ; The rest will be pushed on the stack.
define float @caller(<32 x float> %A) nounwind { define float @caller(<32 x float> %A) nounwind {
; CHECK-LABEL: caller: ; CHECK-LABEL: caller:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -64 ; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: sw ra, 60(sp) ; CHECK-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; CHECK-NEXT: flw fa0, 0(a0) ; CHECK-NEXT: flw fa0, 0(a0)
; CHECK-NEXT: flw fa1, 4(a0) ; CHECK-NEXT: flw fa1, 4(a0)
; CHECK-NEXT: flw fa2, 8(a0) ; CHECK-NEXT: flw fa2, 8(a0)
; CHECK-NEXT: flw fa3, 12(a0) ; CHECK-NEXT: flw fa3, 12(a0)
; CHECK-NEXT: flw fa4, 16(a0) ; CHECK-NEXT: flw fa4, 16(a0)
; CHECK-NEXT: flw fa5, 20(a0) ; CHECK-NEXT: flw fa5, 20(a0)
; CHECK-NEXT: flw fa6, 24(a0) ; CHECK-NEXT: flw fa6, 24(a0)
; CHECK-NEXT: flw fa7, 28(a0) ; CHECK-NEXT: flw fa7, 28(a0)
Show All 29 Lines
; CHECK-NEXT: fsw fs6, 24(sp) ; CHECK-NEXT: fsw fs6, 24(sp)
; CHECK-NEXT: fsw fs5, 20(sp) ; CHECK-NEXT: fsw fs5, 20(sp)
; CHECK-NEXT: fsw fs4, 16(sp) ; CHECK-NEXT: fsw fs4, 16(sp)
; CHECK-NEXT: fsw fs3, 12(sp) ; CHECK-NEXT: fsw fs3, 12(sp)
; CHECK-NEXT: fsw fs2, 8(sp) ; CHECK-NEXT: fsw fs2, 8(sp)
; CHECK-NEXT: fsw fs1, 4(sp) ; CHECK-NEXT: fsw fs1, 4(sp)
; CHECK-NEXT: fsw fs0, 0(sp) ; CHECK-NEXT: fsw fs0, 0(sp)
; CHECK-NEXT: call callee ; CHECK-NEXT: call callee
; CHECK-NEXT: lw ra, 60(sp) ; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%C = call fastcc float @callee(<32 x float> %A) %C = call fastcc float @callee(<32 x float> %A)
ret float %C ret float %C
} }

llvm/test/CodeGen/RISCV/fastcc-int.ll

Show All 16 Lines
} }
; With the fastcc, arguments will be passed by a0-a7 and t2-t6. ; With the fastcc, arguments will be passed by a0-a7 and t2-t6.
; The rest will be pushed on the stack. ; The rest will be pushed on the stack.
define i32 @caller(<16 x i32> %A) nounwind { define i32 @caller(<16 x i32> %A) nounwind {
; RV32-LABEL: caller: ; RV32-LABEL: caller:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -32 ; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: sw ra, 28(sp) ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 24(sp) ; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32-NEXT: lw t0, 0(a0) ; RV32-NEXT: lw t0, 0(a0)
; RV32-NEXT: lw a1, 4(a0) ; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a2, 8(a0) ; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a3, 12(a0) ; RV32-NEXT: lw a3, 12(a0)
; RV32-NEXT: lw a4, 16(a0) ; RV32-NEXT: lw a4, 16(a0)
; RV32-NEXT: lw a5, 20(a0) ; RV32-NEXT: lw a5, 20(a0)
; RV32-NEXT: lw a6, 24(a0) ; RV32-NEXT: lw a6, 24(a0)
; RV32-NEXT: lw a7, 28(a0) ; RV32-NEXT: lw a7, 28(a0)
; RV32-NEXT: lw t2, 32(a0) ; RV32-NEXT: lw t2, 32(a0)
; RV32-NEXT: lw t3, 36(a0) ; RV32-NEXT: lw t3, 36(a0)
; RV32-NEXT: lw t4, 40(a0) ; RV32-NEXT: lw t4, 40(a0)
; RV32-NEXT: lw t5, 44(a0) ; RV32-NEXT: lw t5, 44(a0)
; RV32-NEXT: lw t6, 48(a0) ; RV32-NEXT: lw t6, 48(a0)
; RV32-NEXT: lw t1, 52(a0) ; RV32-NEXT: lw t1, 52(a0)
; RV32-NEXT: lw s0, 56(a0) ; RV32-NEXT: lw s0, 56(a0)
; RV32-NEXT: lw a0, 60(a0) ; RV32-NEXT: lw a0, 60(a0)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw s0, 4(sp) ; RV32-NEXT: sw s0, 4(sp)
; RV32-NEXT: sw t1, 0(sp) ; RV32-NEXT: sw t1, 0(sp)
; RV32-NEXT: mv a0, t0 ; RV32-NEXT: mv a0, t0
; RV32-NEXT: call callee ; RV32-NEXT: call callee
; RV32-NEXT: lw s0, 24(sp) ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 28(sp) ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: caller: ; RV64-LABEL: caller:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -48 ; RV64-NEXT: addi sp, sp, -48
; RV64-NEXT: sd ra, 40(sp) ; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 32(sp) ; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64-NEXT: ld t0, 0(a0) ; RV64-NEXT: ld t0, 0(a0)
; RV64-NEXT: ld a1, 8(a0) ; RV64-NEXT: ld a1, 8(a0)
; RV64-NEXT: ld a2, 16(a0) ; RV64-NEXT: ld a2, 16(a0)
; RV64-NEXT: ld a3, 24(a0) ; RV64-NEXT: ld a3, 24(a0)
; RV64-NEXT: ld a4, 32(a0) ; RV64-NEXT: ld a4, 32(a0)
; RV64-NEXT: ld a5, 40(a0) ; RV64-NEXT: ld a5, 40(a0)
; RV64-NEXT: ld a6, 48(a0) ; RV64-NEXT: ld a6, 48(a0)
; RV64-NEXT: ld a7, 56(a0) ; RV64-NEXT: ld a7, 56(a0)
; RV64-NEXT: ld t2, 64(a0) ; RV64-NEXT: ld t2, 64(a0)
; RV64-NEXT: ld t3, 72(a0) ; RV64-NEXT: ld t3, 72(a0)
; RV64-NEXT: ld t4, 80(a0) ; RV64-NEXT: ld t4, 80(a0)
; RV64-NEXT: ld t5, 88(a0) ; RV64-NEXT: ld t5, 88(a0)
; RV64-NEXT: ld t6, 96(a0) ; RV64-NEXT: ld t6, 96(a0)
; RV64-NEXT: ld t1, 104(a0) ; RV64-NEXT: ld t1, 104(a0)
; RV64-NEXT: ld s0, 112(a0) ; RV64-NEXT: ld s0, 112(a0)
; RV64-NEXT: ld a0, 120(a0) ; RV64-NEXT: ld a0, 120(a0)
; RV64-NEXT: sd a0, 16(sp) ; RV64-NEXT: sd a0, 16(sp)
; RV64-NEXT: sd s0, 8(sp) ; RV64-NEXT: sd s0, 8(sp)
; RV64-NEXT: sd t1, 0(sp) ; RV64-NEXT: sd t1, 0(sp)
; RV64-NEXT: mv a0, t0 ; RV64-NEXT: mv a0, t0
; RV64-NEXT: call callee ; RV64-NEXT: call callee
; RV64-NEXT: ld s0, 32(sp) ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 40(sp) ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 48 ; RV64-NEXT: addi sp, sp, 48
; RV64-NEXT: ret ; RV64-NEXT: ret
%C = call fastcc i32 @callee(<16 x i32> %A) %C = call fastcc i32 @callee(<16 x i32> %A)
ret i32 %C ret i32 %C
} }

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines; RV64FD-NEXT: ret
%a4 = fadd float %a1, %bc2 %a4 = fadd float %a1, %bc2
ret float %a4 ret float %a4
} }
define double @bitcast_double_and(double %a1, double %a2) nounwind { define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_and: ; RV32F-LABEL: bitcast_double_and:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16 ; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp) ; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) ; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0 ; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __adddf3 ; RV32F-NEXT: call __adddf3@plt
; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288 ; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: addi a0, a0, -1 ; RV32F-NEXT: addi a0, a0, -1
; RV32F-NEXT: and a3, a1, a0 ; RV32F-NEXT: and a3, a1, a0
; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0 ; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __adddf3 ; RV32F-NEXT: call __adddf3@plt
; RV32F-NEXT: lw s1, 4(sp) ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_and: ; RV32FD-LABEL: bitcast_double_and:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp) ; RV32FD-NEXT: fld ft0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp) ; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp) ; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp) ; RV32FD-NEXT: fld ft1, 8(sp)
; RV32FD-NEXT: fadd.d ft0, ft1, ft0 ; RV32FD-NEXT: fadd.d ft0, ft1, ft0
; RV32FD-NEXT: fabs.d ft0, ft0 ; RV32FD-NEXT: fabs.d ft0, ft0
; RV32FD-NEXT: fadd.d ft0, ft1, ft0 ; RV32FD-NEXT: fadd.d ft0, ft1, ft0
; RV32FD-NEXT: fsd ft0, 8(sp) ; RV32FD-NEXT: fsd ft0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_and: ; RV64F-LABEL: bitcast_double_and:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __adddf3 ; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: addi a1, zero, -1 ; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: addi a1, a1, -1 ; RV64F-NEXT: addi a1, a1, -1
; RV64F-NEXT: and a1, a0, a1 ; RV64F-NEXT: and a1, a0, a1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __adddf3 ; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: ld s0, 0(sp) ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_and: ; RV64FD-LABEL: bitcast_double_and:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fadd.d ft0, ft1, ft0 ; RV64FD-NEXT: fadd.d ft0, ft1, ft0
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines; RV64FD-NEXT: ret
%a4 = fmul float %a1, %bc2 %a4 = fmul float %a1, %bc2
ret float %a4 ret float %a4
} }
define double @bitcast_double_xor(double %a1, double %a2) nounwind { define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_xor: ; RV32F-LABEL: bitcast_double_xor:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16 ; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp) ; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) ; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0 ; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288 ; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: xor a3, a1, a0 ; RV32F-NEXT: xor a3, a1, a0
; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0 ; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_xor: ; RV32FD-LABEL: bitcast_double_xor:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp) ; RV32FD-NEXT: fld ft0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp) ; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp) ; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp) ; RV32FD-NEXT: fld ft1, 8(sp)
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fneg.d ft0, ft0 ; RV32FD-NEXT: fneg.d ft0, ft0
; RV32FD-NEXT: fmul.d ft0, ft1, ft0 ; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fsd ft0, 8(sp) ; RV32FD-NEXT: fsd ft0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_xor: ; RV64F-LABEL: bitcast_double_xor:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: addi a1, zero, -1 ; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: xor a1, a0, a1 ; RV64F-NEXT: xor a1, a0, a1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_xor: ; RV64FD-LABEL: bitcast_double_xor:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d ft0, ft1, ft0
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines; RV64FD-NEXT: ret
%a4 = fmul float %a1, %bc2 %a4 = fmul float %a1, %bc2
ret float %a4 ret float %a4
} }
define double @bitcast_double_or(double %a1, double %a2) nounwind { define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_or: ; RV32F-LABEL: bitcast_double_or:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16 ; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp) ; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) ; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) ; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1 ; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0 ; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: mv a2, a0 ; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288 ; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: or a3, a1, a0 ; RV32F-NEXT: or a3, a1, a0
; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0 ; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3 ; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) ; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) ; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) ; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16 ; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV32FD-LABEL: bitcast_double_or: ; RV32FD-LABEL: bitcast_double_or:
; RV32FD: # %bb.0: ; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16 ; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp) ; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp) ; RV32FD-NEXT: sw a3, 12(sp)
Show All 9 Lines
; RV32FD-NEXT: lw a0, 8(sp) ; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp) ; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16 ; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret ; RV32FD-NEXT: ret
; ;
; RV64F-LABEL: bitcast_double_or: ; RV64F-LABEL: bitcast_double_or:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16 ; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp) ; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) ; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0 ; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: addi a1, zero, -1 ; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63 ; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: or a1, a0, a1 ; RV64F-NEXT: or a1, a0, a1
; RV64F-NEXT: mv a0, s0 ; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3 ; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) ; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) ; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16 ; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV64FD-LABEL: bitcast_double_or: ; RV64FD-LABEL: bitcast_double_or:
; RV64FD: # %bb.0: ; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1 ; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0 ; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0 ; RV64FD-NEXT: fmul.d ft0, ft1, ft0
Show All 12 Lines

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
declare float @dummy(float) declare float @dummy(float)
define void @br_fcmp_false(float %a, float %b) nounwind { define void @br_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_false: ; RV32IF-LABEL: br_fcmp_false:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: bnez a0, .LBB0_2 ; RV32IF-NEXT: bnez a0, .LBB0_2
; RV32IF-NEXT: # %bb.1: # %if.then ; RV32IF-NEXT: # %bb.1: # %if.then
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB0_2: # %if.else ; RV32IF-NEXT: .LBB0_2: # %if.else
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_false: ; RV64IF-LABEL: br_fcmp_false:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: addi a0, zero, 1 ; RV64IF-NEXT: addi a0, zero, 1
; RV64IF-NEXT: bnez a0, .LBB0_2 ; RV64IF-NEXT: bnez a0, .LBB0_2
; RV64IF-NEXT: # %bb.1: # %if.then ; RV64IF-NEXT: # %bb.1: # %if.then
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB0_2: # %if.else ; RV64IF-NEXT: .LBB0_2: # %if.else
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp false float %a, %b %1 = fcmp false float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
ret void ret void
if.else: if.else:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oeq(float %a, float %b) nounwind { define void @br_fcmp_oeq(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oeq: ; RV32IF-LABEL: br_fcmp_oeq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB1_2 ; RV32IF-NEXT: bnez a0, .LBB1_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB1_2: # %if.then ; RV32IF-NEXT: .LBB1_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_oeq: ; RV64IF-LABEL: br_fcmp_oeq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB1_2 ; RV64IF-NEXT: bnez a0, .LBB1_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB1_2: # %if.then ; RV64IF-NEXT: .LBB1_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: generated code quality for this is very poor due to ; TODO: generated code quality for this is very poor due to
; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires ; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
; expansion. ; expansion.
define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oeq_alt: ; RV32IF-LABEL: br_fcmp_oeq_alt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: beqz a0, .LBB2_2 ; RV32IF-NEXT: beqz a0, .LBB2_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB2_2: # %if.then ; RV32IF-NEXT: .LBB2_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_oeq_alt: ; RV64IF-LABEL: br_fcmp_oeq_alt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: beqz a0, .LBB2_2 ; RV64IF-NEXT: beqz a0, .LBB2_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB2_2: # %if.then ; RV64IF-NEXT: .LBB2_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
if.else: if.else:
ret void ret void
} }
define void @br_fcmp_ogt(float %a, float %b) nounwind { define void @br_fcmp_ogt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ogt: ; RV32IF-LABEL: br_fcmp_ogt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB3_2 ; RV32IF-NEXT: bnez a0, .LBB3_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB3_2: # %if.then ; RV32IF-NEXT: .LBB3_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ogt: ; RV64IF-LABEL: br_fcmp_ogt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB3_2 ; RV64IF-NEXT: bnez a0, .LBB3_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB3_2: # %if.then ; RV64IF-NEXT: .LBB3_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ogt float %a, %b %1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oge(float %a, float %b) nounwind { define void @br_fcmp_oge(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oge: ; RV32IF-LABEL: br_fcmp_oge:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB4_2 ; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: # %if.then ; RV32IF-NEXT: .LBB4_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_oge: ; RV64IF-LABEL: br_fcmp_oge:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB4_2 ; RV64IF-NEXT: bnez a0, .LBB4_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB4_2: # %if.then ; RV64IF-NEXT: .LBB4_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp oge float %a, %b %1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_olt(float %a, float %b) nounwind { define void @br_fcmp_olt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_olt: ; RV32IF-LABEL: br_fcmp_olt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB5_2 ; RV32IF-NEXT: bnez a0, .LBB5_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB5_2: # %if.then ; RV32IF-NEXT: .LBB5_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_olt: ; RV64IF-LABEL: br_fcmp_olt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB5_2 ; RV64IF-NEXT: bnez a0, .LBB5_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB5_2: # %if.then ; RV64IF-NEXT: .LBB5_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp olt float %a, %b %1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ole(float %a, float %b) nounwind { define void @br_fcmp_ole(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ole: ; RV32IF-LABEL: br_fcmp_ole:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB6_2 ; RV32IF-NEXT: bnez a0, .LBB6_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB6_2: # %if.then ; RV32IF-NEXT: .LBB6_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ole: ; RV64IF-LABEL: br_fcmp_ole:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB6_2 ; RV64IF-NEXT: bnez a0, .LBB6_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB6_2: # %if.then ; RV64IF-NEXT: .LBB6_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.s+sltiu+bne -> feq.s+beq ; TODO: feq.s+sltiu+bne -> feq.s+beq
define void @br_fcmp_one(float %a, float %b) nounwind { define void @br_fcmp_one(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_one: ; RV32IF-LABEL: br_fcmp_one:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1 ; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1 ; RV32IF-NEXT: not a1, a1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB7_2 ; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB7_2: # %if.then ; RV32IF-NEXT: .LBB7_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_one: ; RV64IF-LABEL: br_fcmp_one:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1 ; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1 ; RV64IF-NEXT: not a1, a1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB7_2 ; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB7_2: # %if.then ; RV64IF-NEXT: .LBB7_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ord(float %a, float %b) nounwind { define void @br_fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ord: ; RV32IF-LABEL: br_fcmp_ord:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB8_2: # %if.then ; RV32IF-NEXT: .LBB8_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ord: ; RV64IF-LABEL: br_fcmp_ord:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB8_2: # %if.then ; RV64IF-NEXT: .LBB8_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ueq(float %a, float %b) nounwind { define void @br_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ueq: ; RV32IF-LABEL: br_fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: feq.s a2, ft1, ft1 ; RV32IF-NEXT: feq.s a2, ft1, ft1
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: or a0, a0, a1 ; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB9_2 ; RV32IF-NEXT: bnez a0, .LBB9_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then ; RV32IF-NEXT: .LBB9_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ueq: ; RV64IF-LABEL: br_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: feq.s a2, ft1, ft1 ; RV64IF-NEXT: feq.s a2, ft1, ft1
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: or a0, a0, a1 ; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB9_2 ; RV64IF-NEXT: bnez a0, .LBB9_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB9_2: # %if.then ; RV64IF-NEXT: .LBB9_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ugt(float %a, float %b) nounwind { define void @br_fcmp_ugt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ugt: ; RV32IF-LABEL: br_fcmp_ugt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB10_2 ; RV32IF-NEXT: bnez a0, .LBB10_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB10_2: # %if.then ; RV32IF-NEXT: .LBB10_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ugt: ; RV64IF-LABEL: br_fcmp_ugt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB10_2 ; RV64IF-NEXT: bnez a0, .LBB10_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB10_2: # %if.then ; RV64IF-NEXT: .LBB10_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ugt float %a, %b %1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uge(float %a, float %b) nounwind { define void @br_fcmp_uge(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_uge: ; RV32IF-LABEL: br_fcmp_uge:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB11_2 ; RV32IF-NEXT: bnez a0, .LBB11_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB11_2: # %if.then ; RV32IF-NEXT: .LBB11_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_uge: ; RV64IF-LABEL: br_fcmp_uge:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB11_2 ; RV64IF-NEXT: bnez a0, .LBB11_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB11_2: # %if.then ; RV64IF-NEXT: .LBB11_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp uge float %a, %b %1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ult(float %a, float %b) nounwind { define void @br_fcmp_ult(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ult: ; RV32IF-LABEL: br_fcmp_ult:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB12_2 ; RV32IF-NEXT: bnez a0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_2: # %if.then ; RV32IF-NEXT: .LBB12_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ult: ; RV64IF-LABEL: br_fcmp_ult:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB12_2 ; RV64IF-NEXT: bnez a0, .LBB12_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB12_2: # %if.then ; RV64IF-NEXT: .LBB12_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ult float %a, %b %1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ule(float %a, float %b) nounwind { define void @br_fcmp_ule(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ule: ; RV32IF-LABEL: br_fcmp_ule:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB13_2 ; RV32IF-NEXT: bnez a0, .LBB13_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB13_2: # %if.then ; RV32IF-NEXT: .LBB13_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ule: ; RV64IF-LABEL: br_fcmp_ule:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB13_2 ; RV64IF-NEXT: bnez a0, .LBB13_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB13_2: # %if.then ; RV64IF-NEXT: .LBB13_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp ule float %a, %b %1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_une(float %a, float %b) nounwind { define void @br_fcmp_une(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_une: ; RV32IF-LABEL: br_fcmp_une:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB14_2 ; RV32IF-NEXT: bnez a0, .LBB14_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_2: # %if.then ; RV32IF-NEXT: .LBB14_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_une: ; RV64IF-LABEL: br_fcmp_une:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB14_2 ; RV64IF-NEXT: bnez a0, .LBB14_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB14_2: # %if.then ; RV64IF-NEXT: .LBB14_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp une float %a, %b %1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uno(float %a, float %b) nounwind { define void @br_fcmp_uno(float %a, float %b) nounwind {
; TODO: sltiu+bne -> beq ; TODO: sltiu+bne -> beq
; RV32IF-LABEL: br_fcmp_uno: ; RV32IF-LABEL: br_fcmp_uno:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0 ; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: bnez a0, .LBB15_2 ; RV32IF-NEXT: bnez a0, .LBB15_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then ; RV32IF-NEXT: .LBB15_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_uno: ; RV64IF-LABEL: br_fcmp_uno:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0 ; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: bnez a0, .LBB15_2 ; RV64IF-NEXT: bnez a0, .LBB15_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB15_2: # %if.then ; RV64IF-NEXT: .LBB15_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_true(float %a, float %b) nounwind { define void @br_fcmp_true(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_true: ; RV32IF-LABEL: br_fcmp_true:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: addi a0, zero, 1 ; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: bnez a0, .LBB16_2 ; RV32IF-NEXT: bnez a0, .LBB16_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB16_2: # %if.then ; RV32IF-NEXT: .LBB16_2: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_true: ; RV64IF-LABEL: br_fcmp_true:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: addi a0, zero, 1 ; RV64IF-NEXT: addi a0, zero, 1
; RV64IF-NEXT: bnez a0, .LBB16_2 ; RV64IF-NEXT: bnez a0, .LBB16_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB16_2: # %if.then ; RV64IF-NEXT: .LBB16_2: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
%1 = fcmp true float %a, %b %1 = fcmp true float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot ; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
; and RISCVInstrInfo::loadRegFromStackSlot ; and RISCVInstrInfo::loadRegFromStackSlot
define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw ; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
; RV32IF-LABEL: br_fcmp_store_load_stack_slot: ; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
; RV32IF: # %bb.0: # %entry ; RV32IF: # %bb.0: # %entry
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv a0, zero ; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: call dummy ; RV32IF-NEXT: call dummy@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, zero ; RV32IF-NEXT: fmv.w.x ft1, zero
; RV32IF-NEXT: fsw ft1, 8(sp) ; RV32IF-NEXT: fsw ft1, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.1: # %if.end ; RV32IF-NEXT: # %bb.1: # %if.end
; RV32IF-NEXT: mv a0, zero ; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: call dummy ; RV32IF-NEXT: call dummy@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: flw ft1, 8(sp) ; RV32IF-NEXT: flw ft1, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.2: # %if.end4 ; RV32IF-NEXT: # %bb.2: # %if.end4
; RV32IF-NEXT: mv a0, zero ; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB17_3: # %if.then ; RV32IF-NEXT: .LBB17_3: # %if.then
; RV32IF-NEXT: call abort ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_store_load_stack_slot: ; RV64IF-LABEL: br_fcmp_store_load_stack_slot:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -32 ; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp) ; RV64IF-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 16(sp) ; RV64IF-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, zero ; RV64IF-NEXT: fmv.w.x ft0, zero
; RV64IF-NEXT: fsw ft0, 12(sp) ; RV64IF-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.x.w s0, ft0 ; RV64IF-NEXT: fmv.x.w s0, ft0
; RV64IF-NEXT: mv a0, s0 ; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call dummy ; RV64IF-NEXT: call dummy@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: flw ft1, 12(sp) ; RV64IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: feq.s a0, ft0, ft1 ; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: beqz a0, .LBB17_3 ; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.1: # %if.end ; RV64IF-NEXT: # %bb.1: # %if.end
; RV64IF-NEXT: mv a0, s0 ; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call dummy ; RV64IF-NEXT: call dummy@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: flw ft1, 12(sp) ; RV64IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: feq.s a0, ft0, ft1 ; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: beqz a0, .LBB17_3 ; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.2: # %if.end4 ; RV64IF-NEXT: # %bb.2: # %if.end4
; RV64IF-NEXT: mv a0, zero ; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: ld s0, 16(sp) ; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 24(sp) ; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 32 ; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB17_3: # %if.then ; RV64IF-NEXT: .LBB17_3: # %if.then
; RV64IF-NEXT: call abort ; RV64IF-NEXT: call abort@plt
entry: entry:
%call = call float @dummy(float 0.000000e+00) %call = call float @dummy(float 0.000000e+00)
%cmp = fcmp une float %call, 0.000000e+00 %cmp = fcmp une float %call, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
call void @abort() call void @abort()
unreachable unreachable
Show All 13 Lines

llvm/test/CodeGen/RISCV/float-convert.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; Ensure fmv.w.x is generated even for a soft float calling convention
%3 = fadd float %1, %2 %3 = fadd float %1, %2
ret float %3 ret float %3
} }
define i64 @fcvt_l_s(float %a) nounwind { define i64 @fcvt_l_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_l_s: ; RV32IF-LABEL: fcvt_l_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __fixsfdi ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_l_s: ; RV64IF-LABEL: fcvt_l_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptosi float %a to i64 %1 = fptosi float %a to i64
ret i64 %1 ret i64 %1
} }
define i64 @fcvt_lu_s(float %a) nounwind { define i64 @fcvt_lu_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_lu_s: ; RV32IF-LABEL: fcvt_lu_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __fixunssfdi ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_lu_s: ; RV64IF-LABEL: fcvt_lu_s:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fptoui float %a to i64 %1 = fptoui float %a to i64
ret i64 %1 ret i64 %1
} }
define float @fcvt_s_l(i64 %a) nounwind { define float @fcvt_s_l(i64 %a) nounwind {
; RV32IF-LABEL: fcvt_s_l: ; RV32IF-LABEL: fcvt_s_l:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __floatdisf ; RV32IF-NEXT: call __floatdisf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_l: ; RV64IF-LABEL: fcvt_s_l:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.l ft0, a0 ; RV64IF-NEXT: fcvt.s.l ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = sitofp i64 %a to float %1 = sitofp i64 %a to float
ret float %1 ret float %1
} }
define float @fcvt_s_lu(i64 %a) nounwind { define float @fcvt_s_lu(i64 %a) nounwind {
; RV32IF-LABEL: fcvt_s_lu: ; RV32IF-LABEL: fcvt_s_lu:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __floatundisf ; RV32IF-NEXT: call __floatundisf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_s_lu: ; RV64IF-LABEL: fcvt_s_lu:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.lu ft0, a0 ; RV64IF-NEXT: fcvt.s.lu ft0, a0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = uitofp i64 %a to float %1 = uitofp i64 %a to float
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-frem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
define float @frem_f32(float %a, float %b) nounwind { define float @frem_f32(float %a, float %b) nounwind {
; RV32IF-LABEL: frem_f32: ; RV32IF-LABEL: frem_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call fmodf ; RV32IF-NEXT: call fmodf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
%1 = frem float %a, %b %1 = frem float %a, %b
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-intrinsics.ll

Show All 28 Lines
} }
declare float @llvm.powi.f32(float, i32) declare float @llvm.powi.f32(float, i32)
define float @powi_f32(float %a, i32 %b) nounwind { define float @powi_f32(float %a, i32 %b) nounwind {
; RV32IF-LABEL: powi_f32: ; RV32IF-LABEL: powi_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __powisf2 ; RV32IF-NEXT: call __powisf2@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: powi_f32: ; RV64IF-LABEL: powi_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sext.w a1, a1 ; RV64IF-NEXT: sext.w a1, a1
; RV64IF-NEXT: call __powisf2 ; RV64IF-NEXT: call __powisf2@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.powi.f32(float %a, i32 %b) %1 = call float @llvm.powi.f32(float %a, i32 %b)
ret float %1 ret float %1
} }
declare float @llvm.sin.f32(float) declare float @llvm.sin.f32(float)
define float @sin_f32(float %a) nounwind { define float @sin_f32(float %a) nounwind {
; RV32IF-LABEL: sin_f32: ; RV32IF-LABEL: sin_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call sinf ; RV32IF-NEXT: call sinf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: sin_f32: ; RV64IF-LABEL: sin_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call sinf ; RV64IF-NEXT: call sinf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.sin.f32(float %a) %1 = call float @llvm.sin.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.cos.f32(float) declare float @llvm.cos.f32(float)
define float @cos_f32(float %a) nounwind { define float @cos_f32(float %a) nounwind {
; RV32IF-LABEL: cos_f32: ; RV32IF-LABEL: cos_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call cosf ; RV32IF-NEXT: call cosf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: cos_f32: ; RV64IF-LABEL: cos_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call cosf ; RV64IF-NEXT: call cosf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.cos.f32(float %a) %1 = call float @llvm.cos.f32(float %a)
ret float %1 ret float %1
} }
; The sin+cos combination results in an FSINCOS SelectionDAG node. ; The sin+cos combination results in an FSINCOS SelectionDAG node.
define float @sincos_f32(float %a) nounwind { define float @sincos_f32(float %a) nounwind {
; RV32IF-LABEL: sincos_f32: ; RV32IF-LABEL: sincos_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a0 ; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: call sinf ; RV32IF-NEXT: call sinf@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp) ; RV32IF-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv a0, s0 ; RV32IF-NEXT: mv a0, s0
; RV32IF-NEXT: call cosf ; RV32IF-NEXT: call cosf@plt
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: flw ft1, 4(sp) ; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s0, 8(sp) ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: sincos_f32: ; RV64IF-LABEL: sincos_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32 ; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp) ; RV64IF-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 16(sp) ; RV64IF-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a0 ; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: call sinf ; RV64IF-NEXT: call sinf@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 12(sp) ; RV64IF-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: mv a0, s0 ; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call cosf ; RV64IF-NEXT: call cosf@plt
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: flw ft1, 12(sp) ; RV64IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s0, 16(sp) ; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 24(sp) ; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 32 ; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.sin.f32(float %a) %1 = call float @llvm.sin.f32(float %a)
%2 = call float @llvm.cos.f32(float %a) %2 = call float @llvm.cos.f32(float %a)
%3 = fadd float %1, %2 %3 = fadd float %1, %2
ret float %3 ret float %3
} }
declare float @llvm.pow.f32(float, float) declare float @llvm.pow.f32(float, float)
define float @pow_f32(float %a, float %b) nounwind { define float @pow_f32(float %a, float %b) nounwind {
; RV32IF-LABEL: pow_f32: ; RV32IF-LABEL: pow_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call powf ; RV32IF-NEXT: call powf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: pow_f32: ; RV64IF-LABEL: pow_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call powf ; RV64IF-NEXT: call powf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.pow.f32(float %a, float %b) %1 = call float @llvm.pow.f32(float %a, float %b)
ret float %1 ret float %1
} }
declare float @llvm.exp.f32(float) declare float @llvm.exp.f32(float)
define float @exp_f32(float %a) nounwind { define float @exp_f32(float %a) nounwind {
; RV32IF-LABEL: exp_f32: ; RV32IF-LABEL: exp_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call expf ; RV32IF-NEXT: call expf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: exp_f32: ; RV64IF-LABEL: exp_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call expf ; RV64IF-NEXT: call expf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.exp.f32(float %a) %1 = call float @llvm.exp.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.exp2.f32(float) declare float @llvm.exp2.f32(float)
define float @exp2_f32(float %a) nounwind { define float @exp2_f32(float %a) nounwind {
; RV32IF-LABEL: exp2_f32: ; RV32IF-LABEL: exp2_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call exp2f ; RV32IF-NEXT: call exp2f@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: exp2_f32: ; RV64IF-LABEL: exp2_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call exp2f ; RV64IF-NEXT: call exp2f@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.exp2.f32(float %a) %1 = call float @llvm.exp2.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.log.f32(float) declare float @llvm.log.f32(float)
define float @log_f32(float %a) nounwind { define float @log_f32(float %a) nounwind {
; RV32IF-LABEL: log_f32: ; RV32IF-LABEL: log_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call logf ; RV32IF-NEXT: call logf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: log_f32: ; RV64IF-LABEL: log_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call logf ; RV64IF-NEXT: call logf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.log.f32(float %a) %1 = call float @llvm.log.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.log10.f32(float) declare float @llvm.log10.f32(float)
define float @log10_f32(float %a) nounwind { define float @log10_f32(float %a) nounwind {
; RV32IF-LABEL: log10_f32: ; RV32IF-LABEL: log10_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call log10f ; RV32IF-NEXT: call log10f@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: log10_f32: ; RV64IF-LABEL: log10_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call log10f ; RV64IF-NEXT: call log10f@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.log10.f32(float %a) %1 = call float @llvm.log10.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.log2.f32(float) declare float @llvm.log2.f32(float)
define float @log2_f32(float %a) nounwind { define float @log2_f32(float %a) nounwind {
; RV32IF-LABEL: log2_f32: ; RV32IF-LABEL: log2_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call log2f ; RV32IF-NEXT: call log2f@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: log2_f32: ; RV64IF-LABEL: log2_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call log2f ; RV64IF-NEXT: call log2f@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.log2.f32(float %a) %1 = call float @llvm.log2.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.fma.f32(float, float, float) declare float @llvm.fma.f32(float, float, float)
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
} }
declare float @llvm.floor.f32(float) declare float @llvm.floor.f32(float)
define float @floor_f32(float %a) nounwind { define float @floor_f32(float %a) nounwind {
; RV32IF-LABEL: floor_f32: ; RV32IF-LABEL: floor_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call floorf ; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: floor_f32: ; RV64IF-LABEL: floor_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call floorf ; RV64IF-NEXT: call floorf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.floor.f32(float %a) %1 = call float @llvm.floor.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.ceil.f32(float) declare float @llvm.ceil.f32(float)
define float @ceil_f32(float %a) nounwind { define float @ceil_f32(float %a) nounwind {
; RV32IF-LABEL: ceil_f32: ; RV32IF-LABEL: ceil_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call ceilf ; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: ceil_f32: ; RV64IF-LABEL: ceil_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call ceilf ; RV64IF-NEXT: call ceilf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.ceil.f32(float %a) %1 = call float @llvm.ceil.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.trunc.f32(float) declare float @llvm.trunc.f32(float)
define float @trunc_f32(float %a) nounwind { define float @trunc_f32(float %a) nounwind {
; RV32IF-LABEL: trunc_f32: ; RV32IF-LABEL: trunc_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call truncf ; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: trunc_f32: ; RV64IF-LABEL: trunc_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call truncf ; RV64IF-NEXT: call truncf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.trunc.f32(float %a) %1 = call float @llvm.trunc.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.rint.f32(float) declare float @llvm.rint.f32(float)
define float @rint_f32(float %a) nounwind { define float @rint_f32(float %a) nounwind {
; RV32IF-LABEL: rint_f32: ; RV32IF-LABEL: rint_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call rintf ; RV32IF-NEXT: call rintf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: rint_f32: ; RV64IF-LABEL: rint_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call rintf ; RV64IF-NEXT: call rintf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.rint.f32(float %a) %1 = call float @llvm.rint.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.nearbyint.f32(float) declare float @llvm.nearbyint.f32(float)
define float @nearbyint_f32(float %a) nounwind { define float @nearbyint_f32(float %a) nounwind {
; RV32IF-LABEL: nearbyint_f32: ; RV32IF-LABEL: nearbyint_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call nearbyintf ; RV32IF-NEXT: call nearbyintf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: nearbyint_f32: ; RV64IF-LABEL: nearbyint_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call nearbyintf ; RV64IF-NEXT: call nearbyintf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.nearbyint.f32(float %a) %1 = call float @llvm.nearbyint.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.round.f32(float) declare float @llvm.round.f32(float)
define float @round_f32(float %a) nounwind { define float @round_f32(float %a) nounwind {
; RV32IF-LABEL: round_f32: ; RV32IF-LABEL: round_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundf ; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: round_f32: ; RV64IF-LABEL: round_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call roundf ; RV64IF-NEXT: call roundf@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.round.f32(float %a) %1 = call float @llvm.round.f32(float %a)
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/float-mem.ll

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define float @flw_stack(float %a) nounwind { define float @flw_stack(float %a) nounwind {
; RV32IF-LABEL: flw_stack: ; RV32IF-LABEL: flw_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp) ; RV32IF-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: addi a0, sp, 8 ; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead ; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: flw ft0, 8(sp) ; RV32IF-NEXT: flw ft0, 8(sp)
; RV32IF-NEXT: flw ft1, 4(sp) ; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: flw_stack: ; RV64IF-LABEL: flw_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 0(sp) ; RV64IF-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill
; RV64IF-NEXT: addi a0, sp, 4 ; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead ; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: flw ft0, 4(sp) ; RV64IF-NEXT: flw ft0, 4(sp)
; RV64IF-NEXT: flw ft1, 0(sp) ; RV64IF-NEXT: flw ft1, 0(sp) # 4-byte Folded Reload
; RV64IF-NEXT: fadd.s ft0, ft0, ft1 ; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = alloca float, align 4 %1 = alloca float, align 4
%2 = bitcast float* %1 to i8* %2 = bitcast float* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load float, float* %1 %3 = load float, float* %1
%4 = fadd float %3, %a ; force load in to FPR32 %4 = fadd float %3, %a ; force load in to FPR32
ret float %4 ret float %4
} }
define void @fsw_stack(float %a, float %b) nounwind { define void @fsw_stack(float %a, float %b) nounwind {
; RV32IF-LABEL: fsw_stack: ; RV32IF-LABEL: fsw_stack:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, 8(sp) ; RV32IF-NEXT: fsw ft0, 8(sp)
; RV32IF-NEXT: addi a0, sp, 8 ; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead ; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fsw_stack: ; RV64IF-LABEL: fsw_stack:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0 ; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fsw ft0, 4(sp) ; RV64IF-NEXT: fsw ft0, 4(sp)
; RV64IF-NEXT: addi a0, sp, 4 ; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead ; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b ; force store from FPR32 %1 = fadd float %a, %b ; force store from FPR32
%2 = alloca float, align 4 %2 = alloca float, align 4
store float %1, float* %2 store float %1, float* %2
%3 = bitcast float* %2 to i8* %3 = bitcast float* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
} }

llvm/test/CodeGen/RISCV/fp128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
; Besides anything else, these tests help verify that libcall ABI lowering ; Besides anything else, these tests help verify that libcall ABI lowering
; works correctly ; works correctly
define i32 @test_load_and_cmp() nounwind { define i32 @test_load_and_cmp() nounwind {
; RV32I-LABEL: test_load_and_cmp: ; RV32I-LABEL: test_load_and_cmp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0) ; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0) ; RV32I-NEXT: lw a7, %lo(x+4)(a0)
; RV32I-NEXT: lw a3, %lo(x+8)(a0) ; RV32I-NEXT: lw a3, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4) ; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a2, %lo(y+4)(a4) ; RV32I-NEXT: lw a2, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4) ; RV32I-NEXT: lw a1, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4) ; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 20(sp) ; RV32I-NEXT: sw a4, 20(sp)
; RV32I-NEXT: sw a1, 16(sp) ; RV32I-NEXT: sw a1, 16(sp)
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: sw a5, 8(sp) ; RV32I-NEXT: sw a5, 8(sp)
; RV32I-NEXT: sw a0, 36(sp) ; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: sw a3, 32(sp) ; RV32I-NEXT: sw a3, 32(sp)
; RV32I-NEXT: sw a7, 28(sp) ; RV32I-NEXT: sw a7, 28(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 24(sp) ; RV32I-NEXT: sw a6, 24(sp)
; RV32I-NEXT: call __netf2 ; RV32I-NEXT: call __netf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16 %1 = load fp128, fp128* @x, align 16
%2 = load fp128, fp128* @y, align 16 %2 = load fp128, fp128* @y, align 16
%cmp = fcmp une fp128 %1, %2 %cmp = fcmp une fp128 %1, %2
%3 = zext i1 %cmp to i32 %3 = zext i1 %cmp to i32
ret i32 %3 ret i32 %3
} }
define i32 @test_add_and_fptosi() nounwind { define i32 @test_add_and_fptosi() nounwind {
; RV32I-LABEL: test_add_and_fptosi: ; RV32I-LABEL: test_add_and_fptosi:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80 ; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp) ; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0) ; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0) ; RV32I-NEXT: lw a7, %lo(x+4)(a0)
; RV32I-NEXT: lw a2, %lo(x+8)(a0) ; RV32I-NEXT: lw a2, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4) ; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a3, %lo(y+4)(a4) ; RV32I-NEXT: lw a3, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4) ; RV32I-NEXT: lw a1, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4) ; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 36(sp) ; RV32I-NEXT: sw a4, 36(sp)
; RV32I-NEXT: sw a1, 32(sp) ; RV32I-NEXT: sw a1, 32(sp)
; RV32I-NEXT: sw a3, 28(sp) ; RV32I-NEXT: sw a3, 28(sp)
; RV32I-NEXT: sw a5, 24(sp) ; RV32I-NEXT: sw a5, 24(sp)
; RV32I-NEXT: sw a0, 52(sp) ; RV32I-NEXT: sw a0, 52(sp)
; RV32I-NEXT: sw a2, 48(sp) ; RV32I-NEXT: sw a2, 48(sp)
; RV32I-NEXT: sw a7, 44(sp) ; RV32I-NEXT: sw a7, 44(sp)
; RV32I-NEXT: addi a0, sp, 56 ; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24 ; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 40(sp) ; RV32I-NEXT: sw a6, 40(sp)
; RV32I-NEXT: call __addtf3 ; RV32I-NEXT: call __addtf3@plt
; RV32I-NEXT: lw a1, 56(sp) ; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: lw a0, 60(sp) ; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: lw a2, 64(sp) ; RV32I-NEXT: lw a2, 64(sp)
; RV32I-NEXT: lw a3, 68(sp) ; RV32I-NEXT: lw a3, 68(sp)
; RV32I-NEXT: sw a3, 20(sp) ; RV32I-NEXT: sw a3, 20(sp)
; RV32I-NEXT: sw a2, 16(sp) ; RV32I-NEXT: sw a2, 16(sp)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: addi a0, sp, 8 ; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: call __fixtfsi ; RV32I-NEXT: call __fixtfsi@plt
; RV32I-NEXT: lw ra, 76(sp) ; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 80 ; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16 %1 = load fp128, fp128* @x, align 16
%2 = load fp128, fp128* @y, align 16 %2 = load fp128, fp128* @y, align 16
%3 = fadd fp128 %1, %2 %3 = fadd fp128 %1, %2
%4 = fptosi fp128 %3 to i32 %4 = fptosi fp128 %3 to i32
ret i32 %4 ret i32 %4
} }

llvm/test/CodeGen/RISCV/fp16-promote.ll

Show All 10 Lines; CHECK-NEXT: ret
store half %a, half* %q store half %a, half* %q
ret void ret void
} }
define float @test_fpextend_float(half* %p) nounwind { define float @test_fpextend_float(half* %p) nounwind {
; CHECK-LABEL: test_fpextend_float: ; CHECK-LABEL: test_fpextend_float:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: lw ra, 12(sp) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load half, half* %p %a = load half, half* %p
%r = fpext half %a to float %r = fpext half %a to float
ret float %r ret float %r
} }
define double @test_fpextend_double(half* %p) nounwind { define double @test_fpextend_double(half* %p) nounwind {
; CHECK-LABEL: test_fpextend_double: ; CHECK-LABEL: test_fpextend_double:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fcvt.d.s fa0, fa0 ; CHECK-NEXT: fcvt.d.s fa0, fa0
; CHECK-NEXT: lw ra, 12(sp) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load half, half* %p %a = load half, half* %p
%r = fpext half %a to double %r = fpext half %a to double
ret double %r ret double %r
} }
define void @test_fptrunc_float(float %f, half* %p) nounwind { define void @test_fptrunc_float(float %f, half* %p) nounwind {
; CHECK-LABEL: test_fptrunc_float: ; CHECK-LABEL: test_fptrunc_float:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 8(sp) ; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __gnu_f2h_ieee ; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp) ; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = fptrunc float %f to half %a = fptrunc float %f to half
store half %a, half* %p store half %a, half* %p
ret void ret void
} }
define void @test_fptrunc_double(double %d, half* %p) nounwind { define void @test_fptrunc_double(double %d, half* %p) nounwind {
; CHECK-LABEL: test_fptrunc_double: ; CHECK-LABEL: test_fptrunc_double:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 8(sp) ; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __truncdfhf2 ; CHECK-NEXT: call __truncdfhf2@plt
; CHECK-NEXT: sh a0, 0(s0) ; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp) ; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = fptrunc double %d to half %a = fptrunc double %d to half
store half %a, half* %p store half %a, half* %p
ret void ret void
} }
define void @test_fadd(half* %p, half* %q) nounwind { define void @test_fadd(half* %p, half* %q) nounwind {
; CHECK-LABEL: test_fadd: ; CHECK-LABEL: test_fadd:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sw ra, 28(sp) ; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 24(sp) ; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s1, 20(sp) ; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: fsd fs0, 8(sp) ; CHECK-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.s fs0, fa0 ; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: lhu a0, 0(s0) ; CHECK-NEXT: lhu a0, 0(s0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fadd.s fa0, fs0, fa0 ; CHECK-NEXT: fadd.s fa0, fs0, fa0
; CHECK-NEXT: call __gnu_f2h_ieee ; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s1) ; CHECK-NEXT: sh a0, 0(s1)
; CHECK-NEXT: fld fs0, 8(sp) ; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) ; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) ; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) ; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load half, half* %p %a = load half, half* %p
%b = load half, half* %q %b = load half, half* %q
%r = fadd half %a, %b %r = fadd half %a, %b
store half %r, half* %p store half %r, half* %p
ret void ret void
} }
define void @test_fmul(half* %p, half* %q) nounwind { define void @test_fmul(half* %p, half* %q) nounwind {
; CHECK-LABEL: test_fmul: ; CHECK-LABEL: test_fmul:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sw ra, 28(sp) ; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 24(sp) ; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s1, 20(sp) ; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: fsd fs0, 8(sp) ; CHECK-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: lhu a0, 0(a0) ; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.s fs0, fa0 ; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: lhu a0, 0(s0) ; CHECK-NEXT: lhu a0, 0(s0)
; CHECK-NEXT: call __gnu_h2f_ieee ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmul.s fa0, fs0, fa0 ; CHECK-NEXT: fmul.s fa0, fs0, fa0
; CHECK-NEXT: call __gnu_f2h_ieee ; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s1) ; CHECK-NEXT: sh a0, 0(s1)
; CHECK-NEXT: fld fs0, 8(sp) ; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) ; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) ; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) ; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load half, half* %p %a = load half, half* %p
%b = load half, half* %q %b = load half, half* %q
%r = fmul half %a, %b %r = fmul half %a, %b
store half %r, half* %p store half %r, half* %p
ret void ret void
} }

llvm/test/CodeGen/RISCV/frame-info.ll

Show All 13 Lines
; RV64-LABEL: trivial: ; RV64-LABEL: trivial:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32-WITHFP-LABEL: trivial: ; RV32-WITHFP-LABEL: trivial:
; RV32-WITHFP: # %bb.0: ; RV32-WITHFP: # %bb.0:
; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp) ; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) ; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4 ; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: lw s0, 8(sp) ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16 ; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret ; RV32-WITHFP-NEXT: ret
; ;
; RV64-WITHFP-LABEL: trivial: ; RV64-WITHFP-LABEL: trivial:
; RV64-WITHFP: # %bb.0: ; RV64-WITHFP: # %bb.0:
; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp) ; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) ; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8 ; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16 ; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: ld s0, 0(sp) ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16 ; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret ; RV64-WITHFP-NEXT: ret
ret void ret void
} }
define void @stack_alloc(i32 signext %size) { define void @stack_alloc(i32 signext %size) {
; RV32-LABEL: stack_alloc: ; RV32-LABEL: stack_alloc:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 8(sp) ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_offset s0, -8 ; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: addi s0, sp, 16 ; RV32-NEXT: addi s0, sp, 16
; RV32-NEXT: .cfi_def_cfa s0, 0 ; RV32-NEXT: .cfi_def_cfa s0, 0
; RV32-NEXT: addi a0, a0, 15 ; RV32-NEXT: addi a0, a0, 15
; RV32-NEXT: andi a0, a0, -16 ; RV32-NEXT: andi a0, a0, -16
; RV32-NEXT: sub a0, sp, a0 ; RV32-NEXT: sub a0, sp, a0
; RV32-NEXT: mv sp, a0 ; RV32-NEXT: mv sp, a0
; RV32-NEXT: call callee_with_args ; RV32-NEXT: call callee_with_args@plt
; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: addi sp, s0, -16
; RV32-NEXT: lw s0, 8(sp) ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: stack_alloc: ; RV64-LABEL: stack_alloc:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 0(sp) ; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16 ; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: addi s0, sp, 16 ; RV64-NEXT: addi s0, sp, 16
; RV64-NEXT: .cfi_def_cfa s0, 0 ; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: addi a0, a0, 15 ; RV64-NEXT: addi a0, a0, 15
; RV64-NEXT: addi a1, zero, 1 ; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: slli a1, a1, 33 ; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: addi a1, a1, -16 ; RV64-NEXT: addi a1, a1, -16
; RV64-NEXT: and a0, a0, a1 ; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: sub a0, sp, a0 ; RV64-NEXT: sub a0, sp, a0
; RV64-NEXT: mv sp, a0 ; RV64-NEXT: mv sp, a0
; RV64-NEXT: call callee_with_args ; RV64-NEXT: call callee_with_args@plt
; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: addi sp, s0, -16
; RV64-NEXT: ld s0, 0(sp) ; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32-WITHFP-LABEL: stack_alloc: ; RV32-WITHFP-LABEL: stack_alloc:
; RV32-WITHFP: # %bb.0: # %entry ; RV32-WITHFP: # %bb.0: # %entry
; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp) ; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) ; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4 ; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: addi a0, a0, 15 ; RV32-WITHFP-NEXT: addi a0, a0, 15
; RV32-WITHFP-NEXT: andi a0, a0, -16 ; RV32-WITHFP-NEXT: andi a0, a0, -16
; RV32-WITHFP-NEXT: sub a0, sp, a0 ; RV32-WITHFP-NEXT: sub a0, sp, a0
; RV32-WITHFP-NEXT: mv sp, a0 ; RV32-WITHFP-NEXT: mv sp, a0
; RV32-WITHFP-NEXT: call callee_with_args ; RV32-WITHFP-NEXT: call callee_with_args@plt
; RV32-WITHFP-NEXT: addi sp, s0, -16 ; RV32-WITHFP-NEXT: addi sp, s0, -16
; RV32-WITHFP-NEXT: lw s0, 8(sp) ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16 ; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret ; RV32-WITHFP-NEXT: ret
; ;
; RV64-WITHFP-LABEL: stack_alloc: ; RV64-WITHFP-LABEL: stack_alloc:
; RV64-WITHFP: # %bb.0: # %entry ; RV64-WITHFP: # %bb.0: # %entry
; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp) ; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) ; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8 ; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16 ; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: slli a0, a0, 32 ; RV64-WITHFP-NEXT: slli a0, a0, 32
; RV64-WITHFP-NEXT: srli a0, a0, 32 ; RV64-WITHFP-NEXT: srli a0, a0, 32
; RV64-WITHFP-NEXT: addi a0, a0, 15 ; RV64-WITHFP-NEXT: addi a0, a0, 15
; RV64-WITHFP-NEXT: addi a1, zero, 1 ; RV64-WITHFP-NEXT: addi a1, zero, 1
; RV64-WITHFP-NEXT: slli a1, a1, 33 ; RV64-WITHFP-NEXT: slli a1, a1, 33
; RV64-WITHFP-NEXT: addi a1, a1, -16 ; RV64-WITHFP-NEXT: addi a1, a1, -16
; RV64-WITHFP-NEXT: and a0, a0, a1 ; RV64-WITHFP-NEXT: and a0, a0, a1
; RV64-WITHFP-NEXT: sub a0, sp, a0 ; RV64-WITHFP-NEXT: sub a0, sp, a0
; RV64-WITHFP-NEXT: mv sp, a0 ; RV64-WITHFP-NEXT: mv sp, a0
; RV64-WITHFP-NEXT: call callee_with_args ; RV64-WITHFP-NEXT: call callee_with_args@plt
; RV64-WITHFP-NEXT: addi sp, s0, -16 ; RV64-WITHFP-NEXT: addi sp, s0, -16
; RV64-WITHFP-NEXT: ld s0, 0(sp) ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16 ; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret ; RV64-WITHFP-NEXT: ret
entry: entry:
%0 = alloca i8, i32 %size, align 16 %0 = alloca i8, i32 %size, align 16
call void @callee_with_args(i8* nonnull %0) call void @callee_with_args(i8* nonnull %0)
ret void ret void
} }
define void @branch_and_tail_call(i1 %a) { define void @branch_and_tail_call(i1 %a) {
; RV32-LABEL: branch_and_tail_call: ; RV32-LABEL: branch_and_tail_call:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: andi a0, a0, 1 ; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: beqz a0, .LBB2_2 ; RV32-NEXT: beqz a0, .LBB2_2
; RV32-NEXT: # %bb.1: # %blue_pill ; RV32-NEXT: # %bb.1: # %blue_pill
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: tail callee1 ; RV32-NEXT: tail callee1@plt
; RV32-NEXT: .LBB2_2: # %red_pill ; RV32-NEXT: .LBB2_2: # %red_pill
; RV32-NEXT: call callee2 ; RV32-NEXT: call callee2@plt
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: branch_and_tail_call: ; RV64-LABEL: branch_and_tail_call:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: andi a0, a0, 1 ; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: beqz a0, .LBB2_2 ; RV64-NEXT: beqz a0, .LBB2_2
; RV64-NEXT: # %bb.1: # %blue_pill ; RV64-NEXT: # %bb.1: # %blue_pill
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: tail callee1 ; RV64-NEXT: tail callee1@plt
; RV64-NEXT: .LBB2_2: # %red_pill ; RV64-NEXT: .LBB2_2: # %red_pill
; RV64-NEXT: call callee2 ; RV64-NEXT: call callee2@plt
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32-WITHFP-LABEL: branch_and_tail_call: ; RV32-WITHFP-LABEL: branch_and_tail_call:
; RV32-WITHFP: # %bb.0: ; RV32-WITHFP: # %bb.0:
; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp) ; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) ; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4 ; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: andi a0, a0, 1 ; RV32-WITHFP-NEXT: andi a0, a0, 1
; RV32-WITHFP-NEXT: beqz a0, .LBB2_2 ; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill ; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV32-WITHFP-NEXT: lw s0, 8(sp) ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16 ; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: tail callee1 ; RV32-WITHFP-NEXT: tail callee1@plt
; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV32-WITHFP-NEXT: call callee2 ; RV32-WITHFP-NEXT: call callee2@plt
; RV32-WITHFP-NEXT: lw s0, 8(sp) ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16 ; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret ; RV32-WITHFP-NEXT: ret
; ;
; RV64-WITHFP-LABEL: branch_and_tail_call: ; RV64-WITHFP-LABEL: branch_and_tail_call:
; RV64-WITHFP: # %bb.0: ; RV64-WITHFP: # %bb.0:
; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp) ; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) ; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8 ; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16 ; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: andi a0, a0, 1 ; RV64-WITHFP-NEXT: andi a0, a0, 1
; RV64-WITHFP-NEXT: beqz a0, .LBB2_2 ; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill ; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV64-WITHFP-NEXT: ld s0, 0(sp) ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16 ; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: tail callee1 ; RV64-WITHFP-NEXT: tail callee1@plt
; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV64-WITHFP-NEXT: call callee2 ; RV64-WITHFP-NEXT: call callee2@plt
; RV64-WITHFP-NEXT: ld s0, 0(sp) ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16 ; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret ; RV64-WITHFP-NEXT: ret
br i1 %a, label %blue_pill, label %red_pill br i1 %a, label %blue_pill, label %red_pill
blue_pill: blue_pill:
tail call void @callee1() tail call void @callee1()
ret void ret void
red_pill: red_pill:
call void @callee2() call void @callee2()
ret void ret void
} }
declare void @callee1() declare void @callee1()
declare void @callee2() declare void @callee2()
declare void @callee_with_args(i8*) declare void @callee_with_args(i8*)

llvm/test/CodeGen/RISCV/frame.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s ; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
; RUN: llc -mtriple=riscv32 -frame-pointer=all -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -frame-pointer=all -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
%struct.key_t = type { i32, [16 x i8] } %struct.key_t = type { i32, [16 x i8] }
define i32 @test() nounwind { define i32 @test() nounwind {
; RV32I-FPELIM-LABEL: test: ; RV32I-FPELIM-LABEL: test:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw zero, 24(sp) ; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp) ; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp) ; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp) ; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 12 ; RV32I-FPELIM-NEXT: addi a0, sp, 12
; RV32I-FPELIM-NEXT: call test1 ; RV32I-FPELIM-NEXT: call test1@plt
; RV32I-FPELIM-NEXT: mv a0, zero ; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: test: ; RV32I-WITHFP-LABEL: test:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32 ; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: sw zero, -16(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: sw zero, -24(s0) ; RV32I-WITHFP-NEXT: sw zero, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -28(s0) ; RV32I-WITHFP-NEXT: sw zero, -28(s0)
; RV32I-WITHFP-NEXT: sw zero, -32(s0) ; RV32I-WITHFP-NEXT: sw zero, -32(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -28 ; RV32I-WITHFP-NEXT: addi a0, s0, -28
; RV32I-WITHFP-NEXT: call test1 ; RV32I-WITHFP-NEXT: call test1@plt
; RV32I-WITHFP-NEXT: mv a0, zero ; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%key = alloca %struct.key_t, align 4 %key = alloca %struct.key_t, align 4
%1 = bitcast %struct.key_t* %key to i8* %1 = bitcast %struct.key_t* %key to i8*
call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 20, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 20, i1 false)
%2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0 %2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
call void @test1(i8* %2) call void @test1(i8* %2)
ret i32 0 ret i32 0
} }
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
declare void @test1(i8*) declare void @test1(i8*)

llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
declare void @notdead(i8*) declare void @notdead(i8*)
declare i8* @llvm.frameaddress(i32) declare i8* @llvm.frameaddress(i32)
declare i8* @llvm.returnaddress(i32) declare i8* @llvm.returnaddress(i32)
define i8* @test_frameaddress_0() nounwind { define i8* @test_frameaddress_0() nounwind {
; RV32I-LABEL: test_frameaddress_0: ; RV32I-LABEL: test_frameaddress_0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_frameaddress_0: ; RV64I-LABEL: test_frameaddress_0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16 ; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 0) %1 = call i8* @llvm.frameaddress(i32 0)
ret i8* %1 ret i8* %1
} }
define i8* @test_frameaddress_2() nounwind { define i8* @test_frameaddress_2() nounwind {
; RV32I-LABEL: test_frameaddress_2: ; RV32I-LABEL: test_frameaddress_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, -8(s0) ; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_frameaddress_2: ; RV64I-LABEL: test_frameaddress_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16 ; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: ld a0, -16(s0) ; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0) ; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 2) %1 = call i8* @llvm.frameaddress(i32 2)
ret i8* %1 ret i8* %1
} }
define i8* @test_frameaddress_3_alloca() nounwind { define i8* @test_frameaddress_3_alloca() nounwind {
; RV32I-LABEL: test_frameaddress_3_alloca: ; RV32I-LABEL: test_frameaddress_3_alloca:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -112 ; RV32I-NEXT: addi sp, sp, -112
; RV32I-NEXT: sw ra, 108(sp) ; RV32I-NEXT: sw ra, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 104(sp) ; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 112 ; RV32I-NEXT: addi s0, sp, 112
; RV32I-NEXT: addi a0, s0, -108 ; RV32I-NEXT: addi a0, s0, -108
; RV32I-NEXT: call notdead ; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: lw a0, -8(s0) ; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 104(sp) ; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 108(sp) ; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 112 ; RV32I-NEXT: addi sp, sp, 112
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_frameaddress_3_alloca: ; RV64I-LABEL: test_frameaddress_3_alloca:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -128 ; RV64I-NEXT: addi sp, sp, -128
; RV64I-NEXT: sd ra, 120(sp) ; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) ; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 128 ; RV64I-NEXT: addi s0, sp, 128
; RV64I-NEXT: addi a0, s0, -116 ; RV64I-NEXT: addi a0, s0, -116
; RV64I-NEXT: call notdead ; RV64I-NEXT: call notdead@plt
; RV64I-NEXT: ld a0, -16(s0) ; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0) ; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -16(a0) ; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 112(sp) ; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) ; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128 ; RV64I-NEXT: addi sp, sp, 128
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca [100 x i8] %1 = alloca [100 x i8]
%2 = bitcast [100 x i8]* %1 to i8* %2 = bitcast [100 x i8]* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = call i8* @llvm.frameaddress(i32 3) %3 = call i8* @llvm.frameaddress(i32 3)
ret i8* %3 ret i8* %3
} }
Show All 11 Lines; RV64I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 0) %1 = call i8* @llvm.returnaddress(i32 0)
ret i8* %1 ret i8* %1
} }
define i8* @test_returnaddress_2() nounwind { define i8* @test_returnaddress_2() nounwind {
; RV32I-LABEL: test_returnaddress_2: ; RV32I-LABEL: test_returnaddress_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, -8(s0) ; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -4(a0) ; RV32I-NEXT: lw a0, -4(a0)
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_returnaddress_2: ; RV64I-LABEL: test_returnaddress_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16 ; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: ld a0, -16(s0) ; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0) ; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -8(a0) ; RV64I-NEXT: ld a0, -8(a0)
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 2) %1 = call i8* @llvm.returnaddress(i32 2)
ret i8* %1 ret i8* %1
} }

llvm/test/CodeGen/RISCV/ghccc-rv32.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lui a0, %hi(r1) ; CHECK-NEXT: lui a0, %hi(r1)
; CHECK-NEXT: lw s4, %lo(r1)(a0) ; CHECK-NEXT: lw s4, %lo(r1)(a0)
; CHECK-NEXT: lui a0, %hi(hp) ; CHECK-NEXT: lui a0, %hi(hp)
; CHECK-NEXT: lw s3, %lo(hp)(a0) ; CHECK-NEXT: lw s3, %lo(hp)(a0)
; CHECK-NEXT: lui a0, %hi(sp) ; CHECK-NEXT: lui a0, %hi(sp)
; CHECK-NEXT: lw s2, %lo(sp)(a0) ; CHECK-NEXT: lw s2, %lo(sp)(a0)
; CHECK-NEXT: lui a0, %hi(base) ; CHECK-NEXT: lui a0, %hi(base)
; CHECK-NEXT: lw s1, %lo(base)(a0) ; CHECK-NEXT: lw s1, %lo(base)(a0)
; CHECK-NEXT: tail bar ; CHECK-NEXT: tail bar@plt
entry: entry:
%0 = load double, double* @d6 %0 = load double, double* @d6
%1 = load double, double* @d5 %1 = load double, double* @d5
%2 = load double, double* @d4 %2 = load double, double* @d4
%3 = load double, double* @d3 %3 = load double, double* @d3
%4 = load double, double* @d2 %4 = load double, double* @d2
%5 = load double, double* @d1 %5 = load double, double* @d1
%6 = load float, float* @f6 %6 = load float, float* @f6
Show All 25 Lines

llvm/test/CodeGen/RISCV/ghccc-rv64.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lui a0, %hi(r1) ; CHECK-NEXT: lui a0, %hi(r1)
; CHECK-NEXT: ld s4, %lo(r1)(a0) ; CHECK-NEXT: ld s4, %lo(r1)(a0)
; CHECK-NEXT: lui a0, %hi(hp) ; CHECK-NEXT: lui a0, %hi(hp)
; CHECK-NEXT: ld s3, %lo(hp)(a0) ; CHECK-NEXT: ld s3, %lo(hp)(a0)
; CHECK-NEXT: lui a0, %hi(sp) ; CHECK-NEXT: lui a0, %hi(sp)
; CHECK-NEXT: ld s2, %lo(sp)(a0) ; CHECK-NEXT: ld s2, %lo(sp)(a0)
; CHECK-NEXT: lui a0, %hi(base) ; CHECK-NEXT: lui a0, %hi(base)
; CHECK-NEXT: ld s1, %lo(base)(a0) ; CHECK-NEXT: ld s1, %lo(base)(a0)
; CHECK-NEXT: tail bar ; CHECK-NEXT: tail bar@plt
entry: entry:
%0 = load double, double* @d6 %0 = load double, double* @d6
%1 = load double, double* @d5 %1 = load double, double* @d5
%2 = load double, double* @d4 %2 = load double, double* @d4
%3 = load double, double* @d3 %3 = load double, double* @d3
%4 = load double, double* @d2 %4 = load double, double* @d2
%5 = load double, double* @d1 %5 = load double, double* @d1
%6 = load float, float* @f6 %6 = load float, float* @f6
Show All 25 Lines

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
; operations if half precision floating point isn't supported. A combine could ; operations if half precision floating point isn't supported. A combine could
; be written to do the same even when f16 is legal. ; be written to do the same even when f16 is legal.
define half @fcopysign_fneg(half %a, half %b) nounwind { define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV32I-LABEL: fcopysign_fneg: ; RV32I-LABEL: fcopysign_fneg:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: call __gnu_h2f_ieee ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: not a1, s0 ; RV32I-NEXT: not a1, s0
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a2, a2, -1 ; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lui a2, 8 ; RV32I-NEXT: lui a2, 8
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IZFH-LABEL: fcopysign_fneg: ; RV32IZFH-LABEL: fcopysign_fneg:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, fa1 ; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64I-LABEL: fcopysign_fneg: ; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: call __gnu_h2f_ieee ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: not a1, s0 ; RV64I-NEXT: not a1, s0
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 33 ; RV64I-NEXT: slli a2, a2, 33
; RV64I-NEXT: addi a2, a2, -1 ; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: slli a2, a2, 15 ; RV64I-NEXT: slli a2, a2, 15
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s0, 0(sp) ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IZFH-LABEL: fcopysign_fneg: ; RV64IZFH-LABEL: fcopysign_fneg:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, fa1 ; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fneg half %b %1 = fneg half %b
%2 = call half @llvm.copysign.f16(half %a, half %1) %2 = call half @llvm.copysign.f16(half %a, half %1)
ret half %2 ret half %2
} }

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
declare half @dummy(half) declare half @dummy(half)
define void @br_fcmp_false(half %a, half %b) nounwind { define void @br_fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_false: ; RV32IZFH-LABEL: br_fcmp_false:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: addi a0, zero, 1 ; RV32IZFH-NEXT: addi a0, zero, 1
; RV32IZFH-NEXT: bnez a0, .LBB0_2 ; RV32IZFH-NEXT: bnez a0, .LBB0_2
; RV32IZFH-NEXT: # %bb.1: # %if.then ; RV32IZFH-NEXT: # %bb.1: # %if.then
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB0_2: # %if.else ; RV32IZFH-NEXT: .LBB0_2: # %if.else
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH-LABEL: br_fcmp_false:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: addi a0, zero, 1 ; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: bnez a0, .LBB0_2 ; RV64IZFH-NEXT: bnez a0, .LBB0_2
; RV64IZFH-NEXT: # %bb.1: # %if.then ; RV64IZFH-NEXT: # %bb.1: # %if.then
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB0_2: # %if.else ; RV64IZFH-NEXT: .LBB0_2: # %if.else
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp false half %a, %b %1 = fcmp false half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
ret void ret void
if.else: if.else:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oeq(half %a, half %b) nounwind { define void @br_fcmp_oeq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_oeq: ; RV32IZFH-LABEL: br_fcmp_oeq:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: bnez a0, .LBB1_2 ; RV32IZFH-NEXT: bnez a0, .LBB1_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB1_2: # %if.then ; RV32IZFH-NEXT: .LBB1_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_oeq: ; RV64IZFH-LABEL: br_fcmp_oeq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: bnez a0, .LBB1_2 ; RV64IZFH-NEXT: bnez a0, .LBB1_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB1_2: # %if.then ; RV64IZFH-NEXT: .LBB1_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp oeq half %a, %b %1 = fcmp oeq half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: generated code quality for this is very poor due to ; TODO: generated code quality for this is very poor due to
; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires ; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
; expansion. ; expansion.
define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { define void @br_fcmp_oeq_alt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_oeq_alt: ; RV32IZFH-LABEL: br_fcmp_oeq_alt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: beqz a0, .LBB2_2 ; RV32IZFH-NEXT: beqz a0, .LBB2_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB2_2: # %if.then ; RV32IZFH-NEXT: .LBB2_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_oeq_alt: ; RV64IZFH-LABEL: br_fcmp_oeq_alt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: beqz a0, .LBB2_2 ; RV64IZFH-NEXT: beqz a0, .LBB2_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB2_2: # %if.then ; RV64IZFH-NEXT: .LBB2_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp oeq half %a, %b %1 = fcmp oeq half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
if.else: if.else:
ret void ret void
} }
define void @br_fcmp_ogt(half %a, half %b) nounwind { define void @br_fcmp_ogt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ogt: ; RV32IZFH-LABEL: br_fcmp_ogt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: bnez a0, .LBB3_2 ; RV32IZFH-NEXT: bnez a0, .LBB3_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB3_2: # %if.then ; RV32IZFH-NEXT: .LBB3_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ogt: ; RV64IZFH-LABEL: br_fcmp_ogt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: bnez a0, .LBB3_2 ; RV64IZFH-NEXT: bnez a0, .LBB3_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB3_2: # %if.then ; RV64IZFH-NEXT: .LBB3_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ogt half %a, %b %1 = fcmp ogt half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_oge(half %a, half %b) nounwind { define void @br_fcmp_oge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_oge: ; RV32IZFH-LABEL: br_fcmp_oge:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: bnez a0, .LBB4_2 ; RV32IZFH-NEXT: bnez a0, .LBB4_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB4_2: # %if.then ; RV32IZFH-NEXT: .LBB4_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_oge: ; RV64IZFH-LABEL: br_fcmp_oge:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: bnez a0, .LBB4_2 ; RV64IZFH-NEXT: bnez a0, .LBB4_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB4_2: # %if.then ; RV64IZFH-NEXT: .LBB4_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp oge half %a, %b %1 = fcmp oge half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_olt(half %a, half %b) nounwind { define void @br_fcmp_olt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_olt: ; RV32IZFH-LABEL: br_fcmp_olt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: bnez a0, .LBB5_2 ; RV32IZFH-NEXT: bnez a0, .LBB5_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB5_2: # %if.then ; RV32IZFH-NEXT: .LBB5_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_olt: ; RV64IZFH-LABEL: br_fcmp_olt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: bnez a0, .LBB5_2 ; RV64IZFH-NEXT: bnez a0, .LBB5_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB5_2: # %if.then ; RV64IZFH-NEXT: .LBB5_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp olt half %a, %b %1 = fcmp olt half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ole(half %a, half %b) nounwind { define void @br_fcmp_ole(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ole: ; RV32IZFH-LABEL: br_fcmp_ole:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: bnez a0, .LBB6_2 ; RV32IZFH-NEXT: bnez a0, .LBB6_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB6_2: # %if.then ; RV32IZFH-NEXT: .LBB6_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ole: ; RV64IZFH-LABEL: br_fcmp_ole:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: bnez a0, .LBB6_2 ; RV64IZFH-NEXT: bnez a0, .LBB6_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB6_2: # %if.then ; RV64IZFH-NEXT: .LBB6_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ole half %a, %b %1 = fcmp ole half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.h+sltiu+bne -> feq.h+beq ; TODO: feq.h+sltiu+bne -> feq.h+beq
define void @br_fcmp_one(half %a, half %b) nounwind { define void @br_fcmp_one(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_one: ; RV32IZFH-LABEL: br_fcmp_one:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: feq.h a1, fa0, fa1 ; RV32IZFH-NEXT: feq.h a1, fa0, fa1
; RV32IZFH-NEXT: not a1, a1 ; RV32IZFH-NEXT: not a1, a1
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: bnez a0, .LBB7_2 ; RV32IZFH-NEXT: bnez a0, .LBB7_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB7_2: # %if.then ; RV32IZFH-NEXT: .LBB7_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_one: ; RV64IZFH-LABEL: br_fcmp_one:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: feq.h a1, fa0, fa1 ; RV64IZFH-NEXT: feq.h a1, fa0, fa1
; RV64IZFH-NEXT: not a1, a1 ; RV64IZFH-NEXT: not a1, a1
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: bnez a0, .LBB7_2 ; RV64IZFH-NEXT: bnez a0, .LBB7_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB7_2: # %if.then ; RV64IZFH-NEXT: .LBB7_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp one half %a, %b %1 = fcmp one half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ord(half %a, half %b) nounwind { define void @br_fcmp_ord(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ord: ; RV32IZFH-LABEL: br_fcmp_ord:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: bnez a0, .LBB8_2 ; RV32IZFH-NEXT: bnez a0, .LBB8_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB8_2: # %if.then ; RV32IZFH-NEXT: .LBB8_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ord: ; RV64IZFH-LABEL: br_fcmp_ord:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: bnez a0, .LBB8_2 ; RV64IZFH-NEXT: bnez a0, .LBB8_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB8_2: # %if.then ; RV64IZFH-NEXT: .LBB8_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ord half %a, %b %1 = fcmp ord half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ueq(half %a, half %b) nounwind { define void @br_fcmp_ueq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ueq: ; RV32IZFH-LABEL: br_fcmp_ueq:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa1, fa1 ; RV32IZFH-NEXT: feq.h a1, fa1, fa1
; RV32IZFH-NEXT: feq.h a2, fa0, fa0 ; RV32IZFH-NEXT: feq.h a2, fa0, fa0
; RV32IZFH-NEXT: and a1, a2, a1 ; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: seqz a1, a1 ; RV32IZFH-NEXT: seqz a1, a1
; RV32IZFH-NEXT: or a0, a0, a1 ; RV32IZFH-NEXT: or a0, a0, a1
; RV32IZFH-NEXT: bnez a0, .LBB9_2 ; RV32IZFH-NEXT: bnez a0, .LBB9_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB9_2: # %if.then ; RV32IZFH-NEXT: .LBB9_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ueq: ; RV64IZFH-LABEL: br_fcmp_ueq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa1, fa1 ; RV64IZFH-NEXT: feq.h a1, fa1, fa1
; RV64IZFH-NEXT: feq.h a2, fa0, fa0 ; RV64IZFH-NEXT: feq.h a2, fa0, fa0
; RV64IZFH-NEXT: and a1, a2, a1 ; RV64IZFH-NEXT: and a1, a2, a1
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
; RV64IZFH-NEXT: or a0, a0, a1 ; RV64IZFH-NEXT: or a0, a0, a1
; RV64IZFH-NEXT: bnez a0, .LBB9_2 ; RV64IZFH-NEXT: bnez a0, .LBB9_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB9_2: # %if.then ; RV64IZFH-NEXT: .LBB9_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ueq half %a, %b %1 = fcmp ueq half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ugt(half %a, half %b) nounwind { define void @br_fcmp_ugt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ugt: ; RV32IZFH-LABEL: br_fcmp_ugt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB10_2 ; RV32IZFH-NEXT: bnez a0, .LBB10_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB10_2: # %if.then ; RV32IZFH-NEXT: .LBB10_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ugt: ; RV64IZFH-LABEL: br_fcmp_ugt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB10_2 ; RV64IZFH-NEXT: bnez a0, .LBB10_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB10_2: # %if.then ; RV64IZFH-NEXT: .LBB10_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ugt half %a, %b %1 = fcmp ugt half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uge(half %a, half %b) nounwind { define void @br_fcmp_uge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_uge: ; RV32IZFH-LABEL: br_fcmp_uge:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB11_2 ; RV32IZFH-NEXT: bnez a0, .LBB11_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB11_2: # %if.then ; RV32IZFH-NEXT: .LBB11_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_uge: ; RV64IZFH-LABEL: br_fcmp_uge:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB11_2 ; RV64IZFH-NEXT: bnez a0, .LBB11_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB11_2: # %if.then ; RV64IZFH-NEXT: .LBB11_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp uge half %a, %b %1 = fcmp uge half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ult(half %a, half %b) nounwind { define void @br_fcmp_ult(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ult: ; RV32IZFH-LABEL: br_fcmp_ult:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB12_2 ; RV32IZFH-NEXT: bnez a0, .LBB12_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB12_2: # %if.then ; RV32IZFH-NEXT: .LBB12_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ult: ; RV64IZFH-LABEL: br_fcmp_ult:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB12_2 ; RV64IZFH-NEXT: bnez a0, .LBB12_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB12_2: # %if.then ; RV64IZFH-NEXT: .LBB12_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ult half %a, %b %1 = fcmp ult half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ule(half %a, half %b) nounwind { define void @br_fcmp_ule(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ule: ; RV32IZFH-LABEL: br_fcmp_ule:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB13_2 ; RV32IZFH-NEXT: bnez a0, .LBB13_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB13_2: # %if.then ; RV32IZFH-NEXT: .LBB13_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ule: ; RV64IZFH-LABEL: br_fcmp_ule:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB13_2 ; RV64IZFH-NEXT: bnez a0, .LBB13_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB13_2: # %if.then ; RV64IZFH-NEXT: .LBB13_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ule half %a, %b %1 = fcmp ule half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_une(half %a, half %b) nounwind { define void @br_fcmp_une(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_une: ; RV32IZFH-LABEL: br_fcmp_une:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB14_2 ; RV32IZFH-NEXT: bnez a0, .LBB14_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB14_2: # %if.then ; RV32IZFH-NEXT: .LBB14_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_une: ; RV64IZFH-LABEL: br_fcmp_une:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB14_2 ; RV64IZFH-NEXT: bnez a0, .LBB14_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB14_2: # %if.then ; RV64IZFH-NEXT: .LBB14_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp une half %a, %b %1 = fcmp une half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uno(half %a, half %b) nounwind { define void @br_fcmp_uno(half %a, half %b) nounwind {
; TODO: sltiu+bne -> beq ; TODO: sltiu+bne -> beq
; RV32IZFH-LABEL: br_fcmp_uno: ; RV32IZFH-LABEL: br_fcmp_uno:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: seqz a0, a0 ; RV32IZFH-NEXT: seqz a0, a0
; RV32IZFH-NEXT: bnez a0, .LBB15_2 ; RV32IZFH-NEXT: bnez a0, .LBB15_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB15_2: # %if.then ; RV32IZFH-NEXT: .LBB15_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_uno: ; RV64IZFH-LABEL: br_fcmp_uno:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: seqz a0, a0 ; RV64IZFH-NEXT: seqz a0, a0
; RV64IZFH-NEXT: bnez a0, .LBB15_2 ; RV64IZFH-NEXT: bnez a0, .LBB15_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB15_2: # %if.then ; RV64IZFH-NEXT: .LBB15_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp uno half %a, %b %1 = fcmp uno half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_true(half %a, half %b) nounwind { define void @br_fcmp_true(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_true: ; RV32IZFH-LABEL: br_fcmp_true:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: addi a0, zero, 1 ; RV32IZFH-NEXT: addi a0, zero, 1
; RV32IZFH-NEXT: bnez a0, .LBB16_2 ; RV32IZFH-NEXT: bnez a0, .LBB16_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB16_2: # %if.then ; RV32IZFH-NEXT: .LBB16_2: # %if.then
; RV32IZFH-NEXT: call abort ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_true: ; RV64IZFH-LABEL: br_fcmp_true:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: addi a0, zero, 1 ; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: bnez a0, .LBB16_2 ; RV64IZFH-NEXT: bnez a0, .LBB16_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB16_2: # %if.then ; RV64IZFH-NEXT: .LBB16_2: # %if.then
; RV64IZFH-NEXT: call abort ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp true half %a, %b %1 = fcmp true half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }

llvm/test/CodeGen/RISCV/half-convert.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines; RV64IDZFH-NEXT: ret
%1 = fptoui half %a to i32 %1 = fptoui half %a to i32
ret i32 %1 ret i32 %1
} }
define i64 @fcvt_l_h(half %a) nounwind { define i64 @fcvt_l_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_l_h: ; RV32IZFH-LABEL: fcvt_l_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __fixhfdi ; RV32IZFH-NEXT: call __fixhfdi@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_l_h: ; RV32IDZFH-LABEL: fcvt_l_h:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __fixhfdi ; RV32IDZFH-NEXT: call __fixhfdi@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_l_h: ; RV64IZFH-LABEL: fcvt_l_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_l_h: ; RV64IDZFH-LABEL: fcvt_l_h:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%1 = fptosi half %a to i64 %1 = fptosi half %a to i64
ret i64 %1 ret i64 %1
} }
define i64 @fcvt_lu_h(half %a) nounwind { define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_lu_h: ; RV32IZFH-LABEL: fcvt_lu_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __fixunshfdi ; RV32IZFH-NEXT: call __fixunshfdi@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_lu_h: ; RV32IDZFH-LABEL: fcvt_lu_h:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __fixunshfdi ; RV32IDZFH-NEXT: call __fixunshfdi@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_lu_h: ; RV64IZFH-LABEL: fcvt_lu_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines; RV64IDZFH-NEXT: ret
%1 = uitofp i32 %a to half %1 = uitofp i32 %a to half
ret half %1 ret half %1
} }
define half @fcvt_h_l(i64 %a) nounwind { define half @fcvt_h_l(i64 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_l: ; RV32IZFH-LABEL: fcvt_h_l:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __floatdihf ; RV32IZFH-NEXT: call __floatdihf@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_l: ; RV32IDZFH-LABEL: fcvt_h_l:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __floatdihf ; RV32IDZFH-NEXT: call __floatdihf@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_l: ; RV64IZFH-LABEL: fcvt_h_l:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.l fa0, a0 ; RV64IZFH-NEXT: fcvt.h.l fa0, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_l: ; RV64IDZFH-LABEL: fcvt_h_l:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 ; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%1 = sitofp i64 %a to half %1 = sitofp i64 %a to half
ret half %1 ret half %1
} }
define half @fcvt_h_lu(i64 %a) nounwind { define half @fcvt_h_lu(i64 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_lu: ; RV32IZFH-LABEL: fcvt_h_lu:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __floatundihf ; RV32IZFH-NEXT: call __floatundihf@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_lu: ; RV32IDZFH-LABEL: fcvt_h_lu:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16 ; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp) ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __floatundihf ; RV32IDZFH-NEXT: call __floatundihf@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_lu: ; RV64IZFH-LABEL: fcvt_h_lu:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 ; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; RV64IDZFH-NEXT: ret
%1 = fpext half %a to float %1 = fpext half %a to float
ret float %1 ret float %1
} }
define half @fcvt_h_d(double %a) nounwind { define half @fcvt_h_d(double %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_d: ; RV32IZFH-LABEL: fcvt_h_d:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __truncdfhf2 ; RV32IZFH-NEXT: call __truncdfhf2@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_h_d: ; RV32IDZFH-LABEL: fcvt_h_d:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0 ; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_h_d: ; RV64IZFH-LABEL: fcvt_h_d:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __truncdfhf2 ; RV64IZFH-NEXT: call __truncdfhf2@plt
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_h_d: ; RV64IDZFH-LABEL: fcvt_h_d:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0 ; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%1 = fptrunc double %a to half %1 = fptrunc double %a to half
ret half %1 ret half %1
} }
define double @fcvt_d_h(half %a) nounwind { define double @fcvt_d_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_d_h: ; RV32IZFH-LABEL: fcvt_d_h:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call __extendsfdf2 ; RV32IZFH-NEXT: call __extendsfdf2@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_d_h: ; RV32IDZFH-LABEL: fcvt_d_h:
; RV32IDZFH: # %bb.0: ; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0 ; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_d_h: ; RV64IZFH-LABEL: fcvt_d_h:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call __extendsfdf2 ; RV64IZFH-NEXT: call __extendsfdf2@plt
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_d_h: ; RV64IDZFH-LABEL: fcvt_d_h:
; RV64IDZFH: # %bb.0: ; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0 ; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
%1 = fpext half %a to double %1 = fpext half %a to double
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-mem.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define half @flh_stack(half %a) nounwind { define half @flh_stack(half %a) nounwind {
; RV32IZFH-LABEL: flh_stack: ; RV32IZFH-LABEL: flh_stack:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 8(sp) ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fmv.h fs0, fa0 ; RV32IZFH-NEXT: fmv.h fs0, fa0
; RV32IZFH-NEXT: addi a0, sp, 4 ; RV32IZFH-NEXT: addi a0, sp, 4
; RV32IZFH-NEXT: call notdead ; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: flh ft0, 4(sp) ; RV32IZFH-NEXT: flh ft0, 4(sp)
; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0 ; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV32IZFH-NEXT: flw fs0, 8(sp) ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: flh_stack: ; RV64IZFH-LABEL: flh_stack:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fsw fs0, 4(sp) ; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fmv.h fs0, fa0 ; RV64IZFH-NEXT: fmv.h fs0, fa0
; RV64IZFH-NEXT: mv a0, sp ; RV64IZFH-NEXT: mv a0, sp
; RV64IZFH-NEXT: call notdead ; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: flh ft0, 0(sp) ; RV64IZFH-NEXT: flh ft0, 0(sp)
; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0 ; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV64IZFH-NEXT: flw fs0, 4(sp) ; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = alloca half, align 4 %1 = alloca half, align 4
%2 = bitcast half* %1 to i8* %2 = bitcast half* %1 to i8*
call void @notdead(i8* %2) call void @notdead(i8* %2)
%3 = load half, half* %1 %3 = load half, half* %1
%4 = fadd half %3, %a ; force load in to FPR16 %4 = fadd half %3, %a ; force load in to FPR16
ret half %4 ret half %4
} }
define void @fsh_stack(half %a, half %b) nounwind { define void @fsh_stack(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fsh_stack: ; RV32IZFH-LABEL: fsh_stack:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV32IZFH-NEXT: fsh ft0, 8(sp) ; RV32IZFH-NEXT: fsh ft0, 8(sp)
; RV32IZFH-NEXT: addi a0, sp, 8 ; RV32IZFH-NEXT: addi a0, sp, 8
; RV32IZFH-NEXT: call notdead ; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: lw ra, 12(sp) ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fsh_stack: ; RV64IZFH-LABEL: fsh_stack:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV64IZFH-NEXT: fsh ft0, 4(sp) ; RV64IZFH-NEXT: fsh ft0, 4(sp)
; RV64IZFH-NEXT: addi a0, sp, 4 ; RV64IZFH-NEXT: addi a0, sp, 4
; RV64IZFH-NEXT: call notdead ; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: ld ra, 8(sp) ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b ; force store from FPR16 %1 = fadd half %a, %b ; force store from FPR16
%2 = alloca half, align 4 %2 = alloca half, align 4
store half %1, half* %2 store half %1, half* %2
%3 = bitcast half* %2 to i8* %3 = bitcast half* %2 to i8*
call void @notdead(i8* %3) call void @notdead(i8* %3)
ret void ret void
} }

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 3) ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 3)
} }
define dso_local i32 @load_half() nounwind { define dso_local i32 @load_half() nounwind {
; CHECK-LABEL: load_half: ; CHECK-LABEL: load_half:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp) ; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(foo+8) ; CHECK-NEXT: lui a0, %hi(foo+8)
; CHECK-NEXT: lhu a0, %lo(foo+8)(a0) ; CHECK-NEXT: lhu a0, %lo(foo+8)(a0)
; CHECK-NEXT: addi a1, zero, 140 ; CHECK-NEXT: addi a1, zero, 140
; CHECK-NEXT: bne a0, a1, .LBB7_2 ; CHECK-NEXT: bne a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: lw ra, 12(sp) ; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: # %if.then ; CHECK-NEXT: .LBB7_2: # %if.then
; CHECK-NEXT: call abort ; CHECK-NEXT: call abort@plt
entry: entry:
%0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2 %0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2
%cmp = icmp eq i16 %0, 140 %cmp = icmp eq i16 %0, 140
br i1 %cmp, label %if.end, label %if.then br i1 %cmp, label %if.end, label %if.then
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
Show All 18 Lines

llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved. ; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.
define i32 @explicit_register_x1(i32 %a) nounwind { define i32 @explicit_register_x1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x1: ; RV32I-LABEL: explicit_register_x1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv ra, a0 ; RV32I-NEXT: mv ra, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, ra, 0 ; RV32I-NEXT: addi a0, ra, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x1: ; RV64I-LABEL: explicit_register_x1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv ra, a0 ; RV64I-NEXT: mv ra, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, ra, 0 ; RV64I-NEXT: addi a0, ra, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved. ; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.
define i32 @explicit_register_ra(i32 %a) nounwind { define i32 @explicit_register_ra(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_ra: ; RV32I-LABEL: explicit_register_ra:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv ra, a0 ; RV32I-NEXT: mv ra, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, ra, 0 ; RV32I-NEXT: addi a0, ra, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_ra: ; RV64I-LABEL: explicit_register_ra:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv ra, a0 ; RV64I-NEXT: mv ra, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, ra, 0 ; RV64I-NEXT: addi a0, ra, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x2(i32 %a) nounwind { define i32 @explicit_register_x2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x2: ; RV32I-LABEL: explicit_register_x2:
Show All 35 Lines; RV64I-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved. ; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.
define i32 @explicit_register_x3(i32 %a) nounwind { define i32 @explicit_register_x3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x3: ; RV32I-LABEL: explicit_register_x3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw gp, 12(sp) ; RV32I-NEXT: sw gp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv gp, a0 ; RV32I-NEXT: mv gp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, gp, 0 ; RV32I-NEXT: addi a0, gp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw gp, 12(sp) ; RV32I-NEXT: lw gp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x3: ; RV64I-LABEL: explicit_register_x3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd gp, 8(sp) ; RV64I-NEXT: sd gp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv gp, a0 ; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0 ; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) ; RV64I-NEXT: ld gp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved. ; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.
define i32 @explicit_register_gp(i32 %a) nounwind { define i32 @explicit_register_gp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_gp: ; RV32I-LABEL: explicit_register_gp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw gp, 12(sp) ; RV32I-NEXT: sw gp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv gp, a0 ; RV32I-NEXT: mv gp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, gp, 0 ; RV32I-NEXT: addi a0, gp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw gp, 12(sp) ; RV32I-NEXT: lw gp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_gp: ; RV64I-LABEL: explicit_register_gp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd gp, 8(sp) ; RV64I-NEXT: sd gp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv gp, a0 ; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0 ; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) ; RV64I-NEXT: ld gp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved. ; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.
define i32 @explicit_register_x4(i32 %a) nounwind { define i32 @explicit_register_x4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x4: ; RV32I-LABEL: explicit_register_x4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw tp, 12(sp) ; RV32I-NEXT: sw tp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv tp, a0 ; RV32I-NEXT: mv tp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, tp, 0 ; RV32I-NEXT: addi a0, tp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw tp, 12(sp) ; RV32I-NEXT: lw tp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x4: ; RV64I-LABEL: explicit_register_x4:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd tp, 8(sp) ; RV64I-NEXT: sd tp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv tp, a0 ; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0 ; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) ; RV64I-NEXT: ld tp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved. ; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.
define i32 @explicit_register_tp(i32 %a) nounwind { define i32 @explicit_register_tp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_tp: ; RV32I-LABEL: explicit_register_tp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw tp, 12(sp) ; RV32I-NEXT: sw tp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv tp, a0 ; RV32I-NEXT: mv tp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, tp, 0 ; RV32I-NEXT: addi a0, tp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw tp, 12(sp) ; RV32I-NEXT: lw tp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_tp: ; RV64I-LABEL: explicit_register_tp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd tp, 8(sp) ; RV64I-NEXT: sd tp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv tp, a0 ; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0 ; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) ; RV64I-NEXT: ld tp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x5(i32 %a) nounwind { define i32 @explicit_register_x5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x5: ; RV32I-LABEL: explicit_register_x5:
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved. ; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.
define i32 @explicit_register_x8(i32 %a) nounwind { define i32 @explicit_register_x8(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x8: ; RV32I-LABEL: explicit_register_x8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s0, 0 ; RV32I-NEXT: addi a0, s0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 12(sp) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x8: ; RV64I-LABEL: explicit_register_x8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved. ; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.
define i32 @explicit_register_s0(i32 %a) nounwind { define i32 @explicit_register_s0(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s0: ; RV32I-LABEL: explicit_register_s0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s0, 0 ; RV32I-NEXT: addi a0, s0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 12(sp) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s0: ; RV64I-LABEL: explicit_register_s0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved. ; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.
define i32 @explicit_register_fp(i32 %a) nounwind { define i32 @explicit_register_fp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_fp: ; RV32I-LABEL: explicit_register_fp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s0, 0 ; RV32I-NEXT: addi a0, s0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 12(sp) ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_fp: ; RV64I-LABEL: explicit_register_fp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved. ; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.
define i32 @explicit_register_x9(i32 %a) nounwind { define i32 @explicit_register_x9(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x9: ; RV32I-LABEL: explicit_register_x9:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s1, 12(sp) ; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s1, 0 ; RV32I-NEXT: addi a0, s1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s1, 12(sp) ; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x9: ; RV64I-LABEL: explicit_register_x9:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s1, 0 ; RV64I-NEXT: addi a0, s1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved. ; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.
define i32 @explicit_register_s1(i32 %a) nounwind { define i32 @explicit_register_s1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s1: ; RV32I-LABEL: explicit_register_s1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s1, 12(sp) ; RV32I-NEXT: sw s1, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s1, 0 ; RV32I-NEXT: addi a0, s1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s1, 12(sp) ; RV32I-NEXT: lw s1, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s1: ; RV64I-LABEL: explicit_register_s1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s1, 0 ; RV64I-NEXT: addi a0, s1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x10(i32 %a) nounwind { define i32 @explicit_register_x10(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x10: ; RV32I-LABEL: explicit_register_x10:
▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved. ; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.
define i32 @explicit_register_x18(i32 %a) nounwind { define i32 @explicit_register_x18(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x18: ; RV32I-LABEL: explicit_register_x18:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s2, 12(sp) ; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s2, 0 ; RV32I-NEXT: addi a0, s2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s2, 12(sp) ; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x18: ; RV64I-LABEL: explicit_register_x18:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s2, 8(sp) ; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s2, 0 ; RV64I-NEXT: addi a0, s2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s2, 8(sp) ; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved. ; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.
define i32 @explicit_register_s2(i32 %a) nounwind { define i32 @explicit_register_s2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s2: ; RV32I-LABEL: explicit_register_s2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s2, 12(sp) ; RV32I-NEXT: sw s2, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s2, 0 ; RV32I-NEXT: addi a0, s2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s2, 12(sp) ; RV32I-NEXT: lw s2, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s2: ; RV64I-LABEL: explicit_register_s2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s2, 8(sp) ; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s2, 0 ; RV64I-NEXT: addi a0, s2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s2, 8(sp) ; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved. ; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.
define i32 @explicit_register_x19(i32 %a) nounwind { define i32 @explicit_register_x19(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x19: ; RV32I-LABEL: explicit_register_x19:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s3, 0 ; RV32I-NEXT: addi a0, s3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x19: ; RV64I-LABEL: explicit_register_x19:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s3, 0 ; RV64I-NEXT: addi a0, s3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved. ; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.
define i32 @explicit_register_s3(i32 %a) nounwind { define i32 @explicit_register_s3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s3: ; RV32I-LABEL: explicit_register_s3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s3, 0 ; RV32I-NEXT: addi a0, s3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s3: ; RV64I-LABEL: explicit_register_s3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s3, 0 ; RV64I-NEXT: addi a0, s3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved. ; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.
define i32 @explicit_register_x20(i32 %a) nounwind { define i32 @explicit_register_x20(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x20: ; RV32I-LABEL: explicit_register_x20:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s4, 12(sp) ; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s4, 0 ; RV32I-NEXT: addi a0, s4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s4, 12(sp) ; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x20: ; RV64I-LABEL: explicit_register_x20:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s4, 8(sp) ; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s4, 0 ; RV64I-NEXT: addi a0, s4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) ; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved. ; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.
define i32 @explicit_register_s4(i32 %a) nounwind { define i32 @explicit_register_s4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s4: ; RV32I-LABEL: explicit_register_s4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s4, 12(sp) ; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s4, 0 ; RV32I-NEXT: addi a0, s4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s4, 12(sp) ; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s4: ; RV64I-LABEL: explicit_register_s4:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s4, 8(sp) ; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s4, 0 ; RV64I-NEXT: addi a0, s4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) ; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved. ; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.
define i32 @explicit_register_x21(i32 %a) nounwind { define i32 @explicit_register_x21(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x21: ; RV32I-LABEL: explicit_register_x21:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s5, 12(sp) ; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s5, 0 ; RV32I-NEXT: addi a0, s5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s5, 12(sp) ; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x21: ; RV64I-LABEL: explicit_register_x21:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s5, 0 ; RV64I-NEXT: addi a0, s5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved. ; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.
define i32 @explicit_register_s5(i32 %a) nounwind { define i32 @explicit_register_s5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s5: ; RV32I-LABEL: explicit_register_s5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s5, 12(sp) ; RV32I-NEXT: sw s5, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s5, 0 ; RV32I-NEXT: addi a0, s5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s5, 12(sp) ; RV32I-NEXT: lw s5, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s5: ; RV64I-LABEL: explicit_register_s5:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s5, 0 ; RV64I-NEXT: addi a0, s5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved. ; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.
define i32 @explicit_register_x22(i32 %a) nounwind { define i32 @explicit_register_x22(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x22: ; RV32I-LABEL: explicit_register_x22:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s6, 12(sp) ; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s6, 0 ; RV32I-NEXT: addi a0, s6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s6, 12(sp) ; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x22: ; RV64I-LABEL: explicit_register_x22:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s6, 8(sp) ; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s6, 0 ; RV64I-NEXT: addi a0, s6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s6, 8(sp) ; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved. ; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.
define i32 @explicit_register_s6(i32 %a) nounwind { define i32 @explicit_register_s6(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s6: ; RV32I-LABEL: explicit_register_s6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s6, 12(sp) ; RV32I-NEXT: sw s6, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s6, 0 ; RV32I-NEXT: addi a0, s6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s6, 12(sp) ; RV32I-NEXT: lw s6, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s6: ; RV64I-LABEL: explicit_register_s6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s6, 8(sp) ; RV64I-NEXT: sd s6, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s6, 0 ; RV64I-NEXT: addi a0, s6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s6, 8(sp) ; RV64I-NEXT: ld s6, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved. ; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.
define i32 @explicit_register_x23(i32 %a) nounwind { define i32 @explicit_register_x23(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x23: ; RV32I-LABEL: explicit_register_x23:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s7, 0 ; RV32I-NEXT: addi a0, s7, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x23: ; RV64I-LABEL: explicit_register_x23:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s7, 8(sp) ; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s7, 0 ; RV64I-NEXT: addi a0, s7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s7, 8(sp) ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved. ; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.
define i32 @explicit_register_s7(i32 %a) nounwind { define i32 @explicit_register_s7(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s7: ; RV32I-LABEL: explicit_register_s7:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s7, 0 ; RV32I-NEXT: addi a0, s7, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s7: ; RV64I-LABEL: explicit_register_s7:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s7, 8(sp) ; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s7, 0 ; RV64I-NEXT: addi a0, s7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s7, 8(sp) ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved. ; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.
define i32 @explicit_register_x24(i32 %a) nounwind { define i32 @explicit_register_x24(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x24: ; RV32I-LABEL: explicit_register_x24:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s8, 12(sp) ; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s8, 0 ; RV32I-NEXT: addi a0, s8, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s8, 12(sp) ; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x24: ; RV64I-LABEL: explicit_register_x24:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s8, 8(sp) ; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s8, 0 ; RV64I-NEXT: addi a0, s8, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s8, 8(sp) ; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved. ; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.
define i32 @explicit_register_s8(i32 %a) nounwind { define i32 @explicit_register_s8(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s8: ; RV32I-LABEL: explicit_register_s8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s8, 12(sp) ; RV32I-NEXT: sw s8, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s8, 0 ; RV32I-NEXT: addi a0, s8, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s8, 12(sp) ; RV32I-NEXT: lw s8, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s8: ; RV64I-LABEL: explicit_register_s8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s8, 8(sp) ; RV64I-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s8, 0 ; RV64I-NEXT: addi a0, s8, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s8, 8(sp) ; RV64I-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved. ; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.
define i32 @explicit_register_x25(i32 %a) nounwind { define i32 @explicit_register_x25(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x25: ; RV32I-LABEL: explicit_register_x25:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s9, 12(sp) ; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s9, 0 ; RV32I-NEXT: addi a0, s9, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s9, 12(sp) ; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x25: ; RV64I-LABEL: explicit_register_x25:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s9, 0 ; RV64I-NEXT: addi a0, s9, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved. ; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.
define i32 @explicit_register_s9(i32 %a) nounwind { define i32 @explicit_register_s9(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s9: ; RV32I-LABEL: explicit_register_s9:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s9, 12(sp) ; RV32I-NEXT: sw s9, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s9, 0 ; RV32I-NEXT: addi a0, s9, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s9, 12(sp) ; RV32I-NEXT: lw s9, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s9: ; RV64I-LABEL: explicit_register_s9:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s9, 0 ; RV64I-NEXT: addi a0, s9, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved. ; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.
define i32 @explicit_register_x26(i32 %a) nounwind { define i32 @explicit_register_x26(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x26: ; RV32I-LABEL: explicit_register_x26:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s10, 12(sp) ; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s10, a0 ; RV32I-NEXT: mv s10, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s10, 0 ; RV32I-NEXT: addi a0, s10, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s10, 12(sp) ; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x26: ; RV64I-LABEL: explicit_register_x26:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s10, 8(sp) ; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s10, a0 ; RV64I-NEXT: mv s10, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s10, 0 ; RV64I-NEXT: addi a0, s10, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s10, 8(sp) ; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved. ; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.
define i32 @explicit_register_s10(i32 %a) nounwind { define i32 @explicit_register_s10(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s10: ; RV32I-LABEL: explicit_register_s10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s10, 12(sp) ; RV32I-NEXT: sw s10, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s10, a0 ; RV32I-NEXT: mv s10, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s10, 0 ; RV32I-NEXT: addi a0, s10, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s10, 12(sp) ; RV32I-NEXT: lw s10, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s10: ; RV64I-LABEL: explicit_register_s10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s10, 8(sp) ; RV64I-NEXT: sd s10, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s10, a0 ; RV64I-NEXT: mv s10, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s10, 0 ; RV64I-NEXT: addi a0, s10, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s10, 8(sp) ; RV64I-NEXT: ld s10, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved. ; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.
define i32 @explicit_register_x27(i32 %a) nounwind { define i32 @explicit_register_x27(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x27: ; RV32I-LABEL: explicit_register_x27:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s11, 12(sp) ; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s11, a0 ; RV32I-NEXT: mv s11, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s11, 0 ; RV32I-NEXT: addi a0, s11, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s11, 12(sp) ; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x27: ; RV64I-LABEL: explicit_register_x27:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s11, 8(sp) ; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s11, a0 ; RV64I-NEXT: mv s11, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s11, 0 ; RV64I-NEXT: addi a0, s11, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s11, 8(sp) ; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved. ; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.
define i32 @explicit_register_s11(i32 %a) nounwind { define i32 @explicit_register_s11(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s11: ; RV32I-LABEL: explicit_register_s11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s11, 12(sp) ; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s11, a0 ; RV32I-NEXT: mv s11, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, s11, 0 ; RV32I-NEXT: addi a0, s11, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s11, 12(sp) ; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_s11: ; RV64I-LABEL: explicit_register_s11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd s11, 8(sp) ; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s11, a0 ; RV64I-NEXT: mv s11, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s11, 0 ; RV64I-NEXT: addi a0, s11, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s11, 8(sp) ; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x28(i32 %a) nounwind { define i32 @explicit_register_x28(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x28: ; RV32I-LABEL: explicit_register_x28:
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llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll

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} }
; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved. ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.
define i32 @explicit_register_f8(double %a) nounwind { define i32 @explicit_register_f8(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f8: ; RV32IFD-LABEL: explicit_register_f8:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs0, 8(sp) ; RV32IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs0 ; RV32IFD-NEXT: fcvt.w.d a0, fs0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs0, 8(sp) ; RV32IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f8: ; RV64IFD-LABEL: explicit_register_f8:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs0, 8(sp) ; RV64IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: fcvt.w.d a0, fs0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs0, 8(sp) ; RV64IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f8}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f8}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved. ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.
define i32 @explicit_register_fs0(double %a) nounwind { define i32 @explicit_register_fs0(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs0: ; RV32IFD-LABEL: explicit_register_fs0:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs0, 8(sp) ; RV32IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs0 ; RV32IFD-NEXT: fcvt.w.d a0, fs0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs0, 8(sp) ; RV32IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs0: ; RV64IFD-LABEL: explicit_register_fs0:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs0, 8(sp) ; RV64IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: fcvt.w.d a0, fs0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs0, 8(sp) ; RV64IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs0}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs0}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved. ; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.
define i32 @explicit_register_f9(double %a) nounwind { define i32 @explicit_register_f9(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f9: ; RV32IFD-LABEL: explicit_register_f9:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs1, 8(sp) ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs1 ; RV32IFD-NEXT: fcvt.w.d a0, fs1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs1, 8(sp) ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f9: ; RV64IFD-LABEL: explicit_register_f9:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs1, 8(sp) ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: fcvt.w.d a0, fs1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs1, 8(sp) ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f9}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f9}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved. ; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.
define i32 @explicit_register_fs1(double %a) nounwind { define i32 @explicit_register_fs1(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs1: ; RV32IFD-LABEL: explicit_register_fs1:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs1, 8(sp) ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs1 ; RV32IFD-NEXT: fcvt.w.d a0, fs1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs1, 8(sp) ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs1: ; RV64IFD-LABEL: explicit_register_fs1:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs1, 8(sp) ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: fcvt.w.d a0, fs1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs1, 8(sp) ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs1}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs1}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f10(double %a) nounwind { define i32 @explicit_register_f10(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f10: ; RV32IFD-LABEL: explicit_register_f10:
▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines; RV64IFD-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved. ; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.
define i32 @explicit_register_f18(double %a) nounwind { define i32 @explicit_register_f18(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f18: ; RV32IFD-LABEL: explicit_register_f18:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs2, 8(sp) ; RV32IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: fmv.d fs2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs2 ; RV32IFD-NEXT: fcvt.w.d a0, fs2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs2, 8(sp) ; RV32IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f18: ; RV64IFD-LABEL: explicit_register_f18:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs2, 8(sp) ; RV64IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: fcvt.w.d a0, fs2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs2, 8(sp) ; RV64IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f18}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f18}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved. ; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.
define i32 @explicit_register_fs2(double %a) nounwind { define i32 @explicit_register_fs2(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs2: ; RV32IFD-LABEL: explicit_register_fs2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs2, 8(sp) ; RV32IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: fmv.d fs2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs2 ; RV32IFD-NEXT: fcvt.w.d a0, fs2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs2, 8(sp) ; RV32IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs2: ; RV64IFD-LABEL: explicit_register_fs2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs2, 8(sp) ; RV64IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: fcvt.w.d a0, fs2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs2, 8(sp) ; RV64IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs2}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs2}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved. ; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.
define i32 @explicit_register_f19(double %a) nounwind { define i32 @explicit_register_f19(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f19: ; RV32IFD-LABEL: explicit_register_f19:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs3, 8(sp) ; RV32IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs3, fa0 ; RV32IFD-NEXT: fmv.d fs3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs3 ; RV32IFD-NEXT: fcvt.w.d a0, fs3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs3, 8(sp) ; RV32IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f19: ; RV64IFD-LABEL: explicit_register_f19:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs3, 8(sp) ; RV64IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: fmv.d fs3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: fcvt.w.d a0, fs3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs3, 8(sp) ; RV64IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f19}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f19}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved. ; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.
define i32 @explicit_register_fs3(double %a) nounwind { define i32 @explicit_register_fs3(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs3: ; RV32IFD-LABEL: explicit_register_fs3:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs3, 8(sp) ; RV32IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs3, fa0 ; RV32IFD-NEXT: fmv.d fs3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs3 ; RV32IFD-NEXT: fcvt.w.d a0, fs3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs3, 8(sp) ; RV32IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs3: ; RV64IFD-LABEL: explicit_register_fs3:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs3, 8(sp) ; RV64IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: fmv.d fs3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: fcvt.w.d a0, fs3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs3, 8(sp) ; RV64IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs3}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs3}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved. ; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.
define i32 @explicit_register_f20(double %a) nounwind { define i32 @explicit_register_f20(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f20: ; RV32IFD-LABEL: explicit_register_f20:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs4, 8(sp) ; RV32IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs4, fa0 ; RV32IFD-NEXT: fmv.d fs4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs4 ; RV32IFD-NEXT: fcvt.w.d a0, fs4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs4, 8(sp) ; RV32IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f20: ; RV64IFD-LABEL: explicit_register_f20:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs4, 8(sp) ; RV64IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: fmv.d fs4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: fcvt.w.d a0, fs4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs4, 8(sp) ; RV64IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f20}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f20}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved. ; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.
define i32 @explicit_register_fs4(double %a) nounwind { define i32 @explicit_register_fs4(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs4: ; RV32IFD-LABEL: explicit_register_fs4:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs4, 8(sp) ; RV32IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs4, fa0 ; RV32IFD-NEXT: fmv.d fs4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs4 ; RV32IFD-NEXT: fcvt.w.d a0, fs4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs4, 8(sp) ; RV32IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs4: ; RV64IFD-LABEL: explicit_register_fs4:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs4, 8(sp) ; RV64IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: fmv.d fs4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: fcvt.w.d a0, fs4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs4, 8(sp) ; RV64IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs4}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs4}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved. ; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.
define i32 @explicit_register_f21(double %a) nounwind { define i32 @explicit_register_f21(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f21: ; RV32IFD-LABEL: explicit_register_f21:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs5, 8(sp) ; RV32IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs5, fa0 ; RV32IFD-NEXT: fmv.d fs5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs5 ; RV32IFD-NEXT: fcvt.w.d a0, fs5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs5, 8(sp) ; RV32IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f21: ; RV64IFD-LABEL: explicit_register_f21:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs5, 8(sp) ; RV64IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: fmv.d fs5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: fcvt.w.d a0, fs5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs5, 8(sp) ; RV64IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f21}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f21}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved. ; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.
define i32 @explicit_register_fs5(double %a) nounwind { define i32 @explicit_register_fs5(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs5: ; RV32IFD-LABEL: explicit_register_fs5:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs5, 8(sp) ; RV32IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs5, fa0 ; RV32IFD-NEXT: fmv.d fs5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs5 ; RV32IFD-NEXT: fcvt.w.d a0, fs5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs5, 8(sp) ; RV32IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs5: ; RV64IFD-LABEL: explicit_register_fs5:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs5, 8(sp) ; RV64IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: fmv.d fs5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: fcvt.w.d a0, fs5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs5, 8(sp) ; RV64IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs5}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs5}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved. ; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.
define i32 @explicit_register_f22(double %a) nounwind { define i32 @explicit_register_f22(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f22: ; RV32IFD-LABEL: explicit_register_f22:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs6, 8(sp) ; RV32IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs6, fa0 ; RV32IFD-NEXT: fmv.d fs6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs6 ; RV32IFD-NEXT: fcvt.w.d a0, fs6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs6, 8(sp) ; RV32IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f22: ; RV64IFD-LABEL: explicit_register_f22:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs6, 8(sp) ; RV64IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: fmv.d fs6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: fcvt.w.d a0, fs6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs6, 8(sp) ; RV64IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f22}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f22}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved. ; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.
define i32 @explicit_register_fs6(double %a) nounwind { define i32 @explicit_register_fs6(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs6: ; RV32IFD-LABEL: explicit_register_fs6:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs6, 8(sp) ; RV32IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs6, fa0 ; RV32IFD-NEXT: fmv.d fs6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs6 ; RV32IFD-NEXT: fcvt.w.d a0, fs6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs6, 8(sp) ; RV32IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs6: ; RV64IFD-LABEL: explicit_register_fs6:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs6, 8(sp) ; RV64IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: fmv.d fs6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: fcvt.w.d a0, fs6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs6, 8(sp) ; RV64IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs6}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs6}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved. ; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.
define i32 @explicit_register_f23(double %a) nounwind { define i32 @explicit_register_f23(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f23: ; RV32IFD-LABEL: explicit_register_f23:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs7, 8(sp) ; RV32IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs7, fa0 ; RV32IFD-NEXT: fmv.d fs7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs7 ; RV32IFD-NEXT: fcvt.w.d a0, fs7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs7, 8(sp) ; RV32IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f23: ; RV64IFD-LABEL: explicit_register_f23:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs7, 8(sp) ; RV64IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: fmv.d fs7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: fcvt.w.d a0, fs7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs7, 8(sp) ; RV64IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f23}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f23}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved. ; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.
define i32 @explicit_register_fs7(double %a) nounwind { define i32 @explicit_register_fs7(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs7: ; RV32IFD-LABEL: explicit_register_fs7:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs7, 8(sp) ; RV32IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs7, fa0 ; RV32IFD-NEXT: fmv.d fs7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs7 ; RV32IFD-NEXT: fcvt.w.d a0, fs7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs7, 8(sp) ; RV32IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs7: ; RV64IFD-LABEL: explicit_register_fs7:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs7, 8(sp) ; RV64IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: fmv.d fs7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: fcvt.w.d a0, fs7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs7, 8(sp) ; RV64IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs7}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs7}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved. ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.
define i32 @explicit_register_f24(double %a) nounwind { define i32 @explicit_register_f24(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f24: ; RV32IFD-LABEL: explicit_register_f24:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs8, 8(sp) ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs8, fa0 ; RV32IFD-NEXT: fmv.d fs8, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs8 ; RV32IFD-NEXT: fcvt.w.d a0, fs8
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs8, 8(sp) ; RV32IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f24: ; RV64IFD-LABEL: explicit_register_f24:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs8, 8(sp) ; RV64IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: fmv.d fs8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: fcvt.w.d a0, fs8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs8, 8(sp) ; RV64IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f24}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f24}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved. ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.
define i32 @explicit_register_fs8(double %a) nounwind { define i32 @explicit_register_fs8(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs8: ; RV32IFD-LABEL: explicit_register_fs8:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs8, 8(sp) ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs8, fa0 ; RV32IFD-NEXT: fmv.d fs8, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs8 ; RV32IFD-NEXT: fcvt.w.d a0, fs8
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs8, 8(sp) ; RV32IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs8: ; RV64IFD-LABEL: explicit_register_fs8:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs8, 8(sp) ; RV64IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: fmv.d fs8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: fcvt.w.d a0, fs8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs8, 8(sp) ; RV64IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs8}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs8}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved. ; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.
define i32 @explicit_register_f25(double %a) nounwind { define i32 @explicit_register_f25(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f25: ; RV32IFD-LABEL: explicit_register_f25:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs9, 8(sp) ; RV32IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs9, fa0 ; RV32IFD-NEXT: fmv.d fs9, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs9 ; RV32IFD-NEXT: fcvt.w.d a0, fs9
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs9, 8(sp) ; RV32IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f25: ; RV64IFD-LABEL: explicit_register_f25:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs9, 8(sp) ; RV64IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: fmv.d fs9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: fcvt.w.d a0, fs9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs9, 8(sp) ; RV64IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f25}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f25}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved. ; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.
define i32 @explicit_register_fs9(double %a) nounwind { define i32 @explicit_register_fs9(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs9: ; RV32IFD-LABEL: explicit_register_fs9:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs9, 8(sp) ; RV32IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs9, fa0 ; RV32IFD-NEXT: fmv.d fs9, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs9 ; RV32IFD-NEXT: fcvt.w.d a0, fs9
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs9, 8(sp) ; RV32IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs9: ; RV64IFD-LABEL: explicit_register_fs9:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs9, 8(sp) ; RV64IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: fmv.d fs9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: fcvt.w.d a0, fs9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs9, 8(sp) ; RV64IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs9}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs9}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved. ; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.
define i32 @explicit_register_f26(double %a) nounwind { define i32 @explicit_register_f26(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f26: ; RV32IFD-LABEL: explicit_register_f26:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs10, 8(sp) ; RV32IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs10, fa0 ; RV32IFD-NEXT: fmv.d fs10, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs10 ; RV32IFD-NEXT: fcvt.w.d a0, fs10
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs10, 8(sp) ; RV32IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f26: ; RV64IFD-LABEL: explicit_register_f26:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs10, 8(sp) ; RV64IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: fmv.d fs10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: fcvt.w.d a0, fs10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs10, 8(sp) ; RV64IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f26}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f26}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved. ; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.
define i32 @explicit_register_fs10(double %a) nounwind { define i32 @explicit_register_fs10(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs10: ; RV32IFD-LABEL: explicit_register_fs10:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs10, 8(sp) ; RV32IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs10, fa0 ; RV32IFD-NEXT: fmv.d fs10, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs10 ; RV32IFD-NEXT: fcvt.w.d a0, fs10
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs10, 8(sp) ; RV32IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs10: ; RV64IFD-LABEL: explicit_register_fs10:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs10, 8(sp) ; RV64IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: fmv.d fs10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: fcvt.w.d a0, fs10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs10, 8(sp) ; RV64IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs10}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs10}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved. ; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.
define i32 @explicit_register_f27(double %a) nounwind { define i32 @explicit_register_f27(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f27: ; RV32IFD-LABEL: explicit_register_f27:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs11, 8(sp) ; RV32IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs11, fa0 ; RV32IFD-NEXT: fmv.d fs11, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs11 ; RV32IFD-NEXT: fcvt.w.d a0, fs11
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs11, 8(sp) ; RV32IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f27: ; RV64IFD-LABEL: explicit_register_f27:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs11, 8(sp) ; RV64IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: fmv.d fs11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: fcvt.w.d a0, fs11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs11, 8(sp) ; RV64IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f27}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f27}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved. ; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.
define i32 @explicit_register_fs11(double %a) nounwind { define i32 @explicit_register_fs11(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs11: ; RV32IFD-LABEL: explicit_register_fs11:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fsd fs11, 8(sp) ; RV32IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs11, fa0 ; RV32IFD-NEXT: fmv.d fs11, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fs11 ; RV32IFD-NEXT: fcvt.w.d a0, fs11
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: fld fs11, 8(sp) ; RV32IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fs11: ; RV64IFD-LABEL: explicit_register_fs11:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: fsd fs11, 8(sp) ; RV64IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: fmv.d fs11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: fcvt.w.d a0, fs11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs11, 8(sp) ; RV64IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs11}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs11}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f28(double %a) nounwind { define i32 @explicit_register_f28(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f28: ; RV32IFD-LABEL: explicit_register_f28:
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll

Show First 20 Lines • Show All 335 Lines • ▼ Show 20 Lines
} }
; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved. ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.
define i32 @explicit_register_f8(float %a) nounwind { define i32 @explicit_register_f8(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f8: ; RV32IF-LABEL: explicit_register_f8:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs0, 12(sp) ; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs0 ; RV32IF-NEXT: fcvt.w.s a0, fs0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs0, 12(sp) ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f8: ; RV64IF-LABEL: explicit_register_f8:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs0, 12(sp) ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: fcvt.w.s a0, fs0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs0, 12(sp) ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved. ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.
define i32 @explicit_register_fs0(float %a) nounwind { define i32 @explicit_register_fs0(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs0: ; RV32IF-LABEL: explicit_register_fs0:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs0, 12(sp) ; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs0 ; RV32IF-NEXT: fcvt.w.s a0, fs0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs0, 12(sp) ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs0: ; RV64IF-LABEL: explicit_register_fs0:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs0, 12(sp) ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: fcvt.w.s a0, fs0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs0, 12(sp) ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved. ; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.
define i32 @explicit_register_f9(float %a) nounwind { define i32 @explicit_register_f9(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f9: ; RV32IF-LABEL: explicit_register_f9:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs1, 12(sp) ; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: fmv.s fs1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs1 ; RV32IF-NEXT: fcvt.w.s a0, fs1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs1, 12(sp) ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f9: ; RV64IF-LABEL: explicit_register_f9:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs1, 12(sp) ; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: fmv.s fs1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: fcvt.w.s a0, fs1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs1, 12(sp) ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved. ; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.
define i32 @explicit_register_fs1(float %a) nounwind { define i32 @explicit_register_fs1(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs1: ; RV32IF-LABEL: explicit_register_fs1:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs1, 12(sp) ; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: fmv.s fs1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs1 ; RV32IF-NEXT: fcvt.w.s a0, fs1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs1, 12(sp) ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs1: ; RV64IF-LABEL: explicit_register_fs1:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs1, 12(sp) ; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: fmv.s fs1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: fcvt.w.s a0, fs1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs1, 12(sp) ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f10(float %a) nounwind { define i32 @explicit_register_f10(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f10: ; RV32IF-LABEL: explicit_register_f10:
▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines; RV64IF-NEXT: ret
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved. ; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.
define i32 @explicit_register_f18(float %a) nounwind { define i32 @explicit_register_f18(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f18: ; RV32IF-LABEL: explicit_register_f18:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs2, 12(sp) ; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs2, fa0 ; RV32IF-NEXT: fmv.s fs2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs2 ; RV32IF-NEXT: fcvt.w.s a0, fs2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs2, 12(sp) ; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f18: ; RV64IF-LABEL: explicit_register_f18:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs2, 12(sp) ; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: fmv.s fs2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: fcvt.w.s a0, fs2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs2, 12(sp) ; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved. ; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.
define i32 @explicit_register_fs2(float %a) nounwind { define i32 @explicit_register_fs2(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs2: ; RV32IF-LABEL: explicit_register_fs2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs2, 12(sp) ; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs2, fa0 ; RV32IF-NEXT: fmv.s fs2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs2 ; RV32IF-NEXT: fcvt.w.s a0, fs2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs2, 12(sp) ; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs2: ; RV64IF-LABEL: explicit_register_fs2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs2, 12(sp) ; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: fmv.s fs2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: fcvt.w.s a0, fs2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs2, 12(sp) ; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved. ; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.
define i32 @explicit_register_f19(float %a) nounwind { define i32 @explicit_register_f19(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f19: ; RV32IF-LABEL: explicit_register_f19:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs3, 12(sp) ; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs3, fa0 ; RV32IF-NEXT: fmv.s fs3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs3 ; RV32IF-NEXT: fcvt.w.s a0, fs3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs3, 12(sp) ; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f19: ; RV64IF-LABEL: explicit_register_f19:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs3, 12(sp) ; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: fmv.s fs3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: fcvt.w.s a0, fs3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs3, 12(sp) ; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved. ; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.
define i32 @explicit_register_fs3(float %a) nounwind { define i32 @explicit_register_fs3(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs3: ; RV32IF-LABEL: explicit_register_fs3:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs3, 12(sp) ; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs3, fa0 ; RV32IF-NEXT: fmv.s fs3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs3 ; RV32IF-NEXT: fcvt.w.s a0, fs3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs3, 12(sp) ; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs3: ; RV64IF-LABEL: explicit_register_fs3:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs3, 12(sp) ; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: fmv.s fs3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: fcvt.w.s a0, fs3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs3, 12(sp) ; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved. ; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.
define i32 @explicit_register_f20(float %a) nounwind { define i32 @explicit_register_f20(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f20: ; RV32IF-LABEL: explicit_register_f20:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs4, 12(sp) ; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs4, fa0 ; RV32IF-NEXT: fmv.s fs4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs4 ; RV32IF-NEXT: fcvt.w.s a0, fs4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs4, 12(sp) ; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f20: ; RV64IF-LABEL: explicit_register_f20:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs4, 12(sp) ; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: fmv.s fs4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: fcvt.w.s a0, fs4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs4, 12(sp) ; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved. ; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.
define i32 @explicit_register_fs4(float %a) nounwind { define i32 @explicit_register_fs4(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs4: ; RV32IF-LABEL: explicit_register_fs4:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs4, 12(sp) ; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs4, fa0 ; RV32IF-NEXT: fmv.s fs4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs4 ; RV32IF-NEXT: fcvt.w.s a0, fs4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs4, 12(sp) ; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs4: ; RV64IF-LABEL: explicit_register_fs4:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs4, 12(sp) ; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: fmv.s fs4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: fcvt.w.s a0, fs4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs4, 12(sp) ; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved. ; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.
define i32 @explicit_register_f21(float %a) nounwind { define i32 @explicit_register_f21(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f21: ; RV32IF-LABEL: explicit_register_f21:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs5, 12(sp) ; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs5, fa0 ; RV32IF-NEXT: fmv.s fs5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs5 ; RV32IF-NEXT: fcvt.w.s a0, fs5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs5, 12(sp) ; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f21: ; RV64IF-LABEL: explicit_register_f21:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs5, 12(sp) ; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: fmv.s fs5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: fcvt.w.s a0, fs5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs5, 12(sp) ; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved. ; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.
define i32 @explicit_register_fs5(float %a) nounwind { define i32 @explicit_register_fs5(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs5: ; RV32IF-LABEL: explicit_register_fs5:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs5, 12(sp) ; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs5, fa0 ; RV32IF-NEXT: fmv.s fs5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs5 ; RV32IF-NEXT: fcvt.w.s a0, fs5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs5, 12(sp) ; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs5: ; RV64IF-LABEL: explicit_register_fs5:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs5, 12(sp) ; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: fmv.s fs5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: fcvt.w.s a0, fs5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs5, 12(sp) ; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved. ; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.
define i32 @explicit_register_f22(float %a) nounwind { define i32 @explicit_register_f22(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f22: ; RV32IF-LABEL: explicit_register_f22:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs6, 12(sp) ; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs6, fa0 ; RV32IF-NEXT: fmv.s fs6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs6 ; RV32IF-NEXT: fcvt.w.s a0, fs6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs6, 12(sp) ; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f22: ; RV64IF-LABEL: explicit_register_f22:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs6, 12(sp) ; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: fmv.s fs6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: fcvt.w.s a0, fs6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs6, 12(sp) ; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved. ; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.
define i32 @explicit_register_fs6(float %a) nounwind { define i32 @explicit_register_fs6(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs6: ; RV32IF-LABEL: explicit_register_fs6:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs6, 12(sp) ; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs6, fa0 ; RV32IF-NEXT: fmv.s fs6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs6 ; RV32IF-NEXT: fcvt.w.s a0, fs6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs6, 12(sp) ; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs6: ; RV64IF-LABEL: explicit_register_fs6:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs6, 12(sp) ; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: fmv.s fs6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: fcvt.w.s a0, fs6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs6, 12(sp) ; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved. ; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.
define i32 @explicit_register_f23(float %a) nounwind { define i32 @explicit_register_f23(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f23: ; RV32IF-LABEL: explicit_register_f23:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs7, 12(sp) ; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs7, fa0 ; RV32IF-NEXT: fmv.s fs7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs7 ; RV32IF-NEXT: fcvt.w.s a0, fs7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs7, 12(sp) ; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f23: ; RV64IF-LABEL: explicit_register_f23:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs7, 12(sp) ; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: fmv.s fs7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: fcvt.w.s a0, fs7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs7, 12(sp) ; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved. ; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.
define i32 @explicit_register_fs7(float %a) nounwind { define i32 @explicit_register_fs7(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs7: ; RV32IF-LABEL: explicit_register_fs7:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs7, 12(sp) ; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs7, fa0 ; RV32IF-NEXT: fmv.s fs7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs7 ; RV32IF-NEXT: fcvt.w.s a0, fs7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs7, 12(sp) ; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs7: ; RV64IF-LABEL: explicit_register_fs7:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs7, 12(sp) ; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: fmv.s fs7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: fcvt.w.s a0, fs7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs7, 12(sp) ; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved. ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.
define i32 @explicit_register_f24(float %a) nounwind { define i32 @explicit_register_f24(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f24: ; RV32IF-LABEL: explicit_register_f24:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs8, 12(sp) ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs8, fa0 ; RV32IF-NEXT: fmv.s fs8, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs8 ; RV32IF-NEXT: fcvt.w.s a0, fs8
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs8, 12(sp) ; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f24: ; RV64IF-LABEL: explicit_register_f24:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs8, 12(sp) ; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: fmv.s fs8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: fcvt.w.s a0, fs8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs8, 12(sp) ; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved. ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.
define i32 @explicit_register_fs8(float %a) nounwind { define i32 @explicit_register_fs8(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs8: ; RV32IF-LABEL: explicit_register_fs8:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs8, 12(sp) ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs8, fa0 ; RV32IF-NEXT: fmv.s fs8, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs8 ; RV32IF-NEXT: fcvt.w.s a0, fs8
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs8, 12(sp) ; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs8: ; RV64IF-LABEL: explicit_register_fs8:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs8, 12(sp) ; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: fmv.s fs8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: fcvt.w.s a0, fs8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs8, 12(sp) ; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved. ; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.
define i32 @explicit_register_f25(float %a) nounwind { define i32 @explicit_register_f25(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f25: ; RV32IF-LABEL: explicit_register_f25:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs9, 12(sp) ; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs9, fa0 ; RV32IF-NEXT: fmv.s fs9, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs9 ; RV32IF-NEXT: fcvt.w.s a0, fs9
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs9, 12(sp) ; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f25: ; RV64IF-LABEL: explicit_register_f25:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs9, 12(sp) ; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: fmv.s fs9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: fcvt.w.s a0, fs9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs9, 12(sp) ; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved. ; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.
define i32 @explicit_register_fs9(float %a) nounwind { define i32 @explicit_register_fs9(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs9: ; RV32IF-LABEL: explicit_register_fs9:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs9, 12(sp) ; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs9, fa0 ; RV32IF-NEXT: fmv.s fs9, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs9 ; RV32IF-NEXT: fcvt.w.s a0, fs9
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs9, 12(sp) ; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs9: ; RV64IF-LABEL: explicit_register_fs9:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs9, 12(sp) ; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: fmv.s fs9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: fcvt.w.s a0, fs9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs9, 12(sp) ; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved. ; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.
define i32 @explicit_register_f26(float %a) nounwind { define i32 @explicit_register_f26(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f26: ; RV32IF-LABEL: explicit_register_f26:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs10, 12(sp) ; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs10, fa0 ; RV32IF-NEXT: fmv.s fs10, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs10 ; RV32IF-NEXT: fcvt.w.s a0, fs10
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs10, 12(sp) ; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f26: ; RV64IF-LABEL: explicit_register_f26:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs10, 12(sp) ; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: fmv.s fs10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: fcvt.w.s a0, fs10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs10, 12(sp) ; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved. ; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.
define i32 @explicit_register_fs10(float %a) nounwind { define i32 @explicit_register_fs10(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs10: ; RV32IF-LABEL: explicit_register_fs10:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs10, 12(sp) ; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs10, fa0 ; RV32IF-NEXT: fmv.s fs10, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs10 ; RV32IF-NEXT: fcvt.w.s a0, fs10
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs10, 12(sp) ; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs10: ; RV64IF-LABEL: explicit_register_fs10:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs10, 12(sp) ; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: fmv.s fs10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: fcvt.w.s a0, fs10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs10, 12(sp) ; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved. ; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.
define i32 @explicit_register_f27(float %a) nounwind { define i32 @explicit_register_f27(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f27: ; RV32IF-LABEL: explicit_register_f27:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs11, 12(sp) ; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs11, fa0 ; RV32IF-NEXT: fmv.s fs11, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs11 ; RV32IF-NEXT: fcvt.w.s a0, fs11
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs11, 12(sp) ; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f27: ; RV64IF-LABEL: explicit_register_f27:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs11, 12(sp) ; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: fmv.s fs11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: fcvt.w.s a0, fs11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs11, 12(sp) ; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved. ; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.
define i32 @explicit_register_fs11(float %a) nounwind { define i32 @explicit_register_fs11(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs11: ; RV32IF-LABEL: explicit_register_fs11:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: fsw fs11, 12(sp) ; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs11, fa0 ; RV32IF-NEXT: fmv.s fs11, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fs11 ; RV32IF-NEXT: fcvt.w.s a0, fs11
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: flw fs11, 12(sp) ; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fs11: ; RV64IF-LABEL: explicit_register_fs11:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: fsw fs11, 12(sp) ; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: fmv.s fs11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: fcvt.w.s a0, fs11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs11, 12(sp) ; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f28(float %a) nounwind { define i32 @explicit_register_f28(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f28: ; RV32IF-LABEL: explicit_register_f28:
▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \ ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F
; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \ ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD
; ;
; The test case check that the function call in an interrupt handler will use ; The test case check that the function call in an interrupt handler will use
; the correct CallPreservedMask as normal function. So only callee saved ; the correct CallPreservedMask as normal function. So only callee saved
; registers could live through the function call. ; registers could live through the function call.
define dso_local void @handler() nounwind { define dso_local void @handler() nounwind {
; CHECK-RV32-LABEL: handler: ; CHECK-RV32-LABEL: handler:
; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: sw ra, 12(sp) ; CHECK-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 8(sp) ; CHECK-RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: lui a0, 2 ; CHECK-RV32-NEXT: lui a0, 2
; CHECK-RV32-NEXT: addi a0, a0, 4 ; CHECK-RV32-NEXT: addi a0, a0, 4
; CHECK-RV32-NEXT: call read ; CHECK-RV32-NEXT: call read@plt
; CHECK-RV32-NEXT: mv s0, a0 ; CHECK-RV32-NEXT: mv s0, a0
; CHECK-RV32-NEXT: call callee ; CHECK-RV32-NEXT: call callee@plt
; CHECK-RV32-NEXT: mv a0, s0 ; CHECK-RV32-NEXT: mv a0, s0
; CHECK-RV32-NEXT: lw s0, 8(sp) ; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 12(sp) ; CHECK-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: tail write ; CHECK-RV32-NEXT: tail write@plt
; ;
; CHECK-RV32-F-LABEL: handler: ; CHECK-RV32-F-LABEL: handler:
; CHECK-RV32-F: # %bb.0: # %entry ; CHECK-RV32-F: # %bb.0: # %entry
; CHECK-RV32-F-NEXT: addi sp, sp, -16 ; CHECK-RV32-F-NEXT: addi sp, sp, -16
; CHECK-RV32-F-NEXT: sw ra, 12(sp) ; CHECK-RV32-F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw s0, 8(sp) ; CHECK-RV32-F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: lui a0, 2 ; CHECK-RV32-F-NEXT: lui a0, 2
; CHECK-RV32-F-NEXT: addi a0, a0, 4 ; CHECK-RV32-F-NEXT: addi a0, a0, 4
; CHECK-RV32-F-NEXT: call read ; CHECK-RV32-F-NEXT: call read@plt
; CHECK-RV32-F-NEXT: mv s0, a0 ; CHECK-RV32-F-NEXT: mv s0, a0
; CHECK-RV32-F-NEXT: call callee ; CHECK-RV32-F-NEXT: call callee@plt
; CHECK-RV32-F-NEXT: mv a0, s0 ; CHECK-RV32-F-NEXT: mv a0, s0
; CHECK-RV32-F-NEXT: lw s0, 8(sp) ; CHECK-RV32-F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw ra, 12(sp) ; CHECK-RV32-F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: addi sp, sp, 16 ; CHECK-RV32-F-NEXT: addi sp, sp, 16
; CHECK-RV32-F-NEXT: tail write ; CHECK-RV32-F-NEXT: tail write@plt
; ;
; CHECK-RV32-FD-LABEL: handler: ; CHECK-RV32-FD-LABEL: handler:
; CHECK-RV32-FD: # %bb.0: # %entry ; CHECK-RV32-FD: # %bb.0: # %entry
; CHECK-RV32-FD-NEXT: addi sp, sp, -16 ; CHECK-RV32-FD-NEXT: addi sp, sp, -16
; CHECK-RV32-FD-NEXT: sw ra, 12(sp) ; CHECK-RV32-FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw s0, 8(sp) ; CHECK-RV32-FD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: lui a0, 2 ; CHECK-RV32-FD-NEXT: lui a0, 2
; CHECK-RV32-FD-NEXT: addi a0, a0, 4 ; CHECK-RV32-FD-NEXT: addi a0, a0, 4
; CHECK-RV32-FD-NEXT: call read ; CHECK-RV32-FD-NEXT: call read@plt
; CHECK-RV32-FD-NEXT: mv s0, a0 ; CHECK-RV32-FD-NEXT: mv s0, a0
; CHECK-RV32-FD-NEXT: call callee ; CHECK-RV32-FD-NEXT: call callee@plt
; CHECK-RV32-FD-NEXT: mv a0, s0 ; CHECK-RV32-FD-NEXT: mv a0, s0
; CHECK-RV32-FD-NEXT: lw s0, 8(sp) ; CHECK-RV32-FD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw ra, 12(sp) ; CHECK-RV32-FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: addi sp, sp, 16 ; CHECK-RV32-FD-NEXT: addi sp, sp, 16
; CHECK-RV32-FD-NEXT: tail write ; CHECK-RV32-FD-NEXT: tail write@plt
entry: entry:
%call = tail call i32 @read(i32 8196) %call = tail call i32 @read(i32 8196)
tail call void bitcast (void (...)* @callee to void ()*)() tail call void bitcast (void (...)* @callee to void ()*)()
tail call void @write(i32 %call) tail call void @write(i32 %call)
ret void ret void
} }
declare i32 @read(i32) declare i32 @read(i32)
declare void @callee(...) declare void @callee(...)
declare void @write(i32) declare void @write(i32)

llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll

Show All 20 Lines
@a = external global i32 @a = external global i32
@b = external global i32 @b = external global i32
@c = external global i32 @c = external global i32
define void @foo_i32() nounwind #0 { define void @foo_i32() nounwind #0 {
; CHECK-RV32-LABEL: foo_i32: ; CHECK-RV32-LABEL: foo_i32:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: sw a0, 12(sp) ; CHECK-RV32-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 8(sp) ; CHECK-RV32-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: lui a0, %hi(a) ; CHECK-RV32-NEXT: lui a0, %hi(a)
; CHECK-RV32-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32-NEXT: lui a1, %hi(b) ; CHECK-RV32-NEXT: lui a1, %hi(b)
; CHECK-RV32-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32-NEXT: add a0, a1, a0 ; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: lui a1, %hi(c) ; CHECK-RV32-NEXT: lui a1, %hi(c)
; CHECK-RV32-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32-NEXT: lw a1, 8(sp) ; CHECK-RV32-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 12(sp) ; CHECK-RV32-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_i32: ; CHECK-RV32IF-LABEL: foo_i32:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16 ; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw a0, 12(sp) ; CHECK-RV32IF-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a1, 8(sp) ; CHECK-RV32IF-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: lui a0, %hi(a) ; CHECK-RV32IF-NEXT: lui a0, %hi(a)
; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32IF-NEXT: lui a1, %hi(b) ; CHECK-RV32IF-NEXT: lui a1, %hi(b)
; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32IF-NEXT: add a0, a1, a0 ; CHECK-RV32IF-NEXT: add a0, a1, a0
; CHECK-RV32IF-NEXT: lui a1, %hi(c) ; CHECK-RV32IF-NEXT: lui a1, %hi(c)
; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32IF-NEXT: lw a1, 8(sp) ; CHECK-RV32IF-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 12(sp) ; CHECK-RV32IF-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 16 ; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_i32: ; CHECK-RV32IFD-LABEL: foo_i32:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -16 ; CHECK-RV32IFD-NEXT: addi sp, sp, -16
; CHECK-RV32IFD-NEXT: sw a0, 12(sp) ; CHECK-RV32IFD-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a1, 8(sp) ; CHECK-RV32IFD-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(a) ; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32IFD-NEXT: lui a1, %hi(b) ; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32IFD-NEXT: add a0, a1, a0 ; CHECK-RV32IFD-NEXT: add a0, a1, a0
; CHECK-RV32IFD-NEXT: lui a1, %hi(c) ; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32IFD-NEXT: lw a1, 8(sp) ; CHECK-RV32IFD-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 12(sp) ; CHECK-RV32IFD-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 16 ; CHECK-RV32IFD-NEXT: addi sp, sp, 16
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load i32, i32* @a %1 = load i32, i32* @a
%2 = load i32, i32* @b %2 = load i32, i32* @b
%add = add nsw i32 %2, %1 %add = add nsw i32 %2, %1
store i32 %add, i32* @c store i32 %add, i32* @c
ret void ret void
} }
; ;
; Additionally check frame pointer and return address are properly saved. ; Additionally check frame pointer and return address are properly saved.
; ;
define void @foo_fp_i32() nounwind #1 { define void @foo_fp_i32() nounwind #1 {
; CHECK-RV32-LABEL: foo_fp_i32: ; CHECK-RV32-LABEL: foo_fp_i32:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: sw ra, 12(sp) ; CHECK-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 8(sp) ; CHECK-RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 4(sp) ; CHECK-RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 0(sp) ; CHECK-RV32-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: addi s0, sp, 16 ; CHECK-RV32-NEXT: addi s0, sp, 16
; CHECK-RV32-NEXT: lui a0, %hi(a) ; CHECK-RV32-NEXT: lui a0, %hi(a)
; CHECK-RV32-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32-NEXT: lui a1, %hi(b) ; CHECK-RV32-NEXT: lui a1, %hi(b)
; CHECK-RV32-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32-NEXT: add a0, a1, a0 ; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: lui a1, %hi(c) ; CHECK-RV32-NEXT: lui a1, %hi(c)
; CHECK-RV32-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32-NEXT: lw a1, 0(sp) ; CHECK-RV32-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 4(sp) ; CHECK-RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 8(sp) ; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 12(sp) ; CHECK-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_fp_i32: ; CHECK-RV32IF-LABEL: foo_fp_i32:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16 ; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw ra, 12(sp) ; CHECK-RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw s0, 8(sp) ; CHECK-RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 4(sp) ; CHECK-RV32IF-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a1, 0(sp) ; CHECK-RV32IF-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: addi s0, sp, 16 ; CHECK-RV32IF-NEXT: addi s0, sp, 16
; CHECK-RV32IF-NEXT: lui a0, %hi(a) ; CHECK-RV32IF-NEXT: lui a0, %hi(a)
; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32IF-NEXT: lui a1, %hi(b) ; CHECK-RV32IF-NEXT: lui a1, %hi(b)
; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32IF-NEXT: add a0, a1, a0 ; CHECK-RV32IF-NEXT: add a0, a1, a0
; CHECK-RV32IF-NEXT: lui a1, %hi(c) ; CHECK-RV32IF-NEXT: lui a1, %hi(c)
; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32IF-NEXT: lw a1, 0(sp) ; CHECK-RV32IF-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 4(sp) ; CHECK-RV32IF-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw s0, 8(sp) ; CHECK-RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw ra, 12(sp) ; CHECK-RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 16 ; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_i32: ; CHECK-RV32IFD-LABEL: foo_fp_i32:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -16 ; CHECK-RV32IFD-NEXT: addi sp, sp, -16
; CHECK-RV32IFD-NEXT: sw ra, 12(sp) ; CHECK-RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 8(sp) ; CHECK-RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 4(sp) ; CHECK-RV32IFD-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a1, 0(sp) ; CHECK-RV32IFD-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 16 ; CHECK-RV32IFD-NEXT: addi s0, sp, 16
; CHECK-RV32IFD-NEXT: lui a0, %hi(a) ; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0) ; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
; CHECK-RV32IFD-NEXT: lui a1, %hi(b) ; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1) ; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
; CHECK-RV32IFD-NEXT: add a0, a1, a0 ; CHECK-RV32IFD-NEXT: add a0, a1, a0
; CHECK-RV32IFD-NEXT: lui a1, %hi(c) ; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1) ; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
; CHECK-RV32IFD-NEXT: lw a1, 0(sp) ; CHECK-RV32IFD-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 4(sp) ; CHECK-RV32IFD-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 8(sp) ; CHECK-RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw ra, 12(sp) ; CHECK-RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 16 ; CHECK-RV32IFD-NEXT: addi sp, sp, 16
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load i32, i32* @a %1 = load i32, i32* @a
%2 = load i32, i32* @b %2 = load i32, i32* @b
%add = add nsw i32 %2, %1 %add = add nsw i32 %2, %1
store i32 %add, i32* @c store i32 %add, i32* @c
ret void ret void
} }
@e = external global float @e = external global float
@f = external global float @f = external global float
@d = external global float @d = external global float
define void @foo_float() nounwind #0 { define void @foo_float() nounwind #0 {
; CHECK-RV32-LABEL: foo_float: ; CHECK-RV32-LABEL: foo_float:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -64 ; CHECK-RV32-NEXT: addi sp, sp, -64
; CHECK-RV32-NEXT: sw ra, 60(sp) ; CHECK-RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 56(sp) ; CHECK-RV32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 52(sp) ; CHECK-RV32-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 48(sp) ; CHECK-RV32-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 44(sp) ; CHECK-RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 40(sp) ; CHECK-RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 36(sp) ; CHECK-RV32-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 32(sp) ; CHECK-RV32-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 28(sp) ; CHECK-RV32-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 24(sp) ; CHECK-RV32-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 20(sp) ; CHECK-RV32-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 16(sp) ; CHECK-RV32-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 12(sp) ; CHECK-RV32-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 8(sp) ; CHECK-RV32-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 4(sp) ; CHECK-RV32-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 0(sp) ; CHECK-RV32-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: lui a0, %hi(e) ; CHECK-RV32-NEXT: lui a0, %hi(e)
; CHECK-RV32-NEXT: lw a0, %lo(e)(a0) ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
; CHECK-RV32-NEXT: lui a1, %hi(f) ; CHECK-RV32-NEXT: lui a1, %hi(f)
; CHECK-RV32-NEXT: lw a1, %lo(f)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
; CHECK-RV32-NEXT: call __addsf3 ; CHECK-RV32-NEXT: call __addsf3@plt
; CHECK-RV32-NEXT: lui a1, %hi(d) ; CHECK-RV32-NEXT: lui a1, %hi(d)
; CHECK-RV32-NEXT: sw a0, %lo(d)(a1) ; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
; CHECK-RV32-NEXT: lw t6, 0(sp) ; CHECK-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 4(sp) ; CHECK-RV32-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 8(sp) ; CHECK-RV32-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 12(sp) ; CHECK-RV32-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 16(sp) ; CHECK-RV32-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 20(sp) ; CHECK-RV32-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 24(sp) ; CHECK-RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 28(sp) ; CHECK-RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 32(sp) ; CHECK-RV32-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 36(sp) ; CHECK-RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 40(sp) ; CHECK-RV32-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 44(sp) ; CHECK-RV32-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 48(sp) ; CHECK-RV32-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 52(sp) ; CHECK-RV32-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 56(sp) ; CHECK-RV32-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 60(sp) ; CHECK-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 64 ; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_float: ; CHECK-RV32IF-LABEL: foo_float:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -16 ; CHECK-RV32IF-NEXT: addi sp, sp, -16
; CHECK-RV32IF-NEXT: sw a0, 12(sp) ; CHECK-RV32IF-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 8(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 4(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f) ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 4(sp) ; CHECK-RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 8(sp) ; CHECK-RV32IF-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 12(sp) ; CHECK-RV32IF-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 16 ; CHECK-RV32IF-NEXT: addi sp, sp, 16
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_float: ; CHECK-RV32IFD-LABEL: foo_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) ; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f) ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) ; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e %1 = load float, float* @e
%2 = load float, float* @f %2 = load float, float* @f
%add = fadd float %1, %2 %add = fadd float %1, %2
store float %add, float* @d store float %add, float* @d
ret void ret void
} }
; ;
; Additionally check frame pointer and return address are properly saved. ; Additionally check frame pointer and return address are properly saved.
; ;
define void @foo_fp_float() nounwind #1 { define void @foo_fp_float() nounwind #1 {
; CHECK-RV32-LABEL: foo_fp_float: ; CHECK-RV32-LABEL: foo_fp_float:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -80 ; CHECK-RV32-NEXT: addi sp, sp, -80
; CHECK-RV32-NEXT: sw ra, 76(sp) ; CHECK-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 72(sp) ; CHECK-RV32-NEXT: sw t0, 72(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 68(sp) ; CHECK-RV32-NEXT: sw t1, 68(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 64(sp) ; CHECK-RV32-NEXT: sw t2, 64(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 60(sp) ; CHECK-RV32-NEXT: sw s0, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 56(sp) ; CHECK-RV32-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 52(sp) ; CHECK-RV32-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 48(sp) ; CHECK-RV32-NEXT: sw a2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 44(sp) ; CHECK-RV32-NEXT: sw a3, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 40(sp) ; CHECK-RV32-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 36(sp) ; CHECK-RV32-NEXT: sw a5, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 32(sp) ; CHECK-RV32-NEXT: sw a6, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 28(sp) ; CHECK-RV32-NEXT: sw a7, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 24(sp) ; CHECK-RV32-NEXT: sw t3, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 20(sp) ; CHECK-RV32-NEXT: sw t4, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 16(sp) ; CHECK-RV32-NEXT: sw t5, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 12(sp) ; CHECK-RV32-NEXT: sw t6, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: addi s0, sp, 80 ; CHECK-RV32-NEXT: addi s0, sp, 80
; CHECK-RV32-NEXT: lui a0, %hi(e) ; CHECK-RV32-NEXT: lui a0, %hi(e)
; CHECK-RV32-NEXT: lw a0, %lo(e)(a0) ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
; CHECK-RV32-NEXT: lui a1, %hi(f) ; CHECK-RV32-NEXT: lui a1, %hi(f)
; CHECK-RV32-NEXT: lw a1, %lo(f)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
; CHECK-RV32-NEXT: call __addsf3 ; CHECK-RV32-NEXT: call __addsf3@plt
; CHECK-RV32-NEXT: lui a1, %hi(d) ; CHECK-RV32-NEXT: lui a1, %hi(d)
; CHECK-RV32-NEXT: sw a0, %lo(d)(a1) ; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
; CHECK-RV32-NEXT: lw t6, 12(sp) ; CHECK-RV32-NEXT: lw t6, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 16(sp) ; CHECK-RV32-NEXT: lw t5, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 20(sp) ; CHECK-RV32-NEXT: lw t4, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 24(sp) ; CHECK-RV32-NEXT: lw t3, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 28(sp) ; CHECK-RV32-NEXT: lw a7, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 32(sp) ; CHECK-RV32-NEXT: lw a6, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 36(sp) ; CHECK-RV32-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 40(sp) ; CHECK-RV32-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 44(sp) ; CHECK-RV32-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 48(sp) ; CHECK-RV32-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 52(sp) ; CHECK-RV32-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 56(sp) ; CHECK-RV32-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 60(sp) ; CHECK-RV32-NEXT: lw s0, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 64(sp) ; CHECK-RV32-NEXT: lw t2, 64(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 68(sp) ; CHECK-RV32-NEXT: lw t1, 68(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 72(sp) ; CHECK-RV32-NEXT: lw t0, 72(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 76(sp) ; CHECK-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 80 ; CHECK-RV32-NEXT: addi sp, sp, 80
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_fp_float: ; CHECK-RV32IF-LABEL: foo_fp_float:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -32 ; CHECK-RV32IF-NEXT: addi sp, sp, -32
; CHECK-RV32IF-NEXT: sw ra, 28(sp) ; CHECK-RV32IF-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw s0, 24(sp) ; CHECK-RV32IF-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 20(sp) ; CHECK-RV32IF-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 16(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 16(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 12(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: addi s0, sp, 32 ; CHECK-RV32IF-NEXT: addi s0, sp, 32
; CHECK-RV32IF-NEXT: lui a0, %hi(e) ; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f) ; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d) ; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 12(sp) ; CHECK-RV32IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 16(sp) ; CHECK-RV32IF-NEXT: flw ft0, 16(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 20(sp) ; CHECK-RV32IF-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw s0, 24(sp) ; CHECK-RV32IF-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw ra, 28(sp) ; CHECK-RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 32 ; CHECK-RV32IF-NEXT: addi sp, sp, 32
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_float: ; CHECK-RV32IFD-LABEL: foo_fp_float:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) ; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) ; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) ; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(e) ; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0) ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f) ; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0) ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d) ; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0) ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) ; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) ; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) ; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e %1 = load float, float* @e
%2 = load float, float* @f %2 = load float, float* @f
%add = fadd float %1, %2 %add = fadd float %1, %2
store float %add, float* @d store float %add, float* @d
ret void ret void
} }
@h = external global double @h = external global double
@i = external global double @i = external global double
@g = external global double @g = external global double
define void @foo_double() nounwind #0 { define void @foo_double() nounwind #0 {
; CHECK-RV32-LABEL: foo_double: ; CHECK-RV32-LABEL: foo_double:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -64 ; CHECK-RV32-NEXT: addi sp, sp, -64
; CHECK-RV32-NEXT: sw ra, 60(sp) ; CHECK-RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 56(sp) ; CHECK-RV32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 52(sp) ; CHECK-RV32-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 48(sp) ; CHECK-RV32-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 44(sp) ; CHECK-RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 40(sp) ; CHECK-RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 36(sp) ; CHECK-RV32-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 32(sp) ; CHECK-RV32-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 28(sp) ; CHECK-RV32-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 24(sp) ; CHECK-RV32-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 20(sp) ; CHECK-RV32-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 16(sp) ; CHECK-RV32-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 12(sp) ; CHECK-RV32-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 8(sp) ; CHECK-RV32-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 4(sp) ; CHECK-RV32-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 0(sp) ; CHECK-RV32-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: lui a1, %hi(h) ; CHECK-RV32-NEXT: lui a1, %hi(h)
; CHECK-RV32-NEXT: lw a0, %lo(h)(a1) ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1)
; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lui a3, %hi(i)
; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3)
; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: call __adddf3@plt
; CHECK-RV32-NEXT: lui a2, %hi(g) ; CHECK-RV32-NEXT: lui a2, %hi(g)
; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2)
; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
; CHECK-RV32-NEXT: lw t6, 0(sp) ; CHECK-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 4(sp) ; CHECK-RV32-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 8(sp) ; CHECK-RV32-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 12(sp) ; CHECK-RV32-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 16(sp) ; CHECK-RV32-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 20(sp) ; CHECK-RV32-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 24(sp) ; CHECK-RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 28(sp) ; CHECK-RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 32(sp) ; CHECK-RV32-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 36(sp) ; CHECK-RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 40(sp) ; CHECK-RV32-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 44(sp) ; CHECK-RV32-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 48(sp) ; CHECK-RV32-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 52(sp) ; CHECK-RV32-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 56(sp) ; CHECK-RV32-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 60(sp) ; CHECK-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 64 ; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_double: ; CHECK-RV32IF-LABEL: foo_double:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -192 ; CHECK-RV32IF-NEXT: addi sp, sp, -192
; CHECK-RV32IF-NEXT: sw ra, 188(sp) ; CHECK-RV32IF-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t0, 184(sp) ; CHECK-RV32IF-NEXT: sw t0, 184(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t1, 180(sp) ; CHECK-RV32IF-NEXT: sw t1, 180(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t2, 176(sp) ; CHECK-RV32IF-NEXT: sw t2, 176(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 172(sp) ; CHECK-RV32IF-NEXT: sw a0, 172(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a1, 168(sp) ; CHECK-RV32IF-NEXT: sw a1, 168(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a2, 164(sp) ; CHECK-RV32IF-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a3, 160(sp) ; CHECK-RV32IF-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a4, 156(sp) ; CHECK-RV32IF-NEXT: sw a4, 156(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a5, 152(sp) ; CHECK-RV32IF-NEXT: sw a5, 152(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a6, 148(sp) ; CHECK-RV32IF-NEXT: sw a6, 148(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a7, 144(sp) ; CHECK-RV32IF-NEXT: sw a7, 144(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t3, 140(sp) ; CHECK-RV32IF-NEXT: sw t3, 140(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t4, 136(sp) ; CHECK-RV32IF-NEXT: sw t4, 136(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t5, 132(sp) ; CHECK-RV32IF-NEXT: sw t5, 132(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t6, 128(sp) ; CHECK-RV32IF-NEXT: sw t6, 128(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 124(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 120(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft2, 116(sp) ; CHECK-RV32IF-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft3, 112(sp) ; CHECK-RV32IF-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft4, 108(sp) ; CHECK-RV32IF-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft5, 104(sp) ; CHECK-RV32IF-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft6, 100(sp) ; CHECK-RV32IF-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft7, 96(sp) ; CHECK-RV32IF-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa0, 92(sp) ; CHECK-RV32IF-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa1, 88(sp) ; CHECK-RV32IF-NEXT: fsw fa1, 88(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa2, 84(sp) ; CHECK-RV32IF-NEXT: fsw fa2, 84(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa3, 80(sp) ; CHECK-RV32IF-NEXT: fsw fa3, 80(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa4, 76(sp) ; CHECK-RV32IF-NEXT: fsw fa4, 76(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa5, 72(sp) ; CHECK-RV32IF-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa6, 68(sp) ; CHECK-RV32IF-NEXT: fsw fa6, 68(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa7, 64(sp) ; CHECK-RV32IF-NEXT: fsw fa7, 64(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft8, 60(sp) ; CHECK-RV32IF-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft9, 56(sp) ; CHECK-RV32IF-NEXT: fsw ft9, 56(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft10, 52(sp) ; CHECK-RV32IF-NEXT: fsw ft10, 52(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft11, 48(sp) ; CHECK-RV32IF-NEXT: fsw ft11, 48(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs0, 44(sp) ; CHECK-RV32IF-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs1, 40(sp) ; CHECK-RV32IF-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs2, 36(sp) ; CHECK-RV32IF-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs3, 32(sp) ; CHECK-RV32IF-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs4, 28(sp) ; CHECK-RV32IF-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs5, 24(sp) ; CHECK-RV32IF-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs6, 20(sp) ; CHECK-RV32IF-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs7, 16(sp) ; CHECK-RV32IF-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs8, 12(sp) ; CHECK-RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs9, 8(sp) ; CHECK-RV32IF-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs10, 4(sp) ; CHECK-RV32IF-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs11, 0(sp) ; CHECK-RV32IF-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: lui a1, %hi(h) ; CHECK-RV32IF-NEXT: lui a1, %hi(h)
; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1) ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1)
; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lui a3, %hi(i)
; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3)
; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: call __adddf3@plt
; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: lui a2, %hi(g)
; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2)
; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
; CHECK-RV32IF-NEXT: flw fs11, 0(sp) ; CHECK-RV32IF-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs10, 4(sp) ; CHECK-RV32IF-NEXT: flw fs10, 4(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs9, 8(sp) ; CHECK-RV32IF-NEXT: flw fs9, 8(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs8, 12(sp) ; CHECK-RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs7, 16(sp) ; CHECK-RV32IF-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs6, 20(sp) ; CHECK-RV32IF-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs5, 24(sp) ; CHECK-RV32IF-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs4, 28(sp) ; CHECK-RV32IF-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs3, 32(sp) ; CHECK-RV32IF-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs2, 36(sp) ; CHECK-RV32IF-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs1, 40(sp) ; CHECK-RV32IF-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs0, 44(sp) ; CHECK-RV32IF-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft11, 48(sp) ; CHECK-RV32IF-NEXT: flw ft11, 48(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft10, 52(sp) ; CHECK-RV32IF-NEXT: flw ft10, 52(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft9, 56(sp) ; CHECK-RV32IF-NEXT: flw ft9, 56(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft8, 60(sp) ; CHECK-RV32IF-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa7, 64(sp) ; CHECK-RV32IF-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa6, 68(sp) ; CHECK-RV32IF-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa5, 72(sp) ; CHECK-RV32IF-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa4, 76(sp) ; CHECK-RV32IF-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa3, 80(sp) ; CHECK-RV32IF-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa2, 84(sp) ; CHECK-RV32IF-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa1, 88(sp) ; CHECK-RV32IF-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa0, 92(sp) ; CHECK-RV32IF-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft7, 96(sp) ; CHECK-RV32IF-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft6, 100(sp) ; CHECK-RV32IF-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft5, 104(sp) ; CHECK-RV32IF-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft4, 108(sp) ; CHECK-RV32IF-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft3, 112(sp) ; CHECK-RV32IF-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft2, 116(sp) ; CHECK-RV32IF-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft1, 120(sp) ; CHECK-RV32IF-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 124(sp) ; CHECK-RV32IF-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t6, 128(sp) ; CHECK-RV32IF-NEXT: lw t6, 128(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t5, 132(sp) ; CHECK-RV32IF-NEXT: lw t5, 132(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t4, 136(sp) ; CHECK-RV32IF-NEXT: lw t4, 136(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t3, 140(sp) ; CHECK-RV32IF-NEXT: lw t3, 140(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a7, 144(sp) ; CHECK-RV32IF-NEXT: lw a7, 144(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a6, 148(sp) ; CHECK-RV32IF-NEXT: lw a6, 148(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a5, 152(sp) ; CHECK-RV32IF-NEXT: lw a5, 152(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a4, 156(sp) ; CHECK-RV32IF-NEXT: lw a4, 156(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a3, 160(sp) ; CHECK-RV32IF-NEXT: lw a3, 160(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a2, 164(sp) ; CHECK-RV32IF-NEXT: lw a2, 164(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a1, 168(sp) ; CHECK-RV32IF-NEXT: lw a1, 168(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 172(sp) ; CHECK-RV32IF-NEXT: lw a0, 172(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t2, 176(sp) ; CHECK-RV32IF-NEXT: lw t2, 176(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t1, 180(sp) ; CHECK-RV32IF-NEXT: lw t1, 180(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t0, 184(sp) ; CHECK-RV32IF-NEXT: lw t0, 184(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw ra, 188(sp) ; CHECK-RV32IF-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 192 ; CHECK-RV32IF-NEXT: addi sp, sp, 192
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_double: ; CHECK-RV32IFD-LABEL: foo_double:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw a0, 28(sp) ; CHECK-RV32IFD-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i) ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0) ; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 28(sp) ; CHECK-RV32IFD-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h %1 = load double, double* @h
%2 = load double, double* @i %2 = load double, double* @i
%add = fadd double %1, %2 %add = fadd double %1, %2
store double %add, double* @g store double %add, double* @g
ret void ret void
} }
; ;
; Additionally check frame pointer and return address are properly saved. ; Additionally check frame pointer and return address are properly saved.
; ;
define void @foo_fp_double() nounwind #1 { define void @foo_fp_double() nounwind #1 {
; CHECK-RV32-LABEL: foo_fp_double: ; CHECK-RV32-LABEL: foo_fp_double:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -80 ; CHECK-RV32-NEXT: addi sp, sp, -80
; CHECK-RV32-NEXT: sw ra, 76(sp) ; CHECK-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 72(sp) ; CHECK-RV32-NEXT: sw t0, 72(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 68(sp) ; CHECK-RV32-NEXT: sw t1, 68(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 64(sp) ; CHECK-RV32-NEXT: sw t2, 64(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 60(sp) ; CHECK-RV32-NEXT: sw s0, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 56(sp) ; CHECK-RV32-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 52(sp) ; CHECK-RV32-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 48(sp) ; CHECK-RV32-NEXT: sw a2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 44(sp) ; CHECK-RV32-NEXT: sw a3, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 40(sp) ; CHECK-RV32-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 36(sp) ; CHECK-RV32-NEXT: sw a5, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 32(sp) ; CHECK-RV32-NEXT: sw a6, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 28(sp) ; CHECK-RV32-NEXT: sw a7, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 24(sp) ; CHECK-RV32-NEXT: sw t3, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 20(sp) ; CHECK-RV32-NEXT: sw t4, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 16(sp) ; CHECK-RV32-NEXT: sw t5, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 12(sp) ; CHECK-RV32-NEXT: sw t6, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: addi s0, sp, 80 ; CHECK-RV32-NEXT: addi s0, sp, 80
; CHECK-RV32-NEXT: lui a1, %hi(h) ; CHECK-RV32-NEXT: lui a1, %hi(h)
; CHECK-RV32-NEXT: lw a0, %lo(h)(a1) ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1)
; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lui a3, %hi(i)
; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3)
; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: call __adddf3@plt
; CHECK-RV32-NEXT: lui a2, %hi(g) ; CHECK-RV32-NEXT: lui a2, %hi(g)
; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2)
; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
; CHECK-RV32-NEXT: lw t6, 12(sp) ; CHECK-RV32-NEXT: lw t6, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 16(sp) ; CHECK-RV32-NEXT: lw t5, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 20(sp) ; CHECK-RV32-NEXT: lw t4, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 24(sp) ; CHECK-RV32-NEXT: lw t3, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 28(sp) ; CHECK-RV32-NEXT: lw a7, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 32(sp) ; CHECK-RV32-NEXT: lw a6, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 36(sp) ; CHECK-RV32-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 40(sp) ; CHECK-RV32-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 44(sp) ; CHECK-RV32-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 48(sp) ; CHECK-RV32-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 52(sp) ; CHECK-RV32-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 56(sp) ; CHECK-RV32-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 60(sp) ; CHECK-RV32-NEXT: lw s0, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 64(sp) ; CHECK-RV32-NEXT: lw t2, 64(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 68(sp) ; CHECK-RV32-NEXT: lw t1, 68(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 72(sp) ; CHECK-RV32-NEXT: lw t0, 72(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 76(sp) ; CHECK-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 80 ; CHECK-RV32-NEXT: addi sp, sp, 80
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32IF-LABEL: foo_fp_double: ; CHECK-RV32IF-LABEL: foo_fp_double:
; CHECK-RV32IF: # %bb.0: ; CHECK-RV32IF: # %bb.0:
; CHECK-RV32IF-NEXT: addi sp, sp, -208 ; CHECK-RV32IF-NEXT: addi sp, sp, -208
; CHECK-RV32IF-NEXT: sw ra, 204(sp) ; CHECK-RV32IF-NEXT: sw ra, 204(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t0, 200(sp) ; CHECK-RV32IF-NEXT: sw t0, 200(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t1, 196(sp) ; CHECK-RV32IF-NEXT: sw t1, 196(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t2, 192(sp) ; CHECK-RV32IF-NEXT: sw t2, 192(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw s0, 188(sp) ; CHECK-RV32IF-NEXT: sw s0, 188(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a0, 184(sp) ; CHECK-RV32IF-NEXT: sw a0, 184(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a1, 180(sp) ; CHECK-RV32IF-NEXT: sw a1, 180(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a2, 176(sp) ; CHECK-RV32IF-NEXT: sw a2, 176(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a3, 172(sp) ; CHECK-RV32IF-NEXT: sw a3, 172(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a4, 168(sp) ; CHECK-RV32IF-NEXT: sw a4, 168(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a5, 164(sp) ; CHECK-RV32IF-NEXT: sw a5, 164(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a6, 160(sp) ; CHECK-RV32IF-NEXT: sw a6, 160(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw a7, 156(sp) ; CHECK-RV32IF-NEXT: sw a7, 156(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t3, 152(sp) ; CHECK-RV32IF-NEXT: sw t3, 152(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t4, 148(sp) ; CHECK-RV32IF-NEXT: sw t4, 148(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t5, 144(sp) ; CHECK-RV32IF-NEXT: sw t5, 144(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: sw t6, 140(sp) ; CHECK-RV32IF-NEXT: sw t6, 140(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft0, 136(sp) ; CHECK-RV32IF-NEXT: fsw ft0, 136(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft1, 132(sp) ; CHECK-RV32IF-NEXT: fsw ft1, 132(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft2, 128(sp) ; CHECK-RV32IF-NEXT: fsw ft2, 128(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft3, 124(sp) ; CHECK-RV32IF-NEXT: fsw ft3, 124(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft4, 120(sp) ; CHECK-RV32IF-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft5, 116(sp) ; CHECK-RV32IF-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft6, 112(sp) ; CHECK-RV32IF-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft7, 108(sp) ; CHECK-RV32IF-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa0, 104(sp) ; CHECK-RV32IF-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa1, 100(sp) ; CHECK-RV32IF-NEXT: fsw fa1, 100(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa2, 96(sp) ; CHECK-RV32IF-NEXT: fsw fa2, 96(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa3, 92(sp) ; CHECK-RV32IF-NEXT: fsw fa3, 92(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa4, 88(sp) ; CHECK-RV32IF-NEXT: fsw fa4, 88(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa5, 84(sp) ; CHECK-RV32IF-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa6, 80(sp) ; CHECK-RV32IF-NEXT: fsw fa6, 80(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fa7, 76(sp) ; CHECK-RV32IF-NEXT: fsw fa7, 76(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft8, 72(sp) ; CHECK-RV32IF-NEXT: fsw ft8, 72(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft9, 68(sp) ; CHECK-RV32IF-NEXT: fsw ft9, 68(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft10, 64(sp) ; CHECK-RV32IF-NEXT: fsw ft10, 64(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw ft11, 60(sp) ; CHECK-RV32IF-NEXT: fsw ft11, 60(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs0, 56(sp) ; CHECK-RV32IF-NEXT: fsw fs0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs1, 52(sp) ; CHECK-RV32IF-NEXT: fsw fs1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs2, 48(sp) ; CHECK-RV32IF-NEXT: fsw fs2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs3, 44(sp) ; CHECK-RV32IF-NEXT: fsw fs3, 44(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs4, 40(sp) ; CHECK-RV32IF-NEXT: fsw fs4, 40(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs5, 36(sp) ; CHECK-RV32IF-NEXT: fsw fs5, 36(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs6, 32(sp) ; CHECK-RV32IF-NEXT: fsw fs6, 32(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs7, 28(sp) ; CHECK-RV32IF-NEXT: fsw fs7, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs8, 24(sp) ; CHECK-RV32IF-NEXT: fsw fs8, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs9, 20(sp) ; CHECK-RV32IF-NEXT: fsw fs9, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs10, 16(sp) ; CHECK-RV32IF-NEXT: fsw fs10, 16(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: fsw fs11, 12(sp) ; CHECK-RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; CHECK-RV32IF-NEXT: addi s0, sp, 208 ; CHECK-RV32IF-NEXT: addi s0, sp, 208
; CHECK-RV32IF-NEXT: lui a1, %hi(h) ; CHECK-RV32IF-NEXT: lui a1, %hi(h)
; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1) ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1)
; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lui a3, %hi(i)
; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3)
; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: call __adddf3@plt
; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: lui a2, %hi(g)
; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2)
; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
; CHECK-RV32IF-NEXT: flw fs11, 12(sp) ; CHECK-RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs10, 16(sp) ; CHECK-RV32IF-NEXT: flw fs10, 16(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs9, 20(sp) ; CHECK-RV32IF-NEXT: flw fs9, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs8, 24(sp) ; CHECK-RV32IF-NEXT: flw fs8, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs7, 28(sp) ; CHECK-RV32IF-NEXT: flw fs7, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs6, 32(sp) ; CHECK-RV32IF-NEXT: flw fs6, 32(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs5, 36(sp) ; CHECK-RV32IF-NEXT: flw fs5, 36(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs4, 40(sp) ; CHECK-RV32IF-NEXT: flw fs4, 40(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs3, 44(sp) ; CHECK-RV32IF-NEXT: flw fs3, 44(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs2, 48(sp) ; CHECK-RV32IF-NEXT: flw fs2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs1, 52(sp) ; CHECK-RV32IF-NEXT: flw fs1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fs0, 56(sp) ; CHECK-RV32IF-NEXT: flw fs0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft11, 60(sp) ; CHECK-RV32IF-NEXT: flw ft11, 60(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft10, 64(sp) ; CHECK-RV32IF-NEXT: flw ft10, 64(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft9, 68(sp) ; CHECK-RV32IF-NEXT: flw ft9, 68(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft8, 72(sp) ; CHECK-RV32IF-NEXT: flw ft8, 72(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa7, 76(sp) ; CHECK-RV32IF-NEXT: flw fa7, 76(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa6, 80(sp) ; CHECK-RV32IF-NEXT: flw fa6, 80(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa5, 84(sp) ; CHECK-RV32IF-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa4, 88(sp) ; CHECK-RV32IF-NEXT: flw fa4, 88(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa3, 92(sp) ; CHECK-RV32IF-NEXT: flw fa3, 92(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa2, 96(sp) ; CHECK-RV32IF-NEXT: flw fa2, 96(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa1, 100(sp) ; CHECK-RV32IF-NEXT: flw fa1, 100(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw fa0, 104(sp) ; CHECK-RV32IF-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft7, 108(sp) ; CHECK-RV32IF-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft6, 112(sp) ; CHECK-RV32IF-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft5, 116(sp) ; CHECK-RV32IF-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft4, 120(sp) ; CHECK-RV32IF-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft3, 124(sp) ; CHECK-RV32IF-NEXT: flw ft3, 124(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft2, 128(sp) ; CHECK-RV32IF-NEXT: flw ft2, 128(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft1, 132(sp) ; CHECK-RV32IF-NEXT: flw ft1, 132(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: flw ft0, 136(sp) ; CHECK-RV32IF-NEXT: flw ft0, 136(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t6, 140(sp) ; CHECK-RV32IF-NEXT: lw t6, 140(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t5, 144(sp) ; CHECK-RV32IF-NEXT: lw t5, 144(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t4, 148(sp) ; CHECK-RV32IF-NEXT: lw t4, 148(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t3, 152(sp) ; CHECK-RV32IF-NEXT: lw t3, 152(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a7, 156(sp) ; CHECK-RV32IF-NEXT: lw a7, 156(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a6, 160(sp) ; CHECK-RV32IF-NEXT: lw a6, 160(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a5, 164(sp) ; CHECK-RV32IF-NEXT: lw a5, 164(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a4, 168(sp) ; CHECK-RV32IF-NEXT: lw a4, 168(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a3, 172(sp) ; CHECK-RV32IF-NEXT: lw a3, 172(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a2, 176(sp) ; CHECK-RV32IF-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a1, 180(sp) ; CHECK-RV32IF-NEXT: lw a1, 180(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw a0, 184(sp) ; CHECK-RV32IF-NEXT: lw a0, 184(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw s0, 188(sp) ; CHECK-RV32IF-NEXT: lw s0, 188(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t2, 192(sp) ; CHECK-RV32IF-NEXT: lw t2, 192(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t1, 196(sp) ; CHECK-RV32IF-NEXT: lw t1, 196(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw t0, 200(sp) ; CHECK-RV32IF-NEXT: lw t0, 200(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: lw ra, 204(sp) ; CHECK-RV32IF-NEXT: lw ra, 204(sp) # 4-byte Folded Reload
; CHECK-RV32IF-NEXT: addi sp, sp, 208 ; CHECK-RV32IF-NEXT: addi sp, sp, 208
; CHECK-RV32IF-NEXT: mret ; CHECK-RV32IF-NEXT: mret
; ;
; CHECK-RV32IFD-LABEL: foo_fp_double: ; CHECK-RV32IFD-LABEL: foo_fp_double:
; CHECK-RV32IFD: # %bb.0: ; CHECK-RV32IFD: # %bb.0:
; CHECK-RV32IFD-NEXT: addi sp, sp, -32 ; CHECK-RV32IFD-NEXT: addi sp, sp, -32
; CHECK-RV32IFD-NEXT: sw ra, 28(sp) ; CHECK-RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw s0, 24(sp) ; CHECK-RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: sw a0, 20(sp) ; CHECK-RV32IFD-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp) # 8-byte Folded Spill
; CHECK-RV32IFD-NEXT: addi s0, sp, 32 ; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(h) ; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0) ; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i) ; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0) ; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1 ; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g) ; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0) ; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) ; CHECK-RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) ; CHECK-RV32IFD-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw a0, 20(sp) ; CHECK-RV32IFD-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw s0, 24(sp) ; CHECK-RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: lw ra, 28(sp) ; CHECK-RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-RV32IFD-NEXT: addi sp, sp, 32 ; CHECK-RV32IFD-NEXT: addi sp, sp, 32
; CHECK-RV32IFD-NEXT: mret ; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h %1 = load double, double* @h
%2 = load double, double* @i %2 = load double, double* @i
%add = fadd double %1, %2 %add = fadd double %1, %2
store double %add, double* @g store double %add, double* @g
ret void ret void
} }
attributes #0 = { "interrupt"="machine" } attributes #0 = { "interrupt"="machine" }
attributes #1 = { "interrupt"="machine" "frame-pointer"="all" } attributes #1 = { "interrupt"="machine" "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/interrupt-attr.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; ;
declare i32 @otherfoo(...) declare i32 @otherfoo(...)
define void @foo_with_call() #2 { define void @foo_with_call() #2 {
; ;
; CHECK-RV32-LABEL: foo_with_call: ; CHECK-RV32-LABEL: foo_with_call:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -64 ; CHECK-RV32-NEXT: addi sp, sp, -64
; CHECK-RV32-NEXT: sw ra, 60(sp) ; CHECK-RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 56(sp) ; CHECK-RV32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 52(sp) ; CHECK-RV32-NEXT: sw t1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 48(sp) ; CHECK-RV32-NEXT: sw t2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 44(sp) ; CHECK-RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 40(sp) ; CHECK-RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 36(sp) ; CHECK-RV32-NEXT: sw a2, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 32(sp) ; CHECK-RV32-NEXT: sw a3, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 28(sp) ; CHECK-RV32-NEXT: sw a4, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 24(sp) ; CHECK-RV32-NEXT: sw a5, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 20(sp) ; CHECK-RV32-NEXT: sw a6, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 16(sp) ; CHECK-RV32-NEXT: sw a7, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 12(sp) ; CHECK-RV32-NEXT: sw t3, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 8(sp) ; CHECK-RV32-NEXT: sw t4, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 4(sp) ; CHECK-RV32-NEXT: sw t5, 4(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 0(sp) ; CHECK-RV32-NEXT: sw t6, 0(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: call otherfoo ; CHECK-RV32-NEXT: call otherfoo@plt
; CHECK-RV32-NEXT: lw t6, 0(sp) ; CHECK-RV32-NEXT: lw t6, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 4(sp) ; CHECK-RV32-NEXT: lw t5, 4(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 8(sp) ; CHECK-RV32-NEXT: lw t4, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 12(sp) ; CHECK-RV32-NEXT: lw t3, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 16(sp) ; CHECK-RV32-NEXT: lw a7, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 20(sp) ; CHECK-RV32-NEXT: lw a6, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 24(sp) ; CHECK-RV32-NEXT: lw a5, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 28(sp) ; CHECK-RV32-NEXT: lw a4, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 32(sp) ; CHECK-RV32-NEXT: lw a3, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 36(sp) ; CHECK-RV32-NEXT: lw a2, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 40(sp) ; CHECK-RV32-NEXT: lw a1, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 44(sp) ; CHECK-RV32-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 48(sp) ; CHECK-RV32-NEXT: lw t2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 52(sp) ; CHECK-RV32-NEXT: lw t1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 56(sp) ; CHECK-RV32-NEXT: lw t0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 60(sp) ; CHECK-RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 64 ; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32-F-LABEL: foo_with_call: ; CHECK-RV32-F-LABEL: foo_with_call:
; CHECK-RV32-F: # %bb.0: ; CHECK-RV32-F: # %bb.0:
; CHECK-RV32-F-NEXT: addi sp, sp, -192 ; CHECK-RV32-F-NEXT: addi sp, sp, -192
; CHECK-RV32-F-NEXT: sw ra, 188(sp) ; CHECK-RV32-F-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t0, 184(sp) ; CHECK-RV32-F-NEXT: sw t0, 184(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t1, 180(sp) ; CHECK-RV32-F-NEXT: sw t1, 180(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t2, 176(sp) ; CHECK-RV32-F-NEXT: sw t2, 176(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a0, 172(sp) ; CHECK-RV32-F-NEXT: sw a0, 172(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a1, 168(sp) ; CHECK-RV32-F-NEXT: sw a1, 168(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a2, 164(sp) ; CHECK-RV32-F-NEXT: sw a2, 164(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a3, 160(sp) ; CHECK-RV32-F-NEXT: sw a3, 160(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a4, 156(sp) ; CHECK-RV32-F-NEXT: sw a4, 156(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a5, 152(sp) ; CHECK-RV32-F-NEXT: sw a5, 152(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a6, 148(sp) ; CHECK-RV32-F-NEXT: sw a6, 148(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a7, 144(sp) ; CHECK-RV32-F-NEXT: sw a7, 144(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t3, 140(sp) ; CHECK-RV32-F-NEXT: sw t3, 140(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t4, 136(sp) ; CHECK-RV32-F-NEXT: sw t4, 136(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t5, 132(sp) ; CHECK-RV32-F-NEXT: sw t5, 132(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t6, 128(sp) ; CHECK-RV32-F-NEXT: sw t6, 128(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft0, 124(sp) ; CHECK-RV32-F-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft1, 120(sp) ; CHECK-RV32-F-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft2, 116(sp) ; CHECK-RV32-F-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft3, 112(sp) ; CHECK-RV32-F-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft4, 108(sp) ; CHECK-RV32-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft5, 104(sp) ; CHECK-RV32-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft6, 100(sp) ; CHECK-RV32-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft7, 96(sp) ; CHECK-RV32-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa0, 92(sp) ; CHECK-RV32-F-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa1, 88(sp) ; CHECK-RV32-F-NEXT: fsw fa1, 88(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa2, 84(sp) ; CHECK-RV32-F-NEXT: fsw fa2, 84(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa3, 80(sp) ; CHECK-RV32-F-NEXT: fsw fa3, 80(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa4, 76(sp) ; CHECK-RV32-F-NEXT: fsw fa4, 76(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa5, 72(sp) ; CHECK-RV32-F-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa6, 68(sp) ; CHECK-RV32-F-NEXT: fsw fa6, 68(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa7, 64(sp) ; CHECK-RV32-F-NEXT: fsw fa7, 64(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft8, 60(sp) ; CHECK-RV32-F-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft9, 56(sp) ; CHECK-RV32-F-NEXT: fsw ft9, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft10, 52(sp) ; CHECK-RV32-F-NEXT: fsw ft10, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft11, 48(sp) ; CHECK-RV32-F-NEXT: fsw ft11, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs0, 44(sp) ; CHECK-RV32-F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs1, 40(sp) ; CHECK-RV32-F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs2, 36(sp) ; CHECK-RV32-F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs3, 32(sp) ; CHECK-RV32-F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs4, 28(sp) ; CHECK-RV32-F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs5, 24(sp) ; CHECK-RV32-F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs6, 20(sp) ; CHECK-RV32-F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs7, 16(sp) ; CHECK-RV32-F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs8, 12(sp) ; CHECK-RV32-F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs9, 8(sp) ; CHECK-RV32-F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs10, 4(sp) ; CHECK-RV32-F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs11, 0(sp) ; CHECK-RV32-F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: call otherfoo ; CHECK-RV32-F-NEXT: call otherfoo@plt
; CHECK-RV32-F-NEXT: flw fs11, 0(sp) ; CHECK-RV32-F-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs10, 4(sp) ; CHECK-RV32-F-NEXT: flw fs10, 4(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs9, 8(sp) ; CHECK-RV32-F-NEXT: flw fs9, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs8, 12(sp) ; CHECK-RV32-F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs7, 16(sp) ; CHECK-RV32-F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs6, 20(sp) ; CHECK-RV32-F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs5, 24(sp) ; CHECK-RV32-F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs4, 28(sp) ; CHECK-RV32-F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs3, 32(sp) ; CHECK-RV32-F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs2, 36(sp) ; CHECK-RV32-F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs1, 40(sp) ; CHECK-RV32-F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs0, 44(sp) ; CHECK-RV32-F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft11, 48(sp) ; CHECK-RV32-F-NEXT: flw ft11, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft10, 52(sp) ; CHECK-RV32-F-NEXT: flw ft10, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft9, 56(sp) ; CHECK-RV32-F-NEXT: flw ft9, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft8, 60(sp) ; CHECK-RV32-F-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa7, 64(sp) ; CHECK-RV32-F-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa6, 68(sp) ; CHECK-RV32-F-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa5, 72(sp) ; CHECK-RV32-F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa4, 76(sp) ; CHECK-RV32-F-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa3, 80(sp) ; CHECK-RV32-F-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa2, 84(sp) ; CHECK-RV32-F-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa1, 88(sp) ; CHECK-RV32-F-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa0, 92(sp) ; CHECK-RV32-F-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft7, 96(sp) ; CHECK-RV32-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft6, 100(sp) ; CHECK-RV32-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft5, 104(sp) ; CHECK-RV32-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft4, 108(sp) ; CHECK-RV32-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft3, 112(sp) ; CHECK-RV32-F-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft2, 116(sp) ; CHECK-RV32-F-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft1, 120(sp) ; CHECK-RV32-F-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft0, 124(sp) ; CHECK-RV32-F-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t6, 128(sp) ; CHECK-RV32-F-NEXT: lw t6, 128(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t5, 132(sp) ; CHECK-RV32-F-NEXT: lw t5, 132(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t4, 136(sp) ; CHECK-RV32-F-NEXT: lw t4, 136(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t3, 140(sp) ; CHECK-RV32-F-NEXT: lw t3, 140(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a7, 144(sp) ; CHECK-RV32-F-NEXT: lw a7, 144(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a6, 148(sp) ; CHECK-RV32-F-NEXT: lw a6, 148(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a5, 152(sp) ; CHECK-RV32-F-NEXT: lw a5, 152(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a4, 156(sp) ; CHECK-RV32-F-NEXT: lw a4, 156(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a3, 160(sp) ; CHECK-RV32-F-NEXT: lw a3, 160(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a2, 164(sp) ; CHECK-RV32-F-NEXT: lw a2, 164(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a1, 168(sp) ; CHECK-RV32-F-NEXT: lw a1, 168(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a0, 172(sp) ; CHECK-RV32-F-NEXT: lw a0, 172(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t2, 176(sp) ; CHECK-RV32-F-NEXT: lw t2, 176(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t1, 180(sp) ; CHECK-RV32-F-NEXT: lw t1, 180(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t0, 184(sp) ; CHECK-RV32-F-NEXT: lw t0, 184(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw ra, 188(sp) ; CHECK-RV32-F-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: addi sp, sp, 192 ; CHECK-RV32-F-NEXT: addi sp, sp, 192
; CHECK-RV32-F-NEXT: mret ; CHECK-RV32-F-NEXT: mret
; ;
; CHECK-RV32-FD-LABEL: foo_with_call: ; CHECK-RV32-FD-LABEL: foo_with_call:
; CHECK-RV32-FD: # %bb.0: ; CHECK-RV32-FD: # %bb.0:
; CHECK-RV32-FD-NEXT: addi sp, sp, -320 ; CHECK-RV32-FD-NEXT: addi sp, sp, -320
; CHECK-RV32-FD-NEXT: sw ra, 316(sp) ; CHECK-RV32-FD-NEXT: sw ra, 316(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t0, 312(sp) ; CHECK-RV32-FD-NEXT: sw t0, 312(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t1, 308(sp) ; CHECK-RV32-FD-NEXT: sw t1, 308(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t2, 304(sp) ; CHECK-RV32-FD-NEXT: sw t2, 304(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a0, 300(sp) ; CHECK-RV32-FD-NEXT: sw a0, 300(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a1, 296(sp) ; CHECK-RV32-FD-NEXT: sw a1, 296(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a2, 292(sp) ; CHECK-RV32-FD-NEXT: sw a2, 292(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a3, 288(sp) ; CHECK-RV32-FD-NEXT: sw a3, 288(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a4, 284(sp) ; CHECK-RV32-FD-NEXT: sw a4, 284(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a5, 280(sp) ; CHECK-RV32-FD-NEXT: sw a5, 280(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a6, 276(sp) ; CHECK-RV32-FD-NEXT: sw a6, 276(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a7, 272(sp) ; CHECK-RV32-FD-NEXT: sw a7, 272(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t3, 268(sp) ; CHECK-RV32-FD-NEXT: sw t3, 268(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t4, 264(sp) ; CHECK-RV32-FD-NEXT: sw t4, 264(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t5, 260(sp) ; CHECK-RV32-FD-NEXT: sw t5, 260(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t6, 256(sp) ; CHECK-RV32-FD-NEXT: sw t6, 256(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft0, 248(sp) ; CHECK-RV32-FD-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft1, 240(sp) ; CHECK-RV32-FD-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft2, 232(sp) ; CHECK-RV32-FD-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft3, 224(sp) ; CHECK-RV32-FD-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft4, 216(sp) ; CHECK-RV32-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft5, 208(sp) ; CHECK-RV32-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft6, 200(sp) ; CHECK-RV32-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft7, 192(sp) ; CHECK-RV32-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa0, 184(sp) ; CHECK-RV32-FD-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa1, 176(sp) ; CHECK-RV32-FD-NEXT: fsd fa1, 176(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa2, 168(sp) ; CHECK-RV32-FD-NEXT: fsd fa2, 168(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa3, 160(sp) ; CHECK-RV32-FD-NEXT: fsd fa3, 160(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa4, 152(sp) ; CHECK-RV32-FD-NEXT: fsd fa4, 152(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa5, 144(sp) ; CHECK-RV32-FD-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa6, 136(sp) ; CHECK-RV32-FD-NEXT: fsd fa6, 136(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa7, 128(sp) ; CHECK-RV32-FD-NEXT: fsd fa7, 128(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft8, 120(sp) ; CHECK-RV32-FD-NEXT: fsd ft8, 120(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft9, 112(sp) ; CHECK-RV32-FD-NEXT: fsd ft9, 112(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft10, 104(sp) ; CHECK-RV32-FD-NEXT: fsd ft10, 104(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft11, 96(sp) ; CHECK-RV32-FD-NEXT: fsd ft11, 96(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs0, 88(sp) ; CHECK-RV32-FD-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs1, 80(sp) ; CHECK-RV32-FD-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs2, 72(sp) ; CHECK-RV32-FD-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs3, 64(sp) ; CHECK-RV32-FD-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs4, 56(sp) ; CHECK-RV32-FD-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs5, 48(sp) ; CHECK-RV32-FD-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs6, 40(sp) ; CHECK-RV32-FD-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs7, 32(sp) ; CHECK-RV32-FD-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs8, 24(sp) ; CHECK-RV32-FD-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs9, 16(sp) ; CHECK-RV32-FD-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs10, 8(sp) ; CHECK-RV32-FD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs11, 0(sp) ; CHECK-RV32-FD-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: call otherfoo ; CHECK-RV32-FD-NEXT: call otherfoo@plt
; CHECK-RV32-FD-NEXT: fld fs11, 0(sp) ; CHECK-RV32-FD-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs10, 8(sp) ; CHECK-RV32-FD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs9, 16(sp) ; CHECK-RV32-FD-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs8, 24(sp) ; CHECK-RV32-FD-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs7, 32(sp) ; CHECK-RV32-FD-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs6, 40(sp) ; CHECK-RV32-FD-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs5, 48(sp) ; CHECK-RV32-FD-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs4, 56(sp) ; CHECK-RV32-FD-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs3, 64(sp) ; CHECK-RV32-FD-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs2, 72(sp) ; CHECK-RV32-FD-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs1, 80(sp) ; CHECK-RV32-FD-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs0, 88(sp) ; CHECK-RV32-FD-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft11, 96(sp) ; CHECK-RV32-FD-NEXT: fld ft11, 96(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft10, 104(sp) ; CHECK-RV32-FD-NEXT: fld ft10, 104(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft9, 112(sp) ; CHECK-RV32-FD-NEXT: fld ft9, 112(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft8, 120(sp) ; CHECK-RV32-FD-NEXT: fld ft8, 120(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa7, 128(sp) ; CHECK-RV32-FD-NEXT: fld fa7, 128(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa6, 136(sp) ; CHECK-RV32-FD-NEXT: fld fa6, 136(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa5, 144(sp) ; CHECK-RV32-FD-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa4, 152(sp) ; CHECK-RV32-FD-NEXT: fld fa4, 152(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa3, 160(sp) ; CHECK-RV32-FD-NEXT: fld fa3, 160(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa2, 168(sp) ; CHECK-RV32-FD-NEXT: fld fa2, 168(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa1, 176(sp) ; CHECK-RV32-FD-NEXT: fld fa1, 176(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa0, 184(sp) ; CHECK-RV32-FD-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft7, 192(sp) ; CHECK-RV32-FD-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft6, 200(sp) ; CHECK-RV32-FD-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft5, 208(sp) ; CHECK-RV32-FD-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft4, 216(sp) ; CHECK-RV32-FD-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft3, 224(sp) ; CHECK-RV32-FD-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft2, 232(sp) ; CHECK-RV32-FD-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft1, 240(sp) ; CHECK-RV32-FD-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft0, 248(sp) ; CHECK-RV32-FD-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t6, 256(sp) ; CHECK-RV32-FD-NEXT: lw t6, 256(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t5, 260(sp) ; CHECK-RV32-FD-NEXT: lw t5, 260(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t4, 264(sp) ; CHECK-RV32-FD-NEXT: lw t4, 264(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t3, 268(sp) ; CHECK-RV32-FD-NEXT: lw t3, 268(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a7, 272(sp) ; CHECK-RV32-FD-NEXT: lw a7, 272(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a6, 276(sp) ; CHECK-RV32-FD-NEXT: lw a6, 276(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a5, 280(sp) ; CHECK-RV32-FD-NEXT: lw a5, 280(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a4, 284(sp) ; CHECK-RV32-FD-NEXT: lw a4, 284(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a3, 288(sp) ; CHECK-RV32-FD-NEXT: lw a3, 288(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a2, 292(sp) ; CHECK-RV32-FD-NEXT: lw a2, 292(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a1, 296(sp) ; CHECK-RV32-FD-NEXT: lw a1, 296(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a0, 300(sp) ; CHECK-RV32-FD-NEXT: lw a0, 300(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t2, 304(sp) ; CHECK-RV32-FD-NEXT: lw t2, 304(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t1, 308(sp) ; CHECK-RV32-FD-NEXT: lw t1, 308(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t0, 312(sp) ; CHECK-RV32-FD-NEXT: lw t0, 312(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw ra, 316(sp) ; CHECK-RV32-FD-NEXT: lw ra, 316(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: addi sp, sp, 320 ; CHECK-RV32-FD-NEXT: addi sp, sp, 320
; CHECK-RV32-FD-NEXT: mret ; CHECK-RV32-FD-NEXT: mret
; ;
; CHECK-RV64-LABEL: foo_with_call: ; CHECK-RV64-LABEL: foo_with_call:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: addi sp, sp, -128 ; CHECK-RV64-NEXT: addi sp, sp, -128
; CHECK-RV64-NEXT: sd ra, 120(sp) ; CHECK-RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t0, 112(sp) ; CHECK-RV64-NEXT: sd t0, 112(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t1, 104(sp) ; CHECK-RV64-NEXT: sd t1, 104(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t2, 96(sp) ; CHECK-RV64-NEXT: sd t2, 96(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a0, 88(sp) ; CHECK-RV64-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a1, 80(sp) ; CHECK-RV64-NEXT: sd a1, 80(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a2, 72(sp) ; CHECK-RV64-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a3, 64(sp) ; CHECK-RV64-NEXT: sd a3, 64(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a4, 56(sp) ; CHECK-RV64-NEXT: sd a4, 56(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a5, 48(sp) ; CHECK-RV64-NEXT: sd a5, 48(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a6, 40(sp) ; CHECK-RV64-NEXT: sd a6, 40(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a7, 32(sp) ; CHECK-RV64-NEXT: sd a7, 32(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t3, 24(sp) ; CHECK-RV64-NEXT: sd t3, 24(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t4, 16(sp) ; CHECK-RV64-NEXT: sd t4, 16(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t5, 8(sp) ; CHECK-RV64-NEXT: sd t5, 8(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t6, 0(sp) ; CHECK-RV64-NEXT: sd t6, 0(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: call otherfoo ; CHECK-RV64-NEXT: call otherfoo@plt
; CHECK-RV64-NEXT: ld t6, 0(sp) ; CHECK-RV64-NEXT: ld t6, 0(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t5, 8(sp) ; CHECK-RV64-NEXT: ld t5, 8(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t4, 16(sp) ; CHECK-RV64-NEXT: ld t4, 16(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t3, 24(sp) ; CHECK-RV64-NEXT: ld t3, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a7, 32(sp) ; CHECK-RV64-NEXT: ld a7, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a6, 40(sp) ; CHECK-RV64-NEXT: ld a6, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a5, 48(sp) ; CHECK-RV64-NEXT: ld a5, 48(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a4, 56(sp) ; CHECK-RV64-NEXT: ld a4, 56(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a3, 64(sp) ; CHECK-RV64-NEXT: ld a3, 64(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a2, 72(sp) ; CHECK-RV64-NEXT: ld a2, 72(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a1, 80(sp) ; CHECK-RV64-NEXT: ld a1, 80(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a0, 88(sp) ; CHECK-RV64-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t2, 96(sp) ; CHECK-RV64-NEXT: ld t2, 96(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t1, 104(sp) ; CHECK-RV64-NEXT: ld t1, 104(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t0, 112(sp) ; CHECK-RV64-NEXT: ld t0, 112(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld ra, 120(sp) ; CHECK-RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: addi sp, sp, 128 ; CHECK-RV64-NEXT: addi sp, sp, 128
; CHECK-RV64-NEXT: mret ; CHECK-RV64-NEXT: mret
; ;
; CHECK-RV64-F-LABEL: foo_with_call: ; CHECK-RV64-F-LABEL: foo_with_call:
; CHECK-RV64-F: # %bb.0: ; CHECK-RV64-F: # %bb.0:
; CHECK-RV64-F-NEXT: addi sp, sp, -256 ; CHECK-RV64-F-NEXT: addi sp, sp, -256
; CHECK-RV64-F-NEXT: sd ra, 248(sp) ; CHECK-RV64-F-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t0, 240(sp) ; CHECK-RV64-F-NEXT: sd t0, 240(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t1, 232(sp) ; CHECK-RV64-F-NEXT: sd t1, 232(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t2, 224(sp) ; CHECK-RV64-F-NEXT: sd t2, 224(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a0, 216(sp) ; CHECK-RV64-F-NEXT: sd a0, 216(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a1, 208(sp) ; CHECK-RV64-F-NEXT: sd a1, 208(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a2, 200(sp) ; CHECK-RV64-F-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a3, 192(sp) ; CHECK-RV64-F-NEXT: sd a3, 192(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a4, 184(sp) ; CHECK-RV64-F-NEXT: sd a4, 184(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a5, 176(sp) ; CHECK-RV64-F-NEXT: sd a5, 176(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a6, 168(sp) ; CHECK-RV64-F-NEXT: sd a6, 168(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a7, 160(sp) ; CHECK-RV64-F-NEXT: sd a7, 160(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t3, 152(sp) ; CHECK-RV64-F-NEXT: sd t3, 152(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t4, 144(sp) ; CHECK-RV64-F-NEXT: sd t4, 144(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t5, 136(sp) ; CHECK-RV64-F-NEXT: sd t5, 136(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t6, 128(sp) ; CHECK-RV64-F-NEXT: sd t6, 128(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft0, 124(sp) ; CHECK-RV64-F-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft1, 120(sp) ; CHECK-RV64-F-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft2, 116(sp) ; CHECK-RV64-F-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft3, 112(sp) ; CHECK-RV64-F-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft4, 108(sp) ; CHECK-RV64-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft5, 104(sp) ; CHECK-RV64-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft6, 100(sp) ; CHECK-RV64-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft7, 96(sp) ; CHECK-RV64-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa0, 92(sp) ; CHECK-RV64-F-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa1, 88(sp) ; CHECK-RV64-F-NEXT: fsw fa1, 88(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa2, 84(sp) ; CHECK-RV64-F-NEXT: fsw fa2, 84(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa3, 80(sp) ; CHECK-RV64-F-NEXT: fsw fa3, 80(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa4, 76(sp) ; CHECK-RV64-F-NEXT: fsw fa4, 76(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa5, 72(sp) ; CHECK-RV64-F-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa6, 68(sp) ; CHECK-RV64-F-NEXT: fsw fa6, 68(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa7, 64(sp) ; CHECK-RV64-F-NEXT: fsw fa7, 64(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft8, 60(sp) ; CHECK-RV64-F-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft9, 56(sp) ; CHECK-RV64-F-NEXT: fsw ft9, 56(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft10, 52(sp) ; CHECK-RV64-F-NEXT: fsw ft10, 52(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft11, 48(sp) ; CHECK-RV64-F-NEXT: fsw ft11, 48(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs0, 44(sp) ; CHECK-RV64-F-NEXT: fsw fs0, 44(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs1, 40(sp) ; CHECK-RV64-F-NEXT: fsw fs1, 40(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs2, 36(sp) ; CHECK-RV64-F-NEXT: fsw fs2, 36(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs3, 32(sp) ; CHECK-RV64-F-NEXT: fsw fs3, 32(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs4, 28(sp) ; CHECK-RV64-F-NEXT: fsw fs4, 28(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs5, 24(sp) ; CHECK-RV64-F-NEXT: fsw fs5, 24(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs6, 20(sp) ; CHECK-RV64-F-NEXT: fsw fs6, 20(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs7, 16(sp) ; CHECK-RV64-F-NEXT: fsw fs7, 16(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs8, 12(sp) ; CHECK-RV64-F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs9, 8(sp) ; CHECK-RV64-F-NEXT: fsw fs9, 8(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs10, 4(sp) ; CHECK-RV64-F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs11, 0(sp) ; CHECK-RV64-F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: call otherfoo ; CHECK-RV64-F-NEXT: call otherfoo@plt
; CHECK-RV64-F-NEXT: flw fs11, 0(sp) ; CHECK-RV64-F-NEXT: flw fs11, 0(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs10, 4(sp) ; CHECK-RV64-F-NEXT: flw fs10, 4(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs9, 8(sp) ; CHECK-RV64-F-NEXT: flw fs9, 8(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs8, 12(sp) ; CHECK-RV64-F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs7, 16(sp) ; CHECK-RV64-F-NEXT: flw fs7, 16(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs6, 20(sp) ; CHECK-RV64-F-NEXT: flw fs6, 20(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs5, 24(sp) ; CHECK-RV64-F-NEXT: flw fs5, 24(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs4, 28(sp) ; CHECK-RV64-F-NEXT: flw fs4, 28(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs3, 32(sp) ; CHECK-RV64-F-NEXT: flw fs3, 32(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs2, 36(sp) ; CHECK-RV64-F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs1, 40(sp) ; CHECK-RV64-F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs0, 44(sp) ; CHECK-RV64-F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft11, 48(sp) ; CHECK-RV64-F-NEXT: flw ft11, 48(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft10, 52(sp) ; CHECK-RV64-F-NEXT: flw ft10, 52(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft9, 56(sp) ; CHECK-RV64-F-NEXT: flw ft9, 56(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft8, 60(sp) ; CHECK-RV64-F-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa7, 64(sp) ; CHECK-RV64-F-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa6, 68(sp) ; CHECK-RV64-F-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa5, 72(sp) ; CHECK-RV64-F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa4, 76(sp) ; CHECK-RV64-F-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa3, 80(sp) ; CHECK-RV64-F-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa2, 84(sp) ; CHECK-RV64-F-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa1, 88(sp) ; CHECK-RV64-F-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa0, 92(sp) ; CHECK-RV64-F-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft7, 96(sp) ; CHECK-RV64-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft6, 100(sp) ; CHECK-RV64-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft5, 104(sp) ; CHECK-RV64-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft4, 108(sp) ; CHECK-RV64-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft3, 112(sp) ; CHECK-RV64-F-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft2, 116(sp) ; CHECK-RV64-F-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft1, 120(sp) ; CHECK-RV64-F-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft0, 124(sp) ; CHECK-RV64-F-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t6, 128(sp) ; CHECK-RV64-F-NEXT: ld t6, 128(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t5, 136(sp) ; CHECK-RV64-F-NEXT: ld t5, 136(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t4, 144(sp) ; CHECK-RV64-F-NEXT: ld t4, 144(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t3, 152(sp) ; CHECK-RV64-F-NEXT: ld t3, 152(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a7, 160(sp) ; CHECK-RV64-F-NEXT: ld a7, 160(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a6, 168(sp) ; CHECK-RV64-F-NEXT: ld a6, 168(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a5, 176(sp) ; CHECK-RV64-F-NEXT: ld a5, 176(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a4, 184(sp) ; CHECK-RV64-F-NEXT: ld a4, 184(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a3, 192(sp) ; CHECK-RV64-F-NEXT: ld a3, 192(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a2, 200(sp) ; CHECK-RV64-F-NEXT: ld a2, 200(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a1, 208(sp) ; CHECK-RV64-F-NEXT: ld a1, 208(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a0, 216(sp) ; CHECK-RV64-F-NEXT: ld a0, 216(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t2, 224(sp) ; CHECK-RV64-F-NEXT: ld t2, 224(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t1, 232(sp) ; CHECK-RV64-F-NEXT: ld t1, 232(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t0, 240(sp) ; CHECK-RV64-F-NEXT: ld t0, 240(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld ra, 248(sp) ; CHECK-RV64-F-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: addi sp, sp, 256 ; CHECK-RV64-F-NEXT: addi sp, sp, 256
; CHECK-RV64-F-NEXT: mret ; CHECK-RV64-F-NEXT: mret
; ;
; CHECK-RV64-FD-LABEL: foo_with_call: ; CHECK-RV64-FD-LABEL: foo_with_call:
; CHECK-RV64-FD: # %bb.0: ; CHECK-RV64-FD: # %bb.0:
; CHECK-RV64-FD-NEXT: addi sp, sp, -384 ; CHECK-RV64-FD-NEXT: addi sp, sp, -384
; CHECK-RV64-FD-NEXT: sd ra, 376(sp) ; CHECK-RV64-FD-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t0, 368(sp) ; CHECK-RV64-FD-NEXT: sd t0, 368(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t1, 360(sp) ; CHECK-RV64-FD-NEXT: sd t1, 360(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t2, 352(sp) ; CHECK-RV64-FD-NEXT: sd t2, 352(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a0, 344(sp) ; CHECK-RV64-FD-NEXT: sd a0, 344(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a1, 336(sp) ; CHECK-RV64-FD-NEXT: sd a1, 336(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a2, 328(sp) ; CHECK-RV64-FD-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a3, 320(sp) ; CHECK-RV64-FD-NEXT: sd a3, 320(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a4, 312(sp) ; CHECK-RV64-FD-NEXT: sd a4, 312(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a5, 304(sp) ; CHECK-RV64-FD-NEXT: sd a5, 304(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a6, 296(sp) ; CHECK-RV64-FD-NEXT: sd a6, 296(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a7, 288(sp) ; CHECK-RV64-FD-NEXT: sd a7, 288(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t3, 280(sp) ; CHECK-RV64-FD-NEXT: sd t3, 280(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t4, 272(sp) ; CHECK-RV64-FD-NEXT: sd t4, 272(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t5, 264(sp) ; CHECK-RV64-FD-NEXT: sd t5, 264(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t6, 256(sp) ; CHECK-RV64-FD-NEXT: sd t6, 256(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft0, 248(sp) ; CHECK-RV64-FD-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft1, 240(sp) ; CHECK-RV64-FD-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft2, 232(sp) ; CHECK-RV64-FD-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft3, 224(sp) ; CHECK-RV64-FD-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft4, 216(sp) ; CHECK-RV64-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft5, 208(sp) ; CHECK-RV64-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft6, 200(sp) ; CHECK-RV64-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft7, 192(sp) ; CHECK-RV64-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa0, 184(sp) ; CHECK-RV64-FD-NEXT: fsd fa0, 184(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa1, 176(sp) ; CHECK-RV64-FD-NEXT: fsd fa1, 176(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa2, 168(sp) ; CHECK-RV64-FD-NEXT: fsd fa2, 168(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa3, 160(sp) ; CHECK-RV64-FD-NEXT: fsd fa3, 160(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa4, 152(sp) ; CHECK-RV64-FD-NEXT: fsd fa4, 152(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa5, 144(sp) ; CHECK-RV64-FD-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa6, 136(sp) ; CHECK-RV64-FD-NEXT: fsd fa6, 136(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa7, 128(sp) ; CHECK-RV64-FD-NEXT: fsd fa7, 128(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft8, 120(sp) ; CHECK-RV64-FD-NEXT: fsd ft8, 120(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft9, 112(sp) ; CHECK-RV64-FD-NEXT: fsd ft9, 112(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft10, 104(sp) ; CHECK-RV64-FD-NEXT: fsd ft10, 104(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft11, 96(sp) ; CHECK-RV64-FD-NEXT: fsd ft11, 96(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs0, 88(sp) ; CHECK-RV64-FD-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs1, 80(sp) ; CHECK-RV64-FD-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs2, 72(sp) ; CHECK-RV64-FD-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs3, 64(sp) ; CHECK-RV64-FD-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs4, 56(sp) ; CHECK-RV64-FD-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs5, 48(sp) ; CHECK-RV64-FD-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs6, 40(sp) ; CHECK-RV64-FD-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs7, 32(sp) ; CHECK-RV64-FD-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs8, 24(sp) ; CHECK-RV64-FD-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs9, 16(sp) ; CHECK-RV64-FD-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs10, 8(sp) ; CHECK-RV64-FD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs11, 0(sp) ; CHECK-RV64-FD-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: call otherfoo ; CHECK-RV64-FD-NEXT: call otherfoo@plt
; CHECK-RV64-FD-NEXT: fld fs11, 0(sp) ; CHECK-RV64-FD-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs10, 8(sp) ; CHECK-RV64-FD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs9, 16(sp) ; CHECK-RV64-FD-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs8, 24(sp) ; CHECK-RV64-FD-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs7, 32(sp) ; CHECK-RV64-FD-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs6, 40(sp) ; CHECK-RV64-FD-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs5, 48(sp) ; CHECK-RV64-FD-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs4, 56(sp) ; CHECK-RV64-FD-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs3, 64(sp) ; CHECK-RV64-FD-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs2, 72(sp) ; CHECK-RV64-FD-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs1, 80(sp) ; CHECK-RV64-FD-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs0, 88(sp) ; CHECK-RV64-FD-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft11, 96(sp) ; CHECK-RV64-FD-NEXT: fld ft11, 96(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft10, 104(sp) ; CHECK-RV64-FD-NEXT: fld ft10, 104(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft9, 112(sp) ; CHECK-RV64-FD-NEXT: fld ft9, 112(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft8, 120(sp) ; CHECK-RV64-FD-NEXT: fld ft8, 120(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa7, 128(sp) ; CHECK-RV64-FD-NEXT: fld fa7, 128(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa6, 136(sp) ; CHECK-RV64-FD-NEXT: fld fa6, 136(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa5, 144(sp) ; CHECK-RV64-FD-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa4, 152(sp) ; CHECK-RV64-FD-NEXT: fld fa4, 152(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa3, 160(sp) ; CHECK-RV64-FD-NEXT: fld fa3, 160(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa2, 168(sp) ; CHECK-RV64-FD-NEXT: fld fa2, 168(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa1, 176(sp) ; CHECK-RV64-FD-NEXT: fld fa1, 176(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa0, 184(sp) ; CHECK-RV64-FD-NEXT: fld fa0, 184(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft7, 192(sp) ; CHECK-RV64-FD-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft6, 200(sp) ; CHECK-RV64-FD-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft5, 208(sp) ; CHECK-RV64-FD-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft4, 216(sp) ; CHECK-RV64-FD-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft3, 224(sp) ; CHECK-RV64-FD-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft2, 232(sp) ; CHECK-RV64-FD-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft1, 240(sp) ; CHECK-RV64-FD-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft0, 248(sp) ; CHECK-RV64-FD-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t6, 256(sp) ; CHECK-RV64-FD-NEXT: ld t6, 256(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t5, 264(sp) ; CHECK-RV64-FD-NEXT: ld t5, 264(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t4, 272(sp) ; CHECK-RV64-FD-NEXT: ld t4, 272(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t3, 280(sp) ; CHECK-RV64-FD-NEXT: ld t3, 280(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a7, 288(sp) ; CHECK-RV64-FD-NEXT: ld a7, 288(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a6, 296(sp) ; CHECK-RV64-FD-NEXT: ld a6, 296(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a5, 304(sp) ; CHECK-RV64-FD-NEXT: ld a5, 304(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a4, 312(sp) ; CHECK-RV64-FD-NEXT: ld a4, 312(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a3, 320(sp) ; CHECK-RV64-FD-NEXT: ld a3, 320(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a2, 328(sp) ; CHECK-RV64-FD-NEXT: ld a2, 328(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a1, 336(sp) ; CHECK-RV64-FD-NEXT: ld a1, 336(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a0, 344(sp) ; CHECK-RV64-FD-NEXT: ld a0, 344(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t2, 352(sp) ; CHECK-RV64-FD-NEXT: ld t2, 352(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t1, 360(sp) ; CHECK-RV64-FD-NEXT: ld t1, 360(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t0, 368(sp) ; CHECK-RV64-FD-NEXT: ld t0, 368(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld ra, 376(sp) ; CHECK-RV64-FD-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: addi sp, sp, 384 ; CHECK-RV64-FD-NEXT: addi sp, sp, 384
; CHECK-RV64-FD-NEXT: mret ; CHECK-RV64-FD-NEXT: mret
%call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)() %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
ret void ret void
} }
; ;
; Additionally check frame pointer and return address are properly saved. ; Additionally check frame pointer and return address are properly saved.
; ;
define void @foo_fp_with_call() #3 { define void @foo_fp_with_call() #3 {
; ;
; CHECK-RV32-LABEL: foo_fp_with_call: ; CHECK-RV32-LABEL: foo_fp_with_call:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -80 ; CHECK-RV32-NEXT: addi sp, sp, -80
; CHECK-RV32-NEXT: sw ra, 76(sp) ; CHECK-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t0, 72(sp) ; CHECK-RV32-NEXT: sw t0, 72(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t1, 68(sp) ; CHECK-RV32-NEXT: sw t1, 68(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t2, 64(sp) ; CHECK-RV32-NEXT: sw t2, 64(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 60(sp) ; CHECK-RV32-NEXT: sw s0, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a0, 56(sp) ; CHECK-RV32-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a1, 52(sp) ; CHECK-RV32-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a2, 48(sp) ; CHECK-RV32-NEXT: sw a2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a3, 44(sp) ; CHECK-RV32-NEXT: sw a3, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a4, 40(sp) ; CHECK-RV32-NEXT: sw a4, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a5, 36(sp) ; CHECK-RV32-NEXT: sw a5, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a6, 32(sp) ; CHECK-RV32-NEXT: sw a6, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw a7, 28(sp) ; CHECK-RV32-NEXT: sw a7, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t3, 24(sp) ; CHECK-RV32-NEXT: sw t3, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t4, 20(sp) ; CHECK-RV32-NEXT: sw t4, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t5, 16(sp) ; CHECK-RV32-NEXT: sw t5, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw t6, 12(sp) ; CHECK-RV32-NEXT: sw t6, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: addi s0, sp, 80 ; CHECK-RV32-NEXT: addi s0, sp, 80
; CHECK-RV32-NEXT: call otherfoo ; CHECK-RV32-NEXT: call otherfoo@plt
; CHECK-RV32-NEXT: lw t6, 12(sp) ; CHECK-RV32-NEXT: lw t6, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t5, 16(sp) ; CHECK-RV32-NEXT: lw t5, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t4, 20(sp) ; CHECK-RV32-NEXT: lw t4, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t3, 24(sp) ; CHECK-RV32-NEXT: lw t3, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a7, 28(sp) ; CHECK-RV32-NEXT: lw a7, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a6, 32(sp) ; CHECK-RV32-NEXT: lw a6, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a5, 36(sp) ; CHECK-RV32-NEXT: lw a5, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a4, 40(sp) ; CHECK-RV32-NEXT: lw a4, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a3, 44(sp) ; CHECK-RV32-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a2, 48(sp) ; CHECK-RV32-NEXT: lw a2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a1, 52(sp) ; CHECK-RV32-NEXT: lw a1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw a0, 56(sp) ; CHECK-RV32-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 60(sp) ; CHECK-RV32-NEXT: lw s0, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t2, 64(sp) ; CHECK-RV32-NEXT: lw t2, 64(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t1, 68(sp) ; CHECK-RV32-NEXT: lw t1, 68(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw t0, 72(sp) ; CHECK-RV32-NEXT: lw t0, 72(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 76(sp) ; CHECK-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 80 ; CHECK-RV32-NEXT: addi sp, sp, 80
; CHECK-RV32-NEXT: mret ; CHECK-RV32-NEXT: mret
; ;
; CHECK-RV32-F-LABEL: foo_fp_with_call: ; CHECK-RV32-F-LABEL: foo_fp_with_call:
; CHECK-RV32-F: # %bb.0: ; CHECK-RV32-F: # %bb.0:
; CHECK-RV32-F-NEXT: addi sp, sp, -208 ; CHECK-RV32-F-NEXT: addi sp, sp, -208
; CHECK-RV32-F-NEXT: sw ra, 204(sp) ; CHECK-RV32-F-NEXT: sw ra, 204(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t0, 200(sp) ; CHECK-RV32-F-NEXT: sw t0, 200(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t1, 196(sp) ; CHECK-RV32-F-NEXT: sw t1, 196(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t2, 192(sp) ; CHECK-RV32-F-NEXT: sw t2, 192(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw s0, 188(sp) ; CHECK-RV32-F-NEXT: sw s0, 188(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a0, 184(sp) ; CHECK-RV32-F-NEXT: sw a0, 184(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a1, 180(sp) ; CHECK-RV32-F-NEXT: sw a1, 180(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a2, 176(sp) ; CHECK-RV32-F-NEXT: sw a2, 176(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a3, 172(sp) ; CHECK-RV32-F-NEXT: sw a3, 172(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a4, 168(sp) ; CHECK-RV32-F-NEXT: sw a4, 168(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a5, 164(sp) ; CHECK-RV32-F-NEXT: sw a5, 164(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a6, 160(sp) ; CHECK-RV32-F-NEXT: sw a6, 160(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw a7, 156(sp) ; CHECK-RV32-F-NEXT: sw a7, 156(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t3, 152(sp) ; CHECK-RV32-F-NEXT: sw t3, 152(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t4, 148(sp) ; CHECK-RV32-F-NEXT: sw t4, 148(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t5, 144(sp) ; CHECK-RV32-F-NEXT: sw t5, 144(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw t6, 140(sp) ; CHECK-RV32-F-NEXT: sw t6, 140(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft0, 136(sp) ; CHECK-RV32-F-NEXT: fsw ft0, 136(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft1, 132(sp) ; CHECK-RV32-F-NEXT: fsw ft1, 132(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft2, 128(sp) ; CHECK-RV32-F-NEXT: fsw ft2, 128(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft3, 124(sp) ; CHECK-RV32-F-NEXT: fsw ft3, 124(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft4, 120(sp) ; CHECK-RV32-F-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft5, 116(sp) ; CHECK-RV32-F-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft6, 112(sp) ; CHECK-RV32-F-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft7, 108(sp) ; CHECK-RV32-F-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa0, 104(sp) ; CHECK-RV32-F-NEXT: fsw fa0, 104(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa1, 100(sp) ; CHECK-RV32-F-NEXT: fsw fa1, 100(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa2, 96(sp) ; CHECK-RV32-F-NEXT: fsw fa2, 96(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa3, 92(sp) ; CHECK-RV32-F-NEXT: fsw fa3, 92(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa4, 88(sp) ; CHECK-RV32-F-NEXT: fsw fa4, 88(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa5, 84(sp) ; CHECK-RV32-F-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa6, 80(sp) ; CHECK-RV32-F-NEXT: fsw fa6, 80(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fa7, 76(sp) ; CHECK-RV32-F-NEXT: fsw fa7, 76(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft8, 72(sp) ; CHECK-RV32-F-NEXT: fsw ft8, 72(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft9, 68(sp) ; CHECK-RV32-F-NEXT: fsw ft9, 68(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft10, 64(sp) ; CHECK-RV32-F-NEXT: fsw ft10, 64(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw ft11, 60(sp) ; CHECK-RV32-F-NEXT: fsw ft11, 60(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs0, 56(sp) ; CHECK-RV32-F-NEXT: fsw fs0, 56(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs1, 52(sp) ; CHECK-RV32-F-NEXT: fsw fs1, 52(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs2, 48(sp) ; CHECK-RV32-F-NEXT: fsw fs2, 48(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs3, 44(sp) ; CHECK-RV32-F-NEXT: fsw fs3, 44(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs4, 40(sp) ; CHECK-RV32-F-NEXT: fsw fs4, 40(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs5, 36(sp) ; CHECK-RV32-F-NEXT: fsw fs5, 36(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs6, 32(sp) ; CHECK-RV32-F-NEXT: fsw fs6, 32(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs7, 28(sp) ; CHECK-RV32-F-NEXT: fsw fs7, 28(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs8, 24(sp) ; CHECK-RV32-F-NEXT: fsw fs8, 24(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs9, 20(sp) ; CHECK-RV32-F-NEXT: fsw fs9, 20(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs10, 16(sp) ; CHECK-RV32-F-NEXT: fsw fs10, 16(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: fsw fs11, 12(sp) ; CHECK-RV32-F-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: addi s0, sp, 208 ; CHECK-RV32-F-NEXT: addi s0, sp, 208
; CHECK-RV32-F-NEXT: call otherfoo ; CHECK-RV32-F-NEXT: call otherfoo@plt
; CHECK-RV32-F-NEXT: flw fs11, 12(sp) ; CHECK-RV32-F-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs10, 16(sp) ; CHECK-RV32-F-NEXT: flw fs10, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs9, 20(sp) ; CHECK-RV32-F-NEXT: flw fs9, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs8, 24(sp) ; CHECK-RV32-F-NEXT: flw fs8, 24(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs7, 28(sp) ; CHECK-RV32-F-NEXT: flw fs7, 28(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs6, 32(sp) ; CHECK-RV32-F-NEXT: flw fs6, 32(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs5, 36(sp) ; CHECK-RV32-F-NEXT: flw fs5, 36(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs4, 40(sp) ; CHECK-RV32-F-NEXT: flw fs4, 40(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs3, 44(sp) ; CHECK-RV32-F-NEXT: flw fs3, 44(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs2, 48(sp) ; CHECK-RV32-F-NEXT: flw fs2, 48(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs1, 52(sp) ; CHECK-RV32-F-NEXT: flw fs1, 52(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fs0, 56(sp) ; CHECK-RV32-F-NEXT: flw fs0, 56(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft11, 60(sp) ; CHECK-RV32-F-NEXT: flw ft11, 60(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft10, 64(sp) ; CHECK-RV32-F-NEXT: flw ft10, 64(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft9, 68(sp) ; CHECK-RV32-F-NEXT: flw ft9, 68(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft8, 72(sp) ; CHECK-RV32-F-NEXT: flw ft8, 72(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa7, 76(sp) ; CHECK-RV32-F-NEXT: flw fa7, 76(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa6, 80(sp) ; CHECK-RV32-F-NEXT: flw fa6, 80(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa5, 84(sp) ; CHECK-RV32-F-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa4, 88(sp) ; CHECK-RV32-F-NEXT: flw fa4, 88(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa3, 92(sp) ; CHECK-RV32-F-NEXT: flw fa3, 92(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa2, 96(sp) ; CHECK-RV32-F-NEXT: flw fa2, 96(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa1, 100(sp) ; CHECK-RV32-F-NEXT: flw fa1, 100(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw fa0, 104(sp) ; CHECK-RV32-F-NEXT: flw fa0, 104(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft7, 108(sp) ; CHECK-RV32-F-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft6, 112(sp) ; CHECK-RV32-F-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft5, 116(sp) ; CHECK-RV32-F-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft4, 120(sp) ; CHECK-RV32-F-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft3, 124(sp) ; CHECK-RV32-F-NEXT: flw ft3, 124(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft2, 128(sp) ; CHECK-RV32-F-NEXT: flw ft2, 128(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft1, 132(sp) ; CHECK-RV32-F-NEXT: flw ft1, 132(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: flw ft0, 136(sp) ; CHECK-RV32-F-NEXT: flw ft0, 136(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t6, 140(sp) ; CHECK-RV32-F-NEXT: lw t6, 140(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t5, 144(sp) ; CHECK-RV32-F-NEXT: lw t5, 144(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t4, 148(sp) ; CHECK-RV32-F-NEXT: lw t4, 148(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t3, 152(sp) ; CHECK-RV32-F-NEXT: lw t3, 152(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a7, 156(sp) ; CHECK-RV32-F-NEXT: lw a7, 156(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a6, 160(sp) ; CHECK-RV32-F-NEXT: lw a6, 160(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a5, 164(sp) ; CHECK-RV32-F-NEXT: lw a5, 164(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a4, 168(sp) ; CHECK-RV32-F-NEXT: lw a4, 168(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a3, 172(sp) ; CHECK-RV32-F-NEXT: lw a3, 172(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a2, 176(sp) ; CHECK-RV32-F-NEXT: lw a2, 176(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a1, 180(sp) ; CHECK-RV32-F-NEXT: lw a1, 180(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw a0, 184(sp) ; CHECK-RV32-F-NEXT: lw a0, 184(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw s0, 188(sp) ; CHECK-RV32-F-NEXT: lw s0, 188(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t2, 192(sp) ; CHECK-RV32-F-NEXT: lw t2, 192(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t1, 196(sp) ; CHECK-RV32-F-NEXT: lw t1, 196(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw t0, 200(sp) ; CHECK-RV32-F-NEXT: lw t0, 200(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw ra, 204(sp) ; CHECK-RV32-F-NEXT: lw ra, 204(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: addi sp, sp, 208 ; CHECK-RV32-F-NEXT: addi sp, sp, 208
; CHECK-RV32-F-NEXT: mret ; CHECK-RV32-F-NEXT: mret
; ;
; CHECK-RV32-FD-LABEL: foo_fp_with_call: ; CHECK-RV32-FD-LABEL: foo_fp_with_call:
; CHECK-RV32-FD: # %bb.0: ; CHECK-RV32-FD: # %bb.0:
; CHECK-RV32-FD-NEXT: addi sp, sp, -336 ; CHECK-RV32-FD-NEXT: addi sp, sp, -336
; CHECK-RV32-FD-NEXT: sw ra, 332(sp) ; CHECK-RV32-FD-NEXT: sw ra, 332(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t0, 328(sp) ; CHECK-RV32-FD-NEXT: sw t0, 328(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t1, 324(sp) ; CHECK-RV32-FD-NEXT: sw t1, 324(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t2, 320(sp) ; CHECK-RV32-FD-NEXT: sw t2, 320(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw s0, 316(sp) ; CHECK-RV32-FD-NEXT: sw s0, 316(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a0, 312(sp) ; CHECK-RV32-FD-NEXT: sw a0, 312(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a1, 308(sp) ; CHECK-RV32-FD-NEXT: sw a1, 308(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a2, 304(sp) ; CHECK-RV32-FD-NEXT: sw a2, 304(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a3, 300(sp) ; CHECK-RV32-FD-NEXT: sw a3, 300(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a4, 296(sp) ; CHECK-RV32-FD-NEXT: sw a4, 296(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a5, 292(sp) ; CHECK-RV32-FD-NEXT: sw a5, 292(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a6, 288(sp) ; CHECK-RV32-FD-NEXT: sw a6, 288(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw a7, 284(sp) ; CHECK-RV32-FD-NEXT: sw a7, 284(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t3, 280(sp) ; CHECK-RV32-FD-NEXT: sw t3, 280(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t4, 276(sp) ; CHECK-RV32-FD-NEXT: sw t4, 276(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t5, 272(sp) ; CHECK-RV32-FD-NEXT: sw t5, 272(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw t6, 268(sp) ; CHECK-RV32-FD-NEXT: sw t6, 268(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft0, 256(sp) ; CHECK-RV32-FD-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft1, 248(sp) ; CHECK-RV32-FD-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft2, 240(sp) ; CHECK-RV32-FD-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft3, 232(sp) ; CHECK-RV32-FD-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft4, 224(sp) ; CHECK-RV32-FD-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft5, 216(sp) ; CHECK-RV32-FD-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft6, 208(sp) ; CHECK-RV32-FD-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft7, 200(sp) ; CHECK-RV32-FD-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa0, 192(sp) ; CHECK-RV32-FD-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa1, 184(sp) ; CHECK-RV32-FD-NEXT: fsd fa1, 184(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa2, 176(sp) ; CHECK-RV32-FD-NEXT: fsd fa2, 176(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa3, 168(sp) ; CHECK-RV32-FD-NEXT: fsd fa3, 168(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa4, 160(sp) ; CHECK-RV32-FD-NEXT: fsd fa4, 160(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa5, 152(sp) ; CHECK-RV32-FD-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa6, 144(sp) ; CHECK-RV32-FD-NEXT: fsd fa6, 144(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fa7, 136(sp) ; CHECK-RV32-FD-NEXT: fsd fa7, 136(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft8, 128(sp) ; CHECK-RV32-FD-NEXT: fsd ft8, 128(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft9, 120(sp) ; CHECK-RV32-FD-NEXT: fsd ft9, 120(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft10, 112(sp) ; CHECK-RV32-FD-NEXT: fsd ft10, 112(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd ft11, 104(sp) ; CHECK-RV32-FD-NEXT: fsd ft11, 104(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs0, 96(sp) ; CHECK-RV32-FD-NEXT: fsd fs0, 96(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs1, 88(sp) ; CHECK-RV32-FD-NEXT: fsd fs1, 88(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs2, 80(sp) ; CHECK-RV32-FD-NEXT: fsd fs2, 80(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs3, 72(sp) ; CHECK-RV32-FD-NEXT: fsd fs3, 72(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs4, 64(sp) ; CHECK-RV32-FD-NEXT: fsd fs4, 64(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs5, 56(sp) ; CHECK-RV32-FD-NEXT: fsd fs5, 56(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs6, 48(sp) ; CHECK-RV32-FD-NEXT: fsd fs6, 48(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs7, 40(sp) ; CHECK-RV32-FD-NEXT: fsd fs7, 40(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs8, 32(sp) ; CHECK-RV32-FD-NEXT: fsd fs8, 32(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs9, 24(sp) ; CHECK-RV32-FD-NEXT: fsd fs9, 24(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs10, 16(sp) ; CHECK-RV32-FD-NEXT: fsd fs10, 16(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: fsd fs11, 8(sp) ; CHECK-RV32-FD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; CHECK-RV32-FD-NEXT: addi s0, sp, 336 ; CHECK-RV32-FD-NEXT: addi s0, sp, 336
; CHECK-RV32-FD-NEXT: call otherfoo ; CHECK-RV32-FD-NEXT: call otherfoo@plt
; CHECK-RV32-FD-NEXT: fld fs11, 8(sp) ; CHECK-RV32-FD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs10, 16(sp) ; CHECK-RV32-FD-NEXT: fld fs10, 16(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs9, 24(sp) ; CHECK-RV32-FD-NEXT: fld fs9, 24(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs8, 32(sp) ; CHECK-RV32-FD-NEXT: fld fs8, 32(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs7, 40(sp) ; CHECK-RV32-FD-NEXT: fld fs7, 40(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs6, 48(sp) ; CHECK-RV32-FD-NEXT: fld fs6, 48(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs5, 56(sp) ; CHECK-RV32-FD-NEXT: fld fs5, 56(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs4, 64(sp) ; CHECK-RV32-FD-NEXT: fld fs4, 64(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs3, 72(sp) ; CHECK-RV32-FD-NEXT: fld fs3, 72(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs2, 80(sp) ; CHECK-RV32-FD-NEXT: fld fs2, 80(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs1, 88(sp) ; CHECK-RV32-FD-NEXT: fld fs1, 88(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fs0, 96(sp) ; CHECK-RV32-FD-NEXT: fld fs0, 96(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft11, 104(sp) ; CHECK-RV32-FD-NEXT: fld ft11, 104(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft10, 112(sp) ; CHECK-RV32-FD-NEXT: fld ft10, 112(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft9, 120(sp) ; CHECK-RV32-FD-NEXT: fld ft9, 120(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft8, 128(sp) ; CHECK-RV32-FD-NEXT: fld ft8, 128(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa7, 136(sp) ; CHECK-RV32-FD-NEXT: fld fa7, 136(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa6, 144(sp) ; CHECK-RV32-FD-NEXT: fld fa6, 144(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa5, 152(sp) ; CHECK-RV32-FD-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa4, 160(sp) ; CHECK-RV32-FD-NEXT: fld fa4, 160(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa3, 168(sp) ; CHECK-RV32-FD-NEXT: fld fa3, 168(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa2, 176(sp) ; CHECK-RV32-FD-NEXT: fld fa2, 176(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa1, 184(sp) ; CHECK-RV32-FD-NEXT: fld fa1, 184(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld fa0, 192(sp) ; CHECK-RV32-FD-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft7, 200(sp) ; CHECK-RV32-FD-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft6, 208(sp) ; CHECK-RV32-FD-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft5, 216(sp) ; CHECK-RV32-FD-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft4, 224(sp) ; CHECK-RV32-FD-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft3, 232(sp) ; CHECK-RV32-FD-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft2, 240(sp) ; CHECK-RV32-FD-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft1, 248(sp) ; CHECK-RV32-FD-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: fld ft0, 256(sp) ; CHECK-RV32-FD-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t6, 268(sp) ; CHECK-RV32-FD-NEXT: lw t6, 268(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t5, 272(sp) ; CHECK-RV32-FD-NEXT: lw t5, 272(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t4, 276(sp) ; CHECK-RV32-FD-NEXT: lw t4, 276(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t3, 280(sp) ; CHECK-RV32-FD-NEXT: lw t3, 280(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a7, 284(sp) ; CHECK-RV32-FD-NEXT: lw a7, 284(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a6, 288(sp) ; CHECK-RV32-FD-NEXT: lw a6, 288(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a5, 292(sp) ; CHECK-RV32-FD-NEXT: lw a5, 292(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a4, 296(sp) ; CHECK-RV32-FD-NEXT: lw a4, 296(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a3, 300(sp) ; CHECK-RV32-FD-NEXT: lw a3, 300(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a2, 304(sp) ; CHECK-RV32-FD-NEXT: lw a2, 304(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a1, 308(sp) ; CHECK-RV32-FD-NEXT: lw a1, 308(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw a0, 312(sp) ; CHECK-RV32-FD-NEXT: lw a0, 312(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw s0, 316(sp) ; CHECK-RV32-FD-NEXT: lw s0, 316(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t2, 320(sp) ; CHECK-RV32-FD-NEXT: lw t2, 320(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t1, 324(sp) ; CHECK-RV32-FD-NEXT: lw t1, 324(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw t0, 328(sp) ; CHECK-RV32-FD-NEXT: lw t0, 328(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw ra, 332(sp) ; CHECK-RV32-FD-NEXT: lw ra, 332(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: addi sp, sp, 336 ; CHECK-RV32-FD-NEXT: addi sp, sp, 336
; CHECK-RV32-FD-NEXT: mret ; CHECK-RV32-FD-NEXT: mret
; ;
; CHECK-RV64-LABEL: foo_fp_with_call: ; CHECK-RV64-LABEL: foo_fp_with_call:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: addi sp, sp, -144 ; CHECK-RV64-NEXT: addi sp, sp, -144
; CHECK-RV64-NEXT: sd ra, 136(sp) ; CHECK-RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t0, 128(sp) ; CHECK-RV64-NEXT: sd t0, 128(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t1, 120(sp) ; CHECK-RV64-NEXT: sd t1, 120(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t2, 112(sp) ; CHECK-RV64-NEXT: sd t2, 112(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd s0, 104(sp) ; CHECK-RV64-NEXT: sd s0, 104(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a0, 96(sp) ; CHECK-RV64-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a1, 88(sp) ; CHECK-RV64-NEXT: sd a1, 88(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a2, 80(sp) ; CHECK-RV64-NEXT: sd a2, 80(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a3, 72(sp) ; CHECK-RV64-NEXT: sd a3, 72(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a4, 64(sp) ; CHECK-RV64-NEXT: sd a4, 64(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a5, 56(sp) ; CHECK-RV64-NEXT: sd a5, 56(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a6, 48(sp) ; CHECK-RV64-NEXT: sd a6, 48(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd a7, 40(sp) ; CHECK-RV64-NEXT: sd a7, 40(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t3, 32(sp) ; CHECK-RV64-NEXT: sd t3, 32(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t4, 24(sp) ; CHECK-RV64-NEXT: sd t4, 24(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t5, 16(sp) ; CHECK-RV64-NEXT: sd t5, 16(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: sd t6, 8(sp) ; CHECK-RV64-NEXT: sd t6, 8(sp) # 8-byte Folded Spill
; CHECK-RV64-NEXT: addi s0, sp, 144 ; CHECK-RV64-NEXT: addi s0, sp, 144
; CHECK-RV64-NEXT: call otherfoo ; CHECK-RV64-NEXT: call otherfoo@plt
; CHECK-RV64-NEXT: ld t6, 8(sp) ; CHECK-RV64-NEXT: ld t6, 8(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t5, 16(sp) ; CHECK-RV64-NEXT: ld t5, 16(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t4, 24(sp) ; CHECK-RV64-NEXT: ld t4, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t3, 32(sp) ; CHECK-RV64-NEXT: ld t3, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a7, 40(sp) ; CHECK-RV64-NEXT: ld a7, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a6, 48(sp) ; CHECK-RV64-NEXT: ld a6, 48(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a5, 56(sp) ; CHECK-RV64-NEXT: ld a5, 56(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a4, 64(sp) ; CHECK-RV64-NEXT: ld a4, 64(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a3, 72(sp) ; CHECK-RV64-NEXT: ld a3, 72(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a2, 80(sp) ; CHECK-RV64-NEXT: ld a2, 80(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a1, 88(sp) ; CHECK-RV64-NEXT: ld a1, 88(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld a0, 96(sp) ; CHECK-RV64-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s0, 104(sp) ; CHECK-RV64-NEXT: ld s0, 104(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t2, 112(sp) ; CHECK-RV64-NEXT: ld t2, 112(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t1, 120(sp) ; CHECK-RV64-NEXT: ld t1, 120(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld t0, 128(sp) ; CHECK-RV64-NEXT: ld t0, 128(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld ra, 136(sp) ; CHECK-RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: addi sp, sp, 144 ; CHECK-RV64-NEXT: addi sp, sp, 144
; CHECK-RV64-NEXT: mret ; CHECK-RV64-NEXT: mret
; ;
; CHECK-RV64-F-LABEL: foo_fp_with_call: ; CHECK-RV64-F-LABEL: foo_fp_with_call:
; CHECK-RV64-F: # %bb.0: ; CHECK-RV64-F: # %bb.0:
; CHECK-RV64-F-NEXT: addi sp, sp, -272 ; CHECK-RV64-F-NEXT: addi sp, sp, -272
; CHECK-RV64-F-NEXT: sd ra, 264(sp) ; CHECK-RV64-F-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t0, 256(sp) ; CHECK-RV64-F-NEXT: sd t0, 256(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t1, 248(sp) ; CHECK-RV64-F-NEXT: sd t1, 248(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t2, 240(sp) ; CHECK-RV64-F-NEXT: sd t2, 240(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd s0, 232(sp) ; CHECK-RV64-F-NEXT: sd s0, 232(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a0, 224(sp) ; CHECK-RV64-F-NEXT: sd a0, 224(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a1, 216(sp) ; CHECK-RV64-F-NEXT: sd a1, 216(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a2, 208(sp) ; CHECK-RV64-F-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a3, 200(sp) ; CHECK-RV64-F-NEXT: sd a3, 200(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a4, 192(sp) ; CHECK-RV64-F-NEXT: sd a4, 192(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a5, 184(sp) ; CHECK-RV64-F-NEXT: sd a5, 184(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a6, 176(sp) ; CHECK-RV64-F-NEXT: sd a6, 176(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd a7, 168(sp) ; CHECK-RV64-F-NEXT: sd a7, 168(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t3, 160(sp) ; CHECK-RV64-F-NEXT: sd t3, 160(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t4, 152(sp) ; CHECK-RV64-F-NEXT: sd t4, 152(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t5, 144(sp) ; CHECK-RV64-F-NEXT: sd t5, 144(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: sd t6, 136(sp) ; CHECK-RV64-F-NEXT: sd t6, 136(sp) # 8-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft0, 132(sp) ; CHECK-RV64-F-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft1, 128(sp) ; CHECK-RV64-F-NEXT: fsw ft1, 128(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft2, 124(sp) ; CHECK-RV64-F-NEXT: fsw ft2, 124(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft3, 120(sp) ; CHECK-RV64-F-NEXT: fsw ft3, 120(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft4, 116(sp) ; CHECK-RV64-F-NEXT: fsw ft4, 116(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft5, 112(sp) ; CHECK-RV64-F-NEXT: fsw ft5, 112(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft6, 108(sp) ; CHECK-RV64-F-NEXT: fsw ft6, 108(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft7, 104(sp) ; CHECK-RV64-F-NEXT: fsw ft7, 104(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa0, 100(sp) ; CHECK-RV64-F-NEXT: fsw fa0, 100(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa1, 96(sp) ; CHECK-RV64-F-NEXT: fsw fa1, 96(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa2, 92(sp) ; CHECK-RV64-F-NEXT: fsw fa2, 92(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa3, 88(sp) ; CHECK-RV64-F-NEXT: fsw fa3, 88(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa4, 84(sp) ; CHECK-RV64-F-NEXT: fsw fa4, 84(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa5, 80(sp) ; CHECK-RV64-F-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa6, 76(sp) ; CHECK-RV64-F-NEXT: fsw fa6, 76(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fa7, 72(sp) ; CHECK-RV64-F-NEXT: fsw fa7, 72(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft8, 68(sp) ; CHECK-RV64-F-NEXT: fsw ft8, 68(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft9, 64(sp) ; CHECK-RV64-F-NEXT: fsw ft9, 64(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft10, 60(sp) ; CHECK-RV64-F-NEXT: fsw ft10, 60(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw ft11, 56(sp) ; CHECK-RV64-F-NEXT: fsw ft11, 56(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs0, 52(sp) ; CHECK-RV64-F-NEXT: fsw fs0, 52(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs1, 48(sp) ; CHECK-RV64-F-NEXT: fsw fs1, 48(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs2, 44(sp) ; CHECK-RV64-F-NEXT: fsw fs2, 44(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs3, 40(sp) ; CHECK-RV64-F-NEXT: fsw fs3, 40(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs4, 36(sp) ; CHECK-RV64-F-NEXT: fsw fs4, 36(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs5, 32(sp) ; CHECK-RV64-F-NEXT: fsw fs5, 32(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs6, 28(sp) ; CHECK-RV64-F-NEXT: fsw fs6, 28(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs7, 24(sp) ; CHECK-RV64-F-NEXT: fsw fs7, 24(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs8, 20(sp) ; CHECK-RV64-F-NEXT: fsw fs8, 20(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs9, 16(sp) ; CHECK-RV64-F-NEXT: fsw fs9, 16(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs10, 12(sp) ; CHECK-RV64-F-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: fsw fs11, 8(sp) ; CHECK-RV64-F-NEXT: fsw fs11, 8(sp) # 4-byte Folded Spill
; CHECK-RV64-F-NEXT: addi s0, sp, 272 ; CHECK-RV64-F-NEXT: addi s0, sp, 272
; CHECK-RV64-F-NEXT: call otherfoo ; CHECK-RV64-F-NEXT: call otherfoo@plt
; CHECK-RV64-F-NEXT: flw fs11, 8(sp) ; CHECK-RV64-F-NEXT: flw fs11, 8(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs10, 12(sp) ; CHECK-RV64-F-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs9, 16(sp) ; CHECK-RV64-F-NEXT: flw fs9, 16(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs8, 20(sp) ; CHECK-RV64-F-NEXT: flw fs8, 20(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs7, 24(sp) ; CHECK-RV64-F-NEXT: flw fs7, 24(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs6, 28(sp) ; CHECK-RV64-F-NEXT: flw fs6, 28(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs5, 32(sp) ; CHECK-RV64-F-NEXT: flw fs5, 32(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs4, 36(sp) ; CHECK-RV64-F-NEXT: flw fs4, 36(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs3, 40(sp) ; CHECK-RV64-F-NEXT: flw fs3, 40(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs2, 44(sp) ; CHECK-RV64-F-NEXT: flw fs2, 44(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs1, 48(sp) ; CHECK-RV64-F-NEXT: flw fs1, 48(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fs0, 52(sp) ; CHECK-RV64-F-NEXT: flw fs0, 52(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft11, 56(sp) ; CHECK-RV64-F-NEXT: flw ft11, 56(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft10, 60(sp) ; CHECK-RV64-F-NEXT: flw ft10, 60(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft9, 64(sp) ; CHECK-RV64-F-NEXT: flw ft9, 64(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft8, 68(sp) ; CHECK-RV64-F-NEXT: flw ft8, 68(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa7, 72(sp) ; CHECK-RV64-F-NEXT: flw fa7, 72(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa6, 76(sp) ; CHECK-RV64-F-NEXT: flw fa6, 76(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa5, 80(sp) ; CHECK-RV64-F-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa4, 84(sp) ; CHECK-RV64-F-NEXT: flw fa4, 84(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa3, 88(sp) ; CHECK-RV64-F-NEXT: flw fa3, 88(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa2, 92(sp) ; CHECK-RV64-F-NEXT: flw fa2, 92(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa1, 96(sp) ; CHECK-RV64-F-NEXT: flw fa1, 96(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw fa0, 100(sp) ; CHECK-RV64-F-NEXT: flw fa0, 100(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft7, 104(sp) ; CHECK-RV64-F-NEXT: flw ft7, 104(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft6, 108(sp) ; CHECK-RV64-F-NEXT: flw ft6, 108(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft5, 112(sp) ; CHECK-RV64-F-NEXT: flw ft5, 112(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft4, 116(sp) ; CHECK-RV64-F-NEXT: flw ft4, 116(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft3, 120(sp) ; CHECK-RV64-F-NEXT: flw ft3, 120(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft2, 124(sp) ; CHECK-RV64-F-NEXT: flw ft2, 124(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft1, 128(sp) ; CHECK-RV64-F-NEXT: flw ft1, 128(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: flw ft0, 132(sp) ; CHECK-RV64-F-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t6, 136(sp) ; CHECK-RV64-F-NEXT: ld t6, 136(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t5, 144(sp) ; CHECK-RV64-F-NEXT: ld t5, 144(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t4, 152(sp) ; CHECK-RV64-F-NEXT: ld t4, 152(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t3, 160(sp) ; CHECK-RV64-F-NEXT: ld t3, 160(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a7, 168(sp) ; CHECK-RV64-F-NEXT: ld a7, 168(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a6, 176(sp) ; CHECK-RV64-F-NEXT: ld a6, 176(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a5, 184(sp) ; CHECK-RV64-F-NEXT: ld a5, 184(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a4, 192(sp) ; CHECK-RV64-F-NEXT: ld a4, 192(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a3, 200(sp) ; CHECK-RV64-F-NEXT: ld a3, 200(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a2, 208(sp) ; CHECK-RV64-F-NEXT: ld a2, 208(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a1, 216(sp) ; CHECK-RV64-F-NEXT: ld a1, 216(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld a0, 224(sp) ; CHECK-RV64-F-NEXT: ld a0, 224(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld s0, 232(sp) ; CHECK-RV64-F-NEXT: ld s0, 232(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t2, 240(sp) ; CHECK-RV64-F-NEXT: ld t2, 240(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t1, 248(sp) ; CHECK-RV64-F-NEXT: ld t1, 248(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld t0, 256(sp) ; CHECK-RV64-F-NEXT: ld t0, 256(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: ld ra, 264(sp) ; CHECK-RV64-F-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
; CHECK-RV64-F-NEXT: addi sp, sp, 272 ; CHECK-RV64-F-NEXT: addi sp, sp, 272
; CHECK-RV64-F-NEXT: mret ; CHECK-RV64-F-NEXT: mret
; ;
; CHECK-RV64-FD-LABEL: foo_fp_with_call: ; CHECK-RV64-FD-LABEL: foo_fp_with_call:
; CHECK-RV64-FD: # %bb.0: ; CHECK-RV64-FD: # %bb.0:
; CHECK-RV64-FD-NEXT: addi sp, sp, -400 ; CHECK-RV64-FD-NEXT: addi sp, sp, -400
; CHECK-RV64-FD-NEXT: sd ra, 392(sp) ; CHECK-RV64-FD-NEXT: sd ra, 392(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t0, 384(sp) ; CHECK-RV64-FD-NEXT: sd t0, 384(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t1, 376(sp) ; CHECK-RV64-FD-NEXT: sd t1, 376(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t2, 368(sp) ; CHECK-RV64-FD-NEXT: sd t2, 368(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd s0, 360(sp) ; CHECK-RV64-FD-NEXT: sd s0, 360(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a0, 352(sp) ; CHECK-RV64-FD-NEXT: sd a0, 352(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a1, 344(sp) ; CHECK-RV64-FD-NEXT: sd a1, 344(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a2, 336(sp) ; CHECK-RV64-FD-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a3, 328(sp) ; CHECK-RV64-FD-NEXT: sd a3, 328(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a4, 320(sp) ; CHECK-RV64-FD-NEXT: sd a4, 320(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a5, 312(sp) ; CHECK-RV64-FD-NEXT: sd a5, 312(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a6, 304(sp) ; CHECK-RV64-FD-NEXT: sd a6, 304(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd a7, 296(sp) ; CHECK-RV64-FD-NEXT: sd a7, 296(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t3, 288(sp) ; CHECK-RV64-FD-NEXT: sd t3, 288(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t4, 280(sp) ; CHECK-RV64-FD-NEXT: sd t4, 280(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t5, 272(sp) ; CHECK-RV64-FD-NEXT: sd t5, 272(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: sd t6, 264(sp) ; CHECK-RV64-FD-NEXT: sd t6, 264(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft0, 256(sp) ; CHECK-RV64-FD-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft1, 248(sp) ; CHECK-RV64-FD-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft2, 240(sp) ; CHECK-RV64-FD-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft3, 232(sp) ; CHECK-RV64-FD-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft4, 224(sp) ; CHECK-RV64-FD-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft5, 216(sp) ; CHECK-RV64-FD-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft6, 208(sp) ; CHECK-RV64-FD-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft7, 200(sp) ; CHECK-RV64-FD-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa0, 192(sp) ; CHECK-RV64-FD-NEXT: fsd fa0, 192(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa1, 184(sp) ; CHECK-RV64-FD-NEXT: fsd fa1, 184(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa2, 176(sp) ; CHECK-RV64-FD-NEXT: fsd fa2, 176(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa3, 168(sp) ; CHECK-RV64-FD-NEXT: fsd fa3, 168(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa4, 160(sp) ; CHECK-RV64-FD-NEXT: fsd fa4, 160(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa5, 152(sp) ; CHECK-RV64-FD-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa6, 144(sp) ; CHECK-RV64-FD-NEXT: fsd fa6, 144(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fa7, 136(sp) ; CHECK-RV64-FD-NEXT: fsd fa7, 136(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft8, 128(sp) ; CHECK-RV64-FD-NEXT: fsd ft8, 128(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft9, 120(sp) ; CHECK-RV64-FD-NEXT: fsd ft9, 120(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft10, 112(sp) ; CHECK-RV64-FD-NEXT: fsd ft10, 112(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd ft11, 104(sp) ; CHECK-RV64-FD-NEXT: fsd ft11, 104(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs0, 96(sp) ; CHECK-RV64-FD-NEXT: fsd fs0, 96(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs1, 88(sp) ; CHECK-RV64-FD-NEXT: fsd fs1, 88(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs2, 80(sp) ; CHECK-RV64-FD-NEXT: fsd fs2, 80(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs3, 72(sp) ; CHECK-RV64-FD-NEXT: fsd fs3, 72(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs4, 64(sp) ; CHECK-RV64-FD-NEXT: fsd fs4, 64(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs5, 56(sp) ; CHECK-RV64-FD-NEXT: fsd fs5, 56(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs6, 48(sp) ; CHECK-RV64-FD-NEXT: fsd fs6, 48(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs7, 40(sp) ; CHECK-RV64-FD-NEXT: fsd fs7, 40(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs8, 32(sp) ; CHECK-RV64-FD-NEXT: fsd fs8, 32(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs9, 24(sp) ; CHECK-RV64-FD-NEXT: fsd fs9, 24(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs10, 16(sp) ; CHECK-RV64-FD-NEXT: fsd fs10, 16(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: fsd fs11, 8(sp) ; CHECK-RV64-FD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill
; CHECK-RV64-FD-NEXT: addi s0, sp, 400 ; CHECK-RV64-FD-NEXT: addi s0, sp, 400
; CHECK-RV64-FD-NEXT: call otherfoo ; CHECK-RV64-FD-NEXT: call otherfoo@plt
; CHECK-RV64-FD-NEXT: fld fs11, 8(sp) ; CHECK-RV64-FD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs10, 16(sp) ; CHECK-RV64-FD-NEXT: fld fs10, 16(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs9, 24(sp) ; CHECK-RV64-FD-NEXT: fld fs9, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs8, 32(sp) ; CHECK-RV64-FD-NEXT: fld fs8, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs7, 40(sp) ; CHECK-RV64-FD-NEXT: fld fs7, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs6, 48(sp) ; CHECK-RV64-FD-NEXT: fld fs6, 48(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs5, 56(sp) ; CHECK-RV64-FD-NEXT: fld fs5, 56(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs4, 64(sp) ; CHECK-RV64-FD-NEXT: fld fs4, 64(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs3, 72(sp) ; CHECK-RV64-FD-NEXT: fld fs3, 72(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs2, 80(sp) ; CHECK-RV64-FD-NEXT: fld fs2, 80(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs1, 88(sp) ; CHECK-RV64-FD-NEXT: fld fs1, 88(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fs0, 96(sp) ; CHECK-RV64-FD-NEXT: fld fs0, 96(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft11, 104(sp) ; CHECK-RV64-FD-NEXT: fld ft11, 104(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft10, 112(sp) ; CHECK-RV64-FD-NEXT: fld ft10, 112(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft9, 120(sp) ; CHECK-RV64-FD-NEXT: fld ft9, 120(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft8, 128(sp) ; CHECK-RV64-FD-NEXT: fld ft8, 128(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa7, 136(sp) ; CHECK-RV64-FD-NEXT: fld fa7, 136(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa6, 144(sp) ; CHECK-RV64-FD-NEXT: fld fa6, 144(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa5, 152(sp) ; CHECK-RV64-FD-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa4, 160(sp) ; CHECK-RV64-FD-NEXT: fld fa4, 160(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa3, 168(sp) ; CHECK-RV64-FD-NEXT: fld fa3, 168(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa2, 176(sp) ; CHECK-RV64-FD-NEXT: fld fa2, 176(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa1, 184(sp) ; CHECK-RV64-FD-NEXT: fld fa1, 184(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld fa0, 192(sp) ; CHECK-RV64-FD-NEXT: fld fa0, 192(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft7, 200(sp) ; CHECK-RV64-FD-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft6, 208(sp) ; CHECK-RV64-FD-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft5, 216(sp) ; CHECK-RV64-FD-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft4, 224(sp) ; CHECK-RV64-FD-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft3, 232(sp) ; CHECK-RV64-FD-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft2, 240(sp) ; CHECK-RV64-FD-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft1, 248(sp) ; CHECK-RV64-FD-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: fld ft0, 256(sp) ; CHECK-RV64-FD-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t6, 264(sp) ; CHECK-RV64-FD-NEXT: ld t6, 264(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t5, 272(sp) ; CHECK-RV64-FD-NEXT: ld t5, 272(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t4, 280(sp) ; CHECK-RV64-FD-NEXT: ld t4, 280(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t3, 288(sp) ; CHECK-RV64-FD-NEXT: ld t3, 288(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a7, 296(sp) ; CHECK-RV64-FD-NEXT: ld a7, 296(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a6, 304(sp) ; CHECK-RV64-FD-NEXT: ld a6, 304(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a5, 312(sp) ; CHECK-RV64-FD-NEXT: ld a5, 312(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a4, 320(sp) ; CHECK-RV64-FD-NEXT: ld a4, 320(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a3, 328(sp) ; CHECK-RV64-FD-NEXT: ld a3, 328(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a2, 336(sp) ; CHECK-RV64-FD-NEXT: ld a2, 336(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a1, 344(sp) ; CHECK-RV64-FD-NEXT: ld a1, 344(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld a0, 352(sp) ; CHECK-RV64-FD-NEXT: ld a0, 352(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld s0, 360(sp) ; CHECK-RV64-FD-NEXT: ld s0, 360(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t2, 368(sp) ; CHECK-RV64-FD-NEXT: ld t2, 368(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t1, 376(sp) ; CHECK-RV64-FD-NEXT: ld t1, 376(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld t0, 384(sp) ; CHECK-RV64-FD-NEXT: ld t0, 384(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: ld ra, 392(sp) ; CHECK-RV64-FD-NEXT: ld ra, 392(sp) # 8-byte Folded Reload
; CHECK-RV64-FD-NEXT: addi sp, sp, 400 ; CHECK-RV64-FD-NEXT: addi sp, sp, 400
; CHECK-RV64-FD-NEXT: mret ; CHECK-RV64-FD-NEXT: mret
%call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)() %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
ret void ret void
} }
attributes #0 = { nounwind "interrupt"="user" } attributes #0 = { nounwind "interrupt"="user" }
attributes #1 = { nounwind "interrupt"="supervisor" } attributes #1 = { nounwind "interrupt"="supervisor" }
attributes #2 = { nounwind "interrupt"="machine" } attributes #2 = { nounwind "interrupt"="machine" }
attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" } attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/large-stack.ll

Show All 16 Lines
; RV32I-FPELIM-NEXT: addi a0, a0, 1664 ; RV32I-FPELIM-NEXT: addi a0, a0, 1664
; RV32I-FPELIM-NEXT: add sp, sp, a0 ; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: test: ; RV32I-WITHFP-LABEL: test:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -2032 ; RV32I-WITHFP-NEXT: addi sp, sp, -2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: sw ra, 2028(sp) ; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 2024(sp) ; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: .cfi_offset ra, -4 ; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
; RV32I-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
; RV32I-WITHFP-NEXT: addi s0, sp, 2032 ; RV32I-WITHFP-NEXT: addi s0, sp, 2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32I-WITHFP-NEXT: lui a0, 74565 ; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, -352 ; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: sub sp, sp, a0 ; RV32I-WITHFP-NEXT: sub sp, sp, a0
; RV32I-WITHFP-NEXT: lui a0, 74565 ; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, -352 ; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: add sp, sp, a0 ; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) ; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) ; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032 ; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4 %tmp = alloca [ 305419896 x i8 ] , align 4
ret void ret void
} }
; This test case artificially produces register pressure which should force ; This test case artificially produces register pressure which should force
; use of the emergency spill slot. ; use of the emergency spill slot.
define void @test_emergency_spill_slot(i32 %a) { define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-LABEL: test_emergency_spill_slot: ; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -2032 ; RV32I-FPELIM-NEXT: addi sp, sp, -2032
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032 ; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
; RV32I-FPELIM-NEXT: sw s0, 2028(sp) ; RV32I-FPELIM-NEXT: sw s0, 2028(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw s1, 2024(sp) ; RV32I-FPELIM-NEXT: sw s1, 2024(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: .cfi_offset s0, -4 ; RV32I-FPELIM-NEXT: .cfi_offset s0, -4
; RV32I-FPELIM-NEXT: .cfi_offset s1, -8 ; RV32I-FPELIM-NEXT: .cfi_offset s1, -8
; RV32I-FPELIM-NEXT: lui a1, 97 ; RV32I-FPELIM-NEXT: lui a1, 97
; RV32I-FPELIM-NEXT: addi a1, a1, 672 ; RV32I-FPELIM-NEXT: addi a1, a1, 672
; RV32I-FPELIM-NEXT: sub sp, sp, a1 ; RV32I-FPELIM-NEXT: sub sp, sp, a1
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 400016 ; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 400016
; RV32I-FPELIM-NEXT: lui a1, 78 ; RV32I-FPELIM-NEXT: lui a1, 78
; RV32I-FPELIM-NEXT: addi a1, a1, 512 ; RV32I-FPELIM-NEXT: addi a1, a1, 512
; RV32I-FPELIM-NEXT: addi a2, sp, 8 ; RV32I-FPELIM-NEXT: addi a2, sp, 8
; RV32I-FPELIM-NEXT: add a1, a2, a1 ; RV32I-FPELIM-NEXT: add a1, a2, a1
; RV32I-FPELIM-NEXT: #APP ; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop ; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-EMPTY: ; RV32I-FPELIM-EMPTY:
; RV32I-FPELIM-NEXT: #NO_APP ; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: sw a0, 0(a1) ; RV32I-FPELIM-NEXT: sw a0, 0(a1)
; RV32I-FPELIM-NEXT: #APP ; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop ; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-EMPTY: ; RV32I-FPELIM-EMPTY:
; RV32I-FPELIM-NEXT: #NO_APP ; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: lui a0, 97 ; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672 ; RV32I-FPELIM-NEXT: addi a0, a0, 672
; RV32I-FPELIM-NEXT: add sp, sp, a0 ; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: lw s1, 2024(sp) ; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s0, 2028(sp) ; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 2032 ; RV32I-FPELIM-NEXT: addi sp, sp, 2032
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: test_emergency_spill_slot: ; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -2032 ; RV32I-WITHFP-NEXT: addi sp, sp, -2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: sw ra, 2028(sp) ; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 2024(sp) ; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s1, 2020(sp) ; RV32I-WITHFP-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s2, 2016(sp) ; RV32I-WITHFP-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: .cfi_offset ra, -4 ; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
; RV32I-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
; RV32I-WITHFP-NEXT: .cfi_offset s1, -12 ; RV32I-WITHFP-NEXT: .cfi_offset s1, -12
; RV32I-WITHFP-NEXT: .cfi_offset s2, -16 ; RV32I-WITHFP-NEXT: .cfi_offset s2, -16
; RV32I-WITHFP-NEXT: addi s0, sp, 2032 ; RV32I-WITHFP-NEXT: addi s0, sp, 2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0 ; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32I-WITHFP-NEXT: lui a1, 97 ; RV32I-WITHFP-NEXT: lui a1, 97
; RV32I-WITHFP-NEXT: addi a1, a1, 688 ; RV32I-WITHFP-NEXT: addi a1, a1, 688
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; RV32I-WITHFP-NEXT: sw a0, 0(a1) ; RV32I-WITHFP-NEXT: sw a0, 0(a1)
; RV32I-WITHFP-NEXT: #APP ; RV32I-WITHFP-NEXT: #APP
; RV32I-WITHFP-NEXT: nop ; RV32I-WITHFP-NEXT: nop
; RV32I-WITHFP-EMPTY: ; RV32I-WITHFP-EMPTY:
; RV32I-WITHFP-NEXT: #NO_APP ; RV32I-WITHFP-NEXT: #NO_APP
; RV32I-WITHFP-NEXT: lui a0, 97 ; RV32I-WITHFP-NEXT: lui a0, 97
; RV32I-WITHFP-NEXT: addi a0, a0, 688 ; RV32I-WITHFP-NEXT: addi a0, a0, 688
; RV32I-WITHFP-NEXT: add sp, sp, a0 ; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s2, 2016(sp) ; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 2020(sp) ; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) ; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) ; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032 ; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4 %data = alloca [ 100000 x i32 ] , align 4
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000 %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"() %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
%asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0 %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
%asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1 %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
%asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2 %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
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llvm/test/CodeGen/RISCV/mul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s ; RUN: | FileCheck -check-prefix=RV64IM %s
define signext i32 @square(i32 %a) nounwind { define signext i32 @square(i32 %a) nounwind {
; RV32I-LABEL: square: ; RV32I-LABEL: square:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: square: ; RV32IM-LABEL: square:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: mul a0, a0, a0 ; RV32IM-NEXT: mul a0, a0, a0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: square: ; RV64I-LABEL: square:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: square: ; RV64IM-LABEL: square:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: mulw a0, a0, a0 ; RV64IM-NEXT: mulw a0, a0, a0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = mul i32 %a, %a %1 = mul i32 %a, %a
ret i32 %1 ret i32 %1
} }
define signext i32 @mul(i32 %a, i32 %b) nounwind { define signext i32 @mul(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: mul: ; RV32I-LABEL: mul:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: mul: ; RV32IM-LABEL: mul:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: mul a0, a0, a1 ; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: mul: ; RV64I-LABEL: mul:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: mul: ; RV64IM-LABEL: mul:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: mulw a0, a0, a1 ; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = mul i32 %a, %b %1 = mul i32 %a, %b
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
%1 = mul i32 %a, 8 %1 = mul i32 %a, 8
ret i32 %1 ret i32 %1
} }
define i64 @mul64(i64 %a, i64 %b) nounwind { define i64 @mul64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: mul64: ; RV32I-LABEL: mul64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: mul64: ; RV32IM-LABEL: mul64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: mul a3, a0, a3 ; RV32IM-NEXT: mul a3, a0, a3
; RV32IM-NEXT: mulhu a4, a0, a2 ; RV32IM-NEXT: mulhu a4, a0, a2
; RV32IM-NEXT: add a3, a4, a3 ; RV32IM-NEXT: add a3, a4, a3
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: add a1, a3, a1 ; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a0, a0, a2 ; RV32IM-NEXT: mul a0, a0, a2
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: mul64: ; RV64I-LABEL: mul64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: mul64: ; RV64IM-LABEL: mul64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = mul i64 %a, %b %1 = mul i64 %a, %b
Show All 37 Lines; RV64IM-NEXT: ret
%1 = mul i64 %a, 5 %1 = mul i64 %a, 5
ret i64 %1 ret i64 %1
} }
define i32 @mulhs(i32 %a, i32 %b) nounwind { define i32 @mulhs(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: mulhs: ; RV32I-LABEL: mulhs:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srai a3, a2, 31 ; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: mulhs: ; RV32IM-LABEL: mulhs:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: mulh a0, a0, a1 ; RV32IM-NEXT: mulh a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: mulhs: ; RV64I-LABEL: mulhs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: mulhs: ; RV64IM-LABEL: mulhs:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1 ; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = sext i32 %a to i64 %1 = sext i32 %a to i64
%2 = sext i32 %b to i64 %2 = sext i32 %b to i64
%3 = mul i64 %1, %2 %3 = mul i64 %1, %2
%4 = lshr i64 %3, 32 %4 = lshr i64 %3, 32
%5 = trunc i64 %4 to i32 %5 = trunc i64 %4 to i32
ret i32 %5 ret i32 %5
} }
define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind { define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV32I-LABEL: mulhu: ; RV32I-LABEL: mulhu:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: mulhu: ; RV32IM-LABEL: mulhu:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: mulhu a0, a0, a1 ; RV32IM-NEXT: mulhu a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: mulhu: ; RV64I-LABEL: mulhu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: mulhu: ; RV64IM-LABEL: mulhu:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s ; RUN: | FileCheck -check-prefix=RV64IM %s
define i32 @urem(i32 %a, i32 %b) nounwind { define i32 @urem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: urem: ; RV32I-LABEL: urem:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: urem: ; RV32IM-LABEL: urem:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: remu a0, a0, a1 ; RV32IM-NEXT: remu a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: urem: ; RV64I-LABEL: urem:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: urem: ; RV64IM-LABEL: urem:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: remuw a0, a0, a1 ; RV64IM-NEXT: remuw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem i32 %a, %b %1 = urem i32 %a, %b
ret i32 %1 ret i32 %1
} }
define i32 @srem(i32 %a, i32 %b) nounwind { define i32 @srem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srem: ; RV32I-LABEL: srem:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: srem: ; RV32IM-LABEL: srem:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: rem a0, a0, a1 ; RV32IM-NEXT: rem a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: srem: ; RV64I-LABEL: srem:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: srem: ; RV64IM-LABEL: srem:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: remw a0, a0, a1 ; RV64IM-NEXT: remw a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %a, %b %1 = srem i32 %a, %b
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/remat.ll

Show All 18 Lines
; trivially rematerialisable, meaning they are recreated rather than saved to ; trivially rematerialisable, meaning they are recreated rather than saved to
; the stack and restored. It creates high register pressure to force this ; the stack and restored. It creates high register pressure to force this
; situation. ; situation.
define i32 @test() nounwind { define i32 @test() nounwind {
; RV32I-LABEL: test: ; RV32I-LABEL: test:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -64 ; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp) ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 52(sp) ; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 48(sp) ; RV32I-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 44(sp) ; RV32I-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 40(sp) ; RV32I-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 36(sp) ; RV32I-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 32(sp) ; RV32I-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 28(sp) ; RV32I-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 24(sp) ; RV32I-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 20(sp) ; RV32I-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 16(sp) ; RV32I-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 12(sp) ; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s6, %hi(a) ; RV32I-NEXT: lui s6, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s6) ; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11 ; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader ; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s2, %hi(l) ; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k) ; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j) ; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s5, %hi(i) ; RV32I-NEXT: lui s5, %hi(i)
Show All 17 Lines
; RV32I-NEXT: beqz a1, .LBB0_5 ; RV32I-NEXT: beqz a1, .LBB0_5
; RV32I-NEXT: # %bb.4: # %if.then ; RV32I-NEXT: # %bb.4: # %if.then
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a1, %lo(b)(s11) ; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: lw a2, %lo(c)(s10) ; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1) ; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0) ; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_5: # %if.end ; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s3) ; RV32I-NEXT: lw a0, %lo(k)(s3)
; RV32I-NEXT: beqz a0, .LBB0_7 ; RV32I-NEXT: beqz a0, .LBB0_7
; RV32I-NEXT: # %bb.6: # %if.then3 ; RV32I-NEXT: # %bb.6: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(b)(s11) ; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: lw a1, %lo(c)(s10) ; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1) ; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(e)(s0) ; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a4, %lo(f)(s7) ; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: addi a5, zero, 64 ; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_7: # %if.end5 ; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s4) ; RV32I-NEXT: lw a0, %lo(j)(s4)
; RV32I-NEXT: beqz a0, .LBB0_9 ; RV32I-NEXT: beqz a0, .LBB0_9
; RV32I-NEXT: # %bb.8: # %if.then7 ; RV32I-NEXT: # %bb.8: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(c)(s10) ; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1) ; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(e)(s0) ; RV32I-NEXT: lw a2, %lo(e)(s0)
; RV32I-NEXT: lw a3, %lo(f)(s7) ; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8) ; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_9: # %if.end9 ; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s5) ; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.10: # %if.then11 ; RV32I-NEXT: # %bb.10: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(d)(s1) ; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(e)(s0) ; RV32I-NEXT: lw a1, %lo(e)(s0)
; RV32I-NEXT: lw a2, %lo(f)(s7) ; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a3, %lo(g)(s8) ; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9) ; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: addi a5, zero, 32 ; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end ; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1 ; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: lw s11, 12(sp) ; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 16(sp) ; RV32I-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 20(sp) ; RV32I-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 24(sp) ; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 28(sp) ; RV32I-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 32(sp) ; RV32I-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 36(sp) ; RV32I-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 40(sp) ; RV32I-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 44(sp) ; RV32I-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 48(sp) ; RV32I-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 52(sp) ; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64 ; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%.pr = load i32, i32* @a, align 4 %.pr = load i32, i32* @a, align 4
%tobool14 = icmp eq i32 %.pr, 0 %tobool14 = icmp eq i32 %.pr, 0
br i1 %tobool14, label %for.end, label %for.body br i1 %tobool14, label %for.end, label %for.body
for.body: ; preds = %entry, %for.inc for.body: ; preds = %entry, %for.inc
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32Zbb.ll

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
} }
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @ctlz_i32(i32 %a) nounwind { define i32 @ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: ctlz_i32: ; RV32I-LABEL: ctlz_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB8_2 ; RV32I-NEXT: beqz a0, .LBB8_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB8_3 ; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB8_3: # %cond.end ; RV32I-NEXT: .LBB8_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: ctlz_i32: ; RV32IB-LABEL: ctlz_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: clz a0, a0 ; RV32IB-NEXT: clz a0, a0
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBB-LABEL: ctlz_i32: ; RV32IBB-LABEL: ctlz_i32:
; RV32IBB: # %bb.0: ; RV32IBB: # %bb.0:
; RV32IBB-NEXT: clz a0, a0 ; RV32IBB-NEXT: clz a0, a0
; RV32IBB-NEXT: ret ; RV32IBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
define i64 @ctlz_i64(i64 %a) nounwind { define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-LABEL: ctlz_i64: ; RV32I-LABEL: ctlz_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: srli a0, a1, 1 ; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s0, a1, 257 ; RV32I-NEXT: addi s0, a1, 257
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, s4, 1 ; RV32I-NEXT: srli a0, s4, 1
; RV32I-NEXT: or a0, s4, a0 ; RV32I-NEXT: or a0, s4, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s3, .LBB9_2 ; RV32I-NEXT: bnez s3, .LBB9_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB9_3 ; RV32I-NEXT: j .LBB9_3
; RV32I-NEXT: .LBB9_2: ; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB9_3: ; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp) ; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: ctlz_i64: ; RV32IB-LABEL: ctlz_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bnez a1, .LBB9_2 ; RV32IB-NEXT: bnez a1, .LBB9_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: clz a0, a0 ; RV32IB-NEXT: clz a0, a0
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} }
declare i32 @llvm.cttz.i32(i32, i1) declare i32 @llvm.cttz.i32(i32, i1)
define i32 @cttz_i32(i32 %a) nounwind { define i32 @cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: cttz_i32: ; RV32I-LABEL: cttz_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB10_2 ; RV32I-NEXT: beqz a0, .LBB10_2
; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB10_3 ; RV32I-NEXT: j .LBB10_3
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: addi a0, zero, 32 ; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB10_3: # %cond.end ; RV32I-NEXT: .LBB10_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cttz_i32: ; RV32IB-LABEL: cttz_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: ctz a0, a0 ; RV32IB-NEXT: ctz a0, a0
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBB-LABEL: cttz_i32: ; RV32IBB-LABEL: cttz_i32:
; RV32IBB: # %bb.0: ; RV32IBB: # %bb.0:
; RV32IBB-NEXT: ctz a0, a0 ; RV32IBB-NEXT: ctz a0, a0
; RV32IBB-NEXT: ret ; RV32IBB-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.cttz.i64(i64, i1) declare i64 @llvm.cttz.i64(i64, i1)
define i64 @cttz_i64(i64 %a) nounwind { define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-LABEL: cttz_i64: ; RV32I-LABEL: cttz_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB11_2 ; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp) ; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cttz_i64: ; RV32IB-LABEL: cttz_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bnez a0, .LBB11_2 ; RV32IB-NEXT: bnez a0, .LBB11_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: ctz a0, a1 ; RV32IB-NEXT: ctz a0, a1
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} }
declare i32 @llvm.ctpop.i32(i32) declare i32 @llvm.ctpop.i32(i32)
define i32 @ctpop_i32(i32 %a) nounwind { define i32 @ctpop_i32(i32 %a) nounwind {
; RV32I-LABEL: ctpop_i32: ; RV32I-LABEL: ctpop_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819 ; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1 ; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: ctpop_i32: ; RV32IB-LABEL: ctpop_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: pcnt a0, a0 ; RV32IB-NEXT: pcnt a0, a0
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBB-LABEL: ctpop_i32: ; RV32IBB-LABEL: ctpop_i32:
; RV32IBB: # %bb.0: ; RV32IBB: # %bb.0:
; RV32IBB-NEXT: pcnt a0, a0 ; RV32IBB-NEXT: pcnt a0, a0
; RV32IBB-NEXT: ret ; RV32IBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.ctpop.i64(i64) declare i64 @llvm.ctpop.i64(i64)
define i64 @ctpop_i64(i64 %a) nounwind { define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-LABEL: ctpop_i64: ; RV32I-LABEL: ctpop_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, a1, 1 ; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s3, a2, 1365 ; RV32I-NEXT: addi s3, a2, 1365
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s4, a1, -241 ; RV32I-NEXT: addi s4, a1, -241
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: sub a0, s2, a0 ; RV32I-NEXT: sub a0, s2, a0
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: add a0, a0, s5
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: ctpop_i64: ; RV32IB-LABEL: ctpop_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: pcnt a1, a1 ; RV32IB-NEXT: pcnt a1, a1
; RV32IB-NEXT: pcnt a0, a0 ; RV32IB-NEXT: pcnt a0, a0
; RV32IB-NEXT: add a0, a0, a1 ; RV32IB-NEXT: add a0, a0, a1
▲ Show 20 Lines • Show All 499 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll

Show All 9 Lines
; extension isn't enabled. ; extension isn't enabled.
; TODO: f32 parameters on RV64 with a soft-float ABI are anyext. ; TODO: f32 parameters on RV64 with a soft-float ABI are anyext.
define float @float_test(float %a, float %b) nounwind { define float @float_test(float %a, float %b) nounwind {
; RV32IF-LABEL: float_test: ; RV32IF-LABEL: float_test:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a1 ; RV32IF-NEXT: mv s0, a1
; RV32IF-NEXT: call __addsf3 ; RV32IF-NEXT: call __addsf3@plt
; RV32IF-NEXT: mv a1, s0 ; RV32IF-NEXT: mv a1, s0
; RV32IF-NEXT: call __divsf3 ; RV32IF-NEXT: call __divsf3@plt
; RV32IF-NEXT: lw s0, 8(sp) ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: float_test: ; RV64IF-LABEL: float_test:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a1 ; RV64IF-NEXT: mv s0, a1
; RV64IF-NEXT: call __addsf3 ; RV64IF-NEXT: call __addsf3@plt
; RV64IF-NEXT: mv a1, s0 ; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divsf3 ; RV64IF-NEXT: call __divsf3@plt
; RV64IF-NEXT: ld s0, 0(sp) ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
%2 = fdiv float %1, %b %2 = fdiv float %1, %b
ret float %2 ret float %2
} }
define double @double_test(double %a, double %b) nounwind { define double @double_test(double %a, double %b) nounwind {
; RV32IF-LABEL: double_test: ; RV32IF-LABEL: double_test:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s1, 4(sp) ; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a3 ; RV32IF-NEXT: mv s0, a3
; RV32IF-NEXT: mv s1, a2 ; RV32IF-NEXT: mv s1, a2
; RV32IF-NEXT: call __adddf3 ; RV32IF-NEXT: call __adddf3@plt
; RV32IF-NEXT: mv a2, s1 ; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: mv a3, s0 ; RV32IF-NEXT: mv a3, s0
; RV32IF-NEXT: call __divdf3 ; RV32IF-NEXT: call __divdf3@plt
; RV32IF-NEXT: lw s1, 4(sp) ; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: double_test: ; RV64IF-LABEL: double_test:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) ; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a1 ; RV64IF-NEXT: mv s0, a1
; RV64IF-NEXT: call __adddf3 ; RV64IF-NEXT: call __adddf3@plt
; RV64IF-NEXT: mv a1, s0 ; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divdf3 ; RV64IF-NEXT: call __divdf3@plt
; RV64IF-NEXT: ld s0, 0(sp) ; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fadd double %a, %b %1 = fadd double %a, %b
%2 = fdiv double %1, %b %2 = fdiv double %1, %b
ret double %2 ret double %2
} }

llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; This file provides a simple sanity check of half operations for ; This file provides a simple sanity check of half operations for
; RV32I and RV64I. This is primarily intended to ensure that custom ; RV32I and RV64I. This is primarily intended to ensure that custom
; legalisation or DAG combines aren't incorrectly triggered when the Zfh ; legalisation or DAG combines aren't incorrectly triggered when the Zfh
; extension isn't enabled. ; extension isn't enabled.
define half @half_test(half %a, half %b) nounwind { define half @half_test(half %a, half %b) nounwind {
; RV32I-LABEL: half_test: ; RV32I-LABEL: half_test:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: call __gnu_h2f_ieee ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3 ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __divsf3 ; RV32I-NEXT: call __divsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s2, 0(sp) ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: half_test: ; RV64I-LABEL: half_test:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: call __gnu_h2f_ieee ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __divsf3 ; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s2, 0(sp) ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = fdiv half %1, %b %2 = fdiv half %1, %b
ret half %2 ret half %2
} }

llvm/test/CodeGen/RISCV/rv64-large-stack.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
; ;
; The test case check that RV64 could handle the stack adjustment offset exceed ; The test case check that RV64 could handle the stack adjustment offset exceed
; 32-bit. ; 32-bit.
define void @foo() nounwind { define void @foo() nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -2032 ; CHECK-NEXT: addi sp, sp, -2032
; CHECK-NEXT: sd ra, 2024(sp) ; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; CHECK-NEXT: lui a0, 95 ; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505 ; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13 ; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: addi a0, a0, -2000 ; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: call baz ; CHECK-NEXT: call baz@plt
; CHECK-NEXT: lui a0, 95 ; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505 ; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13 ; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: addi a0, a0, -2000 ; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld ra, 2024(sp) ; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032 ; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%w = alloca [100000000 x { fp128, fp128 }], align 16 %w = alloca [100000000 x { fp128, fp128 }], align 16
%arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0 %arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
call void @baz({ fp128, fp128 }* nonnull %arraydecay) call void @baz({ fp128, fp128 }* nonnull %arraydecay)
ret void ret void
} }
declare void @baz({ fp128, fp128 }*) declare void @baz({ fp128, fp128 }*)

llvm/test/CodeGen/RISCV/rv64Zbb.ll

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
} }
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
define signext i32 @ctlz_i32(i32 signext %a) nounwind { define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ctlz_i32: ; RV64I-LABEL: ctlz_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: beqz a0, .LBB9_2 ; RV64I-NEXT: beqz a0, .LBB9_2
; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: addi a0, a0, -32 ; RV64I-NEXT: addi a0, a0, -32
; RV64I-NEXT: j .LBB9_3 ; RV64I-NEXT: j .LBB9_3
; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: .LBB9_3: # %cond.end ; RV64I-NEXT: .LBB9_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: ctlz_i32: ; RV64IB-LABEL: ctlz_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: clzw a0, a0 ; RV64IB-NEXT: clzw a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: ctlz_i32: ; RV64IBB-LABEL: ctlz_i32:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: clzw a0, a0 ; RV64IBB-NEXT: clzw a0, a0
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
define i64 @ctlz_i64(i64 %a) nounwind { define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-LABEL: ctlz_i64: ; RV64I-LABEL: ctlz_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: beqz a0, .LBB10_2 ; RV64I-NEXT: beqz a0, .LBB10_2
; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
Show All 39 Lines
; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB10_3 ; RV64I-NEXT: j .LBB10_3
; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: .LBB10_3: # %cond.end ; RV64I-NEXT: .LBB10_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: ctlz_i64: ; RV64IB-LABEL: ctlz_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: clz a0, a0 ; RV64IB-NEXT: clz a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: ctlz_i64: ; RV64IBB-LABEL: ctlz_i64:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: clz a0, a0 ; RV64IBB-NEXT: clz a0, a0
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
ret i64 %1 ret i64 %1
} }
declare i32 @llvm.cttz.i32(i32, i1) declare i32 @llvm.cttz.i32(i32, i1)
define signext i32 @cttz_i32(i32 signext %a) nounwind { define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-LABEL: cttz_i32: ; RV64I-LABEL: cttz_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: beqz a0, .LBB11_2 ; RV64I-NEXT: beqz a0, .LBB11_2
; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 21845 ; RV64I-NEXT: lui a2, 21845
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
Show All 29 Lines
; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB11_3 ; RV64I-NEXT: j .LBB11_3
; RV64I-NEXT: .LBB11_2: ; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: addi a0, zero, 32 ; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: .LBB11_3: # %cond.end ; RV64I-NEXT: .LBB11_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cttz_i32: ; RV64IB-LABEL: cttz_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: ctzw a0, a0 ; RV64IB-NEXT: ctzw a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: cttz_i32: ; RV64IBB-LABEL: cttz_i32:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: ctzw a0, a0 ; RV64IBB-NEXT: ctzw a0, a0
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.cttz.i64(i64, i1) declare i64 @llvm.cttz.i64(i64, i1)
define i64 @cttz_i64(i64 %a) nounwind { define i64 @cttz_i64(i64 %a) nounwind {
; RV64I-LABEL: cttz_i64: ; RV64I-LABEL: cttz_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: beqz a0, .LBB12_2 ; RV64I-NEXT: beqz a0, .LBB12_2
; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 21845 ; RV64I-NEXT: lui a2, 21845
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
Show All 29 Lines
; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: j .LBB12_3 ; RV64I-NEXT: j .LBB12_3
; RV64I-NEXT: .LBB12_2: ; RV64I-NEXT: .LBB12_2:
; RV64I-NEXT: addi a0, zero, 64 ; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: .LBB12_3: # %cond.end ; RV64I-NEXT: .LBB12_3: # %cond.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cttz_i64: ; RV64IB-LABEL: cttz_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: ctz a0, a0 ; RV64IB-NEXT: ctz a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: cttz_i64: ; RV64IBB-LABEL: cttz_i64:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: ctz a0, a0 ; RV64IBB-NEXT: ctz a0, a0
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %1 ret i64 %1
} }
declare i32 @llvm.ctpop.i32(i32) declare i32 @llvm.ctpop.i32(i32)
define signext i32 @ctpop_i32(i32 signext %a) nounwind { define signext i32 @ctpop_i32(i32 signext %a) nounwind {
; RV64I-LABEL: ctpop_i32: ; RV64I-LABEL: ctpop_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: srliw a0, a0, 1 ; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a1, a0 ; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
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; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: ctpop_i32: ; RV64IB-LABEL: ctpop_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: pcntw a0, a0 ; RV64IB-NEXT: pcntw a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: ctpop_i32: ; RV64IBB-LABEL: ctpop_i32:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: pcntw a0, a0 ; RV64IBB-NEXT: pcntw a0, a0
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a) %1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.ctpop.i64(i64) declare i64 @llvm.ctpop.i64(i64)
define i64 @ctpop_i64(i64 %a) nounwind { define i64 @ctpop_i64(i64 %a) nounwind {
; RV64I-LABEL: ctpop_i64: ; RV64I-LABEL: ctpop_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 21845 ; RV64I-NEXT: lui a2, 21845
; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a2, a2, 12 ; RV64I-NEXT: slli a2, a2, 12
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; RV64I-NEXT: addi a1, a1, -241 ; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 257 ; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: ctpop_i64: ; RV64IB-LABEL: ctpop_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: pcnt a0, a0 ; RV64IB-NEXT: pcnt a0, a0
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
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llvm/test/CodeGen/RISCV/rv64i-complex-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
; The complex floating value will be returned by a single register for LP64 ABI. ; The complex floating value will be returned by a single register for LP64 ABI.
; The test case check that the real part returned by __addsf3 will be ; The test case check that the real part returned by __addsf3 will be
; cleared upper bits by shifts to avoid corrupting the imaginary part. ; cleared upper bits by shifts to avoid corrupting the imaginary part.
define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind { define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-LABEL: complex_float_add: ; CHECK-LABEL: complex_float_add:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: srli s2, a0, 32 ; CHECK-NEXT: srli s2, a0, 32
; CHECK-NEXT: srli s1, a1, 32 ; CHECK-NEXT: srli s1, a1, 32
; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __addsf3 ; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: slli a0, a0, 32 ; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: slli a1, s0, 32 ; CHECK-NEXT: slli a1, s0, 32
; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1 ; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld s2, 0(sp) ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.sroa.0.0.extract.trunc = trunc i64 %a.coerce to i32 %a.sroa.0.0.extract.trunc = trunc i64 %a.coerce to i32
%0 = bitcast i32 %a.sroa.0.0.extract.trunc to float %0 = bitcast i32 %a.sroa.0.0.extract.trunc to float
%a.sroa.2.0.extract.shift = lshr i64 %a.coerce, 32 %a.sroa.2.0.extract.shift = lshr i64 %a.coerce, 32
%a.sroa.2.0.extract.trunc = trunc i64 %a.sroa.2.0.extract.shift to i32 %a.sroa.2.0.extract.trunc = trunc i64 %a.sroa.2.0.extract.shift to i32
%1 = bitcast i32 %a.sroa.2.0.extract.trunc to float %1 = bitcast i32 %a.sroa.2.0.extract.trunc to float
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llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; The test cases check that we use the si versions of the conversions from ; The test cases check that we use the si versions of the conversions from
; double. ; double.
define i32 @fp64_to_ui32(double %a) nounwind { define i32 @fp64_to_ui32(double %a) nounwind {
; RV64I-LABEL: fp64_to_ui32: ; RV64I-LABEL: fp64_to_ui32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IF-LABEL: fp64_to_ui32: ; RV64IF-LABEL: fp64_to_ui32:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: call __fixunsdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
entry: entry:
%conv = fptoui double %a to i32 %conv = fptoui double %a to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fp64_to_si32(double %a) nounwind { define i32 @fp64_to_si32(double %a) nounwind {
; RV64I-LABEL: fp64_to_si32: ; RV64I-LABEL: fp64_to_si32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixdfsi ; RV64I-NEXT: call __fixdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IF-LABEL: fp64_to_si32: ; RV64IF-LABEL: fp64_to_si32:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: call __fixdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
entry: entry:
%conv = fptosi double %a to i32 %conv = fptosi double %a to i32
ret i32 %conv ret i32 %conv
} }
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp { define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
; RV64I-LABEL: strict_fp64_to_ui32: ; RV64I-LABEL: strict_fp64_to_ui32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi ; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IF-LABEL: strict_fp64_to_ui32: ; RV64IF-LABEL: strict_fp64_to_ui32:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixunsdfsi ; RV64IF-NEXT: call __fixunsdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
entry: entry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv ret i32 %conv
} }
define i32 @struct_fp64_to_si32(double %a) nounwind strictfp { define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-LABEL: struct_fp64_to_si32: ; RV64I-LABEL: struct_fp64_to_si32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixdfsi ; RV64I-NEXT: call __fixdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IF-LABEL: struct_fp64_to_si32: ; RV64IF-LABEL: struct_fp64_to_si32:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixdfsi ; RV64IF-NEXT: call __fixdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
entry: entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; The test cases check that the single float arguments won't be extended ; The test cases check that the single float arguments won't be extended
; when passing to softfloat functions. ; when passing to softfloat functions.
; RISCV backend using shouldExtendTypeInLibCall target hook to suppress ; RISCV backend using shouldExtendTypeInLibCall target hook to suppress
; the extension generation. ; the extension generation.
define float @fadd_s(float %a, float %b) nounwind { define float @fadd_s(float %a, float %b) nounwind {
; RV64I-LABEL: fadd_s: ; RV64I-LABEL: fadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fadd float %a, %b %1 = fadd float %a, %b
ret float %1 ret float %1
} }
define float @fsub_s(float %a, float %b) nounwind { define float @fsub_s(float %a, float %b) nounwind {
; RV64I-LABEL: fsub_s: ; RV64I-LABEL: fsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __subsf3 ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fsub float %a, %b %1 = fsub float %a, %b
ret float %1 ret float %1
} }
define float @fmul_s(float %a, float %b) nounwind { define float @fmul_s(float %a, float %b) nounwind {
; RV64I-LABEL: fmul_s: ; RV64I-LABEL: fmul_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fmul float %a, %b %1 = fmul float %a, %b
ret float %1 ret float %1
} }
define float @fdiv_s(float %a, float %b) nounwind { define float @fdiv_s(float %a, float %b) nounwind {
; RV64I-LABEL: fdiv_s: ; RV64I-LABEL: fdiv_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __divsf3 ; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fdiv float %a, %b %1 = fdiv float %a, %b
ret float %1 ret float %1
} }
define i32 @feq_s(float %a, float %b) nounwind { define i32 @feq_s(float %a, float %b) nounwind {
; RV64I-LABEL: feq_s: ; RV64I-LABEL: feq_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __eqsf2 ; RV64I-NEXT: call __eqsf2@plt
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @flt_s(float %a, float %b) nounwind { define i32 @flt_s(float %a, float %b) nounwind {
; RV64I-LABEL: flt_s: ; RV64I-LABEL: flt_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ltsf2 ; RV64I-NEXT: call __ltsf2@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slti a0, a0, 0 ; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp olt float %a, %b %1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fle_s(float %a, float %b) nounwind { define i32 @fle_s(float %a, float %b) nounwind {
; RV64I-LABEL: fle_s: ; RV64I-LABEL: fle_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __lesf2 ; RV64I-NEXT: call __lesf2@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slti a0, a0, 1 ; RV64I-NEXT: slti a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ogt(float %a, float %b) nounwind { define i32 @fcmp_ogt(float %a, float %b) nounwind {
; RV64I-LABEL: fcmp_ogt: ; RV64I-LABEL: fcmp_ogt:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ogt float %a, %b %1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_oge(float %a, float %b) nounwind { define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV64I-LABEL: fcmp_oge: ; RV64I-LABEL: fcmp_oge:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gesf2 ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, -1 ; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp oge float %a, %b %1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(float %a, float %b) nounwind { define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV64I-LABEL: fcmp_ord: ; RV64I-LABEL: fcmp_ord:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_une(float %a, float %b) nounwind { define i32 @fcmp_une(float %a, float %b) nounwind {
; RV64I-LABEL: fcmp_une: ; RV64I-LABEL: fcmp_une:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __nesf2 ; RV64I-NEXT: call __nesf2@plt
; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fcmp une float %a, %b %1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcvt_w_s(float %a) nounwind { define i32 @fcvt_w_s(float %a) nounwind {
; RV64I-LABEL: fcvt_w_s: ; RV64I-LABEL: fcvt_w_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: call __fixsfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi float %a to i32 %1 = fptosi float %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @fcvt_wu_s(float %a) nounwind { define i32 @fcvt_wu_s(float %a) nounwind {
; RV64I-LABEL: fcvt_wu_s: ; RV64I-LABEL: fcvt_wu_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: call __fixunssfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptoui float %a to i32 %1 = fptoui float %a to i32
ret i32 %1 ret i32 %1
} }
define float @fcvt_s_w(i32 %a) nounwind { define float @fcvt_s_w(i32 %a) nounwind {
; RV64I-LABEL: fcvt_s_w: ; RV64I-LABEL: fcvt_s_w:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: call __floatsisf ; RV64I-NEXT: call __floatsisf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = sitofp i32 %a to float %1 = sitofp i32 %a to float
ret float %1 ret float %1
} }
define float @fcvt_s_wu(i32 %a) nounwind { define float @fcvt_s_wu(i32 %a) nounwind {
; RV64I-LABEL: fcvt_s_wu: ; RV64I-LABEL: fcvt_s_wu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: call __floatunsisf ; RV64I-NEXT: call __floatunsisf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = uitofp i32 %a to float %1 = uitofp i32 %a to float
ret float %1 ret float %1
} }
define i64 @fcvt_l_s(float %a) nounwind { define i64 @fcvt_l_s(float %a) nounwind {
; RV64I-LABEL: fcvt_l_s: ; RV64I-LABEL: fcvt_l_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixsfdi ; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi float %a to i64 %1 = fptosi float %a to i64
ret i64 %1 ret i64 %1
} }
define i64 @fcvt_lu_s(float %a) nounwind { define i64 @fcvt_lu_s(float %a) nounwind {
; RV64I-LABEL: fcvt_lu_s: ; RV64I-LABEL: fcvt_lu_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfdi ; RV64I-NEXT: call __fixunssfdi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptoui float %a to i64 %1 = fptoui float %a to i64
ret i64 %1 ret i64 %1
} }
define float @fcvt_s_l(i64 %a) nounwind { define float @fcvt_s_l(i64 %a) nounwind {
; RV64I-LABEL: fcvt_s_l: ; RV64I-LABEL: fcvt_s_l:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floatdisf ; RV64I-NEXT: call __floatdisf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = sitofp i64 %a to float %1 = sitofp i64 %a to float
ret float %1 ret float %1
} }
define float @fcvt_s_lu(i64 %a) nounwind { define float @fcvt_s_lu(i64 %a) nounwind {
; RV64I-LABEL: fcvt_s_lu: ; RV64I-LABEL: fcvt_s_lu:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floatundisf ; RV64I-NEXT: call __floatundisf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = uitofp i64 %a to float %1 = uitofp i64 %a to float
ret float %1 ret float %1
} }
declare float @llvm.sqrt.f32(float) declare float @llvm.sqrt.f32(float)
define float @fsqrt_s(float %a) nounwind { define float @fsqrt_s(float %a) nounwind {
; RV64I-LABEL: fsqrt_s: ; RV64I-LABEL: fsqrt_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call sqrtf ; RV64I-NEXT: call sqrtf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.sqrt.f32(float %a) %1 = call float @llvm.sqrt.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.copysign.f32(float, float) declare float @llvm.copysign.f32(float, float)
Show All 11 Lines
} }
declare float @llvm.minnum.f32(float, float) declare float @llvm.minnum.f32(float, float)
define float @fmin_s(float %a, float %b) nounwind { define float @fmin_s(float %a, float %b) nounwind {
; RV64I-LABEL: fmin_s: ; RV64I-LABEL: fmin_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fminf ; RV64I-NEXT: call fminf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.minnum.f32(float %a, float %b) %1 = call float @llvm.minnum.f32(float %a, float %b)
ret float %1 ret float %1
} }
declare float @llvm.maxnum.f32(float, float) declare float @llvm.maxnum.f32(float, float)
define float @fmax_s(float %a, float %b) nounwind { define float @fmax_s(float %a, float %b) nounwind {
; RV64I-LABEL: fmax_s: ; RV64I-LABEL: fmax_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmaxf ; RV64I-NEXT: call fmaxf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.maxnum.f32(float %a, float %b) %1 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %1 ret float %1
} }
declare float @llvm.fma.f32(float, float, float) declare float @llvm.fma.f32(float, float, float)
define float @fmadd_s(float %a, float %b, float %c) nounwind { define float @fmadd_s(float %a, float %b, float %c) nounwind {
; RV64I-LABEL: fmadd_s: ; RV64I-LABEL: fmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmaf ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c) %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
define float @fmsub_s(float %a, float %b, float %c) nounwind { define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV64I-LABEL: fmsub_s: ; RV64I-LABEL: fmsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a2, a0, a1 ; RV64I-NEXT: xor a2, a0, a1
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call fmaf ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor %c_ = fadd float 0.0, %c ; avoid negation using xor
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc) %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmadd_s(float %a, float %b, float %c) nounwind { define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV64I-LABEL: fnmadd_s: ; RV64I-LABEL: fnmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call fmaf ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s2, 0(sp) ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
%c_ = fadd float 0.0, %c %c_ = fadd float 0.0, %c
%nega = fsub float -0.0, %a_ %nega = fsub float -0.0, %a_
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %negc) %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
ret float %1 ret float %1
} }
define float @fnmsub_s(float %a, float %b, float %c) nounwind { define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV64I-LABEL: fnmsub_s: ; RV64I-LABEL: fnmsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __addsf3 ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: call fmaf ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
%nega = fsub float -0.0, %a_ %nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c) %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
ret float %1 ret float %1
} }
declare float @llvm.ceil.f32(float) declare float @llvm.ceil.f32(float)
define float @fceil_s(float %a) nounwind { define float @fceil_s(float %a) nounwind {
; RV64I-LABEL: fceil_s: ; RV64I-LABEL: fceil_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call ceilf ; RV64I-NEXT: call ceilf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.ceil.f32(float %a) %1 = call float @llvm.ceil.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.cos.f32(float) declare float @llvm.cos.f32(float)
define float @fcos_s(float %a) nounwind { define float @fcos_s(float %a) nounwind {
; RV64I-LABEL: fcos_s: ; RV64I-LABEL: fcos_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call cosf ; RV64I-NEXT: call cosf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.cos.f32(float %a) %1 = call float @llvm.cos.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.sin.f32(float) declare float @llvm.sin.f32(float)
define float @fsin_s(float %a) nounwind { define float @fsin_s(float %a) nounwind {
; RV64I-LABEL: fsin_s: ; RV64I-LABEL: fsin_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call sinf ; RV64I-NEXT: call sinf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.sin.f32(float %a) %1 = call float @llvm.sin.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.exp.f32(float) declare float @llvm.exp.f32(float)
define float @fexp_s(float %a) nounwind { define float @fexp_s(float %a) nounwind {
; RV64I-LABEL: fexp_s: ; RV64I-LABEL: fexp_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call expf ; RV64I-NEXT: call expf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.exp.f32(float %a) %1 = call float @llvm.exp.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.exp2.f32(float) declare float @llvm.exp2.f32(float)
define float @fexp2_s(float %a) nounwind { define float @fexp2_s(float %a) nounwind {
; RV64I-LABEL: fexp2_s: ; RV64I-LABEL: fexp2_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call exp2f ; RV64I-NEXT: call exp2f@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.exp2.f32(float %a) %1 = call float @llvm.exp2.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.floor.f32(float) declare float @llvm.floor.f32(float)
define float @ffloor_s(float %a) nounwind { define float @ffloor_s(float %a) nounwind {
; RV64I-LABEL: ffloor_s: ; RV64I-LABEL: ffloor_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call floorf ; RV64I-NEXT: call floorf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.floor.f32(float %a) %1 = call float @llvm.floor.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.flog.f32(float) declare float @llvm.flog.f32(float)
define float @fflog_s(float %a) nounwind { define float @fflog_s(float %a) nounwind {
; RV64I-LABEL: fflog_s: ; RV64I-LABEL: fflog_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.flog.f32 ; RV64I-NEXT: call llvm.flog.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.flog.f32(float %a) %1 = call float @llvm.flog.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.flog2.f32(float) declare float @llvm.flog2.f32(float)
define float @fflog2_s(float %a) nounwind { define float @fflog2_s(float %a) nounwind {
; RV64I-LABEL: fflog2_s: ; RV64I-LABEL: fflog2_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.flog2.f32 ; RV64I-NEXT: call llvm.flog2.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.flog2.f32(float %a) %1 = call float @llvm.flog2.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.flog10.f32(float) declare float @llvm.flog10.f32(float)
define float @fflog10_s(float %a) nounwind { define float @fflog10_s(float %a) nounwind {
; RV64I-LABEL: fflog10_s: ; RV64I-LABEL: fflog10_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.flog10.f32 ; RV64I-NEXT: call llvm.flog10.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.flog10.f32(float %a) %1 = call float @llvm.flog10.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.fnearbyint.f32(float) declare float @llvm.fnearbyint.f32(float)
define float @fnearbyint_s(float %a) nounwind { define float @fnearbyint_s(float %a) nounwind {
; RV64I-LABEL: fnearbyint_s: ; RV64I-LABEL: fnearbyint_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.fnearbyint.f32 ; RV64I-NEXT: call llvm.fnearbyint.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.fnearbyint.f32(float %a) %1 = call float @llvm.fnearbyint.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.round.f32(float) declare float @llvm.round.f32(float)
define float @fround_s(float %a) nounwind { define float @fround_s(float %a) nounwind {
; RV64I-LABEL: fround_s: ; RV64I-LABEL: fround_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call roundf ; RV64I-NEXT: call roundf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.round.f32(float %a) %1 = call float @llvm.round.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.fpround.f32(float) declare float @llvm.fpround.f32(float)
define float @fpround_s(float %a) nounwind { define float @fpround_s(float %a) nounwind {
; RV64I-LABEL: fpround_s: ; RV64I-LABEL: fpround_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.fpround.f32 ; RV64I-NEXT: call llvm.fpround.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.fpround.f32(float %a) %1 = call float @llvm.fpround.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.rint.f32(float) declare float @llvm.rint.f32(float)
define float @frint_s(float %a) nounwind { define float @frint_s(float %a) nounwind {
; RV64I-LABEL: frint_s: ; RV64I-LABEL: frint_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call rintf ; RV64I-NEXT: call rintf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.rint.f32(float %a) %1 = call float @llvm.rint.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.rem.f32(float) declare float @llvm.rem.f32(float)
define float @frem_s(float %a) nounwind { define float @frem_s(float %a) nounwind {
; RV64I-LABEL: frem_s: ; RV64I-LABEL: frem_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call llvm.rem.f32 ; RV64I-NEXT: call llvm.rem.f32@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.rem.f32(float %a) %1 = call float @llvm.rem.f32(float %a)
ret float %1 ret float %1
} }
declare float @llvm.pow.f32(float %Val, float %power) declare float @llvm.pow.f32(float %Val, float %power)
define float @fpow_s(float %a, float %b) nounwind { define float @fpow_s(float %a, float %b) nounwind {
; RV64I-LABEL: fpow_s: ; RV64I-LABEL: fpow_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call powf ; RV64I-NEXT: call powf@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.pow.f32(float %a, float %b) %1 = call float @llvm.pow.f32(float %a, float %b)
ret float %1 ret float %1
} }
declare float @llvm.powi.f32(float %Val, i32 %power) declare float @llvm.powi.f32(float %Val, i32 %power)
define float @fpowi_s(float %a, i32 %b) nounwind { define float @fpowi_s(float %a, i32 %b) nounwind {
; RV64I-LABEL: fpowi_s: ; RV64I-LABEL: fpowi_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: call __powisf2 ; RV64I-NEXT: call __powisf2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = call float @llvm.powi.f32(float %a, i32 %b) %1 = call float @llvm.powi.f32(float %a, i32 %b)
ret float %1 ret float %1
} }
define double @fp_ext(float %a) nounwind { define double @fp_ext(float %a) nounwind {
; RV64I-LABEL: fp_ext: ; RV64I-LABEL: fp_ext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendsfdf2 ; RV64I-NEXT: call __extendsfdf2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%conv = fpext float %a to double %conv = fpext float %a to double
ret double %conv ret double %conv
} }
define float @fp_trunc(double %a) nounwind { define float @fp_trunc(double %a) nounwind {
; RV64I-LABEL: fp_trunc: ; RV64I-LABEL: fp_trunc:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __truncdfsf2 ; RV64I-NEXT: call __truncdfsf2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%conv = fptrunc double %a to float %conv = fptrunc double %a to float
ret float %conv ret float %conv
} }
define i32 @fp32_to_ui32(float %a) nounwind { define i32 @fp32_to_ui32(float %a) nounwind {
; RV64I-LABEL: fp32_to_ui32: ; RV64I-LABEL: fp32_to_ui32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: call __fixunssfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%conv = fptoui float %a to i32 %conv = fptoui float %a to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fp32_to_si32(float %a) nounwind { define i32 @fp32_to_si32(float %a) nounwind {
; RV64I-LABEL: fp32_to_si32: ; RV64I-LABEL: fp32_to_si32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: call __fixsfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%conv = fptosi float %a to i32 %conv = fptosi float %a to i32
ret i32 %conv ret i32 %conv
} }
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp { define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
; RV64I-LABEL: strict_fp32_to_ui32: ; RV64I-LABEL: strict_fp32_to_ui32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: call __fixunssfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")
ret i32 %conv ret i32 %conv
} }
define i32 @strict_fp32_to_si32(float %a) nounwind strictfp { define i32 @strict_fp32_to_si32(float %a) nounwind strictfp {
; RV64I-LABEL: strict_fp32_to_si32: ; RV64I-LABEL: strict_fp32_to_si32:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: call __fixsfsi@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
entry: entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/RISCV/select-and.ll

Show All 33 Lines
declare signext i32 @both() nounwind declare signext i32 @both() nounwind
declare signext i32 @neither() nounwind declare signext i32 @neither() nounwind
define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind { define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I-LABEL: if_of_and: ; RV32I-LABEL: if_of_and:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: addi a1, zero, 1 ; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: bne a0, a1, .LBB1_2 ; RV32I-NEXT: bne a0, a1, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.then ; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call both ; RV32I-NEXT: call both@plt
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else ; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither ; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end ; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: if_of_and: ; RV64I-LABEL: if_of_and:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: bne a0, a1, .LBB1_2 ; RV64I-NEXT: bne a0, a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then ; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call both ; RV64I-NEXT: call both@plt
; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else ; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither ; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end ; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = and i1 %a, %b %1 = and i1 %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
%2 = tail call i32 @both() %2 = tail call i32 @both()
br label %if.end br label %if.end
Show All 9 Lines

llvm/test/CodeGen/RISCV/select-or.ll

Show All 33 Lines
declare signext i32 @either() nounwind declare signext i32 @either() nounwind
declare signext i32 @neither() nounwind declare signext i32 @neither() nounwind
define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind { define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I-LABEL: if_of_or: ; RV32I-LABEL: if_of_or:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: addi a1, zero, 1 ; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: bne a0, a1, .LBB1_2 ; RV32I-NEXT: bne a0, a1, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.then ; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call either ; RV32I-NEXT: call either@plt
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else ; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither ; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end ; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: if_of_or: ; RV64I-LABEL: if_of_or:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: bne a0, a1, .LBB1_2 ; RV64I-NEXT: bne a0, a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then ; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call either ; RV64I-NEXT: call either@plt
; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else ; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither ; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end ; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = or i1 %a, %b %1 = or i1 %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
%2 = tail call i32 @either() %2 = tail call i32 @either()
br label %if.end br label %if.end
Show All 9 Lines

llvm/test/CodeGen/RISCV/shadowcallstack.ll

Show All 14 Lines; RV64-NEXT: ret
ret void ret void
} }
declare void @foo() declare void @foo()
define void @f2() shadowcallstack { define void @f2() shadowcallstack {
; RV32-LABEL: f2: ; RV32-LABEL: f2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: tail foo ; RV32-NEXT: tail foo@plt
; ;
; RV64-LABEL: f2: ; RV64-LABEL: f2:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: tail foo ; RV64-NEXT: tail foo@plt
tail call void @foo() tail call void @foo()
ret void ret void
} }
declare i32 @bar() declare i32 @bar()
define i32 @f3() shadowcallstack { define i32 @f3() shadowcallstack {
; RV32-LABEL: f3: ; RV32-LABEL: f3:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: sw ra, 0(s2) ; RV32-NEXT: sw ra, 0(s2)
; RV32-NEXT: addi s2, s2, 4 ; RV32-NEXT: addi s2, s2, 4
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: lw ra, -4(s2) ; RV32-NEXT: lw ra, -4(s2)
; RV32-NEXT: addi s2, s2, -4 ; RV32-NEXT: addi s2, s2, -4
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: f3: ; RV64-LABEL: f3:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sd ra, 0(s2) ; RV64-NEXT: sd ra, 0(s2)
; RV64-NEXT: addi s2, s2, 8 ; RV64-NEXT: addi s2, s2, 8
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ld ra, -8(s2) ; RV64-NEXT: ld ra, -8(s2)
; RV64-NEXT: addi s2, s2, -8 ; RV64-NEXT: addi s2, s2, -8
; RV64-NEXT: ret ; RV64-NEXT: ret
%res = call i32 @bar() %res = call i32 @bar()
%res1 = add i32 %res, 1 %res1 = add i32 %res, 1
ret i32 %res ret i32 %res
} }
define i32 @f4() shadowcallstack { define i32 @f4() shadowcallstack {
; RV32-LABEL: f4: ; RV32-LABEL: f4:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: sw ra, 0(s2) ; RV32-NEXT: sw ra, 0(s2)
; RV32-NEXT: addi s2, s2, 4 ; RV32-NEXT: addi s2, s2, 4
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 8(sp) ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 4(sp) ; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s3, 0(sp) ; RV32-NEXT: sw s3, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_offset s0, -8 ; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: .cfi_offset s1, -12 ; RV32-NEXT: .cfi_offset s1, -12
; RV32-NEXT: .cfi_offset s3, -16 ; RV32-NEXT: .cfi_offset s3, -16
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s3, a0 ; RV32-NEXT: mv s3, a0
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s1, a0 ; RV32-NEXT: mv s1, a0
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s0, a0 ; RV32-NEXT: mv s0, a0
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: add a1, s3, s1 ; RV32-NEXT: add a1, s3, s1
; RV32-NEXT: add a0, s0, a0 ; RV32-NEXT: add a0, s0, a0
; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: lw s3, 0(sp) ; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 4(sp) ; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: lw ra, -4(s2) ; RV32-NEXT: lw ra, -4(s2)
; RV32-NEXT: addi s2, s2, -4 ; RV32-NEXT: addi s2, s2, -4
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: f4: ; RV64-LABEL: f4:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sd ra, 0(s2) ; RV64-NEXT: sd ra, 0(s2)
; RV64-NEXT: addi s2, s2, 8 ; RV64-NEXT: addi s2, s2, 8
; RV64-NEXT: addi sp, sp, -32 ; RV64-NEXT: addi sp, sp, -32
; RV64-NEXT: .cfi_def_cfa_offset 32 ; RV64-NEXT: .cfi_def_cfa_offset 32
; RV64-NEXT: sd ra, 24(sp) ; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 16(sp) ; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s1, 8(sp) ; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s3, 0(sp) ; RV64-NEXT: sd s3, 0(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16 ; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: .cfi_offset s1, -24 ; RV64-NEXT: .cfi_offset s1, -24
; RV64-NEXT: .cfi_offset s3, -32 ; RV64-NEXT: .cfi_offset s3, -32
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s3, a0 ; RV64-NEXT: mv s3, a0
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s1, a0 ; RV64-NEXT: mv s1, a0
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s0, a0 ; RV64-NEXT: mv s0, a0
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: add a1, s3, s1 ; RV64-NEXT: add a1, s3, s1
; RV64-NEXT: add a0, s0, a0 ; RV64-NEXT: add a0, s0, a0
; RV64-NEXT: addw a0, a1, a0 ; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ld s3, 0(sp) ; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 8(sp) ; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 16(sp) ; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 24(sp) ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 32 ; RV64-NEXT: addi sp, sp, 32
; RV64-NEXT: ld ra, -8(s2) ; RV64-NEXT: ld ra, -8(s2)
; RV64-NEXT: addi s2, s2, -8 ; RV64-NEXT: addi s2, s2, -8
; RV64-NEXT: ret ; RV64-NEXT: ret
%res1 = call i32 @bar() %res1 = call i32 @bar()
%res2 = call i32 @bar() %res2 = call i32 @bar()
%res3 = call i32 @bar() %res3 = call i32 @bar()
%res4 = call i32 @bar() %res4 = call i32 @bar()
%res12 = add i32 %res1, %res2 %res12 = add i32 %res1, %res2
%res34 = add i32 %res3, %res4 %res34 = add i32 %res3, %res4
%res1234 = add i32 %res12, %res34 %res1234 = add i32 %res12, %res34
ret i32 %res1234 ret i32 %res1234
} }
define i32 @f5() shadowcallstack nounwind { define i32 @f5() shadowcallstack nounwind {
; RV32-LABEL: f5: ; RV32-LABEL: f5:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: sw ra, 0(s2) ; RV32-NEXT: sw ra, 0(s2)
; RV32-NEXT: addi s2, s2, 4 ; RV32-NEXT: addi s2, s2, 4
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: call bar ; RV32-NEXT: call bar@plt
; RV32-NEXT: lw ra, 12(sp) ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: lw ra, -4(s2) ; RV32-NEXT: lw ra, -4(s2)
; RV32-NEXT: addi s2, s2, -4 ; RV32-NEXT: addi s2, s2, -4
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: f5: ; RV64-LABEL: f5:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sd ra, 0(s2) ; RV64-NEXT: sd ra, 0(s2)
; RV64-NEXT: addi s2, s2, 8 ; RV64-NEXT: addi s2, s2, 8
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: sd ra, 8(sp) ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: call bar ; RV64-NEXT: call bar@plt
; RV64-NEXT: ld ra, 8(sp) ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ld ra, -8(s2) ; RV64-NEXT: ld ra, -8(s2)
; RV64-NEXT: addi s2, s2, -8 ; RV64-NEXT: addi s2, s2, -8
; RV64-NEXT: ret ; RV64-NEXT: ret
%res = call i32 @bar() %res = call i32 @bar()
%res1 = add i32 %res, 1 %res1 = add i32 %res, 1
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/RISCV/shifts.ll

Show All 32 Lines; RV64I-NEXT: ret
%1 = lshr i64 %a, %b %1 = lshr i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind { define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: lshr64_minsize: ; RV32I-LABEL: lshr64_minsize:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __lshrdi3 ; RV32I-NEXT: call __lshrdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: lshr64_minsize: ; RV64I-LABEL: lshr64_minsize:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = lshr i64 %a, %b %1 = lshr i64 %a, %b
Show All 26 Lines; RV64I-NEXT: ret
%1 = ashr i64 %a, %b %1 = ashr i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind { define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: ashr64_minsize: ; RV32I-LABEL: ashr64_minsize:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ashrdi3 ; RV32I-NEXT: call __ashrdi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: ashr64_minsize: ; RV64I-LABEL: ashr64_minsize:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1 ; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = ashr i64 %a, %b %1 = ashr i64 %a, %b
Show All 26 Lines; RV64I-NEXT: ret
%1 = shl i64 %a, %b %1 = shl i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind { define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: shl64_minsize: ; RV32I-LABEL: shl64_minsize:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ashldi3 ; RV32I-NEXT: call __ashldi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: shl64_minsize: ; RV64I-LABEL: shl64_minsize:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = shl i64 %a, %b %1 = shl i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i128 @lshr128(i128 %a, i128 %b) nounwind { define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128: ; RV32I-LABEL: lshr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1) ; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1) ; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp) ; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp) ; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp) ; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp) ; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __lshrti3 ; RV32I-NEXT: call __lshrti3@plt
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp) ; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp) ; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp) ; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: sw a1, 8(s0) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: lshr128: ; RV64I-LABEL: lshr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB6_2 ; RV64I-NEXT: bltz a3, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
Show All 12 Lines; RV64I-NEXT: ret
%1 = lshr i128 %a, %b %1 = lshr i128 %a, %b
ret i128 %1 ret i128 %1
} }
define i128 @ashr128(i128 %a, i128 %b) nounwind { define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128: ; RV32I-LABEL: ashr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1) ; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1) ; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp) ; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp) ; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp) ; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp) ; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashrti3 ; RV32I-NEXT: call __ashrti3@plt
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp) ; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp) ; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp) ; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: sw a1, 8(s0) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: ashr128: ; RV64I-LABEL: ashr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB7_2 ; RV64I-NEXT: bltz a3, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
Show All 12 Lines; RV64I-NEXT: ret
%1 = ashr i128 %a, %b %1 = ashr i128 %a, %b
ret i128 %1 ret i128 %1
} }
define i128 @shl128(i128 %a, i128 %b) nounwind { define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128: ; RV32I-LABEL: shl128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1) ; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1) ; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp) ; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp) ; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp) ; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp) ; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashlti3 ; RV32I-NEXT: call __ashlti3@plt
; RV32I-NEXT: lw a0, 36(sp) ; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp) ; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp) ; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp) ; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0) ; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: sw a1, 8(s0) ; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0) ; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0) ; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: shl128: ; RV64I-LABEL: shl128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB8_2 ; RV64I-NEXT: bltz a3, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
Show All 15 Lines

llvm/test/CodeGen/RISCV/shrinkwrap.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \ ; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR ; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
declare void @abort() declare void @abort()
define void @eliminate_restore(i32 %n) nounwind { define void @eliminate_restore(i32 %n) nounwind {
; RV32I-NOSW-LABEL: eliminate_restore: ; RV32I-NOSW-LABEL: eliminate_restore:
; RV32I-NOSW: # %bb.0: ; RV32I-NOSW: # %bb.0:
; RV32I-NOSW-NEXT: addi sp, sp, -16 ; RV32I-NOSW-NEXT: addi sp, sp, -16
; RV32I-NOSW-NEXT: sw ra, 12(sp) ; RV32I-NOSW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NOSW-NEXT: addi a1, zero, 32 ; RV32I-NOSW-NEXT: addi a1, zero, 32
; RV32I-NOSW-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-NOSW-NEXT: bgeu a1, a0, .LBB0_2
; RV32I-NOSW-NEXT: # %bb.1: # %if.end ; RV32I-NOSW-NEXT: # %bb.1: # %if.end
; RV32I-NOSW-NEXT: lw ra, 12(sp) ; RV32I-NOSW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NOSW-NEXT: addi sp, sp, 16 ; RV32I-NOSW-NEXT: addi sp, sp, 16
; RV32I-NOSW-NEXT: ret ; RV32I-NOSW-NEXT: ret
; RV32I-NOSW-NEXT: .LBB0_2: # %if.then ; RV32I-NOSW-NEXT: .LBB0_2: # %if.then
; RV32I-NOSW-NEXT: call abort ; RV32I-NOSW-NEXT: call abort@plt
; ;
; RV32I-SW-LABEL: eliminate_restore: ; RV32I-SW-LABEL: eliminate_restore:
; RV32I-SW: # %bb.0: ; RV32I-SW: # %bb.0:
; RV32I-SW-NEXT: addi a1, zero, 32 ; RV32I-SW-NEXT: addi a1, zero, 32
; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2
; RV32I-SW-NEXT: # %bb.1: # %if.end ; RV32I-SW-NEXT: # %bb.1: # %if.end
; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: ret
; RV32I-SW-NEXT: .LBB0_2: # %if.then ; RV32I-SW-NEXT: .LBB0_2: # %if.then
; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: sw ra, 12(sp) ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: call abort ; RV32I-SW-NEXT: call abort@plt
; ;
; RV32I-SW-SR-LABEL: eliminate_restore: ; RV32I-SW-SR-LABEL: eliminate_restore:
; RV32I-SW-SR: # %bb.0: ; RV32I-SW-SR: # %bb.0:
; RV32I-SW-SR-NEXT: addi a1, zero, 32 ; RV32I-SW-SR-NEXT: addi a1, zero, 32
; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2
; RV32I-SW-SR-NEXT: # %bb.1: # %if.end ; RV32I-SW-SR-NEXT: # %bb.1: # %if.end
; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: ret
; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then ; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then
; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 ; RV32I-SW-SR-NEXT: call t0, __riscv_save_0
; RV32I-SW-SR-NEXT: call abort ; RV32I-SW-SR-NEXT: call abort@plt
%cmp = icmp ule i32 %n, 32 %cmp = icmp ule i32 %n, 32
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
call void @abort() call void @abort()
unreachable unreachable
if.end: if.end:
ret void ret void
} }
declare void @notdead(i8*) declare void @notdead(i8*)
define void @conditional_alloca(i32 %n) nounwind { define void @conditional_alloca(i32 %n) nounwind {
; RV32I-NOSW-LABEL: conditional_alloca: ; RV32I-NOSW-LABEL: conditional_alloca:
; RV32I-NOSW: # %bb.0: ; RV32I-NOSW: # %bb.0:
; RV32I-NOSW-NEXT: addi sp, sp, -16 ; RV32I-NOSW-NEXT: addi sp, sp, -16
; RV32I-NOSW-NEXT: sw ra, 12(sp) ; RV32I-NOSW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NOSW-NEXT: sw s0, 8(sp) ; RV32I-NOSW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NOSW-NEXT: addi s0, sp, 16 ; RV32I-NOSW-NEXT: addi s0, sp, 16
; RV32I-NOSW-NEXT: addi a1, zero, 32 ; RV32I-NOSW-NEXT: addi a1, zero, 32
; RV32I-NOSW-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-NOSW-NEXT: bltu a1, a0, .LBB1_2
; RV32I-NOSW-NEXT: # %bb.1: # %if.then ; RV32I-NOSW-NEXT: # %bb.1: # %if.then
; RV32I-NOSW-NEXT: addi a0, a0, 15 ; RV32I-NOSW-NEXT: addi a0, a0, 15
; RV32I-NOSW-NEXT: andi a0, a0, -16 ; RV32I-NOSW-NEXT: andi a0, a0, -16
; RV32I-NOSW-NEXT: sub a0, sp, a0 ; RV32I-NOSW-NEXT: sub a0, sp, a0
; RV32I-NOSW-NEXT: mv sp, a0 ; RV32I-NOSW-NEXT: mv sp, a0
; RV32I-NOSW-NEXT: call notdead ; RV32I-NOSW-NEXT: call notdead@plt
; RV32I-NOSW-NEXT: .LBB1_2: # %if.end ; RV32I-NOSW-NEXT: .LBB1_2: # %if.end
; RV32I-NOSW-NEXT: addi sp, s0, -16 ; RV32I-NOSW-NEXT: addi sp, s0, -16
; RV32I-NOSW-NEXT: lw s0, 8(sp) ; RV32I-NOSW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NOSW-NEXT: lw ra, 12(sp) ; RV32I-NOSW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NOSW-NEXT: addi sp, sp, 16 ; RV32I-NOSW-NEXT: addi sp, sp, 16
; RV32I-NOSW-NEXT: ret ; RV32I-NOSW-NEXT: ret
; ;
; RV32I-SW-LABEL: conditional_alloca: ; RV32I-SW-LABEL: conditional_alloca:
; RV32I-SW: # %bb.0: ; RV32I-SW: # %bb.0:
; RV32I-SW-NEXT: addi a1, zero, 32 ; RV32I-SW-NEXT: addi a1, zero, 32
; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2
; RV32I-SW-NEXT: # %bb.1: # %if.then ; RV32I-SW-NEXT: # %bb.1: # %if.then
; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: addi sp, sp, -16
; RV32I-SW-NEXT: sw ra, 12(sp) ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: sw s0, 8(sp) ; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-SW-NEXT: addi s0, sp, 16 ; RV32I-SW-NEXT: addi s0, sp, 16
; RV32I-SW-NEXT: addi a0, a0, 15 ; RV32I-SW-NEXT: addi a0, a0, 15
; RV32I-SW-NEXT: andi a0, a0, -16 ; RV32I-SW-NEXT: andi a0, a0, -16
; RV32I-SW-NEXT: sub a0, sp, a0 ; RV32I-SW-NEXT: sub a0, sp, a0
; RV32I-SW-NEXT: mv sp, a0 ; RV32I-SW-NEXT: mv sp, a0
; RV32I-SW-NEXT: call notdead ; RV32I-SW-NEXT: call notdead@plt
; RV32I-SW-NEXT: addi sp, s0, -16 ; RV32I-SW-NEXT: addi sp, s0, -16
; RV32I-SW-NEXT: lw s0, 8(sp) ; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw ra, 12(sp) ; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: addi sp, sp, 16 ; RV32I-SW-NEXT: addi sp, sp, 16
; RV32I-SW-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NEXT: .LBB1_2: # %if.end
; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: ret
; ;
; RV32I-SW-SR-LABEL: conditional_alloca: ; RV32I-SW-SR-LABEL: conditional_alloca:
; RV32I-SW-SR: # %bb.0: ; RV32I-SW-SR: # %bb.0:
; RV32I-SW-SR-NEXT: addi a1, zero, 32 ; RV32I-SW-SR-NEXT: addi a1, zero, 32
; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2
; RV32I-SW-SR-NEXT: # %bb.1: # %if.then ; RV32I-SW-SR-NEXT: # %bb.1: # %if.then
; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 ; RV32I-SW-SR-NEXT: call t0, __riscv_save_1
; RV32I-SW-SR-NEXT: addi s0, sp, 16 ; RV32I-SW-SR-NEXT: addi s0, sp, 16
; RV32I-SW-SR-NEXT: addi a0, a0, 15 ; RV32I-SW-SR-NEXT: addi a0, a0, 15
; RV32I-SW-SR-NEXT: andi a0, a0, -16 ; RV32I-SW-SR-NEXT: andi a0, a0, -16
; RV32I-SW-SR-NEXT: sub a0, sp, a0 ; RV32I-SW-SR-NEXT: sub a0, sp, a0
; RV32I-SW-SR-NEXT: mv sp, a0 ; RV32I-SW-SR-NEXT: mv sp, a0
; RV32I-SW-SR-NEXT: call notdead ; RV32I-SW-SR-NEXT: call notdead@plt
; RV32I-SW-SR-NEXT: addi sp, s0, -16 ; RV32I-SW-SR-NEXT: addi sp, s0, -16
; RV32I-SW-SR-NEXT: tail __riscv_restore_1 ; RV32I-SW-SR-NEXT: tail __riscv_restore_1
; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end ; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end
; RV32I-SW-SR-NEXT: ret ; RV32I-SW-SR-NEXT: ret
%cmp = icmp ule i32 %n, 32 %cmp = icmp ule i32 %n, 32
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
%addr = alloca i8, i32 %n %addr = alloca i8, i32 %n
call void @notdead(i8* %addr) call void @notdead(i8* %addr)
br label %if.end br label %if.end
if.end: if.end:
ret void ret void
} }

llvm/test/CodeGen/RISCV/split-sp-adjust.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; The stack size is 2048 and the SP adjustment will be split. ; The stack size is 2048 and the SP adjustment will be split.
define i32 @SplitSP() nounwind { define i32 @SplitSP() nounwind {
; RV32I-LABEL: SplitSP: ; RV32I-LABEL: SplitSP:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a0, sp, 16 ; RV32I-NEXT: addi a0, sp, 16
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: lw ra, 2028(sp) ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032 ; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%xx = alloca [2028 x i8], align 1 %xx = alloca [2028 x i8], align 1
%0 = getelementptr inbounds [2028 x i8], [2028 x i8]* %xx, i32 0, i32 0 %0 = getelementptr inbounds [2028 x i8], [2028 x i8]* %xx, i32 0, i32 0
%call = call i32 @foo(i8* nonnull %0) %call = call i32 @foo(i8* nonnull %0)
ret i32 0 ret i32 0
} }
; The stack size is 2032 and the SP adjustment will not be split. ; The stack size is 2032 and the SP adjustment will not be split.
define i32 @NoSplitSP() nounwind { define i32 @NoSplitSP() nounwind {
; RV32I-LABEL: NoSplitSP: ; RV32I-LABEL: NoSplitSP:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a0, sp, 4 ; RV32I-NEXT: addi a0, sp, 4
; RV32I-NEXT: call foo ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 2028(sp) ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032 ; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret ; RV32I-NEXT: ret
entry: entry:
%xx = alloca [2024 x i8], align 1 %xx = alloca [2024 x i8], align 1
%0 = getelementptr inbounds [2024 x i8], [2024 x i8]* %xx, i32 0, i32 0 %0 = getelementptr inbounds [2024 x i8], [2024 x i8]* %xx, i32 0, i32 0
%call = call i32 @foo(i8* nonnull %0) %call = call i32 @foo(i8* nonnull %0)
ret i32 0 ret i32 0
} }
declare i32 @foo(i8*) declare i32 @foo(i8*)

llvm/test/CodeGen/RISCV/srem-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define i32 @fold_srem_positive_odd(i32 %x) nounwind { define i32 @fold_srem_positive_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_positive_odd: ; RV32I-LABEL: fold_srem_positive_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_positive_odd: ; RV32IM-LABEL: fold_srem_positive_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 706409 ; RV32IM-NEXT: lui a1, 706409
; RV32IM-NEXT: addi a1, a1, 389 ; RV32IM-NEXT: addi a1, a1, 389
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: add a1, a1, a0 ; RV32IM-NEXT: add a1, a1, a0
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 6 ; RV32IM-NEXT: srai a1, a1, 6
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_positive_odd: ; RV64I-LABEL: fold_srem_positive_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_positive_odd: ; RV64IM-LABEL: fold_srem_positive_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 1045903 ; RV64IM-NEXT: lui a1, 1045903
; RV64IM-NEXT: addiw a1, a1, -733 ; RV64IM-NEXT: addiw a1, a1, -733
Show All 16 Lines; RV64IM-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_positive_even(i32 %x) nounwind { define i32 @fold_srem_positive_even(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_positive_even: ; RV32I-LABEL: fold_srem_positive_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 1060 ; RV32I-NEXT: addi a1, zero, 1060
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_positive_even: ; RV32IM-LABEL: fold_srem_positive_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 253241 ; RV32IM-NEXT: lui a1, 253241
; RV32IM-NEXT: addi a1, a1, -15 ; RV32IM-NEXT: addi a1, a1, -15
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 1060 ; RV32IM-NEXT: addi a2, zero, 1060
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_positive_even: ; RV64I-LABEL: fold_srem_positive_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, 1060 ; RV64I-NEXT: addi a1, zero, 1060
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_positive_even: ; RV64IM-LABEL: fold_srem_positive_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 506482 ; RV64IM-NEXT: lui a1, 506482
; RV64IM-NEXT: addiw a1, a1, -31 ; RV64IM-NEXT: addiw a1, a1, -31
Show All 13 Lines; RV64IM-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_negative_odd(i32 %x) nounwind { define i32 @fold_srem_negative_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_negative_odd: ; RV32I-LABEL: fold_srem_negative_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, -723 ; RV32I-NEXT: addi a1, zero, -723
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_negative_odd: ; RV32IM-LABEL: fold_srem_negative_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 677296 ; RV32IM-NEXT: lui a1, 677296
; RV32IM-NEXT: addi a1, a1, -91 ; RV32IM-NEXT: addi a1, a1, -91
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, -723 ; RV32IM-NEXT: addi a2, zero, -723
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_negative_odd: ; RV64I-LABEL: fold_srem_negative_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, -723 ; RV64I-NEXT: addi a1, zero, -723
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_negative_odd: ; RV64IM-LABEL: fold_srem_negative_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 4781 ; RV64IM-NEXT: lui a1, 4781
; RV64IM-NEXT: addiw a1, a1, 2045 ; RV64IM-NEXT: addiw a1, a1, 2045
Show All 16 Lines; RV64IM-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_negative_even(i32 %x) nounwind { define i32 @fold_srem_negative_even(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_negative_even: ; RV32I-LABEL: fold_srem_negative_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 1048570 ; RV32I-NEXT: lui a1, 1048570
; RV32I-NEXT: addi a1, a1, 1595 ; RV32I-NEXT: addi a1, a1, 1595
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_negative_even: ; RV32IM-LABEL: fold_srem_negative_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 1036895 ; RV32IM-NEXT: lui a1, 1036895
; RV32IM-NEXT: addi a1, a1, 999 ; RV32IM-NEXT: addi a1, a1, 999
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: lui a2, 1048570 ; RV32IM-NEXT: lui a2, 1048570
; RV32IM-NEXT: addi a2, a2, 1595 ; RV32IM-NEXT: addi a2, a2, 1595
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_negative_even: ; RV64I-LABEL: fold_srem_negative_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: lui a1, 1048570 ; RV64I-NEXT: lui a1, 1048570
; RV64I-NEXT: addiw a1, a1, 1595 ; RV64I-NEXT: addiw a1, a1, 1595
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_negative_even: ; RV64IM-LABEL: fold_srem_negative_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 1036895 ; RV64IM-NEXT: lui a1, 1036895
; RV64IM-NEXT: addiw a1, a1, 999 ; RV64IM-NEXT: addiw a1, a1, 999
Show All 17 Lines
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define i32 @combine_srem_sdiv(i32 %x) nounwind { define i32 @combine_srem_sdiv(i32 %x) nounwind {
; RV32I-LABEL: combine_srem_sdiv: ; RV32I-LABEL: combine_srem_sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: add a0, s1, a0
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM-LABEL: combine_srem_sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 706409 ; RV32IM-NEXT: lui a1, 706409
; RV32IM-NEXT: addi a1, a1, 389 ; RV32IM-NEXT: addi a1, a1, 389
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: add a1, a1, a0 ; RV32IM-NEXT: add a1, a1, a0
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 6 ; RV32IM-NEXT: srai a1, a1, 6
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a2, a1, a2 ; RV32IM-NEXT: mul a2, a1, a2
; RV32IM-NEXT: sub a0, a0, a2 ; RV32IM-NEXT: sub a0, a0, a2
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_srem_sdiv: ; RV64I-LABEL: combine_srem_sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w s0, a0 ; RV64I-NEXT: sext.w s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: addw a0, s1, a0 ; RV64I-NEXT: addw a0, s1, a0
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM-LABEL: combine_srem_sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0 ; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: lui a2, 1045903 ; RV64IM-NEXT: lui a2, 1045903
; RV64IM-NEXT: addiw a2, a2, -733 ; RV64IM-NEXT: addiw a2, a2, -733
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
ret i32 %1 ret i32 %1
} }
; Don't fold i64 srem ; Don't fold i64 srem
define i64 @dont_fold_srem_i64(i64 %x) nounwind { define i64 @dont_fold_srem_i64(i64 %x) nounwind {
; RV32I-LABEL: dont_fold_srem_i64: ; RV32I-LABEL: dont_fold_srem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 98 ; RV32I-NEXT: addi a2, zero, 98
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM-LABEL: dont_fold_srem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: addi a2, zero, 98 ; RV32IM-NEXT: addi a2, zero, 98
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i64: ; RV64I-LABEL: dont_fold_srem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM-LABEL: dont_fold_srem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 2675 ; RV64IM-NEXT: lui a1, 2675
; RV64IM-NEXT: addiw a1, a1, -251 ; RV64IM-NEXT: addiw a1, a1, -251
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
Show All 16 Lines

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s ; RUN: | FileCheck -check-prefix=RV64IM %s
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind { define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_srem_vec_1: ; RV32I-LABEL: fold_srem_vec_1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s3, 8(a1)
; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, -124 ; RV32I-NEXT: addi a1, zero, -124
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 98 ; RV32I-NEXT: addi a1, zero, 98
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, -1003 ; RV32I-NEXT: addi a1, zero, -1003
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s1)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s0, 4(s1)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s5, 2(s1)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_1: ; RV32IM-LABEL: fold_srem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a6, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
Show All 40 Lines
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_1: ; RV64I-LABEL: fold_srem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s3, 16(a1)
; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, -124 ; RV64I-NEXT: addi a1, zero, -124
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, -1003 ; RV64I-NEXT: addi a1, zero, -1003
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s1)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s0, 4(s1)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s5, 2(s1)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_1: ; RV64IM-LABEL: fold_srem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a6, 24(a1)
; RV64IM-NEXT: lh a3, 16(a1) ; RV64IM-NEXT: lh a3, 16(a1)
; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a4, 8(a1)
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003> %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind { define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_srem_vec_2: ; RV32I-LABEL: fold_srem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s3, 8(a1)
; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s1)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s0, 4(s1)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s5, 2(s1)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_2: ; RV32IM-LABEL: fold_srem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a6, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
Show All 33 Lines
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh t0, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_2: ; RV64I-LABEL: fold_srem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s3, 16(a1)
; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s1)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s0, 4(s1)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s5, 2(s1)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_2: ; RV64IM-LABEL: fold_srem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a6, 24(a1)
; RV64IM-NEXT: lh a7, 16(a1) ; RV64IM-NEXT: lh a7, 16(a1)
; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a4, 8(a1)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind { define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_srem_sdiv: ; RV32I-LABEL: combine_srem_sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh s2, 0(a1) ; RV32I-NEXT: lh s2, 0(a1)
; RV32I-NEXT: lh s3, 4(a1) ; RV32I-NEXT: lh s3, 4(a1)
; RV32I-NEXT: lh s4, 8(a1) ; RV32I-NEXT: lh s4, 8(a1)
; RV32I-NEXT: lh s1, 12(a1) ; RV32I-NEXT: lh s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add a0, s8, a0
; RV32I-NEXT: add a1, s7, s1 ; RV32I-NEXT: add a1, s7, s1
; RV32I-NEXT: add a2, s6, s4 ; RV32I-NEXT: add a2, s6, s4
; RV32I-NEXT: add a3, s5, s9 ; RV32I-NEXT: add a3, s5, s9
; RV32I-NEXT: sh a3, 6(s0) ; RV32I-NEXT: sh a3, 6(s0)
; RV32I-NEXT: sh a2, 4(s0) ; RV32I-NEXT: sh a2, 4(s0)
; RV32I-NEXT: sh a1, 2(s0) ; RV32I-NEXT: sh a1, 2(s0)
; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM-LABEL: combine_srem_sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 0(a1) ; RV32IM-NEXT: lh a6, 0(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
Show All 37 Lines
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a4, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_srem_sdiv: ; RV64I-LABEL: combine_srem_sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 80(sp) ; RV64I-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 72(sp) ; RV64I-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 64(sp) ; RV64I-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 56(sp) ; RV64I-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 48(sp) ; RV64I-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 40(sp) ; RV64I-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 32(sp) ; RV64I-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 24(sp) ; RV64I-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 16(sp) ; RV64I-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh s2, 0(a1) ; RV64I-NEXT: lh s2, 0(a1)
; RV64I-NEXT: lh s3, 8(a1) ; RV64I-NEXT: lh s3, 8(a1)
; RV64I-NEXT: lh s4, 16(a1) ; RV64I-NEXT: lh s4, 16(a1)
; RV64I-NEXT: lh s1, 24(a1) ; RV64I-NEXT: lh s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: add a0, s8, a0 ; RV64I-NEXT: add a0, s8, a0
; RV64I-NEXT: add a1, s7, s1 ; RV64I-NEXT: add a1, s7, s1
; RV64I-NEXT: add a2, s6, s4 ; RV64I-NEXT: add a2, s6, s4
; RV64I-NEXT: add a3, s5, s9 ; RV64I-NEXT: add a3, s5, s9
; RV64I-NEXT: sh a3, 6(s0) ; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0) ; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0) ; RV64I-NEXT: sh a1, 2(s0)
; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 16(sp) ; RV64I-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 24(sp) ; RV64I-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 32(sp) ; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 40(sp) ; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 48(sp) ; RV64I-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 56(sp) ; RV64I-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 64(sp) ; RV64I-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 72(sp) ; RV64I-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 80(sp) ; RV64I-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM-LABEL: combine_srem_sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 0(a1) ; RV64IM-NEXT: lh a6, 0(a1)
; RV64IM-NEXT: lh a7, 8(a1) ; RV64IM-NEXT: lh a7, 8(a1)
; RV64IM-NEXT: lh a4, 16(a1) ; RV64IM-NEXT: lh a4, 16(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_power_of_two: ; RV32I-LABEL: dont_fold_srem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: lh a0, 12(a1) ; RV32I-NEXT: lh a0, 12(a1)
; RV32I-NEXT: lh a3, 8(a1) ; RV32I-NEXT: lh a3, 8(a1)
; RV32I-NEXT: lh a1, 4(a1) ; RV32I-NEXT: lh a1, 4(a1)
; RV32I-NEXT: srli a4, a2, 26 ; RV32I-NEXT: srli a4, a2, 26
; RV32I-NEXT: add a4, a2, a4 ; RV32I-NEXT: add a4, a2, a4
; RV32I-NEXT: lui a6, 16 ; RV32I-NEXT: lui a6, 16
; RV32I-NEXT: addi a5, a6, -64 ; RV32I-NEXT: addi a5, a6, -64
; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: sub s2, a2, a4 ; RV32I-NEXT: sub s2, a2, a4
; RV32I-NEXT: srli a2, a1, 27 ; RV32I-NEXT: srli a2, a1, 27
; RV32I-NEXT: add a2, a1, a2 ; RV32I-NEXT: add a2, a1, a2
; RV32I-NEXT: addi a4, a6, -32 ; RV32I-NEXT: addi a4, a6, -32
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: sub s3, a1, a2 ; RV32I-NEXT: sub s3, a1, a2
; RV32I-NEXT: srli a1, a3, 29 ; RV32I-NEXT: srli a1, a3, 29
; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: addi a2, a6, -8 ; RV32I-NEXT: addi a2, a6, -8
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub s1, a3, a1 ; RV32I-NEXT: sub s1, a3, a1
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: sh s2, 0(s0) ; RV32I-NEXT: sh s2, 0(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_power_of_two: ; RV32IM-LABEL: dont_fold_srem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 8(a1) ; RV32IM-NEXT: lh a6, 8(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
Show All 28 Lines
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a1, 0(a0)
; RV32IM-NEXT: sh a7, 6(a0) ; RV32IM-NEXT: sh a7, 6(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_power_of_two: ; RV64I-LABEL: dont_fold_srem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: lh a0, 24(a1) ; RV64I-NEXT: lh a0, 24(a1)
; RV64I-NEXT: lh a3, 16(a1) ; RV64I-NEXT: lh a3, 16(a1)
; RV64I-NEXT: lh a1, 8(a1) ; RV64I-NEXT: lh a1, 8(a1)
; RV64I-NEXT: srli a4, a2, 58 ; RV64I-NEXT: srli a4, a2, 58
; RV64I-NEXT: add a4, a2, a4 ; RV64I-NEXT: add a4, a2, a4
; RV64I-NEXT: lui a6, 16 ; RV64I-NEXT: lui a6, 16
; RV64I-NEXT: addiw a5, a6, -64 ; RV64I-NEXT: addiw a5, a6, -64
; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: and a4, a4, a5
; RV64I-NEXT: sub s2, a2, a4 ; RV64I-NEXT: sub s2, a2, a4
; RV64I-NEXT: srli a2, a1, 59 ; RV64I-NEXT: srli a2, a1, 59
; RV64I-NEXT: add a2, a1, a2 ; RV64I-NEXT: add a2, a1, a2
; RV64I-NEXT: addiw a4, a6, -32 ; RV64I-NEXT: addiw a4, a6, -32
; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: sub s3, a1, a2 ; RV64I-NEXT: sub s3, a1, a2
; RV64I-NEXT: srli a1, a3, 61 ; RV64I-NEXT: srli a1, a3, 61
; RV64I-NEXT: add a1, a3, a1 ; RV64I-NEXT: add a1, a3, a1
; RV64I-NEXT: addiw a2, a6, -8 ; RV64I-NEXT: addiw a2, a6, -8
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sub s1, a3, a1 ; RV64I-NEXT: sub s1, a3, a1
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: sh s2, 0(s0) ; RV64I-NEXT: sh s2, 0(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_power_of_two: ; RV64IM-LABEL: dont_fold_srem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 16(a1) ; RV64IM-NEXT: lh a6, 16(a1)
; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a3, 8(a1)
; RV64IM-NEXT: lh a4, 0(a1) ; RV64IM-NEXT: lh a4, 0(a1)
Show All 39 Lines; RV64IM-NEXT: ret
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_one: ; RV32I-LABEL: dont_fold_srem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s1, 8(a1) ; RV32I-NEXT: lh s1, 8(a1)
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 654 ; RV32I-NEXT: addi a1, zero, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a1, zero, 23 ; RV32I-NEXT: addi a1, zero, 23
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s0)
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_one: ; RV32IM-LABEL: dont_fold_srem_one:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a2, 12(a1) ; RV32IM-NEXT: lh a2, 12(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lh a1, 8(a1)
Show All 31 Lines
; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a1, 4(a0) ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_one: ; RV64I-LABEL: dont_fold_srem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s1, 16(a1) ; RV64I-NEXT: lh s1, 16(a1)
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s0)
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_one: ; RV64IM-LABEL: dont_fold_srem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 24(a1) ; RV64IM-NEXT: lh a2, 24(a1)
; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a3, 8(a1)
; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lh a1, 16(a1)
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^15. ; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i16_smax: ; RV32I-LABEL: dont_fold_urem_i16_smax:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh a0, 8(a1) ; RV32I-NEXT: lh a0, 8(a1)
; RV32I-NEXT: srli a1, a2, 17 ; RV32I-NEXT: srli a1, a2, 17
; RV32I-NEXT: add a1, a2, a1 ; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: lui a3, 8 ; RV32I-NEXT: lui a3, 8
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: sub s3, a2, a1 ; RV32I-NEXT: sub s3, a2, a1
; RV32I-NEXT: addi a1, zero, 23 ; RV32I-NEXT: addi a1, zero, 23
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s0)
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i16_smax: ; RV32IM-LABEL: dont_fold_urem_i16_smax:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a2, 4(a1) ; RV32IM-NEXT: lh a2, 4(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a1, 12(a1) ; RV32IM-NEXT: lh a1, 12(a1)
Show All 26 Lines
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: sh a1, 6(a0) ; RV32IM-NEXT: sh a1, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i16_smax: ; RV64I-LABEL: dont_fold_urem_i16_smax:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh a0, 16(a1) ; RV64I-NEXT: lh a0, 16(a1)
; RV64I-NEXT: srli a1, a2, 49 ; RV64I-NEXT: srli a1, a2, 49
; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: lui a3, 8 ; RV64I-NEXT: lui a3, 8
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: sub s3, a2, a1 ; RV64I-NEXT: sub s3, a2, a1
; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s0)
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i16_smax: ; RV64IM-LABEL: dont_fold_urem_i16_smax:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 8(a1) ; RV64IM-NEXT: lh a2, 8(a1)
; RV64IM-NEXT: lh a3, 24(a1) ; RV64IM-NEXT: lh a3, 24(a1)
; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lh a1, 16(a1)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 srem. ; Don't fold i64 srem.
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_i64: ; RV32I-LABEL: dont_fold_srem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s2, 24(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s3, 28(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s4, 16(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s5, 20(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s6, 8(a1)
; RV32I-NEXT: lw s1, 12(a1) ; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: addi a2, zero, 654 ; RV32I-NEXT: addi a2, zero, 654
; RV32I-NEXT: mv a0, s6 ; RV32I-NEXT: mv a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv s9, a1 ; RV32I-NEXT: mv s9, a1
; RV32I-NEXT: addi a2, zero, 23 ; RV32I-NEXT: addi a2, zero, 23
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a2, a0, 1327 ; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: sw a1, 28(s0) ; RV32I-NEXT: sw a1, 28(s0)
; RV32I-NEXT: sw a0, 24(s0) ; RV32I-NEXT: sw a0, 24(s0)
; RV32I-NEXT: sw s1, 20(s0) ; RV32I-NEXT: sw s1, 20(s0)
; RV32I-NEXT: sw s4, 16(s0) ; RV32I-NEXT: sw s4, 16(s0)
; RV32I-NEXT: sw s9, 12(s0) ; RV32I-NEXT: sw s9, 12(s0)
; RV32I-NEXT: sw s6, 8(s0) ; RV32I-NEXT: sw s6, 8(s0)
; RV32I-NEXT: sw s8, 4(s0) ; RV32I-NEXT: sw s8, 4(s0)
; RV32I-NEXT: sw s7, 0(s0) ; RV32I-NEXT: sw s7, 0(s0)
; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM-LABEL: dont_fold_srem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: sw ra, 44(sp) ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 40(sp) ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 36(sp) ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 32(sp) ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s3, 28(sp) ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s4, 24(sp) ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s5, 20(sp) ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s6, 16(sp) ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s9, 4(sp) ; RV32IM-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s2, 24(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s3, 28(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s4, 16(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s5, 20(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s6, 8(a1)
; RV32IM-NEXT: lw s1, 12(a1) ; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0 ; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: addi a2, zero, 1 ; RV32IM-NEXT: addi a2, zero, 1
; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: addi a2, zero, 654 ; RV32IM-NEXT: addi a2, zero, 654
; RV32IM-NEXT: mv a0, s6 ; RV32IM-NEXT: mv a0, s6
; RV32IM-NEXT: mv a1, s1 ; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s6, a0 ; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: mv s9, a1 ; RV32IM-NEXT: mv s9, a1
; RV32IM-NEXT: addi a2, zero, 23 ; RV32IM-NEXT: addi a2, zero, 23
; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s1, a1 ; RV32IM-NEXT: mv s1, a1
; RV32IM-NEXT: lui a0, 1 ; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: addi a2, a0, 1327 ; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: sw a1, 28(s0) ; RV32IM-NEXT: sw a1, 28(s0)
; RV32IM-NEXT: sw a0, 24(s0) ; RV32IM-NEXT: sw a0, 24(s0)
; RV32IM-NEXT: sw s1, 20(s0) ; RV32IM-NEXT: sw s1, 20(s0)
; RV32IM-NEXT: sw s4, 16(s0) ; RV32IM-NEXT: sw s4, 16(s0)
; RV32IM-NEXT: sw s9, 12(s0) ; RV32IM-NEXT: sw s9, 12(s0)
; RV32IM-NEXT: sw s6, 8(s0) ; RV32IM-NEXT: sw s6, 8(s0)
; RV32IM-NEXT: sw s8, 4(s0) ; RV32IM-NEXT: sw s8, 4(s0)
; RV32IM-NEXT: sw s7, 0(s0) ; RV32IM-NEXT: sw s7, 0(s0)
; RV32IM-NEXT: lw s9, 4(sp) ; RV32IM-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s8, 8(sp) ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s7, 12(sp) ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s6, 16(sp) ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s5, 20(sp) ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s4, 24(sp) ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s3, 28(sp) ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 32(sp) ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw ra, 44(sp) ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i64: ; RV64I-LABEL: dont_fold_srem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s2, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sd zero, 0(s0) ; RV64I-NEXT: sd zero, 0(s0)
; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s0)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s0)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM-LABEL: dont_fold_srem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 24(a1) ; RV64IM-NEXT: ld a2, 24(a1)
; RV64IM-NEXT: ld a3, 8(a1) ; RV64IM-NEXT: ld a3, 8(a1)
; RV64IM-NEXT: ld a1, 16(a1) ; RV64IM-NEXT: ld a1, 16(a1)
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
declare void @callee(i8*, i32*) declare void @callee(i8*, i32*)
define void @caller(i32 %n) { define void @caller(i32 %n) {
; RV32I-LABEL: caller: ; RV32I-LABEL: caller:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -128 ; RV32I-NEXT: addi sp, sp, -128
; RV32I-NEXT: .cfi_def_cfa_offset 128 ; RV32I-NEXT: .cfi_def_cfa_offset 128
; RV32I-NEXT: sw ra, 124(sp) ; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 120(sp) ; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 116(sp) ; RV32I-NEXT: sw s1, 116(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4 ; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8 ; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12 ; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: addi s0, sp, 128 ; RV32I-NEXT: addi s0, sp, 128
; RV32I-NEXT: .cfi_def_cfa s0, 0 ; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -64 ; RV32I-NEXT: andi sp, sp, -64
; RV32I-NEXT: mv s1, sp ; RV32I-NEXT: mv s1, sp
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi a1, s1, 64 ; RV32I-NEXT: addi a1, s1, 64
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -128 ; RV32I-NEXT: addi sp, s0, -128
; RV32I-NEXT: lw s1, 116(sp) ; RV32I-NEXT: lw s1, 116(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 120(sp) ; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 124(sp) ; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: addi sp, sp, 128
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller: ; RV64I-LABEL: caller:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -128 ; RV64I-NEXT: addi sp, sp, -128
; RV64I-NEXT: .cfi_def_cfa_offset 128 ; RV64I-NEXT: .cfi_def_cfa_offset 128
; RV64I-NEXT: sd ra, 120(sp) ; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) ; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 104(sp) ; RV64I-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8 ; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16 ; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24 ; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: addi s0, sp, 128 ; RV64I-NEXT: addi s0, sp, 128
; RV64I-NEXT: .cfi_def_cfa s0, 0 ; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -64 ; RV64I-NEXT: andi sp, sp, -64
; RV64I-NEXT: mv s1, sp ; RV64I-NEXT: mv s1, sp
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, 15 ; RV64I-NEXT: addi a0, a0, 15
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: slli a1, a1, 33
; RV64I-NEXT: addi a1, a1, -16 ; RV64I-NEXT: addi a1, a1, -16
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: sub a0, sp, a0 ; RV64I-NEXT: sub a0, sp, a0
; RV64I-NEXT: mv sp, a0 ; RV64I-NEXT: mv sp, a0
; RV64I-NEXT: addi a1, s1, 64 ; RV64I-NEXT: addi a1, s1, 64
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -128 ; RV64I-NEXT: addi sp, s0, -128
; RV64I-NEXT: ld s1, 104(sp) ; RV64I-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 112(sp) ; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) ; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128 ; RV64I-NEXT: addi sp, sp, 128
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
%2 = alloca i32, align 64 %2 = alloca i32, align 64
call void @callee(i8* %1, i32 *%2) call void @callee(i8* %1, i32 *%2)
ret void ret void
} }

llvm/test/CodeGen/RISCV/stack-realignment.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
declare void @callee(i8*) declare void @callee(i8*)
define void @caller32() nounwind { define void @caller32() nounwind {
; RV32I-LABEL: caller32: ; RV32I-LABEL: caller32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64 ; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp) ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 64 ; RV32I-NEXT: addi s0, sp, 64
; RV32I-NEXT: andi sp, sp, -32 ; RV32I-NEXT: andi sp, sp, -32
; RV32I-NEXT: addi a0, sp, 32 ; RV32I-NEXT: addi a0, sp, 32
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -64 ; RV32I-NEXT: addi sp, s0, -64
; RV32I-NEXT: lw s0, 56(sp) ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64 ; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller32: ; RV64I-LABEL: caller32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 64 ; RV64I-NEXT: addi s0, sp, 64
; RV64I-NEXT: andi sp, sp, -32 ; RV64I-NEXT: andi sp, sp, -32
; RV64I-NEXT: addi a0, sp, 32 ; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -64 ; RV64I-NEXT: addi sp, s0, -64
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 32 %1 = alloca i8, align 32
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign32() nounwind "no-realign-stack" { define void @caller_no_realign32() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign32: ; RV32I-LABEL: caller_no_realign32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign32: ; RV64I-LABEL: caller_no_realign32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 32 %1 = alloca i8, align 32
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller64() nounwind { define void @caller64() nounwind {
; RV32I-LABEL: caller64: ; RV32I-LABEL: caller64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -128 ; RV32I-NEXT: addi sp, sp, -128
; RV32I-NEXT: sw ra, 124(sp) ; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 120(sp) ; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 128 ; RV32I-NEXT: addi s0, sp, 128
; RV32I-NEXT: andi sp, sp, -64 ; RV32I-NEXT: andi sp, sp, -64
; RV32I-NEXT: addi a0, sp, 64 ; RV32I-NEXT: addi a0, sp, 64
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -128 ; RV32I-NEXT: addi sp, s0, -128
; RV32I-NEXT: lw s0, 120(sp) ; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 124(sp) ; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 128 ; RV32I-NEXT: addi sp, sp, 128
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller64: ; RV64I-LABEL: caller64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -128 ; RV64I-NEXT: addi sp, sp, -128
; RV64I-NEXT: sd ra, 120(sp) ; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) ; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 128 ; RV64I-NEXT: addi s0, sp, 128
; RV64I-NEXT: andi sp, sp, -64 ; RV64I-NEXT: andi sp, sp, -64
; RV64I-NEXT: addi a0, sp, 64 ; RV64I-NEXT: addi a0, sp, 64
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -128 ; RV64I-NEXT: addi sp, s0, -128
; RV64I-NEXT: ld s0, 112(sp) ; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) ; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128 ; RV64I-NEXT: addi sp, sp, 128
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 64 %1 = alloca i8, align 64
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign64() nounwind "no-realign-stack" { define void @caller_no_realign64() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign64: ; RV32I-LABEL: caller_no_realign64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign64: ; RV64I-LABEL: caller_no_realign64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 64 %1 = alloca i8, align 64
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller128() nounwind { define void @caller128() nounwind {
; RV32I-LABEL: caller128: ; RV32I-LABEL: caller128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -256 ; RV32I-NEXT: addi sp, sp, -256
; RV32I-NEXT: sw ra, 252(sp) ; RV32I-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 248(sp) ; RV32I-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 256 ; RV32I-NEXT: addi s0, sp, 256
; RV32I-NEXT: andi sp, sp, -128 ; RV32I-NEXT: andi sp, sp, -128
; RV32I-NEXT: addi a0, sp, 128 ; RV32I-NEXT: addi a0, sp, 128
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -256 ; RV32I-NEXT: addi sp, s0, -256
; RV32I-NEXT: lw s0, 248(sp) ; RV32I-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 252(sp) ; RV32I-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 256 ; RV32I-NEXT: addi sp, sp, 256
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller128: ; RV64I-LABEL: caller128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -256 ; RV64I-NEXT: addi sp, sp, -256
; RV64I-NEXT: sd ra, 248(sp) ; RV64I-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 240(sp) ; RV64I-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 256 ; RV64I-NEXT: addi s0, sp, 256
; RV64I-NEXT: andi sp, sp, -128 ; RV64I-NEXT: andi sp, sp, -128
; RV64I-NEXT: addi a0, sp, 128 ; RV64I-NEXT: addi a0, sp, 128
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -256 ; RV64I-NEXT: addi sp, s0, -256
; RV64I-NEXT: ld s0, 240(sp) ; RV64I-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 248(sp) ; RV64I-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 256 ; RV64I-NEXT: addi sp, sp, 256
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 128 %1 = alloca i8, align 128
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign128() nounwind "no-realign-stack" { define void @caller_no_realign128() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign128: ; RV32I-LABEL: caller_no_realign128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign128: ; RV64I-LABEL: caller_no_realign128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 128 %1 = alloca i8, align 128
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller256() nounwind { define void @caller256() nounwind {
; RV32I-LABEL: caller256: ; RV32I-LABEL: caller256:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -512 ; RV32I-NEXT: addi sp, sp, -512
; RV32I-NEXT: sw ra, 508(sp) ; RV32I-NEXT: sw ra, 508(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 504(sp) ; RV32I-NEXT: sw s0, 504(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 512 ; RV32I-NEXT: addi s0, sp, 512
; RV32I-NEXT: andi sp, sp, -256 ; RV32I-NEXT: andi sp, sp, -256
; RV32I-NEXT: addi a0, sp, 256 ; RV32I-NEXT: addi a0, sp, 256
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -512 ; RV32I-NEXT: addi sp, s0, -512
; RV32I-NEXT: lw s0, 504(sp) ; RV32I-NEXT: lw s0, 504(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 508(sp) ; RV32I-NEXT: lw ra, 508(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 512 ; RV32I-NEXT: addi sp, sp, 512
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller256: ; RV64I-LABEL: caller256:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -512 ; RV64I-NEXT: addi sp, sp, -512
; RV64I-NEXT: sd ra, 504(sp) ; RV64I-NEXT: sd ra, 504(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 496(sp) ; RV64I-NEXT: sd s0, 496(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 512 ; RV64I-NEXT: addi s0, sp, 512
; RV64I-NEXT: andi sp, sp, -256 ; RV64I-NEXT: andi sp, sp, -256
; RV64I-NEXT: addi a0, sp, 256 ; RV64I-NEXT: addi a0, sp, 256
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -512 ; RV64I-NEXT: addi sp, s0, -512
; RV64I-NEXT: ld s0, 496(sp) ; RV64I-NEXT: ld s0, 496(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 504(sp) ; RV64I-NEXT: ld ra, 504(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 512 ; RV64I-NEXT: addi sp, sp, 512
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 256 %1 = alloca i8, align 256
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign256() nounwind "no-realign-stack" { define void @caller_no_realign256() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign256: ; RV32I-LABEL: caller_no_realign256:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign256: ; RV64I-LABEL: caller_no_realign256:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 256 %1 = alloca i8, align 256
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller512() nounwind { define void @caller512() nounwind {
; RV32I-LABEL: caller512: ; RV32I-LABEL: caller512:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -1536 ; RV32I-NEXT: addi sp, sp, -1536
; RV32I-NEXT: sw ra, 1532(sp) ; RV32I-NEXT: sw ra, 1532(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 1528(sp) ; RV32I-NEXT: sw s0, 1528(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 1536 ; RV32I-NEXT: addi s0, sp, 1536
; RV32I-NEXT: andi sp, sp, -512 ; RV32I-NEXT: andi sp, sp, -512
; RV32I-NEXT: addi a0, sp, 1024 ; RV32I-NEXT: addi a0, sp, 1024
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: addi sp, s0, -1536 ; RV32I-NEXT: addi sp, s0, -1536
; RV32I-NEXT: lw s0, 1528(sp) ; RV32I-NEXT: lw s0, 1528(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 1532(sp) ; RV32I-NEXT: lw ra, 1532(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 1536 ; RV32I-NEXT: addi sp, sp, 1536
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller512: ; RV64I-LABEL: caller512:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -1536 ; RV64I-NEXT: addi sp, sp, -1536
; RV64I-NEXT: sd ra, 1528(sp) ; RV64I-NEXT: sd ra, 1528(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 1520(sp) ; RV64I-NEXT: sd s0, 1520(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 1536 ; RV64I-NEXT: addi s0, sp, 1536
; RV64I-NEXT: andi sp, sp, -512 ; RV64I-NEXT: andi sp, sp, -512
; RV64I-NEXT: addi a0, sp, 1024 ; RV64I-NEXT: addi a0, sp, 1024
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: addi sp, s0, -1536 ; RV64I-NEXT: addi sp, s0, -1536
; RV64I-NEXT: ld s0, 1520(sp) ; RV64I-NEXT: ld s0, 1520(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 1528(sp) ; RV64I-NEXT: ld ra, 1528(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 1536 ; RV64I-NEXT: addi sp, sp, 1536
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 512 %1 = alloca i8, align 512
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign512() nounwind "no-realign-stack" { define void @caller_no_realign512() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign512: ; RV32I-LABEL: caller_no_realign512:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign512: ; RV64I-LABEL: caller_no_realign512:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 512 %1 = alloca i8, align 512
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller1024() nounwind { define void @caller1024() nounwind {
; RV32I-LABEL: caller1024: ; RV32I-LABEL: caller1024:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) ; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 2032 ; RV32I-NEXT: addi s0, sp, 2032
; RV32I-NEXT: addi sp, sp, -1040 ; RV32I-NEXT: addi sp, sp, -1040
; RV32I-NEXT: andi sp, sp, -1024 ; RV32I-NEXT: andi sp, sp, -1024
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, -2048 ; RV32I-NEXT: addi a0, a0, -2048
; RV32I-NEXT: add a0, sp, a0 ; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: mv a0, a0 ; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, -1024 ; RV32I-NEXT: addi a0, a0, -1024
; RV32I-NEXT: sub sp, s0, a0 ; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: addi sp, sp, 1040 ; RV32I-NEXT: addi sp, sp, 1040
; RV32I-NEXT: lw s0, 2024(sp) ; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032 ; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller1024: ; RV64I-LABEL: caller1024:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032 ; RV64I-NEXT: addi sp, sp, -2032
; RV64I-NEXT: sd ra, 2024(sp) ; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) ; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 2032 ; RV64I-NEXT: addi s0, sp, 2032
; RV64I-NEXT: addi sp, sp, -1040 ; RV64I-NEXT: addi sp, sp, -1040
; RV64I-NEXT: andi sp, sp, -1024 ; RV64I-NEXT: andi sp, sp, -1024
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: add a0, sp, a0 ; RV64I-NEXT: add a0, sp, a0
; RV64I-NEXT: mv a0, a0 ; RV64I-NEXT: mv a0, a0
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, -1024 ; RV64I-NEXT: addiw a0, a0, -1024
; RV64I-NEXT: sub sp, s0, a0 ; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: addi sp, sp, 1040 ; RV64I-NEXT: addi sp, sp, 1040
; RV64I-NEXT: ld s0, 2016(sp) ; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) ; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032 ; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 1024 %1 = alloca i8, align 1024
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign1024() nounwind "no-realign-stack" { define void @caller_no_realign1024() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign1024: ; RV32I-LABEL: caller_no_realign1024:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign1024: ; RV64I-LABEL: caller_no_realign1024:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 1024 %1 = alloca i8, align 1024
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller2048() nounwind { define void @caller2048() nounwind {
; RV32I-LABEL: caller2048: ; RV32I-LABEL: caller2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) ; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 2032 ; RV32I-NEXT: addi s0, sp, 2032
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, 16 ; RV32I-NEXT: addi a0, a0, 16
; RV32I-NEXT: sub sp, sp, a0 ; RV32I-NEXT: sub sp, sp, a0
; RV32I-NEXT: andi sp, sp, -2048 ; RV32I-NEXT: andi sp, sp, -2048
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: add a0, sp, a0 ; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: mv a0, a0 ; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lui a0, 2 ; RV32I-NEXT: lui a0, 2
; RV32I-NEXT: addi a0, a0, -2048 ; RV32I-NEXT: addi a0, a0, -2048
; RV32I-NEXT: sub sp, s0, a0 ; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, 16 ; RV32I-NEXT: addi a0, a0, 16
; RV32I-NEXT: add sp, sp, a0 ; RV32I-NEXT: add sp, sp, a0
; RV32I-NEXT: lw s0, 2024(sp) ; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032 ; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller2048: ; RV64I-LABEL: caller2048:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032 ; RV64I-NEXT: addi sp, sp, -2032
; RV64I-NEXT: sd ra, 2024(sp) ; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) ; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 2032 ; RV64I-NEXT: addi s0, sp, 2032
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16 ; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: sub sp, sp, a0 ; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: andi sp, sp, -2048 ; RV64I-NEXT: andi sp, sp, -2048
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: add a0, sp, a0 ; RV64I-NEXT: add a0, sp, a0
; RV64I-NEXT: mv a0, a0 ; RV64I-NEXT: mv a0, a0
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: lui a0, 2 ; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: sub sp, s0, a0 ; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16 ; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: add sp, sp, a0 ; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: ld s0, 2016(sp) ; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) ; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032 ; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 2048 %1 = alloca i8, align 2048
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign2048() nounwind "no-realign-stack" { define void @caller_no_realign2048() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign2048: ; RV32I-LABEL: caller_no_realign2048:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign2048: ; RV64I-LABEL: caller_no_realign2048:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 2048 %1 = alloca i8, align 2048
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller4096() nounwind { define void @caller4096() nounwind {
; RV32I-LABEL: caller4096: ; RV32I-LABEL: caller4096:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032 ; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) ; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) ; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 2032 ; RV32I-NEXT: addi s0, sp, 2032
; RV32I-NEXT: lui a0, 3 ; RV32I-NEXT: lui a0, 3
; RV32I-NEXT: addi a0, a0, -2032 ; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: sub sp, sp, a0 ; RV32I-NEXT: sub sp, sp, a0
; RV32I-NEXT: srli a0, sp, 12 ; RV32I-NEXT: srli a0, sp, 12
; RV32I-NEXT: slli sp, a0, 12 ; RV32I-NEXT: slli sp, a0, 12
; RV32I-NEXT: lui a0, 2 ; RV32I-NEXT: lui a0, 2
; RV32I-NEXT: add a0, sp, a0 ; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: mv a0, a0 ; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lui a0, 3 ; RV32I-NEXT: lui a0, 3
; RV32I-NEXT: sub sp, s0, a0 ; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: lui a0, 3 ; RV32I-NEXT: lui a0, 3
; RV32I-NEXT: addi a0, a0, -2032 ; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: add sp, sp, a0 ; RV32I-NEXT: add sp, sp, a0
; RV32I-NEXT: lw s0, 2024(sp) ; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) ; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032 ; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller4096: ; RV64I-LABEL: caller4096:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032 ; RV64I-NEXT: addi sp, sp, -2032
; RV64I-NEXT: sd ra, 2024(sp) ; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) ; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 2032 ; RV64I-NEXT: addi s0, sp, 2032
; RV64I-NEXT: lui a0, 3 ; RV64I-NEXT: lui a0, 3
; RV64I-NEXT: addiw a0, a0, -2032 ; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: sub sp, sp, a0 ; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: srli a0, sp, 12 ; RV64I-NEXT: srli a0, sp, 12
; RV64I-NEXT: slli sp, a0, 12 ; RV64I-NEXT: slli sp, a0, 12
; RV64I-NEXT: lui a0, 2 ; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: add a0, sp, a0 ; RV64I-NEXT: add a0, sp, a0
; RV64I-NEXT: mv a0, a0 ; RV64I-NEXT: mv a0, a0
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: lui a0, 3 ; RV64I-NEXT: lui a0, 3
; RV64I-NEXT: sub sp, s0, a0 ; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: lui a0, 3 ; RV64I-NEXT: lui a0, 3
; RV64I-NEXT: addiw a0, a0, -2032 ; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: add sp, sp, a0 ; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: ld s0, 2016(sp) ; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) ; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 2032 ; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 4096 %1 = alloca i8, align 4096
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }
define void @caller_no_realign4096() nounwind "no-realign-stack" { define void @caller_no_realign4096() nounwind "no-realign-stack" {
; RV32I-LABEL: caller_no_realign4096: ; RV32I-LABEL: caller_no_realign4096:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a0, sp ; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: caller_no_realign4096: ; RV64I-LABEL: caller_no_realign4096:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp ; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = alloca i8, align 4096 %1 = alloca i8, align 4096
call void @callee(i8* %1) call void @callee(i8* %1)
ret void ret void
} }

llvm/test/CodeGen/RISCV/stack-store-check.ll

Show All 9 Lines
@Y = external local_unnamed_addr global fp128, align 16 @Y = external local_unnamed_addr global fp128, align 16
@T = external local_unnamed_addr global fp128, align 16 @T = external local_unnamed_addr global fp128, align 16
@S = external local_unnamed_addr global fp128, align 16 @S = external local_unnamed_addr global fp128, align 16
define void @main() local_unnamed_addr nounwind { define void @main() local_unnamed_addr nounwind {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -688 ; CHECK-NEXT: addi sp, sp, -688
; CHECK-NEXT: sw ra, 684(sp) ; CHECK-NEXT: sw ra, 684(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 680(sp) ; CHECK-NEXT: sw s0, 680(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s1, 676(sp) ; CHECK-NEXT: sw s1, 676(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s2, 672(sp) ; CHECK-NEXT: sw s2, 672(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s3, 668(sp) ; CHECK-NEXT: sw s3, 668(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s4, 664(sp) ; CHECK-NEXT: sw s4, 664(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s5, 660(sp) ; CHECK-NEXT: sw s5, 660(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s6, 656(sp) ; CHECK-NEXT: sw s6, 656(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s7, 652(sp) ; CHECK-NEXT: sw s7, 652(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s8, 648(sp) ; CHECK-NEXT: sw s8, 648(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s9, 644(sp) ; CHECK-NEXT: sw s9, 644(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s10, 640(sp) ; CHECK-NEXT: sw s10, 640(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s11, 636(sp) ; CHECK-NEXT: sw s11, 636(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(U) ; CHECK-NEXT: lui a0, %hi(U)
; CHECK-NEXT: lw s6, %lo(U)(a0) ; CHECK-NEXT: lw s6, %lo(U)(a0)
; CHECK-NEXT: lw s7, %lo(U+4)(a0) ; CHECK-NEXT: lw s7, %lo(U+4)(a0)
; CHECK-NEXT: lw s8, %lo(U+8)(a0) ; CHECK-NEXT: lw s8, %lo(U+8)(a0)
; CHECK-NEXT: lw s0, %lo(U+12)(a0) ; CHECK-NEXT: lw s0, %lo(U+12)(a0)
; CHECK-NEXT: sw zero, 612(sp) ; CHECK-NEXT: sw zero, 612(sp)
; CHECK-NEXT: sw zero, 608(sp) ; CHECK-NEXT: sw zero, 608(sp)
; CHECK-NEXT: sw zero, 604(sp) ; CHECK-NEXT: sw zero, 604(sp)
; CHECK-NEXT: sw zero, 600(sp) ; CHECK-NEXT: sw zero, 600(sp)
; CHECK-NEXT: sw s0, 596(sp) ; CHECK-NEXT: sw s0, 596(sp)
; CHECK-NEXT: sw s8, 592(sp) ; CHECK-NEXT: sw s8, 592(sp)
; CHECK-NEXT: sw s7, 588(sp) ; CHECK-NEXT: sw s7, 588(sp)
; CHECK-NEXT: addi a0, sp, 616 ; CHECK-NEXT: addi a0, sp, 616
; CHECK-NEXT: addi a1, sp, 600 ; CHECK-NEXT: addi a1, sp, 600
; CHECK-NEXT: addi a2, sp, 584 ; CHECK-NEXT: addi a2, sp, 584
; CHECK-NEXT: sw s6, 584(sp) ; CHECK-NEXT: sw s6, 584(sp)
; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw s3, 616(sp) ; CHECK-NEXT: lw s3, 616(sp)
; CHECK-NEXT: lw s4, 620(sp) ; CHECK-NEXT: lw s4, 620(sp)
; CHECK-NEXT: lw s9, 624(sp) ; CHECK-NEXT: lw s9, 624(sp)
; CHECK-NEXT: lw s11, 628(sp) ; CHECK-NEXT: lw s11, 628(sp)
; CHECK-NEXT: sw s0, 548(sp) ; CHECK-NEXT: sw s0, 548(sp)
; CHECK-NEXT: sw s8, 544(sp) ; CHECK-NEXT: sw s8, 544(sp)
; CHECK-NEXT: sw s7, 540(sp) ; CHECK-NEXT: sw s7, 540(sp)
; CHECK-NEXT: sw s6, 536(sp) ; CHECK-NEXT: sw s6, 536(sp)
; CHECK-NEXT: sw s11, 564(sp) ; CHECK-NEXT: sw s11, 564(sp)
; CHECK-NEXT: sw s9, 560(sp) ; CHECK-NEXT: sw s9, 560(sp)
; CHECK-NEXT: sw s4, 556(sp) ; CHECK-NEXT: sw s4, 556(sp)
; CHECK-NEXT: addi a0, sp, 568 ; CHECK-NEXT: addi a0, sp, 568
; CHECK-NEXT: addi a1, sp, 552 ; CHECK-NEXT: addi a1, sp, 552
; CHECK-NEXT: addi a2, sp, 536 ; CHECK-NEXT: addi a2, sp, 536
; CHECK-NEXT: sw s3, 552(sp) ; CHECK-NEXT: sw s3, 552(sp)
; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 568(sp) ; CHECK-NEXT: lw a0, 568(sp)
; CHECK-NEXT: sw a0, 40(sp) ; CHECK-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 572(sp) ; CHECK-NEXT: lw a0, 572(sp)
; CHECK-NEXT: sw a0, 32(sp) ; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 576(sp) ; CHECK-NEXT: lw a0, 576(sp)
; CHECK-NEXT: sw a0, 24(sp) ; CHECK-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 580(sp) ; CHECK-NEXT: lw a0, 580(sp)
; CHECK-NEXT: sw a0, 16(sp) ; CHECK-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw zero, 500(sp) ; CHECK-NEXT: sw zero, 500(sp)
; CHECK-NEXT: sw zero, 496(sp) ; CHECK-NEXT: sw zero, 496(sp)
; CHECK-NEXT: sw zero, 492(sp) ; CHECK-NEXT: sw zero, 492(sp)
; CHECK-NEXT: sw zero, 488(sp) ; CHECK-NEXT: sw zero, 488(sp)
; CHECK-NEXT: sw s0, 516(sp) ; CHECK-NEXT: sw s0, 516(sp)
; CHECK-NEXT: sw s8, 512(sp) ; CHECK-NEXT: sw s8, 512(sp)
; CHECK-NEXT: sw s7, 508(sp) ; CHECK-NEXT: sw s7, 508(sp)
; CHECK-NEXT: addi a0, sp, 520 ; CHECK-NEXT: addi a0, sp, 520
; CHECK-NEXT: addi a1, sp, 504 ; CHECK-NEXT: addi a1, sp, 504
; CHECK-NEXT: addi a2, sp, 488 ; CHECK-NEXT: addi a2, sp, 488
; CHECK-NEXT: sw s6, 504(sp) ; CHECK-NEXT: sw s6, 504(sp)
; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw s2, 520(sp) ; CHECK-NEXT: lw s2, 520(sp)
; CHECK-NEXT: lw s10, 524(sp) ; CHECK-NEXT: lw s10, 524(sp)
; CHECK-NEXT: lw s5, 528(sp) ; CHECK-NEXT: lw s5, 528(sp)
; CHECK-NEXT: lw s1, 532(sp) ; CHECK-NEXT: lw s1, 532(sp)
; CHECK-NEXT: sw s1, 8(sp) ; CHECK-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(Y1) ; CHECK-NEXT: lui a0, %hi(Y1)
; CHECK-NEXT: lw a1, %lo(Y1)(a0) ; CHECK-NEXT: lw a1, %lo(Y1)(a0)
; CHECK-NEXT: sw a1, 48(sp) ; CHECK-NEXT: sw a1, 48(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a2, %lo(Y1+4)(a0) ; CHECK-NEXT: lw a2, %lo(Y1+4)(a0)
; CHECK-NEXT: sw a2, 52(sp) ; CHECK-NEXT: sw a2, 52(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a3, %lo(Y1+8)(a0) ; CHECK-NEXT: lw a3, %lo(Y1+8)(a0)
; CHECK-NEXT: sw a3, 4(sp) ; CHECK-NEXT: sw a3, 4(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, %lo(Y1+12)(a0) ; CHECK-NEXT: lw a0, %lo(Y1+12)(a0)
; CHECK-NEXT: sw a0, 0(sp) ; CHECK-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw a0, 308(sp) ; CHECK-NEXT: sw a0, 308(sp)
; CHECK-NEXT: sw a3, 304(sp) ; CHECK-NEXT: sw a3, 304(sp)
; CHECK-NEXT: sw a2, 300(sp) ; CHECK-NEXT: sw a2, 300(sp)
; CHECK-NEXT: sw a1, 296(sp) ; CHECK-NEXT: sw a1, 296(sp)
; CHECK-NEXT: sw s11, 324(sp) ; CHECK-NEXT: sw s11, 324(sp)
; CHECK-NEXT: sw s9, 320(sp) ; CHECK-NEXT: sw s9, 320(sp)
; CHECK-NEXT: sw s4, 316(sp) ; CHECK-NEXT: sw s4, 316(sp)
; CHECK-NEXT: addi a0, sp, 328 ; CHECK-NEXT: addi a0, sp, 328
; CHECK-NEXT: addi a1, sp, 312 ; CHECK-NEXT: addi a1, sp, 312
; CHECK-NEXT: addi a2, sp, 296 ; CHECK-NEXT: addi a2, sp, 296
; CHECK-NEXT: sw s3, 312(sp) ; CHECK-NEXT: sw s3, 312(sp)
; CHECK-NEXT: call __multf3 ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 328(sp) ; CHECK-NEXT: lw a0, 328(sp)
; CHECK-NEXT: sw a0, 44(sp) ; CHECK-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 332(sp) ; CHECK-NEXT: lw a0, 332(sp)
; CHECK-NEXT: sw a0, 36(sp) ; CHECK-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 336(sp) ; CHECK-NEXT: lw a0, 336(sp)
; CHECK-NEXT: sw a0, 28(sp) ; CHECK-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 340(sp) ; CHECK-NEXT: lw a0, 340(sp)
; CHECK-NEXT: sw a0, 20(sp) ; CHECK-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 468(sp) ; CHECK-NEXT: sw s0, 468(sp)
; CHECK-NEXT: sw s8, 464(sp) ; CHECK-NEXT: sw s8, 464(sp)
; CHECK-NEXT: sw s7, 460(sp) ; CHECK-NEXT: sw s7, 460(sp)
; CHECK-NEXT: sw s6, 456(sp) ; CHECK-NEXT: sw s6, 456(sp)
; CHECK-NEXT: sw s1, 452(sp) ; CHECK-NEXT: sw s1, 452(sp)
; CHECK-NEXT: sw s5, 448(sp) ; CHECK-NEXT: sw s5, 448(sp)
; CHECK-NEXT: sw s10, 444(sp) ; CHECK-NEXT: sw s10, 444(sp)
; CHECK-NEXT: addi a0, sp, 472 ; CHECK-NEXT: addi a0, sp, 472
; CHECK-NEXT: addi a1, sp, 456 ; CHECK-NEXT: addi a1, sp, 456
; CHECK-NEXT: addi a2, sp, 440 ; CHECK-NEXT: addi a2, sp, 440
; CHECK-NEXT: sw s2, 440(sp) ; CHECK-NEXT: sw s2, 440(sp)
; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a3, 472(sp) ; CHECK-NEXT: lw a3, 472(sp)
; CHECK-NEXT: lw a0, 476(sp) ; CHECK-NEXT: lw a0, 476(sp)
; CHECK-NEXT: lw a1, 480(sp) ; CHECK-NEXT: lw a1, 480(sp)
; CHECK-NEXT: lw a2, 484(sp) ; CHECK-NEXT: lw a2, 484(sp)
; CHECK-NEXT: sw zero, 420(sp) ; CHECK-NEXT: sw zero, 420(sp)
; CHECK-NEXT: sw zero, 416(sp) ; CHECK-NEXT: sw zero, 416(sp)
; CHECK-NEXT: sw zero, 412(sp) ; CHECK-NEXT: sw zero, 412(sp)
; CHECK-NEXT: sw zero, 408(sp) ; CHECK-NEXT: sw zero, 408(sp)
; CHECK-NEXT: sw a2, 404(sp) ; CHECK-NEXT: sw a2, 404(sp)
; CHECK-NEXT: sw a1, 400(sp) ; CHECK-NEXT: sw a1, 400(sp)
; CHECK-NEXT: sw a0, 396(sp) ; CHECK-NEXT: sw a0, 396(sp)
; CHECK-NEXT: addi a0, sp, 424 ; CHECK-NEXT: addi a0, sp, 424
; CHECK-NEXT: addi a1, sp, 408 ; CHECK-NEXT: addi a1, sp, 408
; CHECK-NEXT: addi a2, sp, 392 ; CHECK-NEXT: addi a2, sp, 392
; CHECK-NEXT: sw a3, 392(sp) ; CHECK-NEXT: sw a3, 392(sp)
; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 424(sp) ; CHECK-NEXT: lw a0, 424(sp)
; CHECK-NEXT: lw a1, 436(sp) ; CHECK-NEXT: lw a1, 436(sp)
; CHECK-NEXT: lw a2, 432(sp) ; CHECK-NEXT: lw a2, 432(sp)
; CHECK-NEXT: lw a3, 428(sp) ; CHECK-NEXT: lw a3, 428(sp)
; CHECK-NEXT: lui a4, %hi(X) ; CHECK-NEXT: lui a4, %hi(X)
; CHECK-NEXT: sw a1, %lo(X+12)(a4) ; CHECK-NEXT: sw a1, %lo(X+12)(a4)
; CHECK-NEXT: sw a2, %lo(X+8)(a4) ; CHECK-NEXT: sw a2, %lo(X+8)(a4)
; CHECK-NEXT: sw a3, %lo(X+4)(a4) ; CHECK-NEXT: sw a3, %lo(X+4)(a4)
; CHECK-NEXT: sw a0, %lo(X)(a4) ; CHECK-NEXT: sw a0, %lo(X)(a4)
; CHECK-NEXT: lw s8, 0(sp) ; CHECK-NEXT: lw s8, 0(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s8, 212(sp) ; CHECK-NEXT: sw s8, 212(sp)
; CHECK-NEXT: lw s7, 4(sp) ; CHECK-NEXT: lw s7, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s7, 208(sp) ; CHECK-NEXT: sw s7, 208(sp)
; CHECK-NEXT: lw a0, 52(sp) ; CHECK-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 204(sp) ; CHECK-NEXT: sw a0, 204(sp)
; CHECK-NEXT: lw a0, 48(sp) ; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 200(sp) ; CHECK-NEXT: sw a0, 200(sp)
; CHECK-NEXT: lw s6, 16(sp) ; CHECK-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s6, 228(sp) ; CHECK-NEXT: sw s6, 228(sp)
; CHECK-NEXT: lw s4, 24(sp) ; CHECK-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s4, 224(sp) ; CHECK-NEXT: sw s4, 224(sp)
; CHECK-NEXT: lw s0, 32(sp) ; CHECK-NEXT: lw s0, 32(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s0, 220(sp) ; CHECK-NEXT: sw s0, 220(sp)
; CHECK-NEXT: addi a0, sp, 232 ; CHECK-NEXT: addi a0, sp, 232
; CHECK-NEXT: addi a1, sp, 216 ; CHECK-NEXT: addi a1, sp, 216
; CHECK-NEXT: addi a2, sp, 200 ; CHECK-NEXT: addi a2, sp, 200
; CHECK-NEXT: lw s1, 40(sp) ; CHECK-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s1, 216(sp) ; CHECK-NEXT: sw s1, 216(sp)
; CHECK-NEXT: call __multf3 ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 232(sp) ; CHECK-NEXT: lw a0, 232(sp)
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s3, 236(sp) ; CHECK-NEXT: lw s3, 236(sp)
; CHECK-NEXT: lw s9, 240(sp) ; CHECK-NEXT: lw s9, 240(sp)
; CHECK-NEXT: lw s11, 244(sp) ; CHECK-NEXT: lw s11, 244(sp)
; CHECK-NEXT: sw zero, 356(sp) ; CHECK-NEXT: sw zero, 356(sp)
; CHECK-NEXT: sw zero, 352(sp) ; CHECK-NEXT: sw zero, 352(sp)
; CHECK-NEXT: sw zero, 348(sp) ; CHECK-NEXT: sw zero, 348(sp)
; CHECK-NEXT: sw zero, 344(sp) ; CHECK-NEXT: sw zero, 344(sp)
; CHECK-NEXT: lw a0, 8(sp) ; CHECK-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 372(sp) ; CHECK-NEXT: sw a0, 372(sp)
; CHECK-NEXT: sw s5, 368(sp) ; CHECK-NEXT: sw s5, 368(sp)
; CHECK-NEXT: sw s10, 364(sp) ; CHECK-NEXT: sw s10, 364(sp)
; CHECK-NEXT: addi a0, sp, 376 ; CHECK-NEXT: addi a0, sp, 376
; CHECK-NEXT: addi a1, sp, 360 ; CHECK-NEXT: addi a1, sp, 360
; CHECK-NEXT: addi a2, sp, 344 ; CHECK-NEXT: addi a2, sp, 344
; CHECK-NEXT: sw s2, 360(sp) ; CHECK-NEXT: sw s2, 360(sp)
; CHECK-NEXT: call __multf3 ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 376(sp) ; CHECK-NEXT: lw a0, 376(sp)
; CHECK-NEXT: lw a1, 388(sp) ; CHECK-NEXT: lw a1, 388(sp)
; CHECK-NEXT: lw a2, 384(sp) ; CHECK-NEXT: lw a2, 384(sp)
; CHECK-NEXT: lw a3, 380(sp) ; CHECK-NEXT: lw a3, 380(sp)
; CHECK-NEXT: lui a4, %hi(S) ; CHECK-NEXT: lui a4, %hi(S)
; CHECK-NEXT: sw a1, %lo(S+12)(a4) ; CHECK-NEXT: sw a1, %lo(S+12)(a4)
; CHECK-NEXT: sw a2, %lo(S+8)(a4) ; CHECK-NEXT: sw a2, %lo(S+8)(a4)
; CHECK-NEXT: sw a3, %lo(S+4)(a4) ; CHECK-NEXT: sw a3, %lo(S+4)(a4)
; CHECK-NEXT: sw a0, %lo(S)(a4) ; CHECK-NEXT: sw a0, %lo(S)(a4)
; CHECK-NEXT: sw s6, 260(sp) ; CHECK-NEXT: sw s6, 260(sp)
; CHECK-NEXT: sw s4, 256(sp) ; CHECK-NEXT: sw s4, 256(sp)
; CHECK-NEXT: sw s0, 252(sp) ; CHECK-NEXT: sw s0, 252(sp)
; CHECK-NEXT: sw s1, 248(sp) ; CHECK-NEXT: sw s1, 248(sp)
; CHECK-NEXT: lw a0, 20(sp) ; CHECK-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 276(sp) ; CHECK-NEXT: sw a0, 276(sp)
; CHECK-NEXT: lw a0, 28(sp) ; CHECK-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 272(sp) ; CHECK-NEXT: sw a0, 272(sp)
; CHECK-NEXT: lw a0, 36(sp) ; CHECK-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 268(sp) ; CHECK-NEXT: sw a0, 268(sp)
; CHECK-NEXT: addi a0, sp, 280 ; CHECK-NEXT: addi a0, sp, 280
; CHECK-NEXT: addi a1, sp, 264 ; CHECK-NEXT: addi a1, sp, 264
; CHECK-NEXT: addi a2, sp, 248 ; CHECK-NEXT: addi a2, sp, 248
; CHECK-NEXT: lw a3, 44(sp) ; CHECK-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 264(sp) ; CHECK-NEXT: sw a3, 264(sp)
; CHECK-NEXT: call __subtf3 ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 280(sp) ; CHECK-NEXT: lw a0, 280(sp)
; CHECK-NEXT: lw a1, 292(sp) ; CHECK-NEXT: lw a1, 292(sp)
; CHECK-NEXT: lw a2, 288(sp) ; CHECK-NEXT: lw a2, 288(sp)
; CHECK-NEXT: lw a3, 284(sp) ; CHECK-NEXT: lw a3, 284(sp)
; CHECK-NEXT: lui a4, %hi(T) ; CHECK-NEXT: lui a4, %hi(T)
; CHECK-NEXT: sw a1, %lo(T+12)(a4) ; CHECK-NEXT: sw a1, %lo(T+12)(a4)
; CHECK-NEXT: sw a2, %lo(T+8)(a4) ; CHECK-NEXT: sw a2, %lo(T+8)(a4)
; CHECK-NEXT: sw a3, %lo(T+4)(a4) ; CHECK-NEXT: sw a3, %lo(T+4)(a4)
; CHECK-NEXT: sw a0, %lo(T)(a4) ; CHECK-NEXT: sw a0, %lo(T)(a4)
; CHECK-NEXT: sw zero, 164(sp) ; CHECK-NEXT: sw zero, 164(sp)
; CHECK-NEXT: sw zero, 160(sp) ; CHECK-NEXT: sw zero, 160(sp)
; CHECK-NEXT: sw zero, 156(sp) ; CHECK-NEXT: sw zero, 156(sp)
; CHECK-NEXT: sw zero, 152(sp) ; CHECK-NEXT: sw zero, 152(sp)
; CHECK-NEXT: sw s11, 180(sp) ; CHECK-NEXT: sw s11, 180(sp)
; CHECK-NEXT: sw s9, 176(sp) ; CHECK-NEXT: sw s9, 176(sp)
; CHECK-NEXT: sw s3, 172(sp) ; CHECK-NEXT: sw s3, 172(sp)
; CHECK-NEXT: addi a0, sp, 184 ; CHECK-NEXT: addi a0, sp, 184
; CHECK-NEXT: addi a1, sp, 168 ; CHECK-NEXT: addi a1, sp, 168
; CHECK-NEXT: addi a2, sp, 152 ; CHECK-NEXT: addi a2, sp, 152
; CHECK-NEXT: lw a3, 12(sp) ; CHECK-NEXT: lw a3, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 168(sp) ; CHECK-NEXT: sw a3, 168(sp)
; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a0, 184(sp) ; CHECK-NEXT: lw a0, 184(sp)
; CHECK-NEXT: lw a1, 196(sp) ; CHECK-NEXT: lw a1, 196(sp)
; CHECK-NEXT: lw a2, 192(sp) ; CHECK-NEXT: lw a2, 192(sp)
; CHECK-NEXT: lw a3, 188(sp) ; CHECK-NEXT: lw a3, 188(sp)
; CHECK-NEXT: lui a4, %hi(Y) ; CHECK-NEXT: lui a4, %hi(Y)
; CHECK-NEXT: sw a1, %lo(Y+12)(a4) ; CHECK-NEXT: sw a1, %lo(Y+12)(a4)
; CHECK-NEXT: sw a2, %lo(Y+8)(a4) ; CHECK-NEXT: sw a2, %lo(Y+8)(a4)
; CHECK-NEXT: sw a3, %lo(Y+4)(a4) ; CHECK-NEXT: sw a3, %lo(Y+4)(a4)
; CHECK-NEXT: sw a0, %lo(Y)(a4) ; CHECK-NEXT: sw a0, %lo(Y)(a4)
; CHECK-NEXT: sw zero, 116(sp) ; CHECK-NEXT: sw zero, 116(sp)
; CHECK-NEXT: sw zero, 112(sp) ; CHECK-NEXT: sw zero, 112(sp)
; CHECK-NEXT: sw zero, 108(sp) ; CHECK-NEXT: sw zero, 108(sp)
; CHECK-NEXT: sw zero, 104(sp) ; CHECK-NEXT: sw zero, 104(sp)
; CHECK-NEXT: sw s8, 132(sp) ; CHECK-NEXT: sw s8, 132(sp)
; CHECK-NEXT: sw s7, 128(sp) ; CHECK-NEXT: sw s7, 128(sp)
; CHECK-NEXT: lw a0, 52(sp) ; CHECK-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 124(sp) ; CHECK-NEXT: sw a0, 124(sp)
; CHECK-NEXT: addi a0, sp, 136 ; CHECK-NEXT: addi a0, sp, 136
; CHECK-NEXT: addi a1, sp, 120 ; CHECK-NEXT: addi a1, sp, 120
; CHECK-NEXT: addi a2, sp, 104 ; CHECK-NEXT: addi a2, sp, 104
; CHECK-NEXT: lw a3, 48(sp) ; CHECK-NEXT: lw a3, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 120(sp) ; CHECK-NEXT: sw a3, 120(sp)
; CHECK-NEXT: call __multf3 ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a3, 136(sp) ; CHECK-NEXT: lw a3, 136(sp)
; CHECK-NEXT: lw a0, 140(sp) ; CHECK-NEXT: lw a0, 140(sp)
; CHECK-NEXT: lw a1, 144(sp) ; CHECK-NEXT: lw a1, 144(sp)
; CHECK-NEXT: lw a2, 148(sp) ; CHECK-NEXT: lw a2, 148(sp)
; CHECK-NEXT: lui a4, 786400 ; CHECK-NEXT: lui a4, 786400
; CHECK-NEXT: sw a4, 68(sp) ; CHECK-NEXT: sw a4, 68(sp)
; CHECK-NEXT: sw zero, 64(sp) ; CHECK-NEXT: sw zero, 64(sp)
; CHECK-NEXT: sw zero, 60(sp) ; CHECK-NEXT: sw zero, 60(sp)
; CHECK-NEXT: sw zero, 56(sp) ; CHECK-NEXT: sw zero, 56(sp)
; CHECK-NEXT: sw a2, 84(sp) ; CHECK-NEXT: sw a2, 84(sp)
; CHECK-NEXT: sw a1, 80(sp) ; CHECK-NEXT: sw a1, 80(sp)
; CHECK-NEXT: sw a0, 76(sp) ; CHECK-NEXT: sw a0, 76(sp)
; CHECK-NEXT: addi a0, sp, 88 ; CHECK-NEXT: addi a0, sp, 88
; CHECK-NEXT: addi a1, sp, 72 ; CHECK-NEXT: addi a1, sp, 72
; CHECK-NEXT: addi a2, sp, 56 ; CHECK-NEXT: addi a2, sp, 56
; CHECK-NEXT: sw a3, 72(sp) ; CHECK-NEXT: sw a3, 72(sp)
; CHECK-NEXT: call __addtf3 ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a0, 96(sp) ; CHECK-NEXT: lw a0, 96(sp)
; CHECK-NEXT: lw a1, 100(sp) ; CHECK-NEXT: lw a1, 100(sp)
; CHECK-NEXT: lw a2, 88(sp) ; CHECK-NEXT: lw a2, 88(sp)
; CHECK-NEXT: lw a3, 92(sp) ; CHECK-NEXT: lw a3, 92(sp)
; CHECK-NEXT: lui a4, %hi(Y1) ; CHECK-NEXT: lui a4, %hi(Y1)
; CHECK-NEXT: sw a0, %lo(Y1+8)(a4) ; CHECK-NEXT: sw a0, %lo(Y1+8)(a4)
; CHECK-NEXT: sw a1, %lo(Y1+12)(a4) ; CHECK-NEXT: sw a1, %lo(Y1+12)(a4)
; CHECK-NEXT: sw a2, %lo(Y1)(a4) ; CHECK-NEXT: sw a2, %lo(Y1)(a4)
; CHECK-NEXT: sw a3, %lo(Y1+4)(a4) ; CHECK-NEXT: sw a3, %lo(Y1+4)(a4)
; CHECK-NEXT: lw s11, 636(sp) ; CHECK-NEXT: lw s11, 636(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s10, 640(sp) ; CHECK-NEXT: lw s10, 640(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s9, 644(sp) ; CHECK-NEXT: lw s9, 644(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s8, 648(sp) ; CHECK-NEXT: lw s8, 648(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s7, 652(sp) ; CHECK-NEXT: lw s7, 652(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s6, 656(sp) ; CHECK-NEXT: lw s6, 656(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s5, 660(sp) ; CHECK-NEXT: lw s5, 660(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s4, 664(sp) ; CHECK-NEXT: lw s4, 664(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s3, 668(sp) ; CHECK-NEXT: lw s3, 668(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s2, 672(sp) ; CHECK-NEXT: lw s2, 672(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s1, 676(sp) ; CHECK-NEXT: lw s1, 676(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 680(sp) ; CHECK-NEXT: lw s0, 680(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 684(sp) ; CHECK-NEXT: lw ra, 684(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 688 ; CHECK-NEXT: addi sp, sp, 688
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = load fp128, fp128* @U, align 16 %1 = load fp128, fp128* @U, align 16
%2 = fsub fp128 0xL00000000000000000000000000000000, %1 %2 = fsub fp128 0xL00000000000000000000000000000000, %1
%3 = fsub fp128 %2, %1 %3 = fsub fp128 %2, %1
%4 = fadd fp128 %1, 0xL00000000000000000000000000000000 %4 = fadd fp128 %1, 0xL00000000000000000000000000000000
%5 = load fp128, fp128* @Y1, align 16 %5 = load fp128, fp128* @Y1, align 16
%6 = fmul fp128 %2, %5 %6 = fmul fp128 %2, %5
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llvm/test/CodeGen/RISCV/tls-models.ll

Show All 16 Lines
; No model specified ; No model specified
define i32* @f1() nounwind { define i32* @f1() nounwind {
; RV32-PIC-LABEL: f1: ; RV32-PIC-LABEL: f1:
; RV32-PIC: # %bb.0: # %entry ; RV32-PIC: # %bb.0: # %entry
; RV32-PIC-NEXT: addi sp, sp, -16 ; RV32-PIC-NEXT: addi sp, sp, -16
; RV32-PIC-NEXT: sw ra, 12(sp) ; RV32-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-PIC-NEXT: .LBB0_1: # %entry ; RV32-PIC-NEXT: .LBB0_1: # %entry
; RV32-PIC-NEXT: # Label of block must be emitted ; RV32-PIC-NEXT: # Label of block must be emitted
; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified) ; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified)
; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1) ; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
; RV32-PIC-NEXT: call __tls_get_addr@plt ; RV32-PIC-NEXT: call __tls_get_addr@plt
; RV32-PIC-NEXT: lw ra, 12(sp) ; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: addi sp, sp, 16
; RV32-PIC-NEXT: ret ; RV32-PIC-NEXT: ret
; ;
; RV64-PIC-LABEL: f1: ; RV64-PIC-LABEL: f1:
; RV64-PIC: # %bb.0: # %entry ; RV64-PIC: # %bb.0: # %entry
; RV64-PIC-NEXT: addi sp, sp, -16 ; RV64-PIC-NEXT: addi sp, sp, -16
; RV64-PIC-NEXT: sd ra, 8(sp) ; RV64-PIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-PIC-NEXT: .LBB0_1: # %entry ; RV64-PIC-NEXT: .LBB0_1: # %entry
; RV64-PIC-NEXT: # Label of block must be emitted ; RV64-PIC-NEXT: # Label of block must be emitted
; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified) ; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(unspecified)
; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1) ; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB0_1)
; RV64-PIC-NEXT: call __tls_get_addr@plt ; RV64-PIC-NEXT: call __tls_get_addr@plt
; RV64-PIC-NEXT: ld ra, 8(sp) ; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: addi sp, sp, 16
; RV64-PIC-NEXT: ret ; RV64-PIC-NEXT: ret
; ;
; RV32-NOPIC-LABEL: f1: ; RV32-NOPIC-LABEL: f1:
; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC: # %bb.0: # %entry
; RV32-NOPIC-NEXT: .LBB0_1: # %entry ; RV32-NOPIC-NEXT: .LBB0_1: # %entry
; RV32-NOPIC-NEXT: # Label of block must be emitted ; RV32-NOPIC-NEXT: # Label of block must be emitted
; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) ; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified)
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; localdynamic specified ; localdynamic specified
define i32* @f2() nounwind { define i32* @f2() nounwind {
; RV32-PIC-LABEL: f2: ; RV32-PIC-LABEL: f2:
; RV32-PIC: # %bb.0: # %entry ; RV32-PIC: # %bb.0: # %entry
; RV32-PIC-NEXT: addi sp, sp, -16 ; RV32-PIC-NEXT: addi sp, sp, -16
; RV32-PIC-NEXT: sw ra, 12(sp) ; RV32-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-PIC-NEXT: .LBB1_1: # %entry ; RV32-PIC-NEXT: .LBB1_1: # %entry
; RV32-PIC-NEXT: # Label of block must be emitted ; RV32-PIC-NEXT: # Label of block must be emitted
; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld) ; RV32-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld)
; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1) ; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
; RV32-PIC-NEXT: call __tls_get_addr@plt ; RV32-PIC-NEXT: call __tls_get_addr@plt
; RV32-PIC-NEXT: lw ra, 12(sp) ; RV32-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: addi sp, sp, 16
; RV32-PIC-NEXT: ret ; RV32-PIC-NEXT: ret
; ;
; RV64-PIC-LABEL: f2: ; RV64-PIC-LABEL: f2:
; RV64-PIC: # %bb.0: # %entry ; RV64-PIC: # %bb.0: # %entry
; RV64-PIC-NEXT: addi sp, sp, -16 ; RV64-PIC-NEXT: addi sp, sp, -16
; RV64-PIC-NEXT: sd ra, 8(sp) ; RV64-PIC-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-PIC-NEXT: .LBB1_1: # %entry ; RV64-PIC-NEXT: .LBB1_1: # %entry
; RV64-PIC-NEXT: # Label of block must be emitted ; RV64-PIC-NEXT: # Label of block must be emitted
; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld) ; RV64-PIC-NEXT: auipc a0, %tls_gd_pcrel_hi(ld)
; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1) ; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
; RV64-PIC-NEXT: call __tls_get_addr@plt ; RV64-PIC-NEXT: call __tls_get_addr@plt
; RV64-PIC-NEXT: ld ra, 8(sp) ; RV64-PIC-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: addi sp, sp, 16
; RV64-PIC-NEXT: ret ; RV64-PIC-NEXT: ret
; ;
; RV32-NOPIC-LABEL: f2: ; RV32-NOPIC-LABEL: f2:
; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC: # %bb.0: # %entry
; RV32-NOPIC-NEXT: .LBB1_1: # %entry ; RV32-NOPIC-NEXT: .LBB1_1: # %entry
; RV32-NOPIC-NEXT: # Label of block must be emitted ; RV32-NOPIC-NEXT: # Label of block must be emitted
; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld) ; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld)
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llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-LABEL: muloti_test: ; RISCV32-LABEL: muloti_test:
; RISCV32: # %bb.0: # %start ; RISCV32: # %bb.0: # %start
; RISCV32-NEXT: addi sp, sp, -96 ; RISCV32-NEXT: addi sp, sp, -96
; RISCV32-NEXT: sw ra, 92(sp) ; RISCV32-NEXT: sw ra, 92(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s0, 88(sp) ; RISCV32-NEXT: sw s0, 88(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s1, 84(sp) ; RISCV32-NEXT: sw s1, 84(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s2, 80(sp) ; RISCV32-NEXT: sw s2, 80(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s3, 76(sp) ; RISCV32-NEXT: sw s3, 76(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s4, 72(sp) ; RISCV32-NEXT: sw s4, 72(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s5, 68(sp) ; RISCV32-NEXT: sw s5, 68(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s6, 64(sp) ; RISCV32-NEXT: sw s6, 64(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s7, 60(sp) ; RISCV32-NEXT: sw s7, 60(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s8, 56(sp) ; RISCV32-NEXT: sw s8, 56(sp) # 4-byte Folded Spill
; RISCV32-NEXT: lw s2, 12(a1) ; RISCV32-NEXT: lw s2, 12(a1)
; RISCV32-NEXT: lw s6, 8(a1) ; RISCV32-NEXT: lw s6, 8(a1)
; RISCV32-NEXT: lw s3, 12(a2) ; RISCV32-NEXT: lw s3, 12(a2)
; RISCV32-NEXT: lw s7, 8(a2) ; RISCV32-NEXT: lw s7, 8(a2)
; RISCV32-NEXT: lw s0, 0(a1) ; RISCV32-NEXT: lw s0, 0(a1)
; RISCV32-NEXT: lw s8, 4(a1) ; RISCV32-NEXT: lw s8, 4(a1)
; RISCV32-NEXT: lw s1, 0(a2) ; RISCV32-NEXT: lw s1, 0(a2)
; RISCV32-NEXT: lw s5, 4(a2) ; RISCV32-NEXT: lw s5, 4(a2)
; RISCV32-NEXT: mv s4, a0 ; RISCV32-NEXT: mv s4, a0
; RISCV32-NEXT: sw zero, 20(sp) ; RISCV32-NEXT: sw zero, 20(sp)
; RISCV32-NEXT: sw zero, 16(sp) ; RISCV32-NEXT: sw zero, 16(sp)
; RISCV32-NEXT: sw zero, 36(sp) ; RISCV32-NEXT: sw zero, 36(sp)
; RISCV32-NEXT: sw zero, 32(sp) ; RISCV32-NEXT: sw zero, 32(sp)
; RISCV32-NEXT: sw s5, 12(sp) ; RISCV32-NEXT: sw s5, 12(sp)
; RISCV32-NEXT: sw s1, 8(sp) ; RISCV32-NEXT: sw s1, 8(sp)
; RISCV32-NEXT: sw s8, 28(sp) ; RISCV32-NEXT: sw s8, 28(sp)
; RISCV32-NEXT: addi a0, sp, 40 ; RISCV32-NEXT: addi a0, sp, 40
; RISCV32-NEXT: addi a1, sp, 24 ; RISCV32-NEXT: addi a1, sp, 24
; RISCV32-NEXT: addi a2, sp, 8 ; RISCV32-NEXT: addi a2, sp, 8
; RISCV32-NEXT: sw s0, 24(sp) ; RISCV32-NEXT: sw s0, 24(sp)
; RISCV32-NEXT: call __multi3 ; RISCV32-NEXT: call __multi3@plt
; RISCV32-NEXT: mul a0, s8, s7 ; RISCV32-NEXT: mul a0, s8, s7
; RISCV32-NEXT: mul a1, s3, s0 ; RISCV32-NEXT: mul a1, s3, s0
; RISCV32-NEXT: add a0, a1, a0 ; RISCV32-NEXT: add a0, a1, a0
; RISCV32-NEXT: mulhu a5, s7, s0 ; RISCV32-NEXT: mulhu a5, s7, s0
; RISCV32-NEXT: add a0, a5, a0 ; RISCV32-NEXT: add a0, a5, a0
; RISCV32-NEXT: mul a1, s5, s6 ; RISCV32-NEXT: mul a1, s5, s6
; RISCV32-NEXT: mul a2, s2, s1 ; RISCV32-NEXT: mul a2, s2, s1
; RISCV32-NEXT: add a1, a2, a1 ; RISCV32-NEXT: add a1, a2, a1
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RISCV32-NEXT: lw a3, 40(sp) ; RISCV32-NEXT: lw a3, 40(sp)
; RISCV32-NEXT: or a0, a0, a2 ; RISCV32-NEXT: or a0, a0, a2
; RISCV32-NEXT: andi a0, a0, 1 ; RISCV32-NEXT: andi a0, a0, 1
; RISCV32-NEXT: sw a1, 4(s4) ; RISCV32-NEXT: sw a1, 4(s4)
; RISCV32-NEXT: sw a3, 0(s4) ; RISCV32-NEXT: sw a3, 0(s4)
; RISCV32-NEXT: sw a6, 8(s4) ; RISCV32-NEXT: sw a6, 8(s4)
; RISCV32-NEXT: sw a7, 12(s4) ; RISCV32-NEXT: sw a7, 12(s4)
; RISCV32-NEXT: sb a0, 16(s4) ; RISCV32-NEXT: sb a0, 16(s4)
; RISCV32-NEXT: lw s8, 56(sp) ; RISCV32-NEXT: lw s8, 56(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s7, 60(sp) ; RISCV32-NEXT: lw s7, 60(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s6, 64(sp) ; RISCV32-NEXT: lw s6, 64(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s5, 68(sp) ; RISCV32-NEXT: lw s5, 68(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s4, 72(sp) ; RISCV32-NEXT: lw s4, 72(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s3, 76(sp) ; RISCV32-NEXT: lw s3, 76(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s2, 80(sp) ; RISCV32-NEXT: lw s2, 80(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s1, 84(sp) ; RISCV32-NEXT: lw s1, 84(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s0, 88(sp) ; RISCV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw ra, 92(sp) ; RISCV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
; RISCV32-NEXT: addi sp, sp, 96 ; RISCV32-NEXT: addi sp, sp, 96
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
start: start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0 %1 = extractvalue { i128, i1 } %0, 0
%2 = extractvalue { i128, i1 } %0, 1 %2 = extractvalue { i128, i1 } %0, 1
%3 = zext i1 %2 to i8 %3 = zext i1 %2 to i8
%4 = insertvalue { i128, i8 } undef, i128 %1, 0 %4 = insertvalue { i128, i8 } undef, i128 %1, 0
Show All 10 Lines

llvm/test/CodeGen/RISCV/urem-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define i32 @fold_urem_positive_odd(i32 %x) nounwind { define i32 @fold_urem_positive_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_urem_positive_odd: ; RV32I-LABEL: fold_urem_positive_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_positive_odd: ; RV32IM-LABEL: fold_urem_positive_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 364242 ; RV32IM-NEXT: lui a1, 364242
; RV32IM-NEXT: addi a1, a1, 777 ; RV32IM-NEXT: addi a1, a1, 777
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: sub a2, a0, a1 ; RV32IM-NEXT: sub a2, a0, a1
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a2, a2, 1
; RV32IM-NEXT: add a1, a2, a1 ; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: srli a1, a1, 6 ; RV32IM-NEXT: srli a1, a1, 6
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_positive_odd: ; RV64I-LABEL: fold_urem_positive_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_positive_odd: ; RV64IM-LABEL: fold_urem_positive_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1423 ; RV64IM-NEXT: lui a1, 1423
Show All 17 Lines; RV64IM-NEXT: ret
ret i32 %1 ret i32 %1
} }
define i32 @fold_urem_positive_even(i32 %x) nounwind { define i32 @fold_urem_positive_even(i32 %x) nounwind {
; RV32I-LABEL: fold_urem_positive_even: ; RV32I-LABEL: fold_urem_positive_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 1060 ; RV32I-NEXT: addi a1, zero, 1060
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_positive_even: ; RV32IM-LABEL: fold_urem_positive_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 1012964 ; RV32IM-NEXT: lui a1, 1012964
; RV32IM-NEXT: addi a1, a1, -61 ; RV32IM-NEXT: addi a1, a1, -61
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: srli a1, a1, 10 ; RV32IM-NEXT: srli a1, a1, 10
; RV32IM-NEXT: addi a2, zero, 1060 ; RV32IM-NEXT: addi a2, zero, 1060
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_positive_even: ; RV64I-LABEL: fold_urem_positive_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 1060 ; RV64I-NEXT: addi a1, zero, 1060
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_positive_even: ; RV64IM-LABEL: fold_urem_positive_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1048020 ; RV64IM-NEXT: lui a1, 1048020
Show All 15 Lines
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define i32 @combine_urem_udiv(i32 %x) nounwind { define i32 @combine_urem_udiv(i32 %x) nounwind {
; RV32I-LABEL: combine_urem_udiv: ; RV32I-LABEL: combine_urem_udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: add a0, s1, a0
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_urem_udiv: ; RV32IM-LABEL: combine_urem_udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 364242 ; RV32IM-NEXT: lui a1, 364242
; RV32IM-NEXT: addi a1, a1, 777 ; RV32IM-NEXT: addi a1, a1, 777
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: sub a2, a0, a1 ; RV32IM-NEXT: sub a2, a0, a1
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a2, a2, 1
; RV32IM-NEXT: add a1, a2, a1 ; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: srli a1, a1, 6 ; RV32IM-NEXT: srli a1, a1, 6
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a2, a1, a2 ; RV32IM-NEXT: mul a2, a1, a2
; RV32IM-NEXT: sub a0, a0, a2 ; RV32IM-NEXT: sub a0, a0, a2
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_urem_udiv: ; RV64I-LABEL: combine_urem_udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli s0, a0, 32 ; RV64I-NEXT: srli s0, a0, 32
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: add a0, s1, a0 ; RV64I-NEXT: add a0, s1, a0
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_urem_udiv: ; RV64IM-LABEL: combine_urem_udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1423 ; RV64IM-NEXT: lui a1, 1423
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret i32 %1 ret i32 %1
} }
; Don't fold i64 urem ; Don't fold i64 urem
define i64 @dont_fold_urem_i64(i64 %x) nounwind { define i64 @dont_fold_urem_i64(i64 %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i64: ; RV32I-LABEL: dont_fold_urem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 98 ; RV32I-NEXT: addi a2, zero, 98
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i64: ; RV32IM-LABEL: dont_fold_urem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: addi a2, zero, 98 ; RV32IM-NEXT: addi a2, zero, 98
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i64: ; RV64I-LABEL: dont_fold_urem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM-LABEL: dont_fold_urem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: srli a1, a0, 1 ; RV64IM-NEXT: srli a1, a0, 1
; RV64IM-NEXT: lui a2, 2675 ; RV64IM-NEXT: lui a2, 2675
; RV64IM-NEXT: addiw a2, a2, -251 ; RV64IM-NEXT: addiw a2, a2, -251
Show All 15 Lines

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind { define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_urem_vec_1: ; RV32I-LABEL: fold_urem_vec_1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s3, 8(a1)
; RV32I-NEXT: lhu s0, 4(a1) ; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, 124 ; RV32I-NEXT: addi a1, zero, 124
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 98 ; RV32I-NEXT: addi a1, zero, 98
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 1003 ; RV32I-NEXT: addi a1, zero, 1003
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s1)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s0, 4(s1)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s5, 2(s1)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_1: ; RV32IM-LABEL: fold_urem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a6, 12(a1)
; RV32IM-NEXT: lhu a3, 8(a1) ; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
Show All 34 Lines
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_1: ; RV64I-LABEL: fold_urem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s3, 16(a1)
; RV64I-NEXT: lhu s0, 8(a1) ; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, 124 ; RV64I-NEXT: addi a1, zero, 124
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 1003 ; RV64I-NEXT: addi a1, zero, 1003
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s1)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s0, 4(s1)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s5, 2(s1)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_1: ; RV64IM-LABEL: fold_urem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a6, 24(a1)
; RV64IM-NEXT: lhu a3, 16(a1) ; RV64IM-NEXT: lhu a3, 16(a1)
; RV64IM-NEXT: lhu a4, 8(a1) ; RV64IM-NEXT: lhu a4, 8(a1)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003> %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_urem_vec_2: ; RV32I-LABEL: fold_urem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s3, 8(a1)
; RV32I-NEXT: lhu s0, 4(a1) ; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s1)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s0, 4(s1)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s5, 2(s1)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_2: ; RV32IM-LABEL: fold_urem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a6, 12(a1)
; RV32IM-NEXT: lhu a7, 8(a1) ; RV32IM-NEXT: lhu a7, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
Show All 33 Lines
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh t0, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_2: ; RV64I-LABEL: fold_urem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s3, 16(a1)
; RV64I-NEXT: lhu s0, 8(a1) ; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s1)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s0, 4(s1)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s5, 2(s1)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_2: ; RV64IM-LABEL: fold_urem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a6, 24(a1)
; RV64IM-NEXT: lhu a7, 16(a1) ; RV64IM-NEXT: lhu a7, 16(a1)
; RV64IM-NEXT: lhu a4, 8(a1) ; RV64IM-NEXT: lhu a4, 8(a1)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_urem_udiv: ; RV32I-LABEL: combine_urem_udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 0(a1) ; RV32I-NEXT: lhu s2, 0(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s3, 4(a1)
; RV32I-NEXT: lhu s4, 8(a1) ; RV32I-NEXT: lhu s4, 8(a1)
; RV32I-NEXT: lhu s1, 12(a1) ; RV32I-NEXT: lhu s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add a0, s8, a0
; RV32I-NEXT: add a1, s7, s1 ; RV32I-NEXT: add a1, s7, s1
; RV32I-NEXT: add a2, s6, s4 ; RV32I-NEXT: add a2, s6, s4
; RV32I-NEXT: add a3, s5, s9 ; RV32I-NEXT: add a3, s5, s9
; RV32I-NEXT: sh a3, 6(s0) ; RV32I-NEXT: sh a3, 6(s0)
; RV32I-NEXT: sh a2, 4(s0) ; RV32I-NEXT: sh a2, 4(s0)
; RV32I-NEXT: sh a1, 2(s0) ; RV32I-NEXT: sh a1, 2(s0)
; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_urem_udiv: ; RV32IM-LABEL: combine_urem_udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 0(a1) ; RV32IM-NEXT: lhu a6, 0(a1)
; RV32IM-NEXT: lhu a7, 4(a1) ; RV32IM-NEXT: lhu a7, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
Show All 37 Lines
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_urem_udiv: ; RV64I-LABEL: combine_urem_udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 80(sp) ; RV64I-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 72(sp) ; RV64I-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 64(sp) ; RV64I-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 56(sp) ; RV64I-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 48(sp) ; RV64I-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 40(sp) ; RV64I-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 32(sp) ; RV64I-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 24(sp) ; RV64I-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 16(sp) ; RV64I-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 0(a1) ; RV64I-NEXT: lhu s2, 0(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s3, 8(a1)
; RV64I-NEXT: lhu s4, 16(a1) ; RV64I-NEXT: lhu s4, 16(a1)
; RV64I-NEXT: lhu s1, 24(a1) ; RV64I-NEXT: lhu s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: add a0, s8, a0 ; RV64I-NEXT: add a0, s8, a0
; RV64I-NEXT: add a1, s7, s1 ; RV64I-NEXT: add a1, s7, s1
; RV64I-NEXT: add a2, s6, s4 ; RV64I-NEXT: add a2, s6, s4
; RV64I-NEXT: add a3, s5, s9 ; RV64I-NEXT: add a3, s5, s9
; RV64I-NEXT: sh a3, 6(s0) ; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0) ; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0) ; RV64I-NEXT: sh a1, 2(s0)
; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 16(sp) ; RV64I-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 24(sp) ; RV64I-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 32(sp) ; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 40(sp) ; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 48(sp) ; RV64I-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 56(sp) ; RV64I-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 64(sp) ; RV64I-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 72(sp) ; RV64I-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 80(sp) ; RV64I-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_urem_udiv: ; RV64IM-LABEL: combine_urem_udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 0(a1) ; RV64IM-NEXT: lhu a6, 0(a1)
; RV64IM-NEXT: lhu a7, 8(a1) ; RV64IM-NEXT: lhu a7, 8(a1)
; RV64IM-NEXT: lhu a4, 16(a1) ; RV64IM-NEXT: lhu a4, 16(a1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; RV64IM-NEXT: ret
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_power_of_two: ; RV32I-LABEL: dont_fold_urem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 8(a1) ; RV32I-NEXT: lhu s2, 8(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s3, 4(a1)
; RV32I-NEXT: lhu s1, 0(a1) ; RV32I-NEXT: lhu s1, 0(a1)
; RV32I-NEXT: lhu a2, 12(a1) ; RV32I-NEXT: lhu a2, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: andi a1, s1, 63 ; RV32I-NEXT: andi a1, s1, 63
; RV32I-NEXT: andi a2, s3, 31 ; RV32I-NEXT: andi a2, s3, 31
; RV32I-NEXT: andi a3, s2, 7 ; RV32I-NEXT: andi a3, s2, 7
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh a3, 4(s0) ; RV32I-NEXT: sh a3, 4(s0)
; RV32I-NEXT: sh a2, 2(s0) ; RV32I-NEXT: sh a2, 2(s0)
; RV32I-NEXT: sh a1, 0(s0) ; RV32I-NEXT: sh a1, 0(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_power_of_two: ; RV32IM-LABEL: dont_fold_urem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 8(a1) ; RV32IM-NEXT: lhu a6, 8(a1)
; RV32IM-NEXT: lhu a3, 4(a1) ; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
Show All 15 Lines
; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a1, 0(a0)
; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_power_of_two: ; RV64I-LABEL: dont_fold_urem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 16(a1) ; RV64I-NEXT: lhu s2, 16(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s3, 8(a1)
; RV64I-NEXT: lhu s1, 0(a1) ; RV64I-NEXT: lhu s1, 0(a1)
; RV64I-NEXT: lhu a2, 24(a1) ; RV64I-NEXT: lhu a2, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: andi a1, s1, 63 ; RV64I-NEXT: andi a1, s1, 63
; RV64I-NEXT: andi a2, s3, 31 ; RV64I-NEXT: andi a2, s3, 31
; RV64I-NEXT: andi a3, s2, 7 ; RV64I-NEXT: andi a3, s2, 7
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh a3, 4(s0) ; RV64I-NEXT: sh a3, 4(s0)
; RV64I-NEXT: sh a2, 2(s0) ; RV64I-NEXT: sh a2, 2(s0)
; RV64I-NEXT: sh a1, 0(s0) ; RV64I-NEXT: sh a1, 0(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_power_of_two: ; RV64IM-LABEL: dont_fold_urem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 16(a1) ; RV64IM-NEXT: lhu a6, 16(a1)
; RV64IM-NEXT: lhu a3, 8(a1) ; RV64IM-NEXT: lhu a3, 8(a1)
; RV64IM-NEXT: lhu a4, 0(a1) ; RV64IM-NEXT: lhu a4, 0(a1)
Show All 26 Lines; RV64IM-NEXT: ret
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_one: ; RV32I-LABEL: dont_fold_urem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s1, 8(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu a2, 4(a1) ; RV32I-NEXT: lhu a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 654 ; RV32I-NEXT: addi a1, zero, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a1, zero, 23 ; RV32I-NEXT: addi a1, zero, 23
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s0)
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_one: ; RV32IM-LABEL: dont_fold_urem_one:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a2, 4(a1) ; RV32IM-NEXT: lhu a2, 4(a1)
; RV32IM-NEXT: lhu a3, 12(a1) ; RV32IM-NEXT: lhu a3, 12(a1)
; RV32IM-NEXT: lhu a1, 8(a1) ; RV32IM-NEXT: lhu a1, 8(a1)
Show All 24 Lines
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a1, 4(a0) ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_one: ; RV64I-LABEL: dont_fold_urem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s1, 16(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu a2, 8(a1) ; RV64I-NEXT: lhu a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s0)
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_one: ; RV64IM-LABEL: dont_fold_urem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 24(a1) ; RV64IM-NEXT: lhu a2, 24(a1)
; RV64IM-NEXT: lhu a3, 8(a1) ; RV64IM-NEXT: lhu a3, 8(a1)
; RV64IM-NEXT: lhu a1, 16(a1) ; RV64IM-NEXT: lhu a1, 16(a1)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 urem. ; Don't fold i64 urem.
define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind { define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i64: ; RV32I-LABEL: dont_fold_urem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s2, 24(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s3, 28(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s4, 16(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s5, 20(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s6, 8(a1)
; RV32I-NEXT: lw s1, 12(a1) ; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: addi a2, zero, 654 ; RV32I-NEXT: addi a2, zero, 654
; RV32I-NEXT: mv a0, s6 ; RV32I-NEXT: mv a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv s9, a1 ; RV32I-NEXT: mv s9, a1
; RV32I-NEXT: addi a2, zero, 23 ; RV32I-NEXT: addi a2, zero, 23
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a2, a0, 1327 ; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: sw a1, 28(s0) ; RV32I-NEXT: sw a1, 28(s0)
; RV32I-NEXT: sw a0, 24(s0) ; RV32I-NEXT: sw a0, 24(s0)
; RV32I-NEXT: sw s1, 20(s0) ; RV32I-NEXT: sw s1, 20(s0)
; RV32I-NEXT: sw s4, 16(s0) ; RV32I-NEXT: sw s4, 16(s0)
; RV32I-NEXT: sw s9, 12(s0) ; RV32I-NEXT: sw s9, 12(s0)
; RV32I-NEXT: sw s6, 8(s0) ; RV32I-NEXT: sw s6, 8(s0)
; RV32I-NEXT: sw s8, 4(s0) ; RV32I-NEXT: sw s8, 4(s0)
; RV32I-NEXT: sw s7, 0(s0) ; RV32I-NEXT: sw s7, 0(s0)
; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i64: ; RV32IM-LABEL: dont_fold_urem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: sw ra, 44(sp) ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 40(sp) ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 36(sp) ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 32(sp) ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s3, 28(sp) ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s4, 24(sp) ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s5, 20(sp) ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s6, 16(sp) ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s9, 4(sp) ; RV32IM-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s2, 24(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s3, 28(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s4, 16(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s5, 20(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s6, 8(a1)
; RV32IM-NEXT: lw s1, 12(a1) ; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0 ; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: addi a2, zero, 1 ; RV32IM-NEXT: addi a2, zero, 1
; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: addi a2, zero, 654 ; RV32IM-NEXT: addi a2, zero, 654
; RV32IM-NEXT: mv a0, s6 ; RV32IM-NEXT: mv a0, s6
; RV32IM-NEXT: mv a1, s1 ; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s6, a0 ; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: mv s9, a1 ; RV32IM-NEXT: mv s9, a1
; RV32IM-NEXT: addi a2, zero, 23 ; RV32IM-NEXT: addi a2, zero, 23
; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s1, a1 ; RV32IM-NEXT: mv s1, a1
; RV32IM-NEXT: lui a0, 1 ; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: addi a2, a0, 1327 ; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: sw a1, 28(s0) ; RV32IM-NEXT: sw a1, 28(s0)
; RV32IM-NEXT: sw a0, 24(s0) ; RV32IM-NEXT: sw a0, 24(s0)
; RV32IM-NEXT: sw s1, 20(s0) ; RV32IM-NEXT: sw s1, 20(s0)
; RV32IM-NEXT: sw s4, 16(s0) ; RV32IM-NEXT: sw s4, 16(s0)
; RV32IM-NEXT: sw s9, 12(s0) ; RV32IM-NEXT: sw s9, 12(s0)
; RV32IM-NEXT: sw s6, 8(s0) ; RV32IM-NEXT: sw s6, 8(s0)
; RV32IM-NEXT: sw s8, 4(s0) ; RV32IM-NEXT: sw s8, 4(s0)
; RV32IM-NEXT: sw s7, 0(s0) ; RV32IM-NEXT: sw s7, 0(s0)
; RV32IM-NEXT: lw s9, 4(sp) ; RV32IM-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s8, 8(sp) ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s7, 12(sp) ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s6, 16(sp) ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s5, 20(sp) ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s4, 24(sp) ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s3, 28(sp) ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 32(sp) ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw ra, 44(sp) ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i64: ; RV64I-LABEL: dont_fold_urem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s2, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: addi a1, zero, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sd zero, 0(s0) ; RV64I-NEXT: sd zero, 0(s0)
; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s0)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s0)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM-LABEL: dont_fold_urem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 24(a1) ; RV64IM-NEXT: ld a2, 24(a1)
; RV64IM-NEXT: ld a3, 8(a1) ; RV64IM-NEXT: ld a3, 8(a1)
; RV64IM-NEXT: ld a1, 16(a1) ; RV64IM-NEXT: ld a1, 16(a1)
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/vararg.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1: ; ILP32-ILP32F-WITHFP-LABEL: va1:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 48 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1
Show All 26 Lines
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%argp.cur = load i8*, i8** %va, align 4 %argp.cur = load i8*, i8** %va, align 4
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
store i8* %argp.next, i8** %va, align 4 store i8* %argp.next, i8** %va, align 4
Show All 18 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg: ; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, i32 %2 = va_arg i8** %va, i32
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %2 ret i32 %2
} }
; Ensure the adjustment when restoring the stack pointer using the frame ; Ensure the adjustment when restoring the stack pointer using the frame
; pointer is correct ; pointer is correct
define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind { define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va1_va_arg_alloca: ; ILP32-ILP32F-FPELIM-LABEL: va1_va_arg_alloca:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: sw s1, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi s0, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: mv s1, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv s1, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, s0, 8
; ILP32-ILP32F-FPELIM-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, -16(s0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a1, 15 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a1, 15
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -16
; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-FPELIM-NEXT: sub a0, sp, a0
; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0 ; ILP32-ILP32F-FPELIM-NEXT: mv sp, a0
; ILP32-ILP32F-FPELIM-NEXT: call notdead ; ILP32-ILP32F-FPELIM-NEXT: call notdead@plt
; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1 ; ILP32-ILP32F-FPELIM-NEXT: mv a0, s1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, s0, -16
; ILP32-ILP32F-FPELIM-NEXT: lw s1, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg_alloca: ; ILP32-ILP32F-WITHFP-LABEL: va1_va_arg_alloca:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s1, 4(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a1, 15 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a1, 15
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -16
; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: sub a0, sp, a0
; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: mv sp, a0
; ILP32-ILP32F-WITHFP-NEXT: call notdead ; ILP32-ILP32F-WITHFP-NEXT: call notdead@plt
; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, s1
; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, s0, -16
; ILP32-ILP32F-WITHFP-NEXT: lw s1, 4(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg_alloca: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_va_arg_alloca:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s1, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi s0, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi s0, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s1, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s1, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 8(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 8(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, s0, 8 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, s0, 8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, -16(s0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, -16(s0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a1, 15 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a1, 15
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub a0, sp, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv sp, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead@plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a0, s1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, s0, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s1, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg_alloca: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_va_arg_alloca:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: sd s1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: mv s1, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv s1, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a1, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a0, a0, 32 ; LP64-LP64F-LP64D-FPELIM-NEXT: srli a0, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 15 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 33 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 33
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, -16
; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: sub a0, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead ; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead@plt
; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, s1
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, s0, -32
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg_alloca: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1_va_arg_alloca:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a0, a0, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a0, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 15 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 33 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 33
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -16
; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: sub a0, sp, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv sp, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead ; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead@plt
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s1
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, s0, -32
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, i32 %2 = va_arg i8** %va, i32
%3 = alloca i8, i32 %2 %3 = alloca i8, i32 %2
call void @notdead(i8* %3) call void @notdead(i8* %3)
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %2 ret i32 %2
} }
define void @va1_caller() nounwind { define void @va1_caller() nounwind {
; Pass a double, as a float would be promoted by a C/C++ frontend ; Pass a double, as a float would be promoted by a C/C++ frontend
; ILP32-ILP32F-FPELIM-LABEL: va1_caller: ; ILP32-ILP32F-FPELIM-LABEL: va1_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2 ; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: call va1 ; ILP32-ILP32F-FPELIM-NEXT: call va1
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va1_caller: ; ILP32-ILP32F-WITHFP-LABEL: va1_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2 ; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: call va1 ; ILP32-ILP32F-WITHFP-NEXT: call va1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va1_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 2 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 2
; LP64-LP64F-LP64D-FPELIM-NEXT: call va1 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va1
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1_caller: ; LP64-LP64F-LP64D-WITHFP-LABEL: va1_caller:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 2 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 2
; LP64-LP64F-LP64D-WITHFP-NEXT: call va1 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va1
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2) %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
ret void ret void
} }
; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned" ; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
; register pair (where the first register is even-numbered). ; register pair (where the first register is even-numbered).
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; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4 ; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1) ; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va2: ; ILP32-ILP32F-WITHFP-LABEL: va2:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1) ; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va2: ; LP64-LP64F-LP64D-WITHFP-LABEL: va2:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, -8
; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = bitcast i8** %va to i32* %2 = bitcast i8** %va to i32*
%argp.cur = load i32, i32* %2, align 4 %argp.cur = load i32, i32* %2, align 4
%3 = add i32 %argp.cur, 7 %3 = add i32 %argp.cur, 7
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; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a2) ; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a2)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va2_va_arg: ; ILP32-ILP32F-WITHFP-LABEL: va2_va_arg:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: ori a2, a1, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a2, a1, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a2, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a2) ; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a2)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_va_arg: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_va_arg:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va2_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va2_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, double %2 = va_arg i8** %va, double
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
%3 = bitcast double %2 to i64 %3 = bitcast double %2 to i64
ret i64 %3 ret i64 %3
} }
define void @va2_caller() nounwind { define void @va2_caller() nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va2_caller: ; ILP32-ILP32F-FPELIM-LABEL: va2_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888 ; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: call va2 ; ILP32-ILP32F-FPELIM-NEXT: call va2
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va2_caller: ; ILP32-ILP32F-WITHFP-LABEL: va2_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888 ; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: call va2 ; ILP32-ILP32F-WITHFP-NEXT: call va2
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va2_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va2_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-FPELIM-NEXT: call va2 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va2
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va2_caller: ; LP64-LP64F-LP64D-WITHFP-LABEL: va2_caller:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-WITHFP-NEXT: call va2 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va2
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%1 = call i64 (i8*, ...) @va2(i8* undef, double 1.000000e+00) %1 = call i64 (i8*, ...) @va2(i8* undef, double 1.000000e+00)
ret void ret void
} }
; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the ; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the
; vararg double is passed in a4 and a5 (rather than a3 and a4) ; vararg double is passed in a4 and a5 (rather than a3 and a4)
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; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a4 ; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a4
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3: ; ILP32-ILP32F-WITHFP-LABEL: va3:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: ori a0, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a0, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a3 ; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a3
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a4 ; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a4
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va3: ; LP64-LP64F-LP64D-WITHFP-LABEL: va3:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, -8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, -8
; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a2 ; LP64-LP64F-LP64D-WITHFP-NEXT: and a0, a0, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = bitcast i8** %va to i32* %2 = bitcast i8** %va to i32*
%argp.cur = load i32, i32* %2, align 4 %argp.cur = load i32, i32* %2, align 4
%3 = add i32 %argp.cur, 7 %3 = add i32 %argp.cur, 7
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; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3 ; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg: ; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 20(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3) ; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3)
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a4 ; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a4
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3 ; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
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; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va3_va_arg: ; LP64-LP64F-LP64D-WITHFP-LABEL: va3_va_arg:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a3, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a3, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, double %2 = va_arg i8** %va, double
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
%3 = bitcast double %2 to i64 %3 = bitcast double %2 to i64
%4 = add i64 %b, %3 %4 = add i64 %b, %3
ret i64 %4 ret i64 %4
} }
define void @va3_caller() nounwind { define void @va3_caller() nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va3_caller: ; ILP32-ILP32F-FPELIM-LABEL: va3_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -16
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 2 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 2
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 1111 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 1111
; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144 ; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero ; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero
; ILP32-ILP32F-FPELIM-NEXT: call va3 ; ILP32-ILP32F-FPELIM-NEXT: call va3
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va3_caller: ; ILP32-ILP32F-WITHFP-LABEL: va3_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -16
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 2 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 2
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 1111 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 1111
; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144 ; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero ; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero
; ILP32-ILP32F-WITHFP-NEXT: call va3 ; ILP32-ILP32F-WITHFP-NEXT: call va3
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 1111 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 1111
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 62 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 62
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 2 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 2
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1111 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1111
; LP64-LP64F-LP64D-FPELIM-NEXT: call va3 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va3
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va3_caller: ; LP64-LP64F-LP64D-WITHFP-LABEL: va3_caller:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 62 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 62
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 2 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 2
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1111 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1111
; LP64-LP64F-LP64D-WITHFP-NEXT: call va3 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va3
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00) %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00)
ret void ret void
} }
declare void @llvm.va_copy(i8*, i8*) declare void @llvm.va_copy(i8*, i8*)
define i32 @va4_va_copy(i32 %argno, ...) nounwind { define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; ILP32-ILP32F-FPELIM-LABEL: va4_va_copy: ; ILP32-ILP32F-FPELIM-LABEL: va4_va_copy:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: mv s0, a1 ; ILP32-ILP32F-FPELIM-NEXT: mv s0, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 24 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 0(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 0(sp)
; ILP32-ILP32F-FPELIM-NEXT: call notdead ; ILP32-ILP32F-FPELIM-NEXT: call notdead@plt
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw a0, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 3 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 3
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4
; ILP32-ILP32F-FPELIM-NEXT: addi a2, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a2, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a2, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: lw a2, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 7
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -4
; ILP32-ILP32F-FPELIM-NEXT: addi a3, a0, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, s0 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, s0
; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, a2 ; ILP32-ILP32F-FPELIM-NEXT: add a1, a1, a2
; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0 ; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0
; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy: ; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 28(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 24(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s1, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 32 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 32
; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv s1, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -20(s0)
; ILP32-ILP32F-WITHFP-NEXT: call notdead ; ILP32-ILP32F-WITHFP-NEXT: call notdead@plt
; ILP32-ILP32F-WITHFP-NEXT: lw a0, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 3 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 3
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4
; ILP32-ILP32F-WITHFP-NEXT: addi a2, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a2, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a2, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a2, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 7
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4 ; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -4
; ILP32-ILP32F-WITHFP-NEXT: addi a3, a0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, -16(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0) ; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, s1 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, s1
; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, a2 ; ILP32-ILP32F-WITHFP-NEXT: add a1, a1, a2
; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0 ; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0
; ILP32-ILP32F-WITHFP-NEXT: lw s1, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 24(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 28(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s0, a1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv s0, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 24 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 24
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 0(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 0(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call notdead@plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 3 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 3
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a2, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a2, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 7
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, a0, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, s0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, s0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, a2 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a1, a2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy: ; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: mv s0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: mv s0, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 88(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 88(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 80(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 80(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 72(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 64(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 40 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 40
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead ; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead@plt
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 3 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 3
; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a1, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a1, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a2, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a2, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-FPELIM-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, s0
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: addw a0, a1, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy: ; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -112 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -112
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48
; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv s1, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead ; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead@plt
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 3 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 3
; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a1, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a1, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a2, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a2, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 11
; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4 ; LP64-LP64F-LP64D-WITHFP-NEXT: andi a0, a0, -4
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0)
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, s1
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: addw a0, a1, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: addw a0, a1, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 112 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 112
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%vargs = alloca i8*, align 4 %vargs = alloca i8*, align 4
%wargs = alloca i8*, align 4 %wargs = alloca i8*, align 4
%1 = bitcast i8** %vargs to i8* %1 = bitcast i8** %vargs to i8*
%2 = bitcast i8** %wargs to i8* %2 = bitcast i8** %wargs to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%3 = va_arg i8** %vargs, i32 %3 = va_arg i8** %vargs, i32
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declare i32 @va5_aligned_stack_callee(i32, ...) declare i32 @va5_aligned_stack_callee(i32, ...)
define void @va5_aligned_stack_caller() nounwind { define void @va5_aligned_stack_caller() nounwind {
; The double should be 8-byte aligned on the stack, but the two-element array ; The double should be 8-byte aligned on the stack, but the two-element array
; should only be 4-byte aligned ; should only be 4-byte aligned
; ILP32-ILP32F-FPELIM-LABEL: va5_aligned_stack_caller: ; ILP32-ILP32F-FPELIM-LABEL: va5_aligned_stack_caller:
; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -64 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -64
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 60(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 17 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 17
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 24(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 16 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 16
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 15 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 15
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 262236 ; ILP32-ILP32F-FPELIM-NEXT: lui a0, 262236
; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 655 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 655
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; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048 ; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1 ; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11
; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32 ; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12 ; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13 ; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13
; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4 ; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-FPELIM-NEXT: call va5_aligned_stack_callee@plt
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp) ; ILP32-ILP32F-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 64
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller: ; ILP32-ILP32F-WITHFP-LABEL: va5_aligned_stack_caller:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -64
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 60(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 56(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 64 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 64
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 17 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 17
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 24(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, 24(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 20(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, 20(sp)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 15 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 15
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 16(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, 16(sp)
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 262236 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 262236
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; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048 ; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11
; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12 ; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13 ; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13
; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a5, -32(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, -32(s0)
; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee ; ILP32-ILP32F-WITHFP-NEXT: call va5_aligned_stack_callee@plt
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 64
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va5_aligned_stack_caller:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -64 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -64
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 60(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 262236 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 262236
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 655 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 655
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 377487 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 377487
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 1475 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 1475
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 8(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 8(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 17 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 17
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 24(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 24(sp)
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; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va5_aligned_stack_callee@plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 64
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller: ; LP64-LP64F-LP64D-FPELIM-LABEL: va5_aligned_stack_caller:
; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM: # %bb.0:
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -48 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -48
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 17 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 17
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 16 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 15 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 15
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2049 ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2049
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, -1147 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, -1147
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; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14 ; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, -1967 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, a0, -1967
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 11
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a4, zero, 12 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a4, zero, 12
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a5, zero, 13 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a5, zero, 13
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a7, zero, 14 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi a7, zero, 14
; LP64-LP64F-LP64D-FPELIM-NEXT: sd t0, 0(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd t0, 0(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-FPELIM-NEXT: call va5_aligned_stack_callee@plt
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 48
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller: ; LP64-LP64F-LP64D-WITHFP-LABEL: va5_aligned_stack_caller:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -48
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 48
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 17 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 17
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 24(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 16 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 16(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 15 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 15
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2049 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2049
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; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14 ; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, -1967 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, a0, -1967
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 11
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a4, zero, 12 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a4, zero, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a5, zero, 13 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a5, zero, 13
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a7, zero, 14 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a7, zero, 14
; LP64-LP64F-LP64D-WITHFP-NEXT: sd t0, 0(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd t0, 0(sp)
; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee ; LP64-LP64F-LP64D-WITHFP-NEXT: call va5_aligned_stack_callee@plt
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 48
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11, %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17]) i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
ret void ret void
} }
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; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 20 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 20
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va6_no_fixed_args: ; ILP32-ILP32F-WITHFP-LABEL: va6_no_fixed_args:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -48
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a0, 0(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 4 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va6_no_fixed_args: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va6_no_fixed_args:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
Show All 23 Lines
; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8 ; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va6_no_fixed_args: ; LP64-LP64F-LP64D-WITHFP-LABEL: va6_no_fixed_args:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -96
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0 ; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%2 = va_arg i8** %va, i32 %2 = va_arg i8** %va, i32
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %2 ret i32 %2
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304 ; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304
; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1 ; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1
; ILP32-ILP32F-FPELIM-NEXT: ret ; ILP32-ILP32F-FPELIM-NEXT: ret
; ;
; ILP32-ILP32F-WITHFP-LABEL: va_large_stack: ; ILP32-ILP32F-WITHFP-LABEL: va_large_stack:
; ILP32-ILP32F-WITHFP: # %bb.0: ; ILP32-ILP32F-WITHFP: # %bb.0:
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -2032 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, -2032
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; ILP32-ILP32F-WITHFP-NEXT: sw ra, 1996(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw ra, 1996(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 1992(sp) ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 1992(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 2000 ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 2000
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32 ; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 24414 ; ILP32-ILP32F-WITHFP-NEXT: lui a0, 24414
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1728 ; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1728
; ILP32-ILP32F-WITHFP-NEXT: sub sp, sp, a0 ; ILP32-ILP32F-WITHFP-NEXT: sub sp, sp, a0
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1 ; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: lui a2, 1024162 ; ILP32-ILP32F-WITHFP-NEXT: lui a2, 1024162
; ILP32-ILP32F-WITHFP-NEXT: addi a2, a2, -272 ; ILP32-ILP32F-WITHFP-NEXT: addi a2, a2, -272
; ILP32-ILP32F-WITHFP-NEXT: add a2, s0, a2 ; ILP32-ILP32F-WITHFP-NEXT: add a2, s0, a2
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 0(a2) ; ILP32-ILP32F-WITHFP-NEXT: sw a1, 0(a2)
; ILP32-ILP32F-WITHFP-NEXT: lui a1, 24414 ; ILP32-ILP32F-WITHFP-NEXT: lui a1, 24414
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728 ; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728
; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1 ; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp) ; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032 ; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032
; ILP32-ILP32F-WITHFP-NEXT: ret ; ILP32-ILP32F-WITHFP-NEXT: ret
; ;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 24414 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 304 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, a0, 304
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub sp, sp, a0 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sub sp, sp, a0
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; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336
; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; LP64-LP64F-LP64D-FPELIM-NEXT: ret
; ;
; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack: ; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack:
; LP64-LP64F-LP64D-WITHFP: # %bb.0: ; LP64-LP64F-LP64D-WITHFP: # %bb.0:
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, -2032
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 1960(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 1960(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 1952(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 1952(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 1968 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 1968
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64 ; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 24414 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 24414
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1680 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1680
; LP64-LP64F-LP64D-WITHFP-NEXT: sub sp, sp, a0 ; LP64-LP64F-LP64D-WITHFP-NEXT: sub sp, sp, a0
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4 ; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 1024162 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 1024162
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -288 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -288
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, s0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, s0, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(a1) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(a1)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680
; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032 ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032
; LP64-LP64F-LP64D-WITHFP-NEXT: ret ; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%large = alloca [ 100000000 x i8 ] %large = alloca [ 100000000 x i8 ]
%va = alloca i8*, align 4 %va = alloca i8*, align 4
%1 = bitcast i8** %va to i8* %1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %1) call void @llvm.va_start(i8* %1)
%argp.cur = load i8*, i8** %va, align 4 %argp.cur = load i8*, i8** %va, align 4
%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
store i8* %argp.next, i8** %va, align 4 store i8* %argp.next, i8** %va, align 4
%2 = bitcast i8* %argp.cur to i32* %2 = bitcast i8* %argp.cur to i32*
%3 = load i32, i32* %2, align 4 %3 = load i32, i32* %2, align 4
call void @llvm.va_end(i8* %1) call void @llvm.va_end(i8* %1)
ret i32 %3 ret i32 %3
} }
llvm/test/CodeGen/RISCV/atomic-load-store.ll