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Differential D92841

[RISCV][NFC] Regenerate RISCV CodeGen tests
ClosedPublic

Authored by mundaym on Dec 8 2020, 6:05 AM.

Details

Reviewers
asb
luismarques
lenary
Commits
rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests
Summary

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Diff Detail

Event Timeline

mundaym created this revision.Dec 8 2020, 6:05 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 28 others. · View Herald TranscriptDec 8 2020, 6:05 AM
mundaym requested review of this revision.Dec 8 2020, 6:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 8 2020, 6:05 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
mundaym added reviewers: asb, luismarques, lenary.Dec 8 2020, 6:09 AM
lenary added a comment.Dec 8 2020, 6:48 AM

The spills look right to me. The question we're not sure of is the appearance of the @plt suffixes on all the external calls.

jrtc27 added a comment.Dec 8 2020, 7:00 AM
In D92841#2439763, @lenary wrote:

The spills look right to me. The question we're not sure of is the appearance of the @plt suffixes on all the external calls.

RISC-V's calls are a mess. Without @plt you get an R_RISCV_CALL, and with @plt you get an R_RISCV_CALL_PLT. In LLD both are treated identically. In binutils, the latter always works (it'll get a PLT stub if needed, but not otherwise), whereas the former can cause weird things to happen if you need a PLT stub (and it's dependent on what other relocations for the symbol exist IIRC). Basically, R_RISCV_CALL should never have existed and R_RISCV_CALL_PLT should have been R_RISCV_CALL, but if you want to support linking with binutils then you need the @plt suffix unless you know the symbol will always be local.

See https://github.com/riscv/riscv-elf-psabi-doc/issues/98, https://sourceware.org/bugzilla/show_bug.cgi?id=24685 and D63076.

@MaskRay am I missing anything?

Harbormaster completed remote builds in B81439: Diff 310163.Dec 8 2020, 7:01 AM
lenary added a comment.Dec 8 2020, 1:05 PM

@jrtc27 it sounds like adding @plt into all the tests won't break anything, and will catch if future changes default to non-plt calls, so this change is an improvement?

jrtc27 added a comment.Dec 8 2020, 1:06 PM
In D92841#2440962, @lenary wrote:

@jrtc27 it sounds like adding @plt into all the tests won't break anything, and will catch if future changes default to non-plt calls, so this change is an improvement?

Yes I believe so.

lenary accepted this revision.Dec 8 2020, 2:19 PM

LGTM

This revision is now accepted and ready to land.Dec 8 2020, 2:19 PM
This revision was landed with ongoing or failed builds.Dec 9 2020, 11:43 AM
Closed by commit rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests (authored by mundaym, committed by luismarques). · Explain Why
This revision was automatically updated to reflect the committed changes.
luismarques added a commit: rGe28b6a60bc02: [RISCV][NFC] Regenerate RISCV CodeGen tests.

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Diff 310592

llvm/test/CodeGen/RISCV/alloca.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
declare void @notdead(i8*) declare void @notdead(i8*)
; These tests must ensure the stack pointer is restored using the frame ; These tests must ensure the stack pointer is restored using the frame
; pointer ; pointer
define void @simple_alloca(i32 %n) nounwind { define void @simple_alloca(i32 %n) nounwind {
; RV32I-LABEL: simple_alloca: ; RV32I-LABEL: simple_alloca:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: call notdead ; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
call void @notdead(i8* %1) call void @notdead(i8* %1)
ret void ret void
} }
declare i8* @llvm.stacksave() declare i8* @llvm.stacksave()
declare void @llvm.stackrestore(i8*) declare void @llvm.stackrestore(i8*)
define void @scoped_alloca(i32 %n) nounwind { define void @scoped_alloca(i32 %n) nounwind {
; RV32I-LABEL: scoped_alloca: ; RV32I-LABEL: scoped_alloca:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv s1, sp ; RV32I-NEXT: mv s1, sp
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: call notdead ; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: mv sp, s1 ; RV32I-NEXT: mv sp, s1
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%sp = call i8* @llvm.stacksave() %sp = call i8* @llvm.stacksave()
%addr = alloca i8, i32 %n %addr = alloca i8, i32 %n
call void @notdead(i8* %addr) call void @notdead(i8* %addr)
call void @llvm.stackrestore(i8* %sp) call void @llvm.stackrestore(i8* %sp)
ret void ret void
} }
declare void @func(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @func(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
; Check that outgoing arguments passed on the stack do not corrupt a ; Check that outgoing arguments passed on the stack do not corrupt a
; variable-sized stack object. ; variable-sized stack object.
define void @alloca_callframe(i32 %n) nounwind { define void @alloca_callframe(i32 %n) nounwind {
; RV32I-LABEL: alloca_callframe: ; RV32I-LABEL: alloca_callframe:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 15 ; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a1, zero, 12 ; RV32I-NEXT: addi a1, zero, 12
; RV32I-NEXT: sw a1, 12(sp) ; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a1, zero, 11 ; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, zero, 10 ; RV32I-NEXT: addi a1, zero, 10
; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi t0, zero, 9 ; RV32I-NEXT: addi t0, zero, 9
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 6 ; RV32I-NEXT: addi a5, zero, 6
; RV32I-NEXT: addi a6, zero, 7 ; RV32I-NEXT: addi a6, zero, 7
; RV32I-NEXT: addi a7, zero, 8 ; RV32I-NEXT: addi a7, zero, 8
; RV32I-NEXT: sw t0, 0(sp) ; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: call func ; RV32I-NEXT: call func@plt
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = alloca i8, i32 %n %1 = alloca i8, i32 %n
call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, call void @func(i8* %1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8,
i32 9, i32 10, i32 11, i32 12) i32 9, i32 10, i32 11, i32 12)
ret void ret void
} }

llvm/test/CodeGen/RISCV/analyze-branch.ll

Show All 10 Lines
; !0 corresponds to a branch being taken, !1 to not being takne. ; !0 corresponds to a branch being taken, !1 to not being takne.
!0 = !{!"branch_weights", i32 64, i32 4} !0 = !{!"branch_weights", i32 64, i32 4}
!1 = !{!"branch_weights", i32 4, i32 64} !1 = !{!"branch_weights", i32 4, i32 64}
define void @test_bcc_fallthrough_taken(i32 %in) nounwind { define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
; RV32I-LABEL: test_bcc_fallthrough_taken: ; RV32I-LABEL: test_bcc_fallthrough_taken:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3 ; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true ; RV32I-NEXT: # %bb.1: # %true
; RV32I-NEXT: call test_true ; RV32I-NEXT: call test_true@plt
; RV32I-NEXT: .LBB0_2: # %true ; RV32I-NEXT: .LBB0_2: # %true
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_3: # %false ; RV32I-NEXT: .LBB0_3: # %false
; RV32I-NEXT: call test_false ; RV32I-NEXT: call test_false@plt
; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: j .LBB0_2
%tst = icmp eq i32 %in, 42 %tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !0 br i1 %tst, label %true, label %false, !prof !0
; Expected layout order is: Entry, TrueBlock, FalseBlock ; Expected layout order is: Entry, TrueBlock, FalseBlock
; Entry->TrueBlock is the common path, which should be taken whenever the ; Entry->TrueBlock is the common path, which should be taken whenever the
; conditional branch is false. ; conditional branch is false.
true: true:
call void @test_true() call void @test_true()
ret void ret void
false: false:
call void @test_false() call void @test_false()
ret void ret void
} }
define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind { define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I-LABEL: test_bcc_fallthrough_nottaken: ; RV32I-LABEL: test_bcc_fallthrough_nottaken:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3 ; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false ; RV32I-NEXT: # %bb.1: # %false
; RV32I-NEXT: call test_false ; RV32I-NEXT: call test_false@plt
; RV32I-NEXT: .LBB1_2: # %true ; RV32I-NEXT: .LBB1_2: # %true
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_3: # %true ; RV32I-NEXT: .LBB1_3: # %true
; RV32I-NEXT: call test_true ; RV32I-NEXT: call test_true@plt
; RV32I-NEXT: j .LBB1_2 ; RV32I-NEXT: j .LBB1_2
%tst = icmp eq i32 %in, 42 %tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !1 br i1 %tst, label %true, label %false, !prof !1
; Expected layout order is: Entry, FalseBlock, TrueBlock ; Expected layout order is: Entry, FalseBlock, TrueBlock
; Entry->FalseBlock is the common path, which should be taken whenever the ; Entry->FalseBlock is the common path, which should be taken whenever the
; conditional branch is false ; conditional branch is false
Show All 10 Lines

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: .LBB0_3: ; RV32IA-NEXT: .LBB0_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: .LBB1_3: ; RV32IA-NEXT: .LBB1_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acquire_acquire: ; RV32I-LABEL: cmpxchg_i8_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w a5, a5, (a3) ; RV32IA-NEXT: sc.w a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: .LBB2_3: ; RV32IA-NEXT: .LBB2_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acquire_acquire: ; RV64I-LABEL: cmpxchg_i8_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_monotonic: ; RV32I-LABEL: cmpxchg_i8_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_monotonic: ; RV32IA-LABEL: cmpxchg_i8_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: .LBB3_3: ; RV32IA-NEXT: .LBB3_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_monotonic: ; RV64I-LABEL: cmpxchg_i8_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_monotonic: ; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_release_acquire: ; RV32I-LABEL: cmpxchg_i8_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_release_acquire: ; RV32IA-LABEL: cmpxchg_i8_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: .LBB4_3: ; RV32IA-NEXT: .LBB4_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_release_acquire: ; RV64I-LABEL: cmpxchg_i8_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_release_acquire: ; RV64IA-LABEL: cmpxchg_i8_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: .LBB5_3: ; RV32IA-NEXT: .LBB5_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.rl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: .LBB6_3: ; RV32IA-NEXT: .LBB6_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: .LBB7_3: ; RV32IA-NEXT: .LBB7_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: .LBB8_3: ; RV32IA-NEXT: .LBB8_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sb a1, 11(sp) ; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11 ; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 14 Lines
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: .LBB9_3: ; RV32IA-NEXT: .LBB9_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sb a1, 7(sp) ; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7 ; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 18 Lines; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB10_1 ; RV32IA-NEXT: bnez a4, .LBB10_1
; RV32IA-NEXT: .LBB10_3: ; RV32IA-NEXT: .LBB10_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB11_1 ; RV32IA-NEXT: bnez a4, .LBB11_1
; RV32IA-NEXT: .LBB11_3: ; RV32IA-NEXT: .LBB11_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acquire_acquire: ; RV32I-LABEL: cmpxchg_i16_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w a4, a4, (a3) ; RV32IA-NEXT: sc.w a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB12_1 ; RV32IA-NEXT: bnez a4, .LBB12_1
; RV32IA-NEXT: .LBB12_3: ; RV32IA-NEXT: .LBB12_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acquire_acquire: ; RV64I-LABEL: cmpxchg_i16_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_monotonic: ; RV32I-LABEL: cmpxchg_i16_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_monotonic: ; RV32IA-LABEL: cmpxchg_i16_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB13_1 ; RV32IA-NEXT: bnez a4, .LBB13_1
; RV32IA-NEXT: .LBB13_3: ; RV32IA-NEXT: .LBB13_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_monotonic: ; RV64I-LABEL: cmpxchg_i16_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_monotonic: ; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_release_acquire: ; RV32I-LABEL: cmpxchg_i16_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_release_acquire: ; RV32IA-LABEL: cmpxchg_i16_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB14_1 ; RV32IA-NEXT: bnez a4, .LBB14_1
; RV32IA-NEXT: .LBB14_3: ; RV32IA-NEXT: .LBB14_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_release_acquire: ; RV64I-LABEL: cmpxchg_i16_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_release_acquire: ; RV64IA-LABEL: cmpxchg_i16_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB15_1 ; RV32IA-NEXT: bnez a4, .LBB15_1
; RV32IA-NEXT: .LBB15_3: ; RV32IA-NEXT: .LBB15_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.rl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB16_1 ; RV32IA-NEXT: bnez a4, .LBB16_1
; RV32IA-NEXT: .LBB16_3: ; RV32IA-NEXT: .LBB16_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB17_1 ; RV32IA-NEXT: bnez a4, .LBB17_1
; RV32IA-NEXT: .LBB17_3: ; RV32IA-NEXT: .LBB17_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB18_1 ; RV32IA-NEXT: bnez a4, .LBB18_1
; RV32IA-NEXT: .LBB18_3: ; RV32IA-NEXT: .LBB18_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind {
; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a3, a0, -4 ; RV32IA-NEXT: andi a3, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB19_1 ; RV32IA-NEXT: bnez a4, .LBB19_1
; RV32IA-NEXT: .LBB19_3: ; RV32IA-NEXT: .LBB19_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB20_3 ; RV32IA-NEXT: bne a3, a1, .LBB20_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB20_1 ; RV32IA-NEXT: bnez a4, .LBB20_1
; RV32IA-NEXT: .LBB20_3: ; RV32IA-NEXT: .LBB20_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB20_3 ; RV64IA-NEXT: bne a3, a1, .LBB20_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB20_1 ; RV64IA-NEXT: bnez a4, .LBB20_1
; RV64IA-NEXT: .LBB20_3: ; RV64IA-NEXT: .LBB20_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i32_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i32_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB21_3 ; RV32IA-NEXT: bne a3, a1, .LBB21_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB21_1 ; RV32IA-NEXT: bnez a4, .LBB21_1
; RV32IA-NEXT: .LBB21_3: ; RV32IA-NEXT: .LBB21_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB21_3 ; RV64IA-NEXT: bne a3, a1, .LBB21_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB21_1 ; RV64IA-NEXT: bnez a4, .LBB21_1
; RV64IA-NEXT: .LBB21_3: ; RV64IA-NEXT: .LBB21_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acquire_acquire: ; RV32I-LABEL: cmpxchg_i32_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i32_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB22_3 ; RV32IA-NEXT: bne a3, a1, .LBB22_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV32IA-NEXT: sc.w a4, a2, (a0) ; RV32IA-NEXT: sc.w a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB22_1 ; RV32IA-NEXT: bnez a4, .LBB22_1
; RV32IA-NEXT: .LBB22_3: ; RV32IA-NEXT: .LBB22_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acquire_acquire: ; RV64I-LABEL: cmpxchg_i32_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB22_3 ; RV64IA-NEXT: bne a3, a1, .LBB22_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV64IA-NEXT: sc.w a4, a2, (a0) ; RV64IA-NEXT: sc.w a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB22_1 ; RV64IA-NEXT: bnez a4, .LBB22_1
; RV64IA-NEXT: .LBB22_3: ; RV64IA-NEXT: .LBB22_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_release_monotonic: ; RV32I-LABEL: cmpxchg_i32_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_release_monotonic: ; RV32IA-LABEL: cmpxchg_i32_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB23_3 ; RV32IA-NEXT: bne a3, a1, .LBB23_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB23_1 ; RV32IA-NEXT: bnez a4, .LBB23_1
; RV32IA-NEXT: .LBB23_3: ; RV32IA-NEXT: .LBB23_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_release_monotonic: ; RV64I-LABEL: cmpxchg_i32_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_release_monotonic: ; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB23_3 ; RV64IA-NEXT: bne a3, a1, .LBB23_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB23_1 ; RV64IA-NEXT: bnez a4, .LBB23_1
; RV64IA-NEXT: .LBB23_3: ; RV64IA-NEXT: .LBB23_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_release_acquire: ; RV32I-LABEL: cmpxchg_i32_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_release_acquire: ; RV32IA-LABEL: cmpxchg_i32_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a0) ; RV32IA-NEXT: lr.w a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB24_3 ; RV32IA-NEXT: bne a3, a1, .LBB24_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB24_1 ; RV32IA-NEXT: bnez a4, .LBB24_1
; RV32IA-NEXT: .LBB24_3: ; RV32IA-NEXT: .LBB24_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_release_acquire: ; RV64I-LABEL: cmpxchg_i32_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_release_acquire: ; RV64IA-LABEL: cmpxchg_i32_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0) ; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB24_3 ; RV64IA-NEXT: bne a3, a1, .LBB24_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB24_1 ; RV64IA-NEXT: bnez a4, .LBB24_1
; RV64IA-NEXT: .LBB24_3: ; RV64IA-NEXT: .LBB24_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
ret void ret void
} }
define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB25_3 ; RV32IA-NEXT: bne a3, a1, .LBB25_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB25_1 ; RV32IA-NEXT: bnez a4, .LBB25_1
; RV32IA-NEXT: .LBB25_3: ; RV32IA-NEXT: .LBB25_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB25_3 ; RV64IA-NEXT: bne a3, a1, .LBB25_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB25_1 ; RV64IA-NEXT: bnez a4, .LBB25_1
; RV64IA-NEXT: .LBB25_3: ; RV64IA-NEXT: .LBB25_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a0) ; RV32IA-NEXT: lr.w.aq a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB26_3 ; RV32IA-NEXT: bne a3, a1, .LBB26_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
; RV32IA-NEXT: sc.w.rl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB26_1 ; RV32IA-NEXT: bnez a4, .LBB26_1
; RV32IA-NEXT: .LBB26_3: ; RV32IA-NEXT: .LBB26_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0) ; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB26_3 ; RV64IA-NEXT: bne a3, a1, .LBB26_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
; RV64IA-NEXT: sc.w.rl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB26_1 ; RV64IA-NEXT: bnez a4, .LBB26_1
; RV64IA-NEXT: .LBB26_3: ; RV64IA-NEXT: .LBB26_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB27_3 ; RV32IA-NEXT: bne a3, a1, .LBB27_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB27_1 ; RV32IA-NEXT: bnez a4, .LBB27_1
; RV32IA-NEXT: .LBB27_3: ; RV32IA-NEXT: .LBB27_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB27_3 ; RV64IA-NEXT: bne a3, a1, .LBB27_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB27_1 ; RV64IA-NEXT: bnez a4, .LBB27_1
; RV64IA-NEXT: .LBB27_3: ; RV64IA-NEXT: .LBB27_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB28_3 ; RV32IA-NEXT: bne a3, a1, .LBB28_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB28_1 ; RV32IA-NEXT: bnez a4, .LBB28_1
; RV32IA-NEXT: .LBB28_3: ; RV32IA-NEXT: .LBB28_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB28_3 ; RV64IA-NEXT: bne a3, a1, .LBB28_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB28_1 ; RV64IA-NEXT: bnez a4, .LBB28_1
; RV64IA-NEXT: .LBB28_3: ; RV64IA-NEXT: .LBB28_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind {
; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a1, 8(sp) ; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB29_3 ; RV32IA-NEXT: bne a3, a1, .LBB29_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB29_1 ; RV32IA-NEXT: bnez a4, .LBB29_1
; RV32IA-NEXT: .LBB29_3: ; RV32IA-NEXT: .LBB29_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB29_3 ; RV64IA-NEXT: bne a3, a1, .LBB29_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB29_1 ; RV64IA-NEXT: bnez a4, .LBB29_1
; RV64IA-NEXT: .LBB29_3: ; RV64IA-NEXT: .LBB29_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV32IA-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4 ; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV64I-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic: ; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB30_3 ; RV64IA-NEXT: bne a3, a1, .LBB30_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB30_1 ; RV64IA-NEXT: bnez a4, .LBB30_1
; RV64IA-NEXT: .LBB30_3: ; RV64IA-NEXT: .LBB30_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
ret void ret void
} }
define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64I-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic: ; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB31_3 ; RV64IA-NEXT: bne a3, a1, .LBB31_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB31_1 ; RV64IA-NEXT: bnez a4, .LBB31_1
; RV64IA-NEXT: .LBB31_3: ; RV64IA-NEXT: .LBB31_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
ret void ret void
} }
define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acquire_acquire: ; RV32I-LABEL: cmpxchg_i64_acquire_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acquire_acquire: ; RV32IA-LABEL: cmpxchg_i64_acquire_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acquire_acquire: ; RV64I-LABEL: cmpxchg_i64_acquire_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acquire_acquire: ; RV64IA-LABEL: cmpxchg_i64_acquire_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB32_3 ; RV64IA-NEXT: bne a3, a1, .LBB32_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
; RV64IA-NEXT: sc.d a4, a2, (a0) ; RV64IA-NEXT: sc.d a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB32_1 ; RV64IA-NEXT: bnez a4, .LBB32_1
; RV64IA-NEXT: .LBB32_3: ; RV64IA-NEXT: .LBB32_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
ret void ret void
} }
define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_monotonic: ; RV32I-LABEL: cmpxchg_i64_release_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_monotonic: ; RV32IA-LABEL: cmpxchg_i64_release_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_monotonic: ; RV64I-LABEL: cmpxchg_i64_release_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_release_monotonic: ; RV64IA-LABEL: cmpxchg_i64_release_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB33_3 ; RV64IA-NEXT: bne a3, a1, .LBB33_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB33_1 ; RV64IA-NEXT: bnez a4, .LBB33_1
; RV64IA-NEXT: .LBB33_3: ; RV64IA-NEXT: .LBB33_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
ret void ret void
} }
define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_release_acquire: ; RV32I-LABEL: cmpxchg_i64_release_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_release_acquire: ; RV32IA-LABEL: cmpxchg_i64_release_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_release_acquire: ; RV64I-LABEL: cmpxchg_i64_release_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_release_acquire: ; RV64IA-LABEL: cmpxchg_i64_release_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a3, (a0) ; RV64IA-NEXT: lr.d a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB34_3 ; RV64IA-NEXT: bne a3, a1, .LBB34_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB34_1 ; RV64IA-NEXT: bnez a4, .LBB34_1
; RV64IA-NEXT: .LBB34_3: ; RV64IA-NEXT: .LBB34_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic: ; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB35_3 ; RV64IA-NEXT: bne a3, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB35_1 ; RV64IA-NEXT: bnez a4, .LBB35_1
; RV64IA-NEXT: .LBB35_3: ; RV64IA-NEXT: .LBB35_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void ret void
} }
define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire: ; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a3, (a0) ; RV64IA-NEXT: lr.d.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB36_3 ; RV64IA-NEXT: bne a3, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: sc.d.rl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB36_1 ; RV64IA-NEXT: bnez a4, .LBB36_1
; RV64IA-NEXT: .LBB36_3: ; RV64IA-NEXT: .LBB36_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5 ; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5 ; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB37_3 ; RV64IA-NEXT: bne a3, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB37_1 ; RV64IA-NEXT: bnez a4, .LBB37_1
; RV64IA-NEXT: .LBB37_3: ; RV64IA-NEXT: .LBB37_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB38_3 ; RV64IA-NEXT: bne a3, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB38_1 ; RV64IA-NEXT: bnez a4, .LBB38_1
; RV64IA-NEXT: .LBB38_3: ; RV64IA-NEXT: .LBB38_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind {
; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a6, a4 ; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp) ; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6 ; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a6, a4 ; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp) ; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp) ; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp ; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a2, a3 ; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6 ; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd a1, 0(sp) ; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB39_3 ; RV64IA-NEXT: bne a3, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB39_1 ; RV64IA-NEXT: bnez a4, .LBB39_1
; RV64IA-NEXT: .LBB39_3: ; RV64IA-NEXT: .LBB39_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_unordered: ; RV32I-LABEL: atomic_load_i8_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_unordered: ; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_unordered: ; RV64I-LABEL: atomic_load_i8_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_unordered: ; RV64IA-LABEL: atomic_load_i8_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a unordered, align 1 %1 = load atomic i8, i8* %a unordered, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_monotonic: ; RV32I-LABEL: atomic_load_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_monotonic: ; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_monotonic: ; RV64I-LABEL: atomic_load_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_monotonic: ; RV64IA-LABEL: atomic_load_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a monotonic, align 1 %1 = load atomic i8, i8* %a monotonic, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { define i8 @atomic_load_i8_acquire(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_acquire: ; RV32I-LABEL: atomic_load_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_acquire: ; RV32IA-LABEL: atomic_load_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_acquire: ; RV64I-LABEL: atomic_load_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_acquire: ; RV64IA-LABEL: atomic_load_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a acquire, align 1 %1 = load atomic i8, i8* %a acquire, align 1
ret i8 %1 ret i8 %1
} }
define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_seq_cst: ; RV32I-LABEL: atomic_load_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_1 ; RV32I-NEXT: call __atomic_load_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i8_seq_cst: ; RV32IA-LABEL: atomic_load_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lb a0, 0(a0) ; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i8_seq_cst: ; RV64I-LABEL: atomic_load_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_1 ; RV64I-NEXT: call __atomic_load_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i8_seq_cst: ; RV64IA-LABEL: atomic_load_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lb a0, 0(a0) ; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i8, i8* %a seq_cst, align 1 %1 = load atomic i8, i8* %a seq_cst, align 1
ret i8 %1 ret i8 %1
} }
define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { define i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_unordered: ; RV32I-LABEL: atomic_load_i16_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_unordered: ; RV32IA-LABEL: atomic_load_i16_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_unordered: ; RV64I-LABEL: atomic_load_i16_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_unordered: ; RV64IA-LABEL: atomic_load_i16_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a unordered, align 2 %1 = load atomic i16, i16* %a unordered, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_monotonic: ; RV32I-LABEL: atomic_load_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_monotonic: ; RV32IA-LABEL: atomic_load_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_monotonic: ; RV64I-LABEL: atomic_load_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_monotonic: ; RV64IA-LABEL: atomic_load_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a monotonic, align 2 %1 = load atomic i16, i16* %a monotonic, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { define i16 @atomic_load_i16_acquire(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_acquire: ; RV32I-LABEL: atomic_load_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_acquire: ; RV32IA-LABEL: atomic_load_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_acquire: ; RV64I-LABEL: atomic_load_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_acquire: ; RV64IA-LABEL: atomic_load_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a acquire, align 2 %1 = load atomic i16, i16* %a acquire, align 2
ret i16 %1 ret i16 %1
} }
define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind {
; RV32I-LABEL: atomic_load_i16_seq_cst: ; RV32I-LABEL: atomic_load_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_2 ; RV32I-NEXT: call __atomic_load_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i16_seq_cst: ; RV32IA-LABEL: atomic_load_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lh a0, 0(a0) ; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i16_seq_cst: ; RV64I-LABEL: atomic_load_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_2 ; RV64I-NEXT: call __atomic_load_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i16_seq_cst: ; RV64IA-LABEL: atomic_load_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lh a0, 0(a0) ; RV64IA-NEXT: lh a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i16, i16* %a seq_cst, align 2 %1 = load atomic i16, i16* %a seq_cst, align 2
ret i16 %1 ret i16 %1
} }
define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { define i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_unordered: ; RV32I-LABEL: atomic_load_i32_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_unordered: ; RV32IA-LABEL: atomic_load_i32_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_unordered: ; RV64I-LABEL: atomic_load_i32_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_unordered: ; RV64IA-LABEL: atomic_load_i32_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a unordered, align 4 %1 = load atomic i32, i32* %a unordered, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_monotonic: ; RV32I-LABEL: atomic_load_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_monotonic: ; RV32IA-LABEL: atomic_load_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_monotonic: ; RV64I-LABEL: atomic_load_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_monotonic: ; RV64IA-LABEL: atomic_load_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a monotonic, align 4 %1 = load atomic i32, i32* %a monotonic, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { define i32 @atomic_load_i32_acquire(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_acquire: ; RV32I-LABEL: atomic_load_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_acquire: ; RV32IA-LABEL: atomic_load_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_acquire: ; RV64I-LABEL: atomic_load_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_acquire: ; RV64IA-LABEL: atomic_load_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a acquire, align 4 %1 = load atomic i32, i32* %a acquire, align 4
ret i32 %1 ret i32 %1
} }
define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind {
; RV32I-LABEL: atomic_load_i32_seq_cst: ; RV32I-LABEL: atomic_load_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_4 ; RV32I-NEXT: call __atomic_load_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i32_seq_cst: ; RV32IA-LABEL: atomic_load_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw ; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lw a0, 0(a0) ; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw ; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i32_seq_cst: ; RV64I-LABEL: atomic_load_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_4 ; RV64I-NEXT: call __atomic_load_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i32_seq_cst: ; RV64IA-LABEL: atomic_load_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: lw a0, 0(a0) ; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i32, i32* %a seq_cst, align 4 %1 = load atomic i32, i32* %a seq_cst, align 4
ret i32 %1 ret i32 %1
} }
define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { define i64 @atomic_load_i64_unordered(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_unordered: ; RV32I-LABEL: atomic_load_i64_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_unordered: ; RV32IA-LABEL: atomic_load_i64_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a1, zero ; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_unordered: ; RV64I-LABEL: atomic_load_i64_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_unordered: ; RV64IA-LABEL: atomic_load_i64_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a unordered, align 8 %1 = load atomic i64, i64* %a unordered, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_monotonic: ; RV32I-LABEL: atomic_load_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_monotonic: ; RV32IA-LABEL: atomic_load_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a1, zero ; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_monotonic: ; RV64I-LABEL: atomic_load_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_monotonic: ; RV64IA-LABEL: atomic_load_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a monotonic, align 8 %1 = load atomic i64, i64* %a monotonic, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { define i64 @atomic_load_i64_acquire(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_acquire: ; RV32I-LABEL: atomic_load_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_acquire: ; RV32IA-LABEL: atomic_load_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a1, zero, 2 ; RV32IA-NEXT: addi a1, zero, 2
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_acquire: ; RV64I-LABEL: atomic_load_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 2 ; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_acquire: ; RV64IA-LABEL: atomic_load_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a acquire, align 8 %1 = load atomic i64, i64* %a acquire, align 8
ret i64 %1 ret i64 %1
} }
define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind {
; RV32I-LABEL: atomic_load_i64_seq_cst: ; RV32I-LABEL: atomic_load_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 5 ; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: call __atomic_load_8 ; RV32I-NEXT: call __atomic_load_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_load_i64_seq_cst: ; RV32IA-LABEL: atomic_load_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a1, zero, 5 ; RV32IA-NEXT: addi a1, zero, 5
; RV32IA-NEXT: call __atomic_load_8 ; RV32IA-NEXT: call __atomic_load_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_load_i64_seq_cst: ; RV64I-LABEL: atomic_load_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 5 ; RV64I-NEXT: addi a1, zero, 5
; RV64I-NEXT: call __atomic_load_8 ; RV64I-NEXT: call __atomic_load_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_load_i64_seq_cst: ; RV64IA-LABEL: atomic_load_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, rw ; RV64IA-NEXT: fence rw, rw
; RV64IA-NEXT: ld a0, 0(a0) ; RV64IA-NEXT: ld a0, 0(a0)
; RV64IA-NEXT: fence r, rw ; RV64IA-NEXT: fence r, rw
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = load atomic i64, i64* %a seq_cst, align 8 %1 = load atomic i64, i64* %a seq_cst, align 8
ret i64 %1 ret i64 %1
} }
define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_unordered: ; RV32I-LABEL: atomic_store_i8_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_unordered: ; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_unordered: ; RV64I-LABEL: atomic_store_i8_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_unordered: ; RV64IA-LABEL: atomic_store_i8_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a unordered, align 1 store atomic i8 %b, i8* %a unordered, align 1
ret void ret void
} }
define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_monotonic: ; RV32I-LABEL: atomic_store_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_monotonic: ; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_monotonic: ; RV64I-LABEL: atomic_store_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_monotonic: ; RV64IA-LABEL: atomic_store_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a monotonic, align 1 store atomic i8 %b, i8* %a monotonic, align 1
ret void ret void
} }
define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_release: ; RV32I-LABEL: atomic_store_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_release: ; RV32IA-LABEL: atomic_store_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_release: ; RV64I-LABEL: atomic_store_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_release: ; RV64IA-LABEL: atomic_store_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a release, align 1 store atomic i8 %b, i8* %a release, align 1
ret void ret void
} }
define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomic_store_i8_seq_cst: ; RV32I-LABEL: atomic_store_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_1 ; RV32I-NEXT: call __atomic_store_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i8_seq_cst: ; RV32IA-LABEL: atomic_store_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i8_seq_cst: ; RV64I-LABEL: atomic_store_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_1 ; RV64I-NEXT: call __atomic_store_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i8_seq_cst: ; RV64IA-LABEL: atomic_store_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sb a1, 0(a0) ; RV64IA-NEXT: sb a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i8 %b, i8* %a seq_cst, align 1 store atomic i8 %b, i8* %a seq_cst, align 1
ret void ret void
} }
define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_unordered: ; RV32I-LABEL: atomic_store_i16_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_unordered: ; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_unordered: ; RV64I-LABEL: atomic_store_i16_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_unordered: ; RV64IA-LABEL: atomic_store_i16_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a unordered, align 2 store atomic i16 %b, i16* %a unordered, align 2
ret void ret void
} }
define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_monotonic: ; RV32I-LABEL: atomic_store_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_monotonic: ; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_monotonic: ; RV64I-LABEL: atomic_store_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_monotonic: ; RV64IA-LABEL: atomic_store_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a monotonic, align 2 store atomic i16 %b, i16* %a monotonic, align 2
ret void ret void
} }
define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_release: ; RV32I-LABEL: atomic_store_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_release: ; RV32IA-LABEL: atomic_store_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_release: ; RV64I-LABEL: atomic_store_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_release: ; RV64IA-LABEL: atomic_store_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a release, align 2 store atomic i16 %b, i16* %a release, align 2
ret void ret void
} }
define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomic_store_i16_seq_cst: ; RV32I-LABEL: atomic_store_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_2 ; RV32I-NEXT: call __atomic_store_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i16_seq_cst: ; RV32IA-LABEL: atomic_store_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i16_seq_cst: ; RV64I-LABEL: atomic_store_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_2 ; RV64I-NEXT: call __atomic_store_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i16_seq_cst: ; RV64IA-LABEL: atomic_store_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sh a1, 0(a0) ; RV64IA-NEXT: sh a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i16 %b, i16* %a seq_cst, align 2 store atomic i16 %b, i16* %a seq_cst, align 2
ret void ret void
} }
define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_unordered: ; RV32I-LABEL: atomic_store_i32_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_unordered: ; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_unordered: ; RV64I-LABEL: atomic_store_i32_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_unordered: ; RV64IA-LABEL: atomic_store_i32_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a unordered, align 4 store atomic i32 %b, i32* %a unordered, align 4
ret void ret void
} }
define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_monotonic: ; RV32I-LABEL: atomic_store_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_monotonic: ; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_monotonic: ; RV64I-LABEL: atomic_store_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_monotonic: ; RV64IA-LABEL: atomic_store_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a monotonic, align 4 store atomic i32 %b, i32* %a monotonic, align 4
ret void ret void
} }
define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_release: ; RV32I-LABEL: atomic_store_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_release: ; RV32IA-LABEL: atomic_store_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_release: ; RV64I-LABEL: atomic_store_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_release: ; RV64IA-LABEL: atomic_store_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a release, align 4 store atomic i32 %b, i32* %a release, align 4
ret void ret void
} }
define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomic_store_i32_seq_cst: ; RV32I-LABEL: atomic_store_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_store_4 ; RV32I-NEXT: call __atomic_store_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i32_seq_cst: ; RV32IA-LABEL: atomic_store_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w ; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i32_seq_cst: ; RV64I-LABEL: atomic_store_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_4 ; RV64I-NEXT: call __atomic_store_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i32_seq_cst: ; RV64IA-LABEL: atomic_store_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sw a1, 0(a0) ; RV64IA-NEXT: sw a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i32 %b, i32* %a seq_cst, align 4 store atomic i32 %b, i32* %a seq_cst, align 4
ret void ret void
} }
define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_unordered: ; RV32I-LABEL: atomic_store_i64_unordered:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_unordered: ; RV32IA-LABEL: atomic_store_i64_unordered:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_unordered: ; RV64I-LABEL: atomic_store_i64_unordered:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_unordered: ; RV64IA-LABEL: atomic_store_i64_unordered:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a unordered, align 8 store atomic i64 %b, i64* %a unordered, align 8
ret void ret void
} }
define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_monotonic: ; RV32I-LABEL: atomic_store_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_monotonic: ; RV32IA-LABEL: atomic_store_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_monotonic: ; RV64I-LABEL: atomic_store_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_monotonic: ; RV64IA-LABEL: atomic_store_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a monotonic, align 8 store atomic i64 %b, i64* %a monotonic, align 8
ret void ret void
} }
define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_release: ; RV32I-LABEL: atomic_store_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_release: ; RV32IA-LABEL: atomic_store_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_release: ; RV64I-LABEL: atomic_store_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_release: ; RV64IA-LABEL: atomic_store_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a release, align 8 store atomic i64 %b, i64* %a release, align 8
ret void ret void
} }
define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomic_store_i64_seq_cst: ; RV32I-LABEL: atomic_store_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_store_8 ; RV32I-NEXT: call __atomic_store_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomic_store_i64_seq_cst: ; RV32IA-LABEL: atomic_store_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_store_8 ; RV32IA-NEXT: call __atomic_store_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomic_store_i64_seq_cst: ; RV64I-LABEL: atomic_store_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_store_8 ; RV64I-NEXT: call __atomic_store_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomic_store_i64_seq_cst: ; RV64IA-LABEL: atomic_store_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: fence rw, w ; RV64IA-NEXT: fence rw, w
; RV64IA-NEXT: sd a1, 0(a0) ; RV64IA-NEXT: sd a1, 0(a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
store atomic i64 %b, i64* %a seq_cst, align 8 store atomic i64 %b, i64* %a seq_cst, align 8
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-rmw.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s ; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s ; RUN: | FileCheck -check-prefix=RV64IA %s
define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b monotonic %1 = atomicrmw xchg i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acquire: ; RV32I-LABEL: atomicrmw_xchg_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acquire: ; RV64I-LABEL: atomicrmw_xchg_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acquire %1 = atomicrmw xchg i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_release: ; RV32I-LABEL: atomicrmw_xchg_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_release: ; RV32IA-LABEL: atomicrmw_xchg_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_release: ; RV64I-LABEL: atomicrmw_xchg_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-LABEL: atomicrmw_xchg_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b release %1 = atomicrmw xchg i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b acq_rel %1 = atomicrmw xchg i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_1 ; RV32I-NEXT: call __atomic_exchange_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_1 ; RV64I-NEXT: call __atomic_exchange_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i8* %a, i8 %b seq_cst %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_monotonic: ; RV32I-LABEL: atomicrmw_add_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_monotonic: ; RV32IA-LABEL: atomicrmw_add_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: bnez a5, .LBB5_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_monotonic: ; RV64I-LABEL: atomicrmw_add_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b monotonic %1 = atomicrmw add i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acquire: ; RV32I-LABEL: atomicrmw_add_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acquire: ; RV32IA-LABEL: atomicrmw_add_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: bnez a5, .LBB6_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acquire: ; RV64I-LABEL: atomicrmw_add_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-LABEL: atomicrmw_add_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acquire %1 = atomicrmw add i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_release: ; RV32I-LABEL: atomicrmw_add_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_release: ; RV32IA-LABEL: atomicrmw_add_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_release: ; RV64I-LABEL: atomicrmw_add_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_release: ; RV64IA-LABEL: atomicrmw_add_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b release %1 = atomicrmw add i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_acq_rel: ; RV32I-LABEL: atomicrmw_add_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_acq_rel: ; RV64I-LABEL: atomicrmw_add_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b acq_rel %1 = atomicrmw add i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i8_seq_cst: ; RV32I-LABEL: atomicrmw_add_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_1 ; RV32I-NEXT: call __atomic_fetch_add_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_seq_cst: ; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_1 ; RV64I-NEXT: call __atomic_fetch_add_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i8* %a, i8 %b seq_cst %1 = atomicrmw add i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_monotonic: ; RV32I-LABEL: atomicrmw_sub_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB10_1 ; RV32IA-NEXT: bnez a5, .LBB10_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_monotonic: ; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b monotonic %1 = atomicrmw sub i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acquire: ; RV32I-LABEL: atomicrmw_sub_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acquire: ; RV32IA-LABEL: atomicrmw_sub_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB11_1 ; RV32IA-NEXT: bnez a5, .LBB11_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acquire: ; RV64I-LABEL: atomicrmw_sub_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acquire %1 = atomicrmw sub i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_release: ; RV32I-LABEL: atomicrmw_sub_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_release: ; RV32IA-LABEL: atomicrmw_sub_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: bnez a5, .LBB12_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_release: ; RV64I-LABEL: atomicrmw_sub_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_release: ; RV64IA-LABEL: atomicrmw_sub_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b release %1 = atomicrmw sub i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: bnez a5, .LBB13_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b acq_rel %1 = atomicrmw sub i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_1 ; RV32I-NEXT: call __atomic_fetch_sub_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 11 Lines
; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: bnez a5, .LBB14_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_1 ; RV64I-NEXT: call __atomic_fetch_sub_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 15 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i8* %a, i8 %b seq_cst %1 = atomicrmw sub i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_monotonic: ; RV32I-LABEL: atomicrmw_and_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_monotonic: ; RV32IA-LABEL: atomicrmw_and_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2) ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_monotonic: ; RV64I-LABEL: atomicrmw_and_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b monotonic %1 = atomicrmw and i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acquire: ; RV32I-LABEL: atomicrmw_and_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acquire: ; RV32IA-LABEL: atomicrmw_and_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acquire: ; RV64I-LABEL: atomicrmw_and_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-LABEL: atomicrmw_and_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acquire %1 = atomicrmw and i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_release: ; RV32I-LABEL: atomicrmw_and_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_release: ; RV32IA-LABEL: atomicrmw_and_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_release: ; RV64I-LABEL: atomicrmw_and_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_release: ; RV64IA-LABEL: atomicrmw_and_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b release %1 = atomicrmw and i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_acq_rel: ; RV32I-LABEL: atomicrmw_and_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_acq_rel: ; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b acq_rel %1 = atomicrmw and i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i8_seq_cst: ; RV32I-LABEL: atomicrmw_and_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_1 ; RV32I-NEXT: call __atomic_fetch_and_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1 ; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i8_seq_cst: ; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_1 ; RV64I-NEXT: call __atomic_fetch_and_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 9 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i8* %a, i8 %b seq_cst %1 = atomicrmw and i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_monotonic: ; RV32I-LABEL: atomicrmw_nand_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB20_1 ; RV32IA-NEXT: bnez a5, .LBB20_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_monotonic: ; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b monotonic %1 = atomicrmw nand i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acquire: ; RV32I-LABEL: atomicrmw_nand_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acquire: ; RV32IA-LABEL: atomicrmw_nand_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB21_1 ; RV32IA-NEXT: bnez a5, .LBB21_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acquire: ; RV64I-LABEL: atomicrmw_nand_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acquire %1 = atomicrmw nand i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_release: ; RV32I-LABEL: atomicrmw_nand_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_release: ; RV32IA-LABEL: atomicrmw_nand_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB22_1 ; RV32IA-NEXT: bnez a5, .LBB22_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_release: ; RV64I-LABEL: atomicrmw_nand_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_release: ; RV64IA-LABEL: atomicrmw_nand_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b release %1 = atomicrmw nand i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB23_1 ; RV32IA-NEXT: bnez a5, .LBB23_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b acq_rel %1 = atomicrmw nand i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_1 ; RV32I-NEXT: call __atomic_fetch_nand_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: bnez a5, .LBB24_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_1 ; RV64I-NEXT: call __atomic_fetch_nand_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i8* %a, i8 %b seq_cst %1 = atomicrmw nand i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_monotonic: ; RV32I-LABEL: atomicrmw_or_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_monotonic: ; RV32IA-LABEL: atomicrmw_or_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2) ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_monotonic: ; RV64I-LABEL: atomicrmw_or_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2) ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b monotonic %1 = atomicrmw or i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acquire: ; RV32I-LABEL: atomicrmw_or_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acquire: ; RV32IA-LABEL: atomicrmw_or_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acquire: ; RV64I-LABEL: atomicrmw_or_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-LABEL: atomicrmw_or_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acquire %1 = atomicrmw or i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_release: ; RV32I-LABEL: atomicrmw_or_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_release: ; RV32IA-LABEL: atomicrmw_or_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_release: ; RV64I-LABEL: atomicrmw_or_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_release: ; RV64IA-LABEL: atomicrmw_or_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b release %1 = atomicrmw or i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_acq_rel: ; RV32I-LABEL: atomicrmw_or_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_acq_rel: ; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b acq_rel %1 = atomicrmw or i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i8_seq_cst: ; RV32I-LABEL: atomicrmw_or_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_1 ; RV32I-NEXT: call __atomic_fetch_or_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i8_seq_cst: ; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_1 ; RV64I-NEXT: call __atomic_fetch_or_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i8* %a, i8 %b seq_cst %1 = atomicrmw or i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_monotonic: ; RV32I-LABEL: atomicrmw_xor_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2) ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_monotonic: ; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2) ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b monotonic %1 = atomicrmw xor i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acquire: ; RV32I-LABEL: atomicrmw_xor_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acquire: ; RV32IA-LABEL: atomicrmw_xor_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acquire: ; RV64I-LABEL: atomicrmw_xor_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acquire %1 = atomicrmw xor i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_release: ; RV32I-LABEL: atomicrmw_xor_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_release: ; RV32IA-LABEL: atomicrmw_xor_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_release: ; RV64I-LABEL: atomicrmw_xor_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_release: ; RV64IA-LABEL: atomicrmw_xor_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b release %1 = atomicrmw xor i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b acq_rel %1 = atomicrmw xor i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_1 ; RV32I-NEXT: call __atomic_fetch_xor_1@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_1 ; RV64I-NEXT: call __atomic_fetch_xor_1@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i8* %a, i8 %b seq_cst %1 = atomicrmw xor i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_monotonic: ; RV32I-LABEL: atomicrmw_max_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB35_2 ; RV32I-NEXT: j .LBB35_2
; RV32I-NEXT: .LBB35_1: # %atomicrmw.start ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB35_1 ; RV32I-NEXT: blt s1, a0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB35_1 ; RV32IA-NEXT: bnez a2, .LBB35_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB35_1 ; RV64I-NEXT: blt s1, a0, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b monotonic %1 = atomicrmw max i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acquire: ; RV32I-LABEL: atomicrmw_max_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB36_2 ; RV32I-NEXT: j .LBB36_2
; RV32I-NEXT: .LBB36_1: # %atomicrmw.start ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB36_4 ; RV32I-NEXT: bnez a0, .LBB36_4
; RV32I-NEXT: .LBB36_2: # %atomicrmw.start ; RV32I-NEXT: .LBB36_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB36_1 ; RV32I-NEXT: blt s1, a0, .LBB36_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB36_1 ; RV32I-NEXT: j .LBB36_1
; RV32I-NEXT: .LBB36_4: # %atomicrmw.end ; RV32I-NEXT: .LBB36_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acquire: ; RV32IA-LABEL: atomicrmw_max_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB36_1 ; RV32IA-NEXT: bnez a2, .LBB36_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acquire: ; RV64I-LABEL: atomicrmw_max_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB36_2 ; RV64I-NEXT: j .LBB36_2
; RV64I-NEXT: .LBB36_1: # %atomicrmw.start ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB36_4 ; RV64I-NEXT: bnez a0, .LBB36_4
; RV64I-NEXT: .LBB36_2: # %atomicrmw.start ; RV64I-NEXT: .LBB36_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB36_1 ; RV64I-NEXT: blt s1, a0, .LBB36_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB36_1 ; RV64I-NEXT: j .LBB36_1
; RV64I-NEXT: .LBB36_4: # %atomicrmw.end ; RV64I-NEXT: .LBB36_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acquire %1 = atomicrmw max i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_release: ; RV32I-LABEL: atomicrmw_max_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB37_2 ; RV32I-NEXT: j .LBB37_2
; RV32I-NEXT: .LBB37_1: # %atomicrmw.start ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB37_4 ; RV32I-NEXT: bnez a0, .LBB37_4
; RV32I-NEXT: .LBB37_2: # %atomicrmw.start ; RV32I-NEXT: .LBB37_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB37_1 ; RV32I-NEXT: blt s1, a0, .LBB37_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB37_1 ; RV32I-NEXT: j .LBB37_1
; RV32I-NEXT: .LBB37_4: # %atomicrmw.end ; RV32I-NEXT: .LBB37_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_release: ; RV32IA-LABEL: atomicrmw_max_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB37_1 ; RV32IA-NEXT: bnez a2, .LBB37_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_release: ; RV64I-LABEL: atomicrmw_max_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB37_2 ; RV64I-NEXT: j .LBB37_2
; RV64I-NEXT: .LBB37_1: # %atomicrmw.start ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB37_4 ; RV64I-NEXT: bnez a0, .LBB37_4
; RV64I-NEXT: .LBB37_2: # %atomicrmw.start ; RV64I-NEXT: .LBB37_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB37_1 ; RV64I-NEXT: blt s1, a0, .LBB37_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB37_1 ; RV64I-NEXT: j .LBB37_1
; RV64I-NEXT: .LBB37_4: # %atomicrmw.end ; RV64I-NEXT: .LBB37_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_release: ; RV64IA-LABEL: atomicrmw_max_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b release %1 = atomicrmw max i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acq_rel: ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB38_2 ; RV32I-NEXT: j .LBB38_2
; RV32I-NEXT: .LBB38_1: # %atomicrmw.start ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB38_4 ; RV32I-NEXT: bnez a0, .LBB38_4
; RV32I-NEXT: .LBB38_2: # %atomicrmw.start ; RV32I-NEXT: .LBB38_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB38_1 ; RV32I-NEXT: blt s1, a0, .LBB38_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB38_1 ; RV32I-NEXT: j .LBB38_1
; RV32I-NEXT: .LBB38_4: # %atomicrmw.end ; RV32I-NEXT: .LBB38_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB38_1 ; RV32IA-NEXT: bnez a2, .LBB38_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acq_rel: ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB38_2 ; RV64I-NEXT: j .LBB38_2
; RV64I-NEXT: .LBB38_1: # %atomicrmw.start ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB38_4 ; RV64I-NEXT: bnez a0, .LBB38_4
; RV64I-NEXT: .LBB38_2: # %atomicrmw.start ; RV64I-NEXT: .LBB38_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB38_1 ; RV64I-NEXT: blt s1, a0, .LBB38_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB38_1 ; RV64I-NEXT: j .LBB38_1
; RV64I-NEXT: .LBB38_4: # %atomicrmw.end ; RV64I-NEXT: .LBB38_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acq_rel %1 = atomicrmw max i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_seq_cst: ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB39_2 ; RV32I-NEXT: j .LBB39_2
; RV32I-NEXT: .LBB39_1: # %atomicrmw.start ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB39_4 ; RV32I-NEXT: bnez a0, .LBB39_4
; RV32I-NEXT: .LBB39_2: # %atomicrmw.start ; RV32I-NEXT: .LBB39_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB39_1 ; RV32I-NEXT: blt s1, a0, .LBB39_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB39_1 ; RV32I-NEXT: j .LBB39_1
; RV32I-NEXT: .LBB39_4: # %atomicrmw.end ; RV32I-NEXT: .LBB39_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB39_1 ; RV32IA-NEXT: bnez a2, .LBB39_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB39_2 ; RV64I-NEXT: j .LBB39_2
; RV64I-NEXT: .LBB39_1: # %atomicrmw.start ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB39_4 ; RV64I-NEXT: bnez a0, .LBB39_4
; RV64I-NEXT: .LBB39_2: # %atomicrmw.start ; RV64I-NEXT: .LBB39_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB39_1 ; RV64I-NEXT: blt s1, a0, .LBB39_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB39_1 ; RV64I-NEXT: j .LBB39_1
; RV64I-NEXT: .LBB39_4: # %atomicrmw.end ; RV64I-NEXT: .LBB39_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b seq_cst %1 = atomicrmw max i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic: ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB40_2 ; RV32I-NEXT: j .LBB40_2
; RV32I-NEXT: .LBB40_1: # %atomicrmw.start ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB40_4 ; RV32I-NEXT: bnez a0, .LBB40_4
; RV32I-NEXT: .LBB40_2: # %atomicrmw.start ; RV32I-NEXT: .LBB40_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB40_1 ; RV32I-NEXT: bge s1, a0, .LBB40_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: j .LBB40_1
; RV32I-NEXT: .LBB40_4: # %atomicrmw.end ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB40_1 ; RV32IA-NEXT: bnez a2, .LBB40_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB40_2 ; RV64I-NEXT: j .LBB40_2
; RV64I-NEXT: .LBB40_1: # %atomicrmw.start ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB40_4 ; RV64I-NEXT: bnez a0, .LBB40_4
; RV64I-NEXT: .LBB40_2: # %atomicrmw.start ; RV64I-NEXT: .LBB40_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB40_1 ; RV64I-NEXT: bge s1, a0, .LBB40_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: j .LBB40_1
; RV64I-NEXT: .LBB40_4: # %atomicrmw.end ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b monotonic %1 = atomicrmw min i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acquire: ; RV32I-LABEL: atomicrmw_min_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB41_2 ; RV32I-NEXT: j .LBB41_2
; RV32I-NEXT: .LBB41_1: # %atomicrmw.start ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB41_4 ; RV32I-NEXT: bnez a0, .LBB41_4
; RV32I-NEXT: .LBB41_2: # %atomicrmw.start ; RV32I-NEXT: .LBB41_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB41_1 ; RV32I-NEXT: bge s1, a0, .LBB41_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: j .LBB41_1
; RV32I-NEXT: .LBB41_4: # %atomicrmw.end ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acquire: ; RV32IA-LABEL: atomicrmw_min_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB41_1 ; RV32IA-NEXT: bnez a2, .LBB41_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acquire: ; RV64I-LABEL: atomicrmw_min_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB41_2 ; RV64I-NEXT: j .LBB41_2
; RV64I-NEXT: .LBB41_1: # %atomicrmw.start ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB41_4 ; RV64I-NEXT: bnez a0, .LBB41_4
; RV64I-NEXT: .LBB41_2: # %atomicrmw.start ; RV64I-NEXT: .LBB41_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB41_1 ; RV64I-NEXT: bge s1, a0, .LBB41_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: j .LBB41_1
; RV64I-NEXT: .LBB41_4: # %atomicrmw.end ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acquire %1 = atomicrmw min i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_release: ; RV32I-LABEL: atomicrmw_min_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB42_2 ; RV32I-NEXT: j .LBB42_2
; RV32I-NEXT: .LBB42_1: # %atomicrmw.start ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB42_4 ; RV32I-NEXT: bnez a0, .LBB42_4
; RV32I-NEXT: .LBB42_2: # %atomicrmw.start ; RV32I-NEXT: .LBB42_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB42_1 ; RV32I-NEXT: bge s1, a0, .LBB42_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: j .LBB42_1
; RV32I-NEXT: .LBB42_4: # %atomicrmw.end ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_release: ; RV32IA-LABEL: atomicrmw_min_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB42_1 ; RV32IA-NEXT: bnez a2, .LBB42_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_release: ; RV64I-LABEL: atomicrmw_min_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB42_2 ; RV64I-NEXT: j .LBB42_2
; RV64I-NEXT: .LBB42_1: # %atomicrmw.start ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB42_4 ; RV64I-NEXT: bnez a0, .LBB42_4
; RV64I-NEXT: .LBB42_2: # %atomicrmw.start ; RV64I-NEXT: .LBB42_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB42_1 ; RV64I-NEXT: bge s1, a0, .LBB42_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: j .LBB42_1
; RV64I-NEXT: .LBB42_4: # %atomicrmw.end ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_release: ; RV64IA-LABEL: atomicrmw_min_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b release %1 = atomicrmw min i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acq_rel: ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB43_2 ; RV32I-NEXT: j .LBB43_2
; RV32I-NEXT: .LBB43_1: # %atomicrmw.start ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB43_4 ; RV32I-NEXT: bnez a0, .LBB43_4
; RV32I-NEXT: .LBB43_2: # %atomicrmw.start ; RV32I-NEXT: .LBB43_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB43_1 ; RV32I-NEXT: bge s1, a0, .LBB43_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: j .LBB43_1
; RV32I-NEXT: .LBB43_4: # %atomicrmw.end ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB43_1 ; RV32IA-NEXT: bnez a2, .LBB43_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acq_rel: ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB43_2 ; RV64I-NEXT: j .LBB43_2
; RV64I-NEXT: .LBB43_1: # %atomicrmw.start ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB43_4 ; RV64I-NEXT: bnez a0, .LBB43_4
; RV64I-NEXT: .LBB43_2: # %atomicrmw.start ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB43_1 ; RV64I-NEXT: bge s1, a0, .LBB43_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: j .LBB43_1
; RV64I-NEXT: .LBB43_4: # %atomicrmw.end ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acq_rel %1 = atomicrmw min i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_seq_cst: ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB44_2 ; RV32I-NEXT: j .LBB44_2
; RV32I-NEXT: .LBB44_1: # %atomicrmw.start ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB44_4 ; RV32I-NEXT: bnez a0, .LBB44_4
; RV32I-NEXT: .LBB44_2: # %atomicrmw.start ; RV32I-NEXT: .LBB44_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB44_1 ; RV32I-NEXT: bge s1, a0, .LBB44_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_4: # %atomicrmw.end ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 20 Lines
; RV32IA-NEXT: bnez a2, .LBB44_1 ; RV32IA-NEXT: bnez a2, .LBB44_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB44_2 ; RV64I-NEXT: j .LBB44_2
; RV64I-NEXT: .LBB44_1: # %atomicrmw.start ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB44_1 ; RV64I-NEXT: bge s1, a0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 24 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b seq_cst %1 = atomicrmw min i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic: ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB45_2 ; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB45_4 ; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB45_1 ; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB45_1 ; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end ; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB45_1 ; RV32IA-NEXT: bnez a5, .LBB45_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB45_2 ; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB45_4 ; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB45_1 ; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB45_1 ; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end ; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b monotonic %1 = atomicrmw umax i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acquire: ; RV32I-LABEL: atomicrmw_umax_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB46_2 ; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB46_4 ; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB46_1 ; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end ; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA-LABEL: atomicrmw_umax_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB46_1 ; RV32IA-NEXT: bnez a5, .LBB46_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acquire: ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB46_2 ; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB46_1 ; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acquire %1 = atomicrmw umax i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_release: ; RV32I-LABEL: atomicrmw_umax_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB47_2 ; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB47_4 ; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB47_1 ; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB47_1 ; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end ; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_release: ; RV32IA-LABEL: atomicrmw_umax_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB47_1 ; RV32IA-NEXT: bnez a5, .LBB47_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_release: ; RV64I-LABEL: atomicrmw_umax_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB47_2 ; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB47_4 ; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB47_1 ; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB47_1 ; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end ; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_release: ; RV64IA-LABEL: atomicrmw_umax_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b release %1 = atomicrmw umax i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB48_2 ; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB48_4 ; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB48_1 ; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB48_1 ; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end ; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB48_1 ; RV32IA-NEXT: bnez a5, .LBB48_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB48_2 ; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB48_4 ; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB48_1 ; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB48_1 ; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end ; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acq_rel %1 = atomicrmw umax i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB49_2 ; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB49_4 ; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB49_1 ; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB49_1 ; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end ; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: bnez a5, .LBB49_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB49_2 ; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB49_4 ; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB49_1 ; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB49_1 ; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end ; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b seq_cst %1 = atomicrmw umax i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic: ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB50_2 ; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB50_4 ; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB50_1 ; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB50_1 ; RV32IA-NEXT: bnez a5, .LBB50_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB50_2 ; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB50_4 ; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB50_1 ; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b monotonic %1 = atomicrmw umin i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acquire: ; RV32I-LABEL: atomicrmw_umin_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB51_2 ; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB51_4 ; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB51_1 ; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA-LABEL: atomicrmw_umin_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB51_1 ; RV32IA-NEXT: bnez a5, .LBB51_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acquire: ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB51_2 ; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB51_4 ; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB51_1 ; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acquire %1 = atomicrmw umin i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_release: ; RV32I-LABEL: atomicrmw_umin_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB52_2 ; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB52_4 ; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB52_1 ; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_release: ; RV32IA-LABEL: atomicrmw_umin_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB52_1 ; RV32IA-NEXT: bnez a5, .LBB52_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_release: ; RV64I-LABEL: atomicrmw_umin_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB52_2 ; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB52_4 ; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB52_1 ; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_release: ; RV64IA-LABEL: atomicrmw_umin_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b release %1 = atomicrmw umin i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB53_2 ; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB53_4 ; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB53_1 ; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB53_1 ; RV32IA-NEXT: bnez a5, .LBB53_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB53_2 ; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB53_4 ; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB53_1 ; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acq_rel %1 = atomicrmw umin i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s1, a1, 255
; RV32I-NEXT: j .LBB54_2 ; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1 ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB54_4 ; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB54_1 ; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 15 Lines
; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: bnez a5, .LBB54_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s1, a1, 255
; RV64I-NEXT: j .LBB54_2 ; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1 ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB54_4 ; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB54_1 ; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 19 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b seq_cst %1 = atomicrmw umin i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB55_1 ; RV32IA-NEXT: bnez a5, .LBB55_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b monotonic %1 = atomicrmw xchg i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acquire: ; RV32I-LABEL: atomicrmw_xchg_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB56_1 ; RV32IA-NEXT: bnez a5, .LBB56_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acquire: ; RV64I-LABEL: atomicrmw_xchg_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acquire %1 = atomicrmw xchg i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_release: ; RV32I-LABEL: atomicrmw_xchg_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_release: ; RV32IA-LABEL: atomicrmw_xchg_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB57_1 ; RV32IA-NEXT: bnez a5, .LBB57_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_release: ; RV64I-LABEL: atomicrmw_xchg_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-LABEL: atomicrmw_xchg_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b release %1 = atomicrmw xchg i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB58_1 ; RV32IA-NEXT: bnez a5, .LBB58_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b acq_rel %1 = atomicrmw xchg i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_2 ; RV32I-NEXT: call __atomic_exchange_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: bnez a5, .LBB59_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_2 ; RV64I-NEXT: call __atomic_exchange_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw xchg i16* %a, i16 %b seq_cst %1 = atomicrmw xchg i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_monotonic: ; RV32I-LABEL: atomicrmw_add_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_monotonic: ; RV32IA-LABEL: atomicrmw_add_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB60_1 ; RV32IA-NEXT: bnez a5, .LBB60_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_monotonic: ; RV64I-LABEL: atomicrmw_add_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b monotonic %1 = atomicrmw add i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acquire: ; RV32I-LABEL: atomicrmw_add_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acquire: ; RV32IA-LABEL: atomicrmw_add_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB61_1 ; RV32IA-NEXT: bnez a5, .LBB61_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acquire: ; RV64I-LABEL: atomicrmw_add_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-LABEL: atomicrmw_add_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acquire %1 = atomicrmw add i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_release: ; RV32I-LABEL: atomicrmw_add_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_release: ; RV32IA-LABEL: atomicrmw_add_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB62_1 ; RV32IA-NEXT: bnez a5, .LBB62_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_release: ; RV64I-LABEL: atomicrmw_add_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_release: ; RV64IA-LABEL: atomicrmw_add_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b release %1 = atomicrmw add i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_acq_rel: ; RV32I-LABEL: atomicrmw_add_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB63_1 ; RV32IA-NEXT: bnez a5, .LBB63_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_acq_rel: ; RV64I-LABEL: atomicrmw_add_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b acq_rel %1 = atomicrmw add i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i16_seq_cst: ; RV32I-LABEL: atomicrmw_add_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_2 ; RV32I-NEXT: call __atomic_fetch_add_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB64_1 ; RV32IA-NEXT: bnez a5, .LBB64_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_seq_cst: ; RV64I-LABEL: atomicrmw_add_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_2 ; RV64I-NEXT: call __atomic_fetch_add_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw add i16* %a, i16 %b seq_cst %1 = atomicrmw add i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_monotonic: ; RV32I-LABEL: atomicrmw_sub_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB65_1 ; RV32IA-NEXT: bnez a5, .LBB65_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_monotonic: ; RV64I-LABEL: atomicrmw_sub_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b monotonic %1 = atomicrmw sub i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acquire: ; RV32I-LABEL: atomicrmw_sub_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acquire: ; RV32IA-LABEL: atomicrmw_sub_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB66_1 ; RV32IA-NEXT: bnez a5, .LBB66_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acquire: ; RV64I-LABEL: atomicrmw_sub_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-LABEL: atomicrmw_sub_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acquire %1 = atomicrmw sub i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_release: ; RV32I-LABEL: atomicrmw_sub_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_release: ; RV32IA-LABEL: atomicrmw_sub_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB67_1 ; RV32IA-NEXT: bnez a5, .LBB67_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_release: ; RV64I-LABEL: atomicrmw_sub_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_release: ; RV64IA-LABEL: atomicrmw_sub_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b release %1 = atomicrmw sub i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB68_1 ; RV32IA-NEXT: bnez a5, .LBB68_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b acq_rel %1 = atomicrmw sub i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_2 ; RV32I-NEXT: call __atomic_fetch_sub_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 12 Lines
; RV32IA-NEXT: bnez a5, .LBB69_1 ; RV32IA-NEXT: bnez a5, .LBB69_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_2 ; RV64I-NEXT: call __atomic_fetch_sub_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 16 Lines; RV64IA-NEXT: ret
%1 = atomicrmw sub i16* %a, i16 %b seq_cst %1 = atomicrmw sub i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_monotonic: ; RV32I-LABEL: atomicrmw_and_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_monotonic: ; RV32IA-LABEL: atomicrmw_and_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2) ; RV32IA-NEXT: amoand.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_monotonic: ; RV64I-LABEL: atomicrmw_and_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b monotonic %1 = atomicrmw and i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acquire: ; RV32I-LABEL: atomicrmw_and_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acquire: ; RV32IA-LABEL: atomicrmw_and_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acquire: ; RV64I-LABEL: atomicrmw_and_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-LABEL: atomicrmw_and_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acquire %1 = atomicrmw and i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_release: ; RV32I-LABEL: atomicrmw_and_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_release: ; RV32IA-LABEL: atomicrmw_and_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_release: ; RV64I-LABEL: atomicrmw_and_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_release: ; RV64IA-LABEL: atomicrmw_and_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b release %1 = atomicrmw and i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_acq_rel: ; RV32I-LABEL: atomicrmw_and_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_acq_rel: ; RV64I-LABEL: atomicrmw_and_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b acq_rel %1 = atomicrmw and i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i16_seq_cst: ; RV32I-LABEL: atomicrmw_and_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_2 ; RV32I-NEXT: call __atomic_fetch_and_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: not a4, a4
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a4, a1 ; RV32IA-NEXT: or a1, a4, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i16_seq_cst: ; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_2 ; RV64I-NEXT: call __atomic_fetch_and_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 10 Lines; RV64IA-NEXT: ret
%1 = atomicrmw and i16* %a, i16 %b seq_cst %1 = atomicrmw and i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_monotonic: ; RV32I-LABEL: atomicrmw_nand_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB75_1 ; RV32IA-NEXT: bnez a5, .LBB75_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_monotonic: ; RV64I-LABEL: atomicrmw_nand_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b monotonic %1 = atomicrmw nand i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acquire: ; RV32I-LABEL: atomicrmw_nand_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acquire: ; RV32IA-LABEL: atomicrmw_nand_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB76_1 ; RV32IA-NEXT: bnez a5, .LBB76_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acquire: ; RV64I-LABEL: atomicrmw_nand_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-LABEL: atomicrmw_nand_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acquire %1 = atomicrmw nand i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_release: ; RV32I-LABEL: atomicrmw_nand_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_release: ; RV32IA-LABEL: atomicrmw_nand_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB77_1 ; RV32IA-NEXT: bnez a5, .LBB77_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_release: ; RV64I-LABEL: atomicrmw_nand_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_release: ; RV64IA-LABEL: atomicrmw_nand_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b release %1 = atomicrmw nand i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB78_1 ; RV32IA-NEXT: bnez a5, .LBB78_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b acq_rel %1 = atomicrmw nand i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_2 ; RV32I-NEXT: call __atomic_fetch_nand_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 13 Lines
; RV32IA-NEXT: bnez a5, .LBB79_1 ; RV32IA-NEXT: bnez a5, .LBB79_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_2 ; RV64I-NEXT: call __atomic_fetch_nand_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 17 Lines; RV64IA-NEXT: ret
%1 = atomicrmw nand i16* %a, i16 %b seq_cst %1 = atomicrmw nand i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_monotonic: ; RV32I-LABEL: atomicrmw_or_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_monotonic: ; RV32IA-LABEL: atomicrmw_or_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2) ; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_monotonic: ; RV64I-LABEL: atomicrmw_or_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2) ; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b monotonic %1 = atomicrmw or i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acquire: ; RV32I-LABEL: atomicrmw_or_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acquire: ; RV32IA-LABEL: atomicrmw_or_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acquire: ; RV64I-LABEL: atomicrmw_or_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-LABEL: atomicrmw_or_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acquire %1 = atomicrmw or i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_release: ; RV32I-LABEL: atomicrmw_or_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_release: ; RV32IA-LABEL: atomicrmw_or_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_release: ; RV64I-LABEL: atomicrmw_or_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_release: ; RV64IA-LABEL: atomicrmw_or_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b release %1 = atomicrmw or i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_acq_rel: ; RV32I-LABEL: atomicrmw_or_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_acq_rel: ; RV64I-LABEL: atomicrmw_or_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b acq_rel %1 = atomicrmw or i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i16_seq_cst: ; RV32I-LABEL: atomicrmw_or_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_2 ; RV32I-NEXT: call __atomic_fetch_or_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i16_seq_cst: ; RV64I-LABEL: atomicrmw_or_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_2 ; RV64I-NEXT: call __atomic_fetch_or_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i16* %a, i16 %b seq_cst %1 = atomicrmw or i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_monotonic: ; RV32I-LABEL: atomicrmw_xor_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2) ; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_monotonic: ; RV64I-LABEL: atomicrmw_xor_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2) ; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b monotonic %1 = atomicrmw xor i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acquire: ; RV32I-LABEL: atomicrmw_xor_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acquire: ; RV32IA-LABEL: atomicrmw_xor_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acquire: ; RV64I-LABEL: atomicrmw_xor_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acquire %1 = atomicrmw xor i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_release: ; RV32I-LABEL: atomicrmw_xor_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_release: ; RV32IA-LABEL: atomicrmw_xor_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_release: ; RV64I-LABEL: atomicrmw_xor_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_release: ; RV64IA-LABEL: atomicrmw_xor_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b release %1 = atomicrmw xor i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b acq_rel %1 = atomicrmw xor i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_2 ; RV32I-NEXT: call __atomic_fetch_xor_2@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a2, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0 ; RV32IA-NEXT: srl a0, a1, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_2 ; RV64I-NEXT: call __atomic_fetch_xor_2@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) ; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0 ; RV64IA-NEXT: srlw a0, a1, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i16* %a, i16 %b seq_cst %1 = atomicrmw xor i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_monotonic: ; RV32I-LABEL: atomicrmw_max_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB90_2 ; RV32I-NEXT: j .LBB90_2
; RV32I-NEXT: .LBB90_1: # %atomicrmw.start ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB90_4 ; RV32I-NEXT: bnez a0, .LBB90_4
; RV32I-NEXT: .LBB90_2: # %atomicrmw.start ; RV32I-NEXT: .LBB90_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB90_1 ; RV32I-NEXT: blt s1, a0, .LBB90_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB90_1 ; RV32I-NEXT: j .LBB90_1
; RV32I-NEXT: .LBB90_4: # %atomicrmw.end ; RV32I-NEXT: .LBB90_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB90_1 ; RV32IA-NEXT: bnez a2, .LBB90_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB90_2 ; RV64I-NEXT: j .LBB90_2
; RV64I-NEXT: .LBB90_1: # %atomicrmw.start ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB90_4 ; RV64I-NEXT: bnez a0, .LBB90_4
; RV64I-NEXT: .LBB90_2: # %atomicrmw.start ; RV64I-NEXT: .LBB90_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB90_1 ; RV64I-NEXT: blt s1, a0, .LBB90_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB90_1 ; RV64I-NEXT: j .LBB90_1
; RV64I-NEXT: .LBB90_4: # %atomicrmw.end ; RV64I-NEXT: .LBB90_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b monotonic %1 = atomicrmw max i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acquire: ; RV32I-LABEL: atomicrmw_max_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB91_2 ; RV32I-NEXT: j .LBB91_2
; RV32I-NEXT: .LBB91_1: # %atomicrmw.start ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB91_4 ; RV32I-NEXT: bnez a0, .LBB91_4
; RV32I-NEXT: .LBB91_2: # %atomicrmw.start ; RV32I-NEXT: .LBB91_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB91_1 ; RV32I-NEXT: blt s1, a0, .LBB91_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB91_1 ; RV32I-NEXT: j .LBB91_1
; RV32I-NEXT: .LBB91_4: # %atomicrmw.end ; RV32I-NEXT: .LBB91_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acquire: ; RV32IA-LABEL: atomicrmw_max_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB91_1 ; RV32IA-NEXT: bnez a2, .LBB91_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acquire: ; RV64I-LABEL: atomicrmw_max_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB91_2 ; RV64I-NEXT: j .LBB91_2
; RV64I-NEXT: .LBB91_1: # %atomicrmw.start ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB91_4 ; RV64I-NEXT: bnez a0, .LBB91_4
; RV64I-NEXT: .LBB91_2: # %atomicrmw.start ; RV64I-NEXT: .LBB91_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB91_1 ; RV64I-NEXT: blt s1, a0, .LBB91_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB91_1 ; RV64I-NEXT: j .LBB91_1
; RV64I-NEXT: .LBB91_4: # %atomicrmw.end ; RV64I-NEXT: .LBB91_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-LABEL: atomicrmw_max_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acquire %1 = atomicrmw max i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_release: ; RV32I-LABEL: atomicrmw_max_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB92_2 ; RV32I-NEXT: j .LBB92_2
; RV32I-NEXT: .LBB92_1: # %atomicrmw.start ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB92_4 ; RV32I-NEXT: bnez a0, .LBB92_4
; RV32I-NEXT: .LBB92_2: # %atomicrmw.start ; RV32I-NEXT: .LBB92_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB92_1 ; RV32I-NEXT: blt s1, a0, .LBB92_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB92_1 ; RV32I-NEXT: j .LBB92_1
; RV32I-NEXT: .LBB92_4: # %atomicrmw.end ; RV32I-NEXT: .LBB92_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_release: ; RV32IA-LABEL: atomicrmw_max_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB92_1 ; RV32IA-NEXT: bnez a2, .LBB92_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_release: ; RV64I-LABEL: atomicrmw_max_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB92_2 ; RV64I-NEXT: j .LBB92_2
; RV64I-NEXT: .LBB92_1: # %atomicrmw.start ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB92_4 ; RV64I-NEXT: bnez a0, .LBB92_4
; RV64I-NEXT: .LBB92_2: # %atomicrmw.start ; RV64I-NEXT: .LBB92_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB92_1 ; RV64I-NEXT: blt s1, a0, .LBB92_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB92_1 ; RV64I-NEXT: j .LBB92_1
; RV64I-NEXT: .LBB92_4: # %atomicrmw.end ; RV64I-NEXT: .LBB92_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_release: ; RV64IA-LABEL: atomicrmw_max_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b release %1 = atomicrmw max i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acq_rel: ; RV32I-LABEL: atomicrmw_max_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB93_2 ; RV32I-NEXT: j .LBB93_2
; RV32I-NEXT: .LBB93_1: # %atomicrmw.start ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB93_4 ; RV32I-NEXT: bnez a0, .LBB93_4
; RV32I-NEXT: .LBB93_2: # %atomicrmw.start ; RV32I-NEXT: .LBB93_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB93_1 ; RV32I-NEXT: blt s1, a0, .LBB93_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB93_1 ; RV32I-NEXT: j .LBB93_1
; RV32I-NEXT: .LBB93_4: # %atomicrmw.end ; RV32I-NEXT: .LBB93_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB93_1 ; RV32IA-NEXT: bnez a2, .LBB93_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acq_rel: ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB93_2 ; RV64I-NEXT: j .LBB93_2
; RV64I-NEXT: .LBB93_1: # %atomicrmw.start ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB93_4 ; RV64I-NEXT: bnez a0, .LBB93_4
; RV64I-NEXT: .LBB93_2: # %atomicrmw.start ; RV64I-NEXT: .LBB93_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB93_1 ; RV64I-NEXT: blt s1, a0, .LBB93_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB93_1 ; RV64I-NEXT: j .LBB93_1
; RV64I-NEXT: .LBB93_4: # %atomicrmw.end ; RV64I-NEXT: .LBB93_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acq_rel %1 = atomicrmw max i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_seq_cst: ; RV32I-LABEL: atomicrmw_max_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB94_2 ; RV32I-NEXT: j .LBB94_2
; RV32I-NEXT: .LBB94_1: # %atomicrmw.start ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB94_4 ; RV32I-NEXT: bnez a0, .LBB94_4
; RV32I-NEXT: .LBB94_2: # %atomicrmw.start ; RV32I-NEXT: .LBB94_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB94_1 ; RV32I-NEXT: blt s1, a0, .LBB94_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB94_1 ; RV32I-NEXT: j .LBB94_1
; RV32I-NEXT: .LBB94_4: # %atomicrmw.end ; RV32I-NEXT: .LBB94_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB94_1 ; RV32IA-NEXT: bnez a2, .LBB94_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB94_2 ; RV64I-NEXT: j .LBB94_2
; RV64I-NEXT: .LBB94_1: # %atomicrmw.start ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB94_4 ; RV64I-NEXT: bnez a0, .LBB94_4
; RV64I-NEXT: .LBB94_2: # %atomicrmw.start ; RV64I-NEXT: .LBB94_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB94_1 ; RV64I-NEXT: blt s1, a0, .LBB94_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB94_1 ; RV64I-NEXT: j .LBB94_1
; RV64I-NEXT: .LBB94_4: # %atomicrmw.end ; RV64I-NEXT: .LBB94_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b seq_cst %1 = atomicrmw max i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic: ; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB95_2 ; RV32I-NEXT: j .LBB95_2
; RV32I-NEXT: .LBB95_1: # %atomicrmw.start ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB95_4 ; RV32I-NEXT: bnez a0, .LBB95_4
; RV32I-NEXT: .LBB95_2: # %atomicrmw.start ; RV32I-NEXT: .LBB95_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB95_1 ; RV32I-NEXT: bge s1, a0, .LBB95_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: j .LBB95_1
; RV32I-NEXT: .LBB95_4: # %atomicrmw.end ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB95_1 ; RV32IA-NEXT: bnez a2, .LBB95_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB95_2 ; RV64I-NEXT: j .LBB95_2
; RV64I-NEXT: .LBB95_1: # %atomicrmw.start ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB95_4 ; RV64I-NEXT: bnez a0, .LBB95_4
; RV64I-NEXT: .LBB95_2: # %atomicrmw.start ; RV64I-NEXT: .LBB95_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB95_1 ; RV64I-NEXT: bge s1, a0, .LBB95_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: j .LBB95_1
; RV64I-NEXT: .LBB95_4: # %atomicrmw.end ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b monotonic %1 = atomicrmw min i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acquire: ; RV32I-LABEL: atomicrmw_min_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB96_2 ; RV32I-NEXT: j .LBB96_2
; RV32I-NEXT: .LBB96_1: # %atomicrmw.start ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB96_4 ; RV32I-NEXT: bnez a0, .LBB96_4
; RV32I-NEXT: .LBB96_2: # %atomicrmw.start ; RV32I-NEXT: .LBB96_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB96_1 ; RV32I-NEXT: bge s1, a0, .LBB96_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: j .LBB96_1
; RV32I-NEXT: .LBB96_4: # %atomicrmw.end ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acquire: ; RV32IA-LABEL: atomicrmw_min_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB96_1 ; RV32IA-NEXT: bnez a2, .LBB96_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acquire: ; RV64I-LABEL: atomicrmw_min_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB96_2 ; RV64I-NEXT: j .LBB96_2
; RV64I-NEXT: .LBB96_1: # %atomicrmw.start ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB96_4 ; RV64I-NEXT: bnez a0, .LBB96_4
; RV64I-NEXT: .LBB96_2: # %atomicrmw.start ; RV64I-NEXT: .LBB96_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB96_1 ; RV64I-NEXT: bge s1, a0, .LBB96_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: j .LBB96_1
; RV64I-NEXT: .LBB96_4: # %atomicrmw.end ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-LABEL: atomicrmw_min_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acquire %1 = atomicrmw min i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_release: ; RV32I-LABEL: atomicrmw_min_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB97_2 ; RV32I-NEXT: j .LBB97_2
; RV32I-NEXT: .LBB97_1: # %atomicrmw.start ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB97_4 ; RV32I-NEXT: bnez a0, .LBB97_4
; RV32I-NEXT: .LBB97_2: # %atomicrmw.start ; RV32I-NEXT: .LBB97_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB97_1 ; RV32I-NEXT: bge s1, a0, .LBB97_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: j .LBB97_1
; RV32I-NEXT: .LBB97_4: # %atomicrmw.end ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_release: ; RV32IA-LABEL: atomicrmw_min_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB97_1 ; RV32IA-NEXT: bnez a2, .LBB97_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_release: ; RV64I-LABEL: atomicrmw_min_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB97_2 ; RV64I-NEXT: j .LBB97_2
; RV64I-NEXT: .LBB97_1: # %atomicrmw.start ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB97_4 ; RV64I-NEXT: bnez a0, .LBB97_4
; RV64I-NEXT: .LBB97_2: # %atomicrmw.start ; RV64I-NEXT: .LBB97_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB97_1 ; RV64I-NEXT: bge s1, a0, .LBB97_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: j .LBB97_1
; RV64I-NEXT: .LBB97_4: # %atomicrmw.end ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_release: ; RV64IA-LABEL: atomicrmw_min_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b release %1 = atomicrmw min i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acq_rel: ; RV32I-LABEL: atomicrmw_min_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB98_2 ; RV32I-NEXT: j .LBB98_2
; RV32I-NEXT: .LBB98_1: # %atomicrmw.start ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB98_4 ; RV32I-NEXT: bnez a0, .LBB98_4
; RV32I-NEXT: .LBB98_2: # %atomicrmw.start ; RV32I-NEXT: .LBB98_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB98_1 ; RV32I-NEXT: bge s1, a0, .LBB98_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: j .LBB98_1
; RV32I-NEXT: .LBB98_4: # %atomicrmw.end ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB98_1 ; RV32IA-NEXT: bnez a2, .LBB98_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acq_rel: ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB98_2 ; RV64I-NEXT: j .LBB98_2
; RV64I-NEXT: .LBB98_1: # %atomicrmw.start ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB98_4 ; RV64I-NEXT: bnez a0, .LBB98_4
; RV64I-NEXT: .LBB98_2: # %atomicrmw.start ; RV64I-NEXT: .LBB98_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB98_1 ; RV64I-NEXT: bge s1, a0, .LBB98_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: j .LBB98_1
; RV64I-NEXT: .LBB98_4: # %atomicrmw.end ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acq_rel %1 = atomicrmw min i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_seq_cst: ; RV32I-LABEL: atomicrmw_min_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB99_2 ; RV32I-NEXT: j .LBB99_2
; RV32I-NEXT: .LBB99_1: # %atomicrmw.start ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB99_4 ; RV32I-NEXT: bnez a0, .LBB99_4
; RV32I-NEXT: .LBB99_2: # %atomicrmw.start ; RV32I-NEXT: .LBB99_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB99_1 ; RV32I-NEXT: bge s1, a0, .LBB99_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: j .LBB99_1
; RV32I-NEXT: .LBB99_4: # %atomicrmw.end ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 21 Lines
; RV32IA-NEXT: bnez a2, .LBB99_1 ; RV32IA-NEXT: bnez a2, .LBB99_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB99_2 ; RV64I-NEXT: j .LBB99_2
; RV64I-NEXT: .LBB99_1: # %atomicrmw.start ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB99_4 ; RV64I-NEXT: bnez a0, .LBB99_4
; RV64I-NEXT: .LBB99_2: # %atomicrmw.start ; RV64I-NEXT: .LBB99_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB99_1 ; RV64I-NEXT: bge s1, a0, .LBB99_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: j .LBB99_1
; RV64I-NEXT: .LBB99_4: # %atomicrmw.end ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 25 Lines; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b seq_cst %1 = atomicrmw min i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_monotonic: ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: j .LBB100_2
; RV32I-NEXT: .LBB100_1: # %atomicrmw.start ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB100_4 ; RV32I-NEXT: bnez a0, .LBB100_4
; RV32I-NEXT: .LBB100_2: # %atomicrmw.start ; RV32I-NEXT: .LBB100_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB100_1 ; RV32I-NEXT: bltu s1, a0, .LBB100_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB100_1 ; RV32I-NEXT: j .LBB100_1
; RV32I-NEXT: .LBB100_4: # %atomicrmw.end ; RV32I-NEXT: .LBB100_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB100_1 ; RV32IA-NEXT: bnez a5, .LBB100_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: j .LBB100_2
; RV64I-NEXT: .LBB100_1: # %atomicrmw.start ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB100_4 ; RV64I-NEXT: bnez a0, .LBB100_4
; RV64I-NEXT: .LBB100_2: # %atomicrmw.start ; RV64I-NEXT: .LBB100_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB100_1 ; RV64I-NEXT: bltu s1, a0, .LBB100_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB100_1 ; RV64I-NEXT: j .LBB100_1
; RV64I-NEXT: .LBB100_4: # %atomicrmw.end ; RV64I-NEXT: .LBB100_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b monotonic %1 = atomicrmw umax i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acquire: ; RV32I-LABEL: atomicrmw_umax_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: j .LBB101_2
; RV32I-NEXT: .LBB101_1: # %atomicrmw.start ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB101_4 ; RV32I-NEXT: bnez a0, .LBB101_4
; RV32I-NEXT: .LBB101_2: # %atomicrmw.start ; RV32I-NEXT: .LBB101_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB101_1 ; RV32I-NEXT: bltu s1, a0, .LBB101_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB101_1 ; RV32I-NEXT: j .LBB101_1
; RV32I-NEXT: .LBB101_4: # %atomicrmw.end ; RV32I-NEXT: .LBB101_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA-LABEL: atomicrmw_umax_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB101_1 ; RV32IA-NEXT: bnez a5, .LBB101_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acquire: ; RV64I-LABEL: atomicrmw_umax_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: j .LBB101_2
; RV64I-NEXT: .LBB101_1: # %atomicrmw.start ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB101_4 ; RV64I-NEXT: bnez a0, .LBB101_4
; RV64I-NEXT: .LBB101_2: # %atomicrmw.start ; RV64I-NEXT: .LBB101_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB101_1 ; RV64I-NEXT: bltu s1, a0, .LBB101_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB101_1 ; RV64I-NEXT: j .LBB101_1
; RV64I-NEXT: .LBB101_4: # %atomicrmw.end ; RV64I-NEXT: .LBB101_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acquire %1 = atomicrmw umax i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_release: ; RV32I-LABEL: atomicrmw_umax_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: j .LBB102_2
; RV32I-NEXT: .LBB102_1: # %atomicrmw.start ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB102_4 ; RV32I-NEXT: bnez a0, .LBB102_4
; RV32I-NEXT: .LBB102_2: # %atomicrmw.start ; RV32I-NEXT: .LBB102_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB102_1 ; RV32I-NEXT: bltu s1, a0, .LBB102_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB102_1 ; RV32I-NEXT: j .LBB102_1
; RV32I-NEXT: .LBB102_4: # %atomicrmw.end ; RV32I-NEXT: .LBB102_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_release: ; RV32IA-LABEL: atomicrmw_umax_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB102_1 ; RV32IA-NEXT: bnez a5, .LBB102_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_release: ; RV64I-LABEL: atomicrmw_umax_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: j .LBB102_2
; RV64I-NEXT: .LBB102_1: # %atomicrmw.start ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB102_4 ; RV64I-NEXT: bnez a0, .LBB102_4
; RV64I-NEXT: .LBB102_2: # %atomicrmw.start ; RV64I-NEXT: .LBB102_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB102_1 ; RV64I-NEXT: bltu s1, a0, .LBB102_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB102_1 ; RV64I-NEXT: j .LBB102_1
; RV64I-NEXT: .LBB102_4: # %atomicrmw.end ; RV64I-NEXT: .LBB102_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_release: ; RV64IA-LABEL: atomicrmw_umax_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b release %1 = atomicrmw umax i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: j .LBB103_2
; RV32I-NEXT: .LBB103_1: # %atomicrmw.start ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB103_4 ; RV32I-NEXT: bnez a0, .LBB103_4
; RV32I-NEXT: .LBB103_2: # %atomicrmw.start ; RV32I-NEXT: .LBB103_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB103_1 ; RV32I-NEXT: bltu s1, a0, .LBB103_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB103_1 ; RV32I-NEXT: j .LBB103_1
; RV32I-NEXT: .LBB103_4: # %atomicrmw.end ; RV32I-NEXT: .LBB103_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB103_1 ; RV32IA-NEXT: bnez a5, .LBB103_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: j .LBB103_2
; RV64I-NEXT: .LBB103_1: # %atomicrmw.start ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB103_4 ; RV64I-NEXT: bnez a0, .LBB103_4
; RV64I-NEXT: .LBB103_2: # %atomicrmw.start ; RV64I-NEXT: .LBB103_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB103_1 ; RV64I-NEXT: bltu s1, a0, .LBB103_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB103_1 ; RV64I-NEXT: j .LBB103_1
; RV64I-NEXT: .LBB103_4: # %atomicrmw.end ; RV64I-NEXT: .LBB103_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acq_rel %1 = atomicrmw umax i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: j .LBB104_2
; RV32I-NEXT: .LBB104_1: # %atomicrmw.start ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB104_4 ; RV32I-NEXT: bnez a0, .LBB104_4
; RV32I-NEXT: .LBB104_2: # %atomicrmw.start ; RV32I-NEXT: .LBB104_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB104_1 ; RV32I-NEXT: bltu s1, a0, .LBB104_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB104_1 ; RV32I-NEXT: j .LBB104_1
; RV32I-NEXT: .LBB104_4: # %atomicrmw.end ; RV32I-NEXT: .LBB104_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: bnez a5, .LBB104_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: j .LBB104_2
; RV64I-NEXT: .LBB104_1: # %atomicrmw.start ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB104_4 ; RV64I-NEXT: bnez a0, .LBB104_4
; RV64I-NEXT: .LBB104_2: # %atomicrmw.start ; RV64I-NEXT: .LBB104_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB104_1 ; RV64I-NEXT: bltu s1, a0, .LBB104_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB104_1 ; RV64I-NEXT: j .LBB104_1
; RV64I-NEXT: .LBB104_4: # %atomicrmw.end ; RV64I-NEXT: .LBB104_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b seq_cst %1 = atomicrmw umax i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_monotonic: ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: j .LBB105_2
; RV32I-NEXT: .LBB105_1: # %atomicrmw.start ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB105_4 ; RV32I-NEXT: bnez a0, .LBB105_4
; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB105_1 ; RV32I-NEXT: bgeu s1, a0, .LBB105_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: j .LBB105_1
; RV32I-NEXT: .LBB105_4: # %atomicrmw.end ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB105_1 ; RV32IA-NEXT: bnez a5, .LBB105_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: j .LBB105_2
; RV64I-NEXT: .LBB105_1: # %atomicrmw.start ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB105_4 ; RV64I-NEXT: bnez a0, .LBB105_4
; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB105_1 ; RV64I-NEXT: bgeu s1, a0, .LBB105_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: j .LBB105_1
; RV64I-NEXT: .LBB105_4: # %atomicrmw.end ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b monotonic %1 = atomicrmw umin i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acquire: ; RV32I-LABEL: atomicrmw_umin_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: j .LBB106_2
; RV32I-NEXT: .LBB106_1: # %atomicrmw.start ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB106_4 ; RV32I-NEXT: bnez a0, .LBB106_4
; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB106_1 ; RV32I-NEXT: bgeu s1, a0, .LBB106_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: j .LBB106_1
; RV32I-NEXT: .LBB106_4: # %atomicrmw.end ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA-LABEL: atomicrmw_umin_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB106_1 ; RV32IA-NEXT: bnez a5, .LBB106_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acquire: ; RV64I-LABEL: atomicrmw_umin_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: j .LBB106_2
; RV64I-NEXT: .LBB106_1: # %atomicrmw.start ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB106_4 ; RV64I-NEXT: bnez a0, .LBB106_4
; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB106_1 ; RV64I-NEXT: bgeu s1, a0, .LBB106_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: j .LBB106_1
; RV64I-NEXT: .LBB106_4: # %atomicrmw.end ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acquire %1 = atomicrmw umin i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_release: ; RV32I-LABEL: atomicrmw_umin_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: j .LBB107_2
; RV32I-NEXT: .LBB107_1: # %atomicrmw.start ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB107_4 ; RV32I-NEXT: bnez a0, .LBB107_4
; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB107_1 ; RV32I-NEXT: bgeu s1, a0, .LBB107_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: j .LBB107_1
; RV32I-NEXT: .LBB107_4: # %atomicrmw.end ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_release: ; RV32IA-LABEL: atomicrmw_umin_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB107_1 ; RV32IA-NEXT: bnez a5, .LBB107_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_release: ; RV64I-LABEL: atomicrmw_umin_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: j .LBB107_2
; RV64I-NEXT: .LBB107_1: # %atomicrmw.start ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB107_4 ; RV64I-NEXT: bnez a0, .LBB107_4
; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB107_1 ; RV64I-NEXT: bgeu s1, a0, .LBB107_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: j .LBB107_1
; RV64I-NEXT: .LBB107_4: # %atomicrmw.end ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_release: ; RV64IA-LABEL: atomicrmw_umin_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b release %1 = atomicrmw umin i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: j .LBB108_2
; RV32I-NEXT: .LBB108_1: # %atomicrmw.start ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB108_4 ; RV32I-NEXT: bnez a0, .LBB108_4
; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB108_1 ; RV32I-NEXT: bgeu s1, a0, .LBB108_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: j .LBB108_1
; RV32I-NEXT: .LBB108_4: # %atomicrmw.end ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB108_1 ; RV32IA-NEXT: bnez a5, .LBB108_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: j .LBB108_2
; RV64I-NEXT: .LBB108_1: # %atomicrmw.start ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB108_4 ; RV64I-NEXT: bnez a0, .LBB108_4
; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB108_1 ; RV64I-NEXT: bgeu s1, a0, .LBB108_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: j .LBB108_1
; RV64I-NEXT: .LBB108_4: # %atomicrmw.end ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acq_rel %1 = atomicrmw umin i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s1, s2, s0
; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: j .LBB109_2
; RV32I-NEXT: .LBB109_1: # %atomicrmw.start ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2 ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB109_4 ; RV32I-NEXT: bnez a0, .LBB109_4
; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB109_1 ; RV32I-NEXT: bgeu s1, a0, .LBB109_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: j .LBB109_1
; RV32I-NEXT: .LBB109_4: # %atomicrmw.end ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a6, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
Show All 16 Lines
; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: bnez a5, .LBB109_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s1, s2, s0
; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: j .LBB109_2
; RV64I-NEXT: .LBB109_1: # %atomicrmw.start ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2 ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB109_4 ; RV64I-NEXT: bnez a0, .LBB109_4
; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB109_1 ; RV64I-NEXT: bgeu s1, a0, .LBB109_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: j .LBB109_1
; RV64I-NEXT: .LBB109_4: # %atomicrmw.end ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
Show All 20 Lines; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b seq_cst %1 = atomicrmw umin i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w a0, a1, (a0) ; RV32IA-NEXT: amoswap.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w a0, a1, (a0) ; RV64IA-NEXT: amoswap.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b monotonic %1 = atomicrmw xchg i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_acquire: ; RV32I-LABEL: atomicrmw_xchg_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_acquire: ; RV64I-LABEL: atomicrmw_xchg_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b acquire %1 = atomicrmw xchg i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_release: ; RV32I-LABEL: atomicrmw_xchg_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_release: ; RV32IA-LABEL: atomicrmw_xchg_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_release: ; RV64I-LABEL: atomicrmw_xchg_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_release: ; RV64IA-LABEL: atomicrmw_xchg_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b release %1 = atomicrmw xchg i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b acq_rel %1 = atomicrmw xchg i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_exchange_4 ; RV32I-NEXT: call __atomic_exchange_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_4 ; RV64I-NEXT: call __atomic_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i32* %a, i32 %b seq_cst %1 = atomicrmw xchg i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_monotonic: ; RV32I-LABEL: atomicrmw_add_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_monotonic: ; RV32IA-LABEL: atomicrmw_add_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_monotonic: ; RV64I-LABEL: atomicrmw_add_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_monotonic: ; RV64IA-LABEL: atomicrmw_add_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b monotonic %1 = atomicrmw add i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_acquire: ; RV32I-LABEL: atomicrmw_add_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_acquire: ; RV32IA-LABEL: atomicrmw_add_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_acquire: ; RV64I-LABEL: atomicrmw_add_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_acquire: ; RV64IA-LABEL: atomicrmw_add_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b acquire %1 = atomicrmw add i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_release: ; RV32I-LABEL: atomicrmw_add_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_release: ; RV32IA-LABEL: atomicrmw_add_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_release: ; RV64I-LABEL: atomicrmw_add_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_release: ; RV64IA-LABEL: atomicrmw_add_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b release %1 = atomicrmw add i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_acq_rel: ; RV32I-LABEL: atomicrmw_add_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_acq_rel: ; RV64I-LABEL: atomicrmw_add_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b acq_rel %1 = atomicrmw add i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i32_seq_cst: ; RV32I-LABEL: atomicrmw_add_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_4 ; RV32I-NEXT: call __atomic_fetch_add_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i32_seq_cst: ; RV64I-LABEL: atomicrmw_add_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_4 ; RV64I-NEXT: call __atomic_fetch_add_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i32* %a, i32 %b seq_cst %1 = atomicrmw add i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_monotonic: ; RV32I-LABEL: atomicrmw_sub_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w a0, a1, (a0) ; RV32IA-NEXT: amoadd.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_monotonic: ; RV64I-LABEL: atomicrmw_sub_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w a0, a1, (a0) ; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b monotonic %1 = atomicrmw sub i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_acquire: ; RV32I-LABEL: atomicrmw_sub_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_acquire: ; RV32IA-LABEL: atomicrmw_sub_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_acquire: ; RV64I-LABEL: atomicrmw_sub_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_acquire: ; RV64IA-LABEL: atomicrmw_sub_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b acquire %1 = atomicrmw sub i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_release: ; RV32I-LABEL: atomicrmw_sub_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_release: ; RV32IA-LABEL: atomicrmw_sub_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_release: ; RV64I-LABEL: atomicrmw_sub_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_release: ; RV64IA-LABEL: atomicrmw_sub_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b release %1 = atomicrmw sub i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b acq_rel %1 = atomicrmw sub i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_4 ; RV32I-NEXT: call __atomic_fetch_sub_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: neg a1, a1 ; RV32IA-NEXT: neg a1, a1
; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i32_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_4 ; RV64I-NEXT: call __atomic_fetch_sub_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i32* %a, i32 %b seq_cst %1 = atomicrmw sub i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_monotonic: ; RV32I-LABEL: atomicrmw_and_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_monotonic: ; RV32IA-LABEL: atomicrmw_and_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w a0, a1, (a0) ; RV32IA-NEXT: amoand.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_monotonic: ; RV64I-LABEL: atomicrmw_and_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_monotonic: ; RV64IA-LABEL: atomicrmw_and_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w a0, a1, (a0) ; RV64IA-NEXT: amoand.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b monotonic %1 = atomicrmw and i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_acquire: ; RV32I-LABEL: atomicrmw_and_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_acquire: ; RV32IA-LABEL: atomicrmw_and_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_acquire: ; RV64I-LABEL: atomicrmw_and_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_acquire: ; RV64IA-LABEL: atomicrmw_and_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b acquire %1 = atomicrmw and i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_release: ; RV32I-LABEL: atomicrmw_and_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_release: ; RV32IA-LABEL: atomicrmw_and_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_release: ; RV64I-LABEL: atomicrmw_and_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_release: ; RV64IA-LABEL: atomicrmw_and_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b release %1 = atomicrmw and i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_acq_rel: ; RV32I-LABEL: atomicrmw_and_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_acq_rel: ; RV64I-LABEL: atomicrmw_and_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b acq_rel %1 = atomicrmw and i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i32_seq_cst: ; RV32I-LABEL: atomicrmw_and_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_4 ; RV32I-NEXT: call __atomic_fetch_and_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i32_seq_cst: ; RV64I-LABEL: atomicrmw_and_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_4 ; RV64I-NEXT: call __atomic_fetch_and_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i32* %a, i32 %b seq_cst %1 = atomicrmw and i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_monotonic: ; RV32I-LABEL: atomicrmw_nand_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a0) ; RV32IA-NEXT: lr.w a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB130_1 ; RV32IA-NEXT: bnez a3, .LBB130_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_monotonic: ; RV64I-LABEL: atomicrmw_nand_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB130_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a0) ; RV64IA-NEXT: lr.w a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB130_1 ; RV64IA-NEXT: bnez a3, .LBB130_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b monotonic %1 = atomicrmw nand i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_acquire: ; RV32I-LABEL: atomicrmw_nand_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_acquire: ; RV32IA-LABEL: atomicrmw_nand_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w a3, a3, (a0) ; RV32IA-NEXT: sc.w a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB131_1 ; RV32IA-NEXT: bnez a3, .LBB131_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_acquire: ; RV64I-LABEL: atomicrmw_nand_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_acquire: ; RV64IA-LABEL: atomicrmw_nand_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB131_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: sc.w a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB131_1 ; RV64IA-NEXT: bnez a3, .LBB131_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b acquire %1 = atomicrmw nand i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_release: ; RV32I-LABEL: atomicrmw_nand_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_release: ; RV32IA-LABEL: atomicrmw_nand_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a0) ; RV32IA-NEXT: lr.w a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB132_1 ; RV32IA-NEXT: bnez a3, .LBB132_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_release: ; RV64I-LABEL: atomicrmw_nand_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_release: ; RV64IA-LABEL: atomicrmw_nand_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB132_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a0) ; RV64IA-NEXT: lr.w a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB132_1 ; RV64IA-NEXT: bnez a3, .LBB132_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b release %1 = atomicrmw nand i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a0) ; RV32IA-NEXT: lr.w.aq a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.rl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB133_1 ; RV32IA-NEXT: bnez a3, .LBB133_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB133_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a0) ; RV64IA-NEXT: lr.w.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.rl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB133_1 ; RV64IA-NEXT: bnez a3, .LBB133_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b acq_rel %1 = atomicrmw nand i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_4 ; RV32I-NEXT: call __atomic_fetch_nand_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB134_1 ; RV32IA-NEXT: bnez a3, .LBB134_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_4 ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB134_1 ; RV64IA-NEXT: bnez a3, .LBB134_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i32* %a, i32 %b seq_cst %1 = atomicrmw nand i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_monotonic: ; RV32I-LABEL: atomicrmw_or_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_monotonic: ; RV32IA-LABEL: atomicrmw_or_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w a0, a1, (a0) ; RV32IA-NEXT: amoor.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_monotonic: ; RV64I-LABEL: atomicrmw_or_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_monotonic: ; RV64IA-LABEL: atomicrmw_or_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w a0, a1, (a0) ; RV64IA-NEXT: amoor.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b monotonic %1 = atomicrmw or i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_acquire: ; RV32I-LABEL: atomicrmw_or_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_acquire: ; RV32IA-LABEL: atomicrmw_or_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_acquire: ; RV64I-LABEL: atomicrmw_or_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_acquire: ; RV64IA-LABEL: atomicrmw_or_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b acquire %1 = atomicrmw or i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_release: ; RV32I-LABEL: atomicrmw_or_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_release: ; RV32IA-LABEL: atomicrmw_or_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_release: ; RV64I-LABEL: atomicrmw_or_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_release: ; RV64IA-LABEL: atomicrmw_or_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b release %1 = atomicrmw or i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_acq_rel: ; RV32I-LABEL: atomicrmw_or_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_acq_rel: ; RV64I-LABEL: atomicrmw_or_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b acq_rel %1 = atomicrmw or i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i32_seq_cst: ; RV32I-LABEL: atomicrmw_or_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_4 ; RV32I-NEXT: call __atomic_fetch_or_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i32_seq_cst: ; RV64I-LABEL: atomicrmw_or_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_4 ; RV64I-NEXT: call __atomic_fetch_or_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i32* %a, i32 %b seq_cst %1 = atomicrmw or i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_monotonic: ; RV32I-LABEL: atomicrmw_xor_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w a0, a1, (a0) ; RV32IA-NEXT: amoxor.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_monotonic: ; RV64I-LABEL: atomicrmw_xor_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w a0, a1, (a0) ; RV64IA-NEXT: amoxor.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b monotonic %1 = atomicrmw xor i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_acquire: ; RV32I-LABEL: atomicrmw_xor_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_acquire: ; RV32IA-LABEL: atomicrmw_xor_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_acquire: ; RV64I-LABEL: atomicrmw_xor_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_acquire: ; RV64IA-LABEL: atomicrmw_xor_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b acquire %1 = atomicrmw xor i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_release: ; RV32I-LABEL: atomicrmw_xor_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_release: ; RV32IA-LABEL: atomicrmw_xor_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_release: ; RV64I-LABEL: atomicrmw_xor_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_release: ; RV64IA-LABEL: atomicrmw_xor_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b release %1 = atomicrmw xor i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 4 ; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b acq_rel %1 = atomicrmw xor i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i32_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_4 ; RV32I-NEXT: call __atomic_fetch_xor_4@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i32_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_4 ; RV64I-NEXT: call __atomic_fetch_xor_4@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i32* %a, i32 %b seq_cst %1 = atomicrmw xor i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_monotonic: ; RV32I-LABEL: atomicrmw_max_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB145_2 ; RV32I-NEXT: j .LBB145_2
; RV32I-NEXT: .LBB145_1: # %atomicrmw.start ; RV32I-NEXT: .LBB145_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB145_4 ; RV32I-NEXT: bnez a0, .LBB145_4
; RV32I-NEXT: .LBB145_2: # %atomicrmw.start ; RV32I-NEXT: .LBB145_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB145_1 ; RV32I-NEXT: blt s1, a3, .LBB145_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB145_1 ; RV32I-NEXT: j .LBB145_1
; RV32I-NEXT: .LBB145_4: # %atomicrmw.end ; RV32I-NEXT: .LBB145_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_monotonic: ; RV32IA-LABEL: atomicrmw_max_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w a0, a1, (a0) ; RV32IA-NEXT: amomax.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_monotonic: ; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB145_4 ; RV64I-NEXT: bnez a0, .LBB145_4
; RV64I-NEXT: .LBB145_2: # %atomicrmw.start ; RV64I-NEXT: .LBB145_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB145_1 ; RV64I-NEXT: blt s1, a0, .LBB145_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB145_1 ; RV64I-NEXT: j .LBB145_1
; RV64I-NEXT: .LBB145_4: # %atomicrmw.end ; RV64I-NEXT: .LBB145_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic: ; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w a0, a1, (a0) ; RV64IA-NEXT: amomax.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b monotonic %1 = atomicrmw max i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acquire: ; RV32I-LABEL: atomicrmw_max_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB146_2 ; RV32I-NEXT: j .LBB146_2
; RV32I-NEXT: .LBB146_1: # %atomicrmw.start ; RV32I-NEXT: .LBB146_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB146_4 ; RV32I-NEXT: bnez a0, .LBB146_4
; RV32I-NEXT: .LBB146_2: # %atomicrmw.start ; RV32I-NEXT: .LBB146_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB146_1 ; RV32I-NEXT: blt s1, a3, .LBB146_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB146_1 ; RV32I-NEXT: j .LBB146_1
; RV32I-NEXT: .LBB146_4: # %atomicrmw.end ; RV32I-NEXT: .LBB146_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acquire: ; RV32IA-LABEL: atomicrmw_max_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acquire: ; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB146_4 ; RV64I-NEXT: bnez a0, .LBB146_4
; RV64I-NEXT: .LBB146_2: # %atomicrmw.start ; RV64I-NEXT: .LBB146_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB146_1 ; RV64I-NEXT: blt s1, a0, .LBB146_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB146_1 ; RV64I-NEXT: j .LBB146_1
; RV64I-NEXT: .LBB146_4: # %atomicrmw.end ; RV64I-NEXT: .LBB146_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acquire: ; RV64IA-LABEL: atomicrmw_max_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acquire %1 = atomicrmw max i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_release: ; RV32I-LABEL: atomicrmw_max_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB147_2 ; RV32I-NEXT: j .LBB147_2
; RV32I-NEXT: .LBB147_1: # %atomicrmw.start ; RV32I-NEXT: .LBB147_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB147_4 ; RV32I-NEXT: bnez a0, .LBB147_4
; RV32I-NEXT: .LBB147_2: # %atomicrmw.start ; RV32I-NEXT: .LBB147_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB147_1 ; RV32I-NEXT: blt s1, a3, .LBB147_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB147_1 ; RV32I-NEXT: j .LBB147_1
; RV32I-NEXT: .LBB147_4: # %atomicrmw.end ; RV32I-NEXT: .LBB147_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_release: ; RV32IA-LABEL: atomicrmw_max_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_release: ; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB147_4 ; RV64I-NEXT: bnez a0, .LBB147_4
; RV64I-NEXT: .LBB147_2: # %atomicrmw.start ; RV64I-NEXT: .LBB147_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB147_1 ; RV64I-NEXT: blt s1, a0, .LBB147_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB147_1 ; RV64I-NEXT: j .LBB147_1
; RV64I-NEXT: .LBB147_4: # %atomicrmw.end ; RV64I-NEXT: .LBB147_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_release: ; RV64IA-LABEL: atomicrmw_max_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b release %1 = atomicrmw max i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acq_rel: ; RV32I-LABEL: atomicrmw_max_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB148_2 ; RV32I-NEXT: j .LBB148_2
; RV32I-NEXT: .LBB148_1: # %atomicrmw.start ; RV32I-NEXT: .LBB148_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB148_4 ; RV32I-NEXT: bnez a0, .LBB148_4
; RV32I-NEXT: .LBB148_2: # %atomicrmw.start ; RV32I-NEXT: .LBB148_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB148_1 ; RV32I-NEXT: blt s1, a3, .LBB148_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB148_1 ; RV32I-NEXT: j .LBB148_1
; RV32I-NEXT: .LBB148_4: # %atomicrmw.end ; RV32I-NEXT: .LBB148_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_acq_rel: ; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB148_4 ; RV64I-NEXT: bnez a0, .LBB148_4
; RV64I-NEXT: .LBB148_2: # %atomicrmw.start ; RV64I-NEXT: .LBB148_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB148_1 ; RV64I-NEXT: blt s1, a0, .LBB148_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB148_1 ; RV64I-NEXT: j .LBB148_1
; RV64I-NEXT: .LBB148_4: # %atomicrmw.end ; RV64I-NEXT: .LBB148_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b acq_rel %1 = atomicrmw max i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_seq_cst: ; RV32I-LABEL: atomicrmw_max_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB149_2 ; RV32I-NEXT: j .LBB149_2
; RV32I-NEXT: .LBB149_1: # %atomicrmw.start ; RV32I-NEXT: .LBB149_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB149_4 ; RV32I-NEXT: bnez a0, .LBB149_4
; RV32I-NEXT: .LBB149_2: # %atomicrmw.start ; RV32I-NEXT: .LBB149_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a3, .LBB149_1 ; RV32I-NEXT: blt s1, a3, .LBB149_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB149_1 ; RV32I-NEXT: j .LBB149_1
; RV32I-NEXT: .LBB149_4: # %atomicrmw.end ; RV32I-NEXT: .LBB149_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i32_seq_cst: ; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB149_4 ; RV64I-NEXT: bnez a0, .LBB149_4
; RV64I-NEXT: .LBB149_2: # %atomicrmw.start ; RV64I-NEXT: .LBB149_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB149_1 ; RV64I-NEXT: blt s1, a0, .LBB149_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB149_1 ; RV64I-NEXT: j .LBB149_1
; RV64I-NEXT: .LBB149_4: # %atomicrmw.end ; RV64I-NEXT: .LBB149_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i32* %a, i32 %b seq_cst %1 = atomicrmw max i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_monotonic: ; RV32I-LABEL: atomicrmw_min_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB150_2 ; RV32I-NEXT: j .LBB150_2
; RV32I-NEXT: .LBB150_1: # %atomicrmw.start ; RV32I-NEXT: .LBB150_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB150_4 ; RV32I-NEXT: bnez a0, .LBB150_4
; RV32I-NEXT: .LBB150_2: # %atomicrmw.start ; RV32I-NEXT: .LBB150_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB150_1 ; RV32I-NEXT: bge s1, a3, .LBB150_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB150_1 ; RV32I-NEXT: j .LBB150_1
; RV32I-NEXT: .LBB150_4: # %atomicrmw.end ; RV32I-NEXT: .LBB150_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_monotonic: ; RV32IA-LABEL: atomicrmw_min_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w a0, a1, (a0) ; RV32IA-NEXT: amomin.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_monotonic: ; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB150_4 ; RV64I-NEXT: bnez a0, .LBB150_4
; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB150_1 ; RV64I-NEXT: bge s1, a0, .LBB150_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: j .LBB150_1
; RV64I-NEXT: .LBB150_4: # %atomicrmw.end ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic: ; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w a0, a1, (a0) ; RV64IA-NEXT: amomin.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b monotonic %1 = atomicrmw min i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acquire: ; RV32I-LABEL: atomicrmw_min_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB151_2 ; RV32I-NEXT: j .LBB151_2
; RV32I-NEXT: .LBB151_1: # %atomicrmw.start ; RV32I-NEXT: .LBB151_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB151_4 ; RV32I-NEXT: bnez a0, .LBB151_4
; RV32I-NEXT: .LBB151_2: # %atomicrmw.start ; RV32I-NEXT: .LBB151_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB151_1 ; RV32I-NEXT: bge s1, a3, .LBB151_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB151_1 ; RV32I-NEXT: j .LBB151_1
; RV32I-NEXT: .LBB151_4: # %atomicrmw.end ; RV32I-NEXT: .LBB151_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acquire: ; RV32IA-LABEL: atomicrmw_min_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acquire: ; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB151_4 ; RV64I-NEXT: bnez a0, .LBB151_4
; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB151_1 ; RV64I-NEXT: bge s1, a0, .LBB151_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: j .LBB151_1
; RV64I-NEXT: .LBB151_4: # %atomicrmw.end ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acquire: ; RV64IA-LABEL: atomicrmw_min_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acquire %1 = atomicrmw min i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_release: ; RV32I-LABEL: atomicrmw_min_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB152_2 ; RV32I-NEXT: j .LBB152_2
; RV32I-NEXT: .LBB152_1: # %atomicrmw.start ; RV32I-NEXT: .LBB152_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB152_4 ; RV32I-NEXT: bnez a0, .LBB152_4
; RV32I-NEXT: .LBB152_2: # %atomicrmw.start ; RV32I-NEXT: .LBB152_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB152_1 ; RV32I-NEXT: bge s1, a3, .LBB152_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB152_1 ; RV32I-NEXT: j .LBB152_1
; RV32I-NEXT: .LBB152_4: # %atomicrmw.end ; RV32I-NEXT: .LBB152_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_release: ; RV32IA-LABEL: atomicrmw_min_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_release: ; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB152_4 ; RV64I-NEXT: bnez a0, .LBB152_4
; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB152_1 ; RV64I-NEXT: bge s1, a0, .LBB152_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: j .LBB152_1
; RV64I-NEXT: .LBB152_4: # %atomicrmw.end ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_release: ; RV64IA-LABEL: atomicrmw_min_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b release %1 = atomicrmw min i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acq_rel: ; RV32I-LABEL: atomicrmw_min_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB153_2 ; RV32I-NEXT: j .LBB153_2
; RV32I-NEXT: .LBB153_1: # %atomicrmw.start ; RV32I-NEXT: .LBB153_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB153_4 ; RV32I-NEXT: bnez a0, .LBB153_4
; RV32I-NEXT: .LBB153_2: # %atomicrmw.start ; RV32I-NEXT: .LBB153_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB153_1 ; RV32I-NEXT: bge s1, a3, .LBB153_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB153_1 ; RV32I-NEXT: j .LBB153_1
; RV32I-NEXT: .LBB153_4: # %atomicrmw.end ; RV32I-NEXT: .LBB153_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_acq_rel: ; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB153_4 ; RV64I-NEXT: bnez a0, .LBB153_4
; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB153_1 ; RV64I-NEXT: bge s1, a0, .LBB153_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: j .LBB153_1
; RV64I-NEXT: .LBB153_4: # %atomicrmw.end ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b acq_rel %1 = atomicrmw min i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_seq_cst: ; RV32I-LABEL: atomicrmw_min_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB154_2 ; RV32I-NEXT: j .LBB154_2
; RV32I-NEXT: .LBB154_1: # %atomicrmw.start ; RV32I-NEXT: .LBB154_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB154_4 ; RV32I-NEXT: bnez a0, .LBB154_4
; RV32I-NEXT: .LBB154_2: # %atomicrmw.start ; RV32I-NEXT: .LBB154_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a3, .LBB154_1 ; RV32I-NEXT: bge s1, a3, .LBB154_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB154_1 ; RV32I-NEXT: j .LBB154_1
; RV32I-NEXT: .LBB154_4: # %atomicrmw.end ; RV32I-NEXT: .LBB154_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i32_seq_cst: ; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB154_4 ; RV64I-NEXT: bnez a0, .LBB154_4
; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB154_1 ; RV64I-NEXT: bge s1, a0, .LBB154_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: j .LBB154_1
; RV64I-NEXT: .LBB154_4: # %atomicrmw.end ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i32* %a, i32 %b seq_cst %1 = atomicrmw min i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_monotonic: ; RV32I-LABEL: atomicrmw_umax_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB155_2 ; RV32I-NEXT: j .LBB155_2
; RV32I-NEXT: .LBB155_1: # %atomicrmw.start ; RV32I-NEXT: .LBB155_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB155_4 ; RV32I-NEXT: bnez a0, .LBB155_4
; RV32I-NEXT: .LBB155_2: # %atomicrmw.start ; RV32I-NEXT: .LBB155_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB155_1 ; RV32I-NEXT: bltu s1, a3, .LBB155_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB155_1 ; RV32I-NEXT: j .LBB155_1
; RV32I-NEXT: .LBB155_4: # %atomicrmw.end ; RV32I-NEXT: .LBB155_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic: ; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB155_4 ; RV64I-NEXT: bnez a0, .LBB155_4
; RV64I-NEXT: .LBB155_2: # %atomicrmw.start ; RV64I-NEXT: .LBB155_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB155_1 ; RV64I-NEXT: bltu s1, a0, .LBB155_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB155_1 ; RV64I-NEXT: j .LBB155_1
; RV64I-NEXT: .LBB155_4: # %atomicrmw.end ; RV64I-NEXT: .LBB155_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b monotonic %1 = atomicrmw umax i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acquire: ; RV32I-LABEL: atomicrmw_umax_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB156_2 ; RV32I-NEXT: j .LBB156_2
; RV32I-NEXT: .LBB156_1: # %atomicrmw.start ; RV32I-NEXT: .LBB156_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB156_4 ; RV32I-NEXT: bnez a0, .LBB156_4
; RV32I-NEXT: .LBB156_2: # %atomicrmw.start ; RV32I-NEXT: .LBB156_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB156_1 ; RV32I-NEXT: bltu s1, a3, .LBB156_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB156_1 ; RV32I-NEXT: j .LBB156_1
; RV32I-NEXT: .LBB156_4: # %atomicrmw.end ; RV32I-NEXT: .LBB156_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acquire: ; RV32IA-LABEL: atomicrmw_umax_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acquire: ; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB156_4 ; RV64I-NEXT: bnez a0, .LBB156_4
; RV64I-NEXT: .LBB156_2: # %atomicrmw.start ; RV64I-NEXT: .LBB156_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB156_1 ; RV64I-NEXT: bltu s1, a0, .LBB156_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB156_1 ; RV64I-NEXT: j .LBB156_1
; RV64I-NEXT: .LBB156_4: # %atomicrmw.end ; RV64I-NEXT: .LBB156_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acquire: ; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acquire %1 = atomicrmw umax i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_release: ; RV32I-LABEL: atomicrmw_umax_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB157_2 ; RV32I-NEXT: j .LBB157_2
; RV32I-NEXT: .LBB157_1: # %atomicrmw.start ; RV32I-NEXT: .LBB157_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB157_4 ; RV32I-NEXT: bnez a0, .LBB157_4
; RV32I-NEXT: .LBB157_2: # %atomicrmw.start ; RV32I-NEXT: .LBB157_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB157_1 ; RV32I-NEXT: bltu s1, a3, .LBB157_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB157_1 ; RV32I-NEXT: j .LBB157_1
; RV32I-NEXT: .LBB157_4: # %atomicrmw.end ; RV32I-NEXT: .LBB157_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_release: ; RV32IA-LABEL: atomicrmw_umax_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_release: ; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB157_4 ; RV64I-NEXT: bnez a0, .LBB157_4
; RV64I-NEXT: .LBB157_2: # %atomicrmw.start ; RV64I-NEXT: .LBB157_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB157_1 ; RV64I-NEXT: bltu s1, a0, .LBB157_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB157_1 ; RV64I-NEXT: j .LBB157_1
; RV64I-NEXT: .LBB157_4: # %atomicrmw.end ; RV64I-NEXT: .LBB157_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_release: ; RV64IA-LABEL: atomicrmw_umax_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b release %1 = atomicrmw umax i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB158_2 ; RV32I-NEXT: j .LBB158_2
; RV32I-NEXT: .LBB158_1: # %atomicrmw.start ; RV32I-NEXT: .LBB158_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB158_4 ; RV32I-NEXT: bnez a0, .LBB158_4
; RV32I-NEXT: .LBB158_2: # %atomicrmw.start ; RV32I-NEXT: .LBB158_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB158_1 ; RV32I-NEXT: bltu s1, a3, .LBB158_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB158_1 ; RV32I-NEXT: j .LBB158_1
; RV32I-NEXT: .LBB158_4: # %atomicrmw.end ; RV32I-NEXT: .LBB158_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB158_4 ; RV64I-NEXT: bnez a0, .LBB158_4
; RV64I-NEXT: .LBB158_2: # %atomicrmw.start ; RV64I-NEXT: .LBB158_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB158_1 ; RV64I-NEXT: bltu s1, a0, .LBB158_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB158_1 ; RV64I-NEXT: j .LBB158_1
; RV64I-NEXT: .LBB158_4: # %atomicrmw.end ; RV64I-NEXT: .LBB158_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b acq_rel %1 = atomicrmw umax i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB159_2 ; RV32I-NEXT: j .LBB159_2
; RV32I-NEXT: .LBB159_1: # %atomicrmw.start ; RV32I-NEXT: .LBB159_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB159_4 ; RV32I-NEXT: bnez a0, .LBB159_4
; RV32I-NEXT: .LBB159_2: # %atomicrmw.start ; RV32I-NEXT: .LBB159_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a3, .LBB159_1 ; RV32I-NEXT: bltu s1, a3, .LBB159_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB159_1 ; RV32I-NEXT: j .LBB159_1
; RV32I-NEXT: .LBB159_4: # %atomicrmw.end ; RV32I-NEXT: .LBB159_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB159_4 ; RV64I-NEXT: bnez a0, .LBB159_4
; RV64I-NEXT: .LBB159_2: # %atomicrmw.start ; RV64I-NEXT: .LBB159_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB159_1 ; RV64I-NEXT: bltu s1, a0, .LBB159_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB159_1 ; RV64I-NEXT: j .LBB159_1
; RV64I-NEXT: .LBB159_4: # %atomicrmw.end ; RV64I-NEXT: .LBB159_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i32* %a, i32 %b seq_cst %1 = atomicrmw umax i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_monotonic: ; RV32I-LABEL: atomicrmw_umin_i32_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB160_2 ; RV32I-NEXT: j .LBB160_2
; RV32I-NEXT: .LBB160_1: # %atomicrmw.start ; RV32I-NEXT: .LBB160_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB160_4 ; RV32I-NEXT: bnez a0, .LBB160_4
; RV32I-NEXT: .LBB160_2: # %atomicrmw.start ; RV32I-NEXT: .LBB160_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB160_1 ; RV32I-NEXT: bgeu s1, a3, .LBB160_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB160_1 ; RV32I-NEXT: j .LBB160_1
; RV32I-NEXT: .LBB160_4: # %atomicrmw.end ; RV32I-NEXT: .LBB160_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w a0, a1, (a0) ; RV32IA-NEXT: amominu.w a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic: ; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB160_4 ; RV64I-NEXT: bnez a0, .LBB160_4
; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB160_1 ; RV64I-NEXT: bgeu s1, a0, .LBB160_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: j .LBB160_1
; RV64I-NEXT: .LBB160_4: # %atomicrmw.end ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w a0, a1, (a0) ; RV64IA-NEXT: amominu.w a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b monotonic %1 = atomicrmw umin i32* %a, i32 %b monotonic
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acquire: ; RV32I-LABEL: atomicrmw_umin_i32_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB161_2 ; RV32I-NEXT: j .LBB161_2
; RV32I-NEXT: .LBB161_1: # %atomicrmw.start ; RV32I-NEXT: .LBB161_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB161_4 ; RV32I-NEXT: bnez a0, .LBB161_4
; RV32I-NEXT: .LBB161_2: # %atomicrmw.start ; RV32I-NEXT: .LBB161_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB161_1 ; RV32I-NEXT: bgeu s1, a3, .LBB161_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB161_1 ; RV32I-NEXT: j .LBB161_1
; RV32I-NEXT: .LBB161_4: # %atomicrmw.end ; RV32I-NEXT: .LBB161_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acquire: ; RV32IA-LABEL: atomicrmw_umin_i32_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acquire: ; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB161_4 ; RV64I-NEXT: bnez a0, .LBB161_4
; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB161_1 ; RV64I-NEXT: bgeu s1, a0, .LBB161_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: j .LBB161_1
; RV64I-NEXT: .LBB161_4: # %atomicrmw.end ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acquire: ; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aq a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acquire %1 = atomicrmw umin i32* %a, i32 %b acquire
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_release: ; RV32I-LABEL: atomicrmw_umin_i32_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB162_2 ; RV32I-NEXT: j .LBB162_2
; RV32I-NEXT: .LBB162_1: # %atomicrmw.start ; RV32I-NEXT: .LBB162_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB162_4 ; RV32I-NEXT: bnez a0, .LBB162_4
; RV32I-NEXT: .LBB162_2: # %atomicrmw.start ; RV32I-NEXT: .LBB162_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB162_1 ; RV32I-NEXT: bgeu s1, a3, .LBB162_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB162_1 ; RV32I-NEXT: j .LBB162_1
; RV32I-NEXT: .LBB162_4: # %atomicrmw.end ; RV32I-NEXT: .LBB162_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_release: ; RV32IA-LABEL: atomicrmw_umin_i32_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_release: ; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB162_4 ; RV64I-NEXT: bnez a0, .LBB162_4
; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB162_1 ; RV64I-NEXT: bgeu s1, a0, .LBB162_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: j .LBB162_1
; RV64I-NEXT: .LBB162_4: # %atomicrmw.end ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_release: ; RV64IA-LABEL: atomicrmw_umin_i32_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.rl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b release %1 = atomicrmw umin i32* %a, i32 %b release
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB163_2 ; RV32I-NEXT: j .LBB163_2
; RV32I-NEXT: .LBB163_1: # %atomicrmw.start ; RV32I-NEXT: .LBB163_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB163_4 ; RV32I-NEXT: bnez a0, .LBB163_4
; RV32I-NEXT: .LBB163_2: # %atomicrmw.start ; RV32I-NEXT: .LBB163_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB163_1 ; RV32I-NEXT: bgeu s1, a3, .LBB163_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB163_1 ; RV32I-NEXT: j .LBB163_1
; RV32I-NEXT: .LBB163_4: # %atomicrmw.end ; RV32I-NEXT: .LBB163_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB163_4 ; RV64I-NEXT: bnez a0, .LBB163_4
; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB163_1 ; RV64I-NEXT: bgeu s1, a0, .LBB163_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: j .LBB163_1
; RV64I-NEXT: .LBB163_4: # %atomicrmw.end ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b acq_rel %1 = atomicrmw umin i32* %a, i32 %b acq_rel
ret i32 %1 ret i32 %1
} }
define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0) ; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: j .LBB164_2 ; RV32I-NEXT: j .LBB164_2
; RV32I-NEXT: .LBB164_1: # %atomicrmw.start ; RV32I-NEXT: .LBB164_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV32I-NEXT: sw a3, 0(sp) ; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_4 ; RV32I-NEXT: call __atomic_compare_exchange_4@plt
; RV32I-NEXT: lw a3, 0(sp) ; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB164_4 ; RV32I-NEXT: bnez a0, .LBB164_4
; RV32I-NEXT: .LBB164_2: # %atomicrmw.start ; RV32I-NEXT: .LBB164_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB164_1 ; RV32I-NEXT: bgeu s1, a3, .LBB164_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB164_1 ; RV32I-NEXT: j .LBB164_1
; RV32I-NEXT: .LBB164_4: # %atomicrmw.end ; RV32I-NEXT: .LBB164_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0) ; RV64I-NEXT: lwu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s1, a1
; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4 ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB164_4 ; RV64I-NEXT: bnez a0, .LBB164_4
; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sext.w a0, a3 ; RV64I-NEXT: sext.w a0, a3
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB164_1 ; RV64I-NEXT: bgeu s1, a0, .LBB164_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: j .LBB164_1
; RV64I-NEXT: .LBB164_4: # %atomicrmw.end ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0) ; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i32* %a, i32 %b seq_cst %1 = atomicrmw umin i32* %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32I-LABEL: atomicrmw_xchg_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV32IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64I-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic: ; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d a0, a1, (a0) ; RV64IA-NEXT: amoswap.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b monotonic %1 = atomicrmw xchg i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_acquire: ; RV32I-LABEL: atomicrmw_xchg_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_acquire: ; RV32IA-LABEL: atomicrmw_xchg_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_acquire: ; RV64I-LABEL: atomicrmw_xchg_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_acquire: ; RV64IA-LABEL: atomicrmw_xchg_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b acquire %1 = atomicrmw xchg i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_release: ; RV32I-LABEL: atomicrmw_xchg_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_release: ; RV32IA-LABEL: atomicrmw_xchg_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_release: ; RV64I-LABEL: atomicrmw_xchg_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_release: ; RV64IA-LABEL: atomicrmw_xchg_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b release %1 = atomicrmw xchg i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV64I-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b acq_rel %1 = atomicrmw xchg i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_exchange_8 ; RV32I-NEXT: call __atomic_exchange_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_exchange_8 ; RV32IA-NEXT: call __atomic_exchange_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_exchange_8 ; RV64I-NEXT: call __atomic_exchange_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg i64* %a, i64 %b seq_cst %1 = atomicrmw xchg i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_monotonic: ; RV32I-LABEL: atomicrmw_add_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_monotonic: ; RV32IA-LABEL: atomicrmw_add_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_monotonic: ; RV64I-LABEL: atomicrmw_add_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_monotonic: ; RV64IA-LABEL: atomicrmw_add_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b monotonic %1 = atomicrmw add i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_acquire: ; RV32I-LABEL: atomicrmw_add_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_acquire: ; RV32IA-LABEL: atomicrmw_add_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_acquire: ; RV64I-LABEL: atomicrmw_add_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_acquire: ; RV64IA-LABEL: atomicrmw_add_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b acquire %1 = atomicrmw add i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_release: ; RV32I-LABEL: atomicrmw_add_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_release: ; RV32IA-LABEL: atomicrmw_add_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_release: ; RV64I-LABEL: atomicrmw_add_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_release: ; RV64IA-LABEL: atomicrmw_add_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b release %1 = atomicrmw add i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_acq_rel: ; RV32I-LABEL: atomicrmw_add_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_add_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_acq_rel: ; RV64I-LABEL: atomicrmw_add_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_add_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b acq_rel %1 = atomicrmw add i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_add_i64_seq_cst: ; RV32I-LABEL: atomicrmw_add_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_add_8 ; RV32I-NEXT: call __atomic_fetch_add_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_add_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_add_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_add_8 ; RV32IA-NEXT: call __atomic_fetch_add_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i64_seq_cst: ; RV64I-LABEL: atomicrmw_add_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_add_8 ; RV64I-NEXT: call __atomic_fetch_add_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_add_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_add_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add i64* %a, i64 %b seq_cst %1 = atomicrmw add i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_monotonic: ; RV32I-LABEL: atomicrmw_sub_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV32IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_monotonic: ; RV64I-LABEL: atomicrmw_sub_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_monotonic: ; RV64IA-LABEL: atomicrmw_sub_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d a0, a1, (a0) ; RV64IA-NEXT: amoadd.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b monotonic %1 = atomicrmw sub i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_acquire: ; RV32I-LABEL: atomicrmw_sub_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_acquire: ; RV32IA-LABEL: atomicrmw_sub_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_acquire: ; RV64I-LABEL: atomicrmw_sub_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_acquire: ; RV64IA-LABEL: atomicrmw_sub_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b acquire %1 = atomicrmw sub i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_release: ; RV32I-LABEL: atomicrmw_sub_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_release: ; RV32IA-LABEL: atomicrmw_sub_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_release: ; RV64I-LABEL: atomicrmw_sub_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_release: ; RV64IA-LABEL: atomicrmw_sub_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b release %1 = atomicrmw sub i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32I-LABEL: atomicrmw_sub_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_sub_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_acq_rel: ; RV64I-LABEL: atomicrmw_sub_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b acq_rel %1 = atomicrmw sub i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32I-LABEL: atomicrmw_sub_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_sub_8 ; RV32I-NEXT: call __atomic_fetch_sub_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_sub_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_sub_8 ; RV32IA-NEXT: call __atomic_fetch_sub_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i64_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_sub_8 ; RV64I-NEXT: call __atomic_fetch_sub_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: neg a1, a1
; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub i64* %a, i64 %b seq_cst %1 = atomicrmw sub i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_monotonic: ; RV32I-LABEL: atomicrmw_and_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_monotonic: ; RV32IA-LABEL: atomicrmw_and_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_monotonic: ; RV64I-LABEL: atomicrmw_and_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_monotonic: ; RV64IA-LABEL: atomicrmw_and_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d a0, a1, (a0) ; RV64IA-NEXT: amoand.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b monotonic %1 = atomicrmw and i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_acquire: ; RV32I-LABEL: atomicrmw_and_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_acquire: ; RV32IA-LABEL: atomicrmw_and_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_acquire: ; RV64I-LABEL: atomicrmw_and_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_acquire: ; RV64IA-LABEL: atomicrmw_and_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b acquire %1 = atomicrmw and i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_release: ; RV32I-LABEL: atomicrmw_and_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_release: ; RV32IA-LABEL: atomicrmw_and_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_release: ; RV64I-LABEL: atomicrmw_and_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_release: ; RV64IA-LABEL: atomicrmw_and_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b release %1 = atomicrmw and i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_acq_rel: ; RV32I-LABEL: atomicrmw_and_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_and_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_acq_rel: ; RV64I-LABEL: atomicrmw_and_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_and_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b acq_rel %1 = atomicrmw and i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_and_i64_seq_cst: ; RV32I-LABEL: atomicrmw_and_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_and_8 ; RV32I-NEXT: call __atomic_fetch_and_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_and_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_and_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_and_8 ; RV32IA-NEXT: call __atomic_fetch_and_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_and_i64_seq_cst: ; RV64I-LABEL: atomicrmw_and_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_and_8 ; RV64I-NEXT: call __atomic_fetch_and_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_and_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_and_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw and i64* %a, i64 %b seq_cst %1 = atomicrmw and i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_monotonic: ; RV32I-LABEL: atomicrmw_nand_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_monotonic: ; RV32IA-LABEL: atomicrmw_nand_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_monotonic: ; RV64I-LABEL: atomicrmw_nand_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_monotonic: ; RV64IA-LABEL: atomicrmw_nand_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB185_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a2, (a0) ; RV64IA-NEXT: lr.d a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d a3, a3, (a0) ; RV64IA-NEXT: sc.d a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB185_1 ; RV64IA-NEXT: bnez a3, .LBB185_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b monotonic %1 = atomicrmw nand i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_acquire: ; RV32I-LABEL: atomicrmw_nand_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_acquire: ; RV32IA-LABEL: atomicrmw_nand_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_acquire: ; RV64I-LABEL: atomicrmw_nand_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_acquire: ; RV64IA-LABEL: atomicrmw_nand_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB186_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a2, (a0) ; RV64IA-NEXT: lr.d.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d a3, a3, (a0) ; RV64IA-NEXT: sc.d a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB186_1 ; RV64IA-NEXT: bnez a3, .LBB186_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b acquire %1 = atomicrmw nand i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_release: ; RV32I-LABEL: atomicrmw_nand_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_release: ; RV32IA-LABEL: atomicrmw_nand_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_release: ; RV64I-LABEL: atomicrmw_nand_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_release: ; RV64IA-LABEL: atomicrmw_nand_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB187_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d a2, (a0) ; RV64IA-NEXT: lr.d a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.rl a3, a3, (a0) ; RV64IA-NEXT: sc.d.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB187_1 ; RV64IA-NEXT: bnez a3, .LBB187_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b release %1 = atomicrmw nand i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32I-LABEL: atomicrmw_nand_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_nand_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_acq_rel: ; RV64I-LABEL: atomicrmw_nand_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_nand_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB188_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aq a2, (a0) ; RV64IA-NEXT: lr.d.aq a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.rl a3, a3, (a0) ; RV64IA-NEXT: sc.d.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB188_1 ; RV64IA-NEXT: bnez a3, .LBB188_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b acq_rel %1 = atomicrmw nand i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32I-LABEL: atomicrmw_nand_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_nand_8 ; RV32I-NEXT: call __atomic_fetch_nand_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_nand_8 ; RV32IA-NEXT: call __atomic_fetch_nand_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_nand_8 ; RV64I-NEXT: call __atomic_fetch_nand_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: lr.d.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.d.aqrl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB189_1 ; RV64IA-NEXT: bnez a3, .LBB189_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand i64* %a, i64 %b seq_cst %1 = atomicrmw nand i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_monotonic: ; RV32I-LABEL: atomicrmw_or_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_monotonic: ; RV32IA-LABEL: atomicrmw_or_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_monotonic: ; RV64I-LABEL: atomicrmw_or_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_monotonic: ; RV64IA-LABEL: atomicrmw_or_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d a0, a1, (a0) ; RV64IA-NEXT: amoor.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b monotonic %1 = atomicrmw or i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_acquire: ; RV32I-LABEL: atomicrmw_or_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_acquire: ; RV32IA-LABEL: atomicrmw_or_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_acquire: ; RV64I-LABEL: atomicrmw_or_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_acquire: ; RV64IA-LABEL: atomicrmw_or_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b acquire %1 = atomicrmw or i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_release: ; RV32I-LABEL: atomicrmw_or_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_release: ; RV32IA-LABEL: atomicrmw_or_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_release: ; RV64I-LABEL: atomicrmw_or_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_release: ; RV64IA-LABEL: atomicrmw_or_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b release %1 = atomicrmw or i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_acq_rel: ; RV32I-LABEL: atomicrmw_or_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_or_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_acq_rel: ; RV64I-LABEL: atomicrmw_or_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_or_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b acq_rel %1 = atomicrmw or i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_or_i64_seq_cst: ; RV32I-LABEL: atomicrmw_or_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_or_8 ; RV32I-NEXT: call __atomic_fetch_or_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_or_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_or_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_or_8 ; RV32IA-NEXT: call __atomic_fetch_or_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_or_i64_seq_cst: ; RV64I-LABEL: atomicrmw_or_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_or_8 ; RV64I-NEXT: call __atomic_fetch_or_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_or_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_or_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw or i64* %a, i64 %b seq_cst %1 = atomicrmw or i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_monotonic: ; RV32I-LABEL: atomicrmw_xor_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV32IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv a3, zero ; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_monotonic: ; RV64I-LABEL: atomicrmw_xor_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a2, zero
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_monotonic: ; RV64IA-LABEL: atomicrmw_xor_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d a0, a1, (a0) ; RV64IA-NEXT: amoxor.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b monotonic %1 = atomicrmw xor i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_acquire: ; RV32I-LABEL: atomicrmw_xor_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_acquire: ; RV32IA-LABEL: atomicrmw_xor_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 2 ; RV32IA-NEXT: addi a3, zero, 2
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_acquire: ; RV64I-LABEL: atomicrmw_xor_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 2 ; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_acquire: ; RV64IA-LABEL: atomicrmw_xor_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aq a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b acquire %1 = atomicrmw xor i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_release: ; RV32I-LABEL: atomicrmw_xor_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_release: ; RV32IA-LABEL: atomicrmw_xor_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 3 ; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_release: ; RV64I-LABEL: atomicrmw_xor_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 3 ; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_release: ; RV64IA-LABEL: atomicrmw_xor_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.rl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b release %1 = atomicrmw xor i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_acq_rel: ; RV32I-LABEL: atomicrmw_xor_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_xor_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 4 ; RV32IA-NEXT: addi a3, zero, 4
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_acq_rel: ; RV64I-LABEL: atomicrmw_xor_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 4 ; RV64I-NEXT: addi a2, zero, 4
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b acq_rel %1 = atomicrmw xor i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_xor_i64_seq_cst: ; RV32I-LABEL: atomicrmw_xor_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: call __atomic_fetch_xor_8 ; RV32I-NEXT: call __atomic_fetch_xor_8@plt
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst: ; RV32IA-LABEL: atomicrmw_xor_i64_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16 ; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp) ; RV32IA-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IA-NEXT: addi a3, zero, 5 ; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_fetch_xor_8 ; RV32IA-NEXT: call __atomic_fetch_xor_8@plt
; RV32IA-NEXT: lw ra, 12(sp) ; RV32IA-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 16 ; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xor_i64_seq_cst: ; RV64I-LABEL: atomicrmw_xor_i64_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, 5 ; RV64I-NEXT: addi a2, zero, 5
; RV64I-NEXT: call __atomic_fetch_xor_8 ; RV64I-NEXT: call __atomic_fetch_xor_8@plt
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xor i64* %a, i64 %b seq_cst %1 = atomicrmw xor i64* %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_monotonic: ; RV32I-LABEL: atomicrmw_max_i64_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB200_2 ; RV32I-NEXT: j .LBB200_2
; RV32I-NEXT: .LBB200_1: # %atomicrmw.start ; RV32I-NEXT: .LBB200_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB200_7 ; RV32I-NEXT: bnez a0, .LBB200_7
; RV32I-NEXT: .LBB200_2: # %atomicrmw.start ; RV32I-NEXT: .LBB200_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB200_4 ; RV32I-NEXT: beq a5, s1, .LBB200_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB200_1 ; RV32I-NEXT: j .LBB200_1
; RV32I-NEXT: .LBB200_7: # %atomicrmw.end ; RV32I-NEXT: .LBB200_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_monotonic: ; RV32IA-LABEL: atomicrmw_max_i64_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB200_2 ; RV32IA-NEXT: j .LBB200_2
; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB200_7 ; RV32IA-NEXT: bnez a0, .LBB200_7
; RV32IA-NEXT: .LBB200_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB200_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB200_4 ; RV32IA-NEXT: beq a5, s1, .LBB200_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB200_1 ; RV32IA-NEXT: j .LBB200_1
; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_monotonic: ; RV64I-LABEL: atomicrmw_max_i64_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB200_2 ; RV64I-NEXT: j .LBB200_2
; RV64I-NEXT: .LBB200_1: # %atomicrmw.start ; RV64I-NEXT: .LBB200_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB200_4 ; RV64I-NEXT: bnez a0, .LBB200_4
; RV64I-NEXT: .LBB200_2: # %atomicrmw.start ; RV64I-NEXT: .LBB200_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB200_1 ; RV64I-NEXT: blt s1, a3, .LBB200_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB200_1 ; RV64I-NEXT: j .LBB200_1
; RV64I-NEXT: .LBB200_4: # %atomicrmw.end ; RV64I-NEXT: .LBB200_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_monotonic: ; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d a0, a1, (a0) ; RV64IA-NEXT: amomax.d a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b monotonic %1 = atomicrmw max i64* %a, i64 %b monotonic
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acquire: ; RV32I-LABEL: atomicrmw_max_i64_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB201_2 ; RV32I-NEXT: j .LBB201_2
; RV32I-NEXT: .LBB201_1: # %atomicrmw.start ; RV32I-NEXT: .LBB201_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB201_7 ; RV32I-NEXT: bnez a0, .LBB201_7
; RV32I-NEXT: .LBB201_2: # %atomicrmw.start ; RV32I-NEXT: .LBB201_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB201_4 ; RV32I-NEXT: beq a5, s1, .LBB201_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB201_1 ; RV32I-NEXT: j .LBB201_1
; RV32I-NEXT: .LBB201_7: # %atomicrmw.end ; RV32I-NEXT: .LBB201_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acquire: ; RV32IA-LABEL: atomicrmw_max_i64_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB201_2 ; RV32IA-NEXT: j .LBB201_2
; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB201_7 ; RV32IA-NEXT: bnez a0, .LBB201_7
; RV32IA-NEXT: .LBB201_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB201_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB201_4 ; RV32IA-NEXT: beq a5, s1, .LBB201_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB201_1 ; RV32IA-NEXT: j .LBB201_1
; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acquire: ; RV64I-LABEL: atomicrmw_max_i64_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB201_2 ; RV64I-NEXT: j .LBB201_2
; RV64I-NEXT: .LBB201_1: # %atomicrmw.start ; RV64I-NEXT: .LBB201_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB201_4 ; RV64I-NEXT: bnez a0, .LBB201_4
; RV64I-NEXT: .LBB201_2: # %atomicrmw.start ; RV64I-NEXT: .LBB201_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB201_1 ; RV64I-NEXT: blt s1, a3, .LBB201_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB201_1 ; RV64I-NEXT: j .LBB201_1
; RV64I-NEXT: .LBB201_4: # %atomicrmw.end ; RV64I-NEXT: .LBB201_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acquire: ; RV64IA-LABEL: atomicrmw_max_i64_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aq a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aq a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acquire %1 = atomicrmw max i64* %a, i64 %b acquire
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_release: ; RV32I-LABEL: atomicrmw_max_i64_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB202_2 ; RV32I-NEXT: j .LBB202_2
; RV32I-NEXT: .LBB202_1: # %atomicrmw.start ; RV32I-NEXT: .LBB202_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB202_7 ; RV32I-NEXT: bnez a0, .LBB202_7
; RV32I-NEXT: .LBB202_2: # %atomicrmw.start ; RV32I-NEXT: .LBB202_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB202_4 ; RV32I-NEXT: beq a5, s1, .LBB202_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB202_1 ; RV32I-NEXT: j .LBB202_1
; RV32I-NEXT: .LBB202_7: # %atomicrmw.end ; RV32I-NEXT: .LBB202_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_release: ; RV32IA-LABEL: atomicrmw_max_i64_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB202_2 ; RV32IA-NEXT: j .LBB202_2
; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB202_7 ; RV32IA-NEXT: bnez a0, .LBB202_7
; RV32IA-NEXT: .LBB202_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB202_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB202_4 ; RV32IA-NEXT: beq a5, s1, .LBB202_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB202_1 ; RV32IA-NEXT: j .LBB202_1
; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_release: ; RV64I-LABEL: atomicrmw_max_i64_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB202_2 ; RV64I-NEXT: j .LBB202_2
; RV64I-NEXT: .LBB202_1: # %atomicrmw.start ; RV64I-NEXT: .LBB202_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB202_4 ; RV64I-NEXT: bnez a0, .LBB202_4
; RV64I-NEXT: .LBB202_2: # %atomicrmw.start ; RV64I-NEXT: .LBB202_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB202_1 ; RV64I-NEXT: blt s1, a3, .LBB202_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB202_1 ; RV64I-NEXT: j .LBB202_1
; RV64I-NEXT: .LBB202_4: # %atomicrmw.end ; RV64I-NEXT: .LBB202_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_release: ; RV64IA-LABEL: atomicrmw_max_i64_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.rl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.rl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b release %1 = atomicrmw max i64* %a, i64 %b release
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_acq_rel: ; RV32I-LABEL: atomicrmw_max_i64_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB203_2 ; RV32I-NEXT: j .LBB203_2
; RV32I-NEXT: .LBB203_1: # %atomicrmw.start ; RV32I-NEXT: .LBB203_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2 ; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_8 ; RV32I-NEXT: call __atomic_compare_exchange_8@plt
; RV32I-NEXT: lw a5, 12(sp) ; RV32I-NEXT: lw a5, 12(sp)
; RV32I-NEXT: lw a4, 8(sp) ; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB203_7 ; RV32I-NEXT: bnez a0, .LBB203_7
; RV32I-NEXT: .LBB203_2: # %atomicrmw.start ; RV32I-NEXT: .LBB203_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: beq a5, s1, .LBB203_4 ; RV32I-NEXT: beq a5, s1, .LBB203_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
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; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: j .LBB203_1 ; RV32I-NEXT: j .LBB203_1
; RV32I-NEXT: .LBB203_7: # %atomicrmw.end ; RV32I-NEXT: .LBB203_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -32 ; RV32IA-NEXT: addi sp, sp, -32
; RV32IA-NEXT: sw ra, 28(sp) ; RV32IA-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s0, 24(sp) ; RV32IA-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IA-NEXT: mv s0, a0 ; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0) ; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0) ; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2 ; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1 ; RV32IA-NEXT: mv s2, a1
; RV32IA-NEXT: j .LBB203_2 ; RV32IA-NEXT: j .LBB203_2
; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: sw a4, 8(sp) ; RV32IA-NEXT: sw a4, 8(sp)
; RV32IA-NEXT: sw a5, 12(sp) ; RV32IA-NEXT: sw a5, 12(sp)
; RV32IA-NEXT: addi a1, sp, 8 ; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0 ; RV32IA-NEXT: mv a0, s0
; RV32IA-NEXT: call __atomic_compare_exchange_8 ; RV32IA-NEXT: call __atomic_compare_exchange_8@plt
; RV32IA-NEXT: lw a5, 12(sp) ; RV32IA-NEXT: lw a5, 12(sp)
; RV32IA-NEXT: lw a4, 8(sp) ; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB203_7 ; RV32IA-NEXT: bnez a0, .LBB203_7
; RV32IA-NEXT: .LBB203_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB203_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: beq a5, s1, .LBB203_4 ; RV32IA-NEXT: beq a5, s1, .LBB203_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start ; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
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; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: mv a2, s2 ; RV32IA-NEXT: mv a2, s2
; RV32IA-NEXT: mv a3, s1 ; RV32IA-NEXT: mv a3, s1
; RV32IA-NEXT: j .LBB203_1 ; RV32IA-NEXT: j .LBB203_1
; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end ; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4 ; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5 ; RV32IA-NEXT: mv a1, a5
; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) ; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s0, 24(sp) ; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw ra, 28(sp) ; RV32IA-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IA-NEXT: addi sp, sp, 32 ; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i64_acq_rel: ; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: j .LBB203_2 ; RV64I-NEXT: j .LBB203_2
; RV64I-NEXT: .LBB203_1: # %atomicrmw.start ; RV64I-NEXT: .LBB203_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV64I-NEXT: sd a3, 0(sp) ; RV64I-NEXT: sd a3, 0(sp)
; RV64I-NEXT: mv a1, sp ; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_8 ; RV64I-NEXT: call __atomic_compare_exchange_8@plt
; RV64I-NEXT: ld a3, 0(sp) ; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB203_4 ; RV64I-NEXT: bnez a0, .LBB203_4
; RV64I-NEXT: .LBB203_2: # %atomicrmw.start ; RV64I-NEXT: .LBB203_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB203_1 ; RV64I-NEXT: blt s1, a3, .LBB203_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB203_1 ; RV64I-NEXT: j .LBB203_1
; RV64I-NEXT: .LBB203_4: # %atomicrmw.end ; RV64I-NEXT: .LBB203_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i64_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0) ; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i64* %a, i64 %b acq_rel %1 = atomicrmw max i64* %a, i64 %b acq_rel
ret i64 %1 ret i64 %1
} }
define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i64_seq_cst: ; RV32I-LABEL: atomicrmw_max_i64_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0) ; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0) ; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: j .LBB204_2 ; RV32I-NEXT: j .LBB204_2
; RV32I-NEXT: .LBB204_1: # %atomicrmw.start ; RV32I-NEXT: .LBB204_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 12(sp) ; RV32I-NEXT: sw a5, 12(sp)
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5 ; RV32I-NEXT: addi a5, zero, 5