[DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR

[joechrisellis]

Summary

This avoids TypeSize-related warnings.

[joechrisellis]

Uploaded this patch without tests for now. I had a go at writing some tests that invoke the modified codepath here, but I couldn't come up with anything small that would produce a TypeSize-related warnings.

[joechrisellis]

Add test.

[david-arm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

21109

You can use getVectorMinNumElements() here if you want?

llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll

28

The insert intrinsic expects a <vscale x 8 x double> here I think, right? i.e. nxv2f64.nxv8f64

[joechrisellis]

Address @david-arm's comments.

• Fix use of incorrect intrinsic.
• Use getVectorMinElements() instead of getVectorElementCount().getKnownMinValue().

[sdesmalen]

llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll

10

It's more robust not to test for specific warnings, but just check no warnings are emitted at all. When the time comes that the warning becomes an error, all tests are still guaranteed to pass.

[joechrisellis]

Address @sdesmalen's comment.

• Do not test for specific warnings, but for all warnings.

[sdesmalen]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
 
   // If we are inserting a bitcast value into an undef, with the same
   // number of elements, just use the bitcast input of the extract.
   // i.e. INSERT_SUBVECTOR UNDEF (BITCAST N1) N2 ->
   //        BITCAST (INSERT_SUBVECTOR UNDEF N1 N2)
   if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
       N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR &&
       N1.getOperand(0).getOperand(1) == N2 &&
-      N1.getOperand(0).getOperand(0).getValueType().getVectorNumElements() ==
-          VT.getVectorNumElements() &&
+      N1.getOperand(0).getOperand(0).getValueType().getVectorElementCount() ==
+          VT.getVectorElementCount() &&
       N1.getOperand(0).getOperand(0).getValueType().getSizeInBits() ==
           VT.getSizeInBits()) {
     return DAG.getBitcast(VT, N1.getOperand(0).getOperand(0));
   }
 
   // If both N1 and N2 are bitcast values on which insert_subvector
   // would makes sense, pull the bitcast through.
   // i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 ->
   //        BITCAST (INSERT_SUBVECTOR N0 N1 N2)
   if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
     SDValue CN0 = N0.getOperand(0);
     SDValue CN1 = N1.getOperand(0);
     EVT CN0VT = CN0.getValueType();
     EVT CN1VT = CN1.getValueType();
     if (CN0VT.isVector() && CN1VT.isVector() &&
         CN0VT.getVectorElementType() == CN1VT.getVectorElementType() &&
-        CN0VT.getVectorNumElements() == VT.getVectorNumElements()) {
+        CN0VT.getVectorElementCount() == VT.getVectorElementCount()) {
       SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N),
                                       CN0.getValueType(), CN0, CN1, N2);
       return DAG.getBitcast(VT, NewINSERT);
     }
   }
 
   // Combine INSERT_SUBVECTORs where we are inserting to the same index.
   // INSERT_SUBVECTOR( INSERT_SUBVECTOR( Vec, SubOld, Idx ), SubNew, Idx )
if (InsIdx < OtherIdx) {
       return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()),
                          VT, NewOp, N0.getOperand(1), N0.getOperand(2));
     }
   }
 
   // If the input vector is a concatenation, and the insert replaces
   // one of the pieces, we can optimize into a single concat_vectors.
   if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
-      N0.getOperand(0).getValueType() == N1.getValueType()) {
-    unsigned Factor = N1.getValueType().getVectorNumElements();
+      N0.getOperand(0).getValueType() == N1.getValueType() &&
+      N0.getOperand(0).getValueType().isScalableVector() ==
+          N1.getValueType().isScalableVector()) {
+    unsigned Factor =
+        N1.getValueType().getVectorElementCount().getKnownMinValue();
     SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
     Ops[InsIdx / Factor] = N1;
     return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
   }
 
   // Simplify source operands based on insertion.
   if (SimplifyDemandedVectorElts(SDValue(N, 0)))
     return SDValue(N, 0);

llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll

+; RUN: llc < %s -o /dev/null 2>&1 | FileCheck --allow-empty %s
+
+; This regression test is defending against a ElementCount warning 'Possible incorrect use of
+; EVT::getVectorNumElements() for scalable vector'. This warning appeared in
+; DAGCombiner::visitINSERT_SUBVECTOR because of the use of getVectorNumElements() on scalable
+; types.
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; CHECK-NOT: warning: {{.*}}Possible incorrect use of EVT::getVectorNumElements() for scalable vector
+
+target triple = "aarch64-unknown-linux-gnu"
+attributes #0 = {"target-features"="+sve"}
+
+declare <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64)
+declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64)
+
+declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv8f64(<vscale x 2 x double>, <8 x double>, i64)
+
+define <vscale x 2 x double> @reproducer_one(<vscale x 4 x float> %vec_a) #0 {
+  %a = call <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %vec_a, i64 0)
+  %b = bitcast <16 x float> %a to <8 x double>
+  %retval = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> undef, <8 x double> %b, i64 0)
+  ret <vscale x 2 x double> %retval
+}
+
+define <vscale x 2 x double> @reproducer_two(<4 x double> %a, <4 x double> %b) #0 {
+  %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  %retval = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv8f64(<vscale x 2 x double> undef, <8 x double> %concat, i64 0)
+  ret <vscale x 2 x double> %retval
+}