[Debugify] Support checking Machine IR debug info

[xiangzhangllvm]

Summary

Add mir-check-debug pass to check MIR-level debug info.

For IR-level, currently, LLVM have debugify + check-debugify to generate and check debug IR.
Much like the IR-level pass debugify, mir-debugify inserts sequentially increasing line locations to each MachineInstr in a Module,
But there is no equivalent MIR-level check-debugify pass, So now we support it at "mir-check-debug".

Currently (our first step), what mir-check-debug do is similar with check-debugify, to check the integrity of line info in DILocation and DILocalVariable
which mir-debugify generated before.

The 3 tests in patch show how this tools work.

[djtodoro]

Thanks for doing this! (some initial comments inline)

Please add some context about this into https://llvm.org/docs/HowToUpdateDebugInfo.html#id14.

llvm/lib/CodeGen/MachineCheckDebug.cpp

97 ↗

(On Diff #305666)

clang-format please

llvm/lib/CodeGen/MachineDebugify.cpp

145

clang-format please

149

the comments should go above

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir

47

we can get rid of these tbaa metadata

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir

32

I think we do not need all of these attributes, only name and alignment

[xiangzhangllvm]

All done, @djtodoro thanks very much for you review !

[pengfei]

llvm/docs/HowToUpdateDebugInfo.rst

346

Remove the right parentheses.

[xiangzhangllvm]

llvm/docs/HowToUpdateDebugInfo.rst

346

Oh! Yes, Thanks a lot !

[djtodoro]

llvm/include/llvm/CodeGen/TargetPassConfig.h

316

please add synthesized debug info, since this checks the debugging info from debugify only (for now)

llvm/lib/CodeGen/CMakeLists.txt

77

I would pick MachineCheckDebugify, wdyt?

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

I think we should do this for finding missing variables; but for the checking of missing lines we should check more machine instructions (especially the instrs other than debug ones), right? Any reason we shouldn't do that?

Please check the checkDebugifyMetadata() (from Debugify.cpp) how it was done.

[xiangzhangllvm]

llvm/lib/CodeGen/CMakeLists.txt

77

Yes, I noticed that, I also found mir-strip-debug implemented in MachineStripDebug.cpp, so I sync it with mir-strip-debug.

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

Because the MirDebugify will generate DBG_VALUE for every MIRs, all these MIRs' debug location will be saved in these generated DBG_VALUEs. So here we just need to check the line info in these DBG_VALUEs. It is also ok the check the non_debug MIR again, but it is duplicated.

[LuoYuanke]

llvm/lib/CodeGen/MachineCheckDebug.cpp

28 ↗

(On Diff #305941)

Why is it struct, not class?

llvm/lib/CodeGen/MachineDebugify.cpp

58

Why terminator instruction don't need debug info?

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir

59

Do we need blank character between ';' and 'DBG_VALUE'?

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebug.cpp

28 ↗

(On Diff #305941)

Struct is similar with "Class", (default to public for its members)
I sync this code from mir-strip-debug pass.

llvm/lib/CodeGen/MachineDebugify.cpp

58

because later LiveDebugVariables will drops out-of-liveness DBG_VALUEs, as the register allocator will not maintain the location of its vreg for positions that aren't live.
Pls refer https://github.com/llvm/llvm-project/blob/68ac02c0dd2b8fda52ac132a86f72f2ad6b139a5/llvm/lib/CodeGen/LiveDebugVariables.cpp#L657

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

Hi, @djtodoro
Say it is "duplicated" may not accurate, here we only check the debug location in DBG_VALUE MIRs is more strict than check both of them. Because the optimizations may change/update the value of DBG_VALUE (its 1st operand), but they shouldn't change/remove the location info of it. And directly remove a DBG_VALUE should always report warning.

[xiangzhangllvm]

llvm/lib/CodeGen/CMakeLists.txt

77

If you still prefer MachineCheckDebugify, I am ok to update it, include the option name.

[djtodoro]

llvm/lib/CodeGen/CMakeLists.txt

77

But there is still MachineDebugify.cpp, so I think MachineCheckDebugify.cpp is more appropriate name.

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

On the IR level, debugify utility pass can tell us: there is an instruction I with empty DebugLoc after a pass. How it works: before a pass, it attaches synthetic dbg loc onto each IR instruction, and after the pass it checks if it preserved the dbg loc.

Can we do the same for MIR Debugify? For example: the mir-debugify attaches a dbgLoc on an MI (non debug one), and then the mir-check-debigify checks if a pass preserved that dbg location? Is it even possible at MIR level?

[jmorse]

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

I agree with Djordje, the line numbers attached to DBG_VALUE instructions are of little interest and never reach an output file, it's the non-meta instructions that are the subject of optimisations, and thus should be the target of line number checkers.

llvm/lib/CodeGen/MachineDebugify.cpp

58

Terminators probably shouldn't have variable location information attached to them. However this block is adding line numbers / source locations to instructions, and terminator line numbers can be useful (for example tail calls, or representing the end of a lexical block).

114–115

If I'm reading this correctly, won't NumLines always finish with the value NextLine-1, the counter used when setting line numbers above??

118

Couldn't this just be extracted from the Line2Var collection built earlier?

138

139

[MaskRay]

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.ll

2

Does this file add new coverage?

This file explain its purpose in the file header. The body of foo is mostly unused, you can add just a ret. If you don't otherwise check the output, use -filetype=null

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

Hello @jmorse @djtodoro, first thanks for your comments, I was thinking about it before, and it is nice discuss with you now:
What we really want (MIR/IR)check-debug doing for us ?
Take (IR)check-debug for e.g.
In my eyes, we use check-debug to check if the optimizations incorrectly optimized the debug info of IRs. Right?
Some optimizations may correctly optimized the IRs by removing them with carefully handling its debug info. (e.g. --instsimplify), for these cases, I think, check-debug should not report WARNING messages out.

Take llvm lit test llvm/test/DebugInfo/debugify.ll for e.g.
There is unused %sum=... in it, let's remove it in instruction simplify.
After debugify, it will be:

define i32 @bar() !dbg !12 {
  call void @foo(), !dbg !15
  %sum = add i32 0, 1, !dbg !16
  call void @llvm.dbg.value(metadata i32 %sum, metadata !14, metadata !DIExpression()), !dbg !16
  ret i32 0, !dbg !17
}

If I run

opt -debugify --instsimplify -check-debugify -S -o - DebugInfo/debugify.ll

it will report WARNING in -check-debugify:

WARNING: Missing line 3
CheckModuleDebugify: PASS
......
define i32 @bar() !dbg !12 {
  call void @foo(), !dbg !15
  call void @llvm.dbg.value(metadata i32 0, metadata !14, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !16
  ret i32 0, !dbg !17
}

because the check-debug will check the line info of removed instruction.
What is more, removing instruction is very common in optimization passes, and debugify will add different line info for every instructions, so once remove any non-debug instructions, it will give out WARNINGs. Even they correctly remove them (by updating its llvm.dbg.value (0/undef, ....).

If the test is big, we may need to check a lot of warnings one by one.

And that was why my current patch didn't check the line info for non-debug MIRs.

llvm/lib/CodeGen/MachineDebugify.cpp

114–115

Here is really risk:
I write it here because NextLine-1 may less than line in DILocation generated at (IR)debugify before.
Line 120 update the line from IR (not MIR).
I'll refine here, tks!

118

Yes, but seems same, and doesn't it is better here? -- the life range of Varset is short.

[xiangzhangllvm]

llvm/lib/CodeGen/MachineDebugify.cpp

138

I'll fix them, thank you!

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.ll

2

Terminator IR ret is too simple to check the debug info.
Currently I check two MIR pass will pass this debug info check.
And I think it is better for this *.ll file to keep "same" with its MIR file check-line-and-variables.mir.
tks!

[djtodoro]

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

Yes, but that is why it is being reported as warning...
Use case: For example, we use debugify and realize that a bunch of add instructions don't have a dbg location attached after a pass X - we investigate pass X, and find out that there is a creating of the instruction add, but we have missed to add I->setDebugLoc(). It makes sense when dealing with non-dbg instructions only, since the locations of these are used during debugging sessions, since only these instructions end up in the final code.

Please consider the code from trunk (IR Debugify.cpp):

// Find missing lines.
for (Instruction &I : instructions(F)) {
  if (isa<DbgValueInst>(&I) || isa<PHINode>(&I))
    continue;

  auto DL = I.getDebugLoc();
  if (DL && DL.getLine() != 0) {
    MissingLines.reset(DL.getLine() - 1);
    continue;
  }

  if (!DL) {
    dbg() << "WARNING: Instruction with empty DebugLoc in function ";
    dbg() << F.getName() << " --";
    I.print(dbg());
    dbg() << "\n";
  }
}

This gives us a chance to investigate if a pass drops the location accidentally or it should have done it, but only for non-debug ones, as:

if (isa<DbgValueInst>(&I) || isa<PHINode>(&I))
  continue;

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebug.cpp

58 ↗

(On Diff #305941)

Thanks for the explanation, I'll check the non-debug MIR.

[djtodoro]

Thanks!

llvm/lib/CodeGen/MachineCheckDebugify.cpp

57

I'm not against adding two loops -- one for finding missing lines, and the other one for finding missing variables.

59

Not sure we want to report missing dbgLoc for meta instructions other than DBG_VALUE (e.g., DBG_LABEL does not end up in the final code as well..)

68

Early continue?

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

57

Yes, two loops is clear

59

For missing line, we should check all the MIRs which contribute the line number in MachineDebugify -- (non DBG_VALUEs), so here we just need to check MI.isDebugValue().

68

Still need to do line 73, I'll let it clear by using 2 loops soon. thank you!

72

Duplicated "\n" with MI.print(), remove here.

[djtodoro]

Nice! (few nits inline)

llvm/lib/CodeGen/MachineCheckDebugify.cpp

10

checks

11

checks

59

I see, but that should be fixed at MachineDebugify side first. At least, we can put a TODO (or FIXME) marker, saying "Avoid meta instructions other than dbg_val"

66

Nit: please add \n here.

72

Nit: please add \n here.

[xiangzhangllvm]

Thanks very much for your reviews!!

[djtodoro]

Thanks for addressing the comments! We are almost there.

llvm/docs/HowToUpdateDebugInfo.rst

412

The name of option -debugify-and-check-strip-all-safe seems a bit confusing ...

llvm/lib/CodeGen/MachineCheckDebugify.cpp

53–56

We don't need MaybeMF,

MachineFunction *MF = MMI.getMachineFunction(F);
if (!MF)
  continue;

and use *MF.

llvm/lib/CodeGen/TargetPassConfig.cpp

126

The description should be more precise.

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

53–56

Yes, I'll refine here, thank you again : )

llvm/lib/CodeGen/TargetPassConfig.cpp

126

The name and description of "debugify-and-check-strip-all-safe" refer to upper "debugify-and-strip-all-safe", Maybe It is a little different for our non-English speaking people to name or descript well. Do you have good suggestion of its name ?
How about I refine the description to "Debugify MIR before each pass except those known to be unsafe when debug info is present, then run mir-check-debugify for them, and finally strip the debug info with mir-strip-debug" ?

[djtodoro]

llvm/lib/CodeGen/TargetPassConfig.cpp

126

The name and description of "debugify-and-check-strip-all-safe" refer to upper "debugify-and-strip-all-safe"

I think "debugify-check-and-strip-all-safe" would be more appropriate, wdyt?

(DebugifyAndCheckStripAll should be DebugifyCheckAndStripAll)

How about I refine the description to "Debugify MIR before each pass except those known to be unsafe when debug info is present, then run mir-check-debugify for them, and finally strip the debug info with mir-strip-debug" ?

Hmm... we are checking/stripping after each pass right?

"Debugify MIR before, by checking and stripping the debug info after, each pass except those known to be unsafe when debug info is present" ?

[xiangzhangllvm]

llvm/lib/CodeGen/TargetPassConfig.cpp

126

think "debugify-check-and-strip-all-safe" would be more appropriate, wdyt?

Looks good!

Hmm... we are checking/stripping after each pass right?

Yes, same with "debugify-and-strip-all-safe".

"Debugify MIR before, by checking and stripping the debug info after, each pass except those known to be unsafe when debug info is present"

That's better, thank you!!

[djtodoro]

LGTM, thanks!

(please leave some time (a few days) to other reviewers to take a look)

llvm/lib/CodeGen/MachineCheckDebugify.cpp

77

Please add a TODO marker for DBG_INSTR_REF as well (it is still under an experimental option, but we should be aware it is coming).

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

77

OK, I'll mark it when I commit it (next week).
For DBG_INSTR_REF it is a good idea to split the value and location for llvm.dbg.value.
Thanks for all your works !!

[vsk]

llvm/docs/HowToUpdateDebugInfo.rst

346

nit, s/with/to the/

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

Why does this need to be named differently from the IR-level named debugify metadata?

41

I don't think it's a good idea to introduce a copy of the IR-level check-debugify logic, since this makes it possible for the IR & MIR-level checking behaviors to diverge.

Can you find a way to factor out and reuse the checking logic? One way to do it might be to introduce a generic DebugifyChecker which parses the named metadata and operates on DebugLoc.

[xiangzhangllvm]

llvm/docs/HowToUpdateDebugInfo.rst

346

Hi @vsk Do you mean refine "is similar with IR-level" to "is similar to IR-level" ?

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

The MIR Check base on the MIR debugify, the "llvm.mir.debugify" will save the line number and variable number in MIR debugify.
Please refer llvm/lib/CodeGen/MachineDebugify.cpp line 160,162

41

It is not get/check IR-level metadata info, as explained before, here use the getDebugifyOperand to get "llvm.mir.debugify" info which generated by MIR debugify.

[vsk]

llvm/docs/HowToUpdateDebugInfo.rst

346

Yep!

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

Yes, I understand that. What's not clear to me is why the named metadata needs to be different from the IR-level named metadata ('llvm.debugify').

41

Hm, I don't think we're on the same page. My concern is that this patch copies logic from checkDebugifyMetadata (in lib/Transforms/Utils/Debugify.cpp), such as the logic to set up bitvectors to track missing lines. Could you please find a way to implement the warnings in a generic way, and reuse that facility in both the IR & MIR check-debugify passes?

[xiangzhangllvm]

llvm/docs/HowToUpdateDebugInfo.rst

346

I'll fix it soon, thank you!

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

There is 2 reasons:

1. 'llvm.debugify' collected IR debug info (line + var number), if we "overwrite" the MIR debug info into it, it is confused to read it.
2. In fact, Machine debugify is called from (IR level) debugify. If we write the MIR debug info into 'llvm.debugify' metadata, it will be "overwrite" by IR debug info at last.

41

en..., In fact, we intentionally make the logic same with IR debugify, it is reasonable to check MIR similar with IR. (It has already help me to find some debug info problems in some MIR optimizations). It is trouble to reuse that facility in both the IR & MIR. The logic of MIR-debugify is some with IR-debugify too, but MIR-debugify also implemented in a independent pass.

[xiangzhangllvm]

Mark TODO for DBG_INSTR_REF and refine docs/HowToUpdateDebugInfo.rst

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

41

en..., In fact, we intentionally make the logic same with IR debugify, it is reasonable to check MIR similar with IR. (It has already help me to find some debug info problems in some MIR optimizations). It is trouble to reuse that facility in both the IR & MIR. The logic of MIR-debugify is some with IR-debugify too, but MIR-debugify also implemented in a independent pass.

[vsk]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

Ah, got it. The reason the named metadata nodes are kept separate is so the IR in a .mir file can be checked, and so there's no confusion about whether the metadata describes IR/MIR.

One small clarification -- it looks like it is the other way around: MachineDebugify calls the IR-level debugify (in DebugifyMachineModule::runOnModule).

41

I think we're still talking a bit past each other. Could you elaborate on this point:

It is trouble to reuse that facility in both the IR & MIR. The logic of MIR-debugify is some with IR-debugify too

The way I see it, the IR-level and MIR-level checking is very similar. I'm simply asking for the similar pieces to be factored out into a generic implementation.

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

34

One small clarification -- it looks like it is the other way around: MachineDebugify calls the IR-level debugify (in DebugifyMachineModule::runOnModule).

Yes, That's more accurate.

41

I thought your point is: reuse the same code (Debugify.cpp: checkDebugifyMetadata) to check both IR and MIR. right?
The troubles are

1. We must complex current clear checkDebugifyMetadata to fit the MIR check,(the line/variable numbers are different, the IR/MIR iterator is different, all need to fit) and call relations. What's more, Current key code in mir-check-debugify just tens of lines, very small.

2)Current mir-check-debugify is a simple and dependent pass, easy to extend later, if reuse the Debugify.cpp code, it at last need to call IR-level debugify as mir-debugify. (We mostly use -run-pass=mir-check-debugify to run it.)

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

41

The logic of MIR-debugify is same with IR-debugify too

Both of them mainly add debug IR/MIR for very instructions, and MIR-debugify really called IR-debugify's code, but it just want to use IR-debugify to create metadata.

[vsk]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

41

I thought your point is: reuse the same code (Debugify.cpp: checkDebugifyMetadata) to check both IR and MIR. right?

Ah, no, not the exact same code, no. There are certain similarities between the checking logic in checkDebugifyMetadata, and the checking logic introduced in this patch. Instead of having two copies of the same checking logic that can diverge over time, I'm suggesting that you factor out the similar pieces into a single generic implementation. The parts of the logic that are IR or MIR specific, of course, can/should remain separate.

[xiangzhangllvm]

llvm/lib/CodeGen/MachineCheckDebugify.cpp

41

Yes, merging same logic is the general rule of coding.
But if it makes things complex or down the readability, I prefer not merging.
Currently, both IR/MIR check is very simple and clear, merging won't take profit. If we do merging, we at least need to do:

1. Adding function call, let both passes can call it.
2. Adding pass Line/variable numbers and others to the function.
3. Distinguish IR/MIR (Function/MachineFunction, BB/MBB, I/MI) in the function.
4. Distinguish "isa<DbgValueInst>(&I)" with "MI.isDebugValue()" and so on.

[thakis]

Apologies, I reverted this because else reverting D78135 (which breaks check-llvm) creates merge conflicts that I can't quickly figure out.

[thakis]

In D91595#2453735, @thakis wrote:

Apologies, I reverted this because else reverting D78135 (which breaks check-llvm) creates merge conflicts that I can't quickly figure out.

D78135 was innocent, but this change here apparently caused these debugify test failures:
http://lab.llvm.org:8011/#/builders/109/builds/4730
http://45.33.8.238/linux/35299/step_12.txt

These tests stopped failing after the revert of this change here landed. So please check these tests before relanding.

[xiangzhangllvm]

Apologies, I reverted this because else reverting D78135 https://reviews.llvm.org/D78135 which breaks check-llvm) creates merge conflicts that I can't quickly figure out.

Yes, it cause fail in the tests of D78135, I'll update it. thank you.

[djtodoro]

Hi @xiangzhangllvm, please wait for @vsk to approve as well, since he is author of the original debugify IR patch and he is very involved in the area.
Thanks a lot for your patience and work.

[xiangzhangllvm]

OK, thanks for reminding.

[xiangzhangllvm]

Update affected tests: AArch64/GlobalISel/constant-mir-debugify.mir and phi-mir-debugify.mir
Because this patch add metadata "llvm.mir.debugify", it affected the index of some old test.
For e.g. change Checking "debug-location !10" to Checking "debug-location !11"

[xiangzhangllvm]

Hello @vsk ,could you help accept it ?

[vsk]

Hi @xiangzhangllvm, apologies for the delay.

But if it makes things complex or down the readability, I prefer not merging.
Currently, both IR/MIR check is very simple and clear, merging won't take profit.

Imo this overstates the difficulty of code sharing in this context, and underweights the potential long-term effects of having divergent code paths that are supposed to do the same thing. I urge you to reconsider :).

I'm not sure I'll have time to continue with this review, so I'll let other voices take over.

[xiangzhangllvm]

Imo this overstates the difficulty of code sharing in this context, and underweights the potential long-term effects of having divergent code paths that are supposed to do the same thing. I urge you to reconsider :).

Hi @vsk, I am fine to merge if you still feel the following explanation doesn't hold water：

1. The logic here not 100% same, currently, mir-check doesn't check the phi node. (which will eliminate at back end)
2. I still feel it is trouble to "Distinguish isa<DbgValueInst>(&I) with MI.isDebugValue() and so on"
3. In my eyes, the small logic of ir/mir check here is just happen to be same/similar, not must (or no need) to be, make them not affect each other is better.

I'm not sure I'll have time to continue with this review, so I'll let other voices take over.

Thank you for your continuous reviews, I wish we can reach an agreement on the "merge" : )

[xiangzhangllvm]

As this review has last so long, (1 month), It has accepted before and I fixed all reviewers' comments except @vsk 's "merging" suggestion.
I want to let this patch in first.
About @vsk 's "merging" suggestion, I am almost sure that the code will be some ugly compared with current code,
So I'll use another special patch to handle his "merging" suggestion, let/wait @vsk to accept it or not.
tks!

llvm/docs/HowToUpdateDebugInfo.rst

 
 Mutation testing for MIR-level transformations
 ----------------------------------------------
 
 A variant of the ``debugify`` utility described in
 :ref:`Mutation testing for IR-level transformations<IRDebugify>` can be used
 for MIR-level transformations as well: much like the IR-level pass,
 ``mir-debugify`` inserts sequentially increasing line locations to each
-``MachineInstr`` in a ``Module`` (although there is no equivalent MIR-level
-``check-debugify`` pass).
+``MachineInstr`` in a ``Module``. And the MIR-level ``mir-check-debugify`` is
+similar to IR-level ``check-debugify`` pass.
 
 For example, here is a snippet before:
 
 .. code-block:: llvm
 
   name:            test
   body:             |
     bb.1 (%ir-block.0):

 ``-debugify-and-strip-all-safe``. This can be combined with ``-start-before``
 and ``-start-after``. For example:
 
 .. code-block:: bash
 
   $ llc -debugify-and-strip-all-safe -run-pass=... <other llc args>
   $ llc -debugify-and-strip-all-safe -O1 <other llc args>
 
+If you want to check it after each pass in a pipeline, use
+``-debugify-check-and-strip-all-safe``. This can also be combined with
+``-start-before`` and ``-start-after``. For example:
+
+.. code-block:: bash
+
+  $ llc -debugify-check-and-strip-all-safe -run-pass=... <other llc args>
+  $ llc -debugify-check-and-strip-all-safe -O1 <other llc args>
+
+To check all debug info from a test, use ``mir-check-debugify``, like:
+
+.. code-block:: bash
+
+  $ llc -run-pass=mir-debugify,other-pass,mir-check-debugify
+
 To strip out all debug info from a test, use ``mir-strip-debug``, like:
 
 .. code-block:: bash
 
   $ llc -run-pass=mir-debugify,other-pass,mir-strip-debug
 
-It can be useful to combine ``mir-debugify`` and ``mir-strip-debug`` to
-identify backend transformations which break in the presence of debug info.
-For example, to run the AArch64 backend tests with all normal passes
-"sandwiched" in between MIRDebugify and MIRStripDebugify mutation passes, run:
+It can be useful to combine ``mir-debugify``, ``mir-check-debugify`` and/or
+``mir-strip-debug`` to identify backend transformations which break in
+the presence of debug info. For example, to run the AArch64 backend tests
+with all normal passes "sandwiched" in between MIRDebugify and
+MIRStripDebugify mutation passes, run:
 
 .. code-block:: bash
 
   $ llvm-lit test/CodeGen/AArch64 -Dllc="llc -debugify-and-strip-all-safe"
 
 Using LostDebugLocObserver
 --------------------------
 
 TODO

llvm/include/llvm/CodeGen/Passes.h

/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
   ModulePass *createDebugifyMachineModulePass();
 
   /// Creates MIR Strip Debug pass. \see MachineStripDebug.cpp
   /// If OnlyDebugified is true then it will only strip debug info if it was
   /// added by a Debugify pass. The module will be left unchanged if the debug
   /// info was generated by another source such as clang.
   ModulePass *createStripDebugMachineModulePass(bool OnlyDebugified);
 
+  /// Creates MIR Check Debug pass. \see MachineCheckDebugify.cpp
+  ModulePass *createCheckDebugMachineModulePass();
+
   /// The pass fixups statepoint machine instruction to replace usage of
   /// caller saved registers with stack slots.
   extern char &FixupStatepointCallerSavedID;
 
   /// The pass transform load/store <256 x i32> to AMX load/store intrinsics
   /// or split the data to two <128 x i32>.
   FunctionPass *createX86LowerAMXTypePass();
 } // End llvm namespace
 
 #endif

llvm/include/llvm/CodeGen/TargetPassConfig.h

public:
   void addVerifyPass(const std::string &Banner);
 
   /// Add a pass to add synthesized debug info to the MIR.
   void addDebugifyPass();
 
   /// Add a pass to remove debug info from the MIR.
   void addStripDebugPass();
 
+  /// Add a pass to check synthesized debug info for MIR.
+  void addCheckDebugPass();
+
   /// Add standard passes before a pass that's about to be added. For example,
   /// the DebugifyMachineModulePass if it is enabled.
   void addMachinePrePasses(bool AllowDebugify = true);
 
   /// Add standard passes after a pass that has just been added. For example,
   /// the MachineVerifier if it is enabled.
   void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
                             bool AllowStrip = true);

llvm/include/llvm/InitializePasses.h

 void initializeCFLSteensAAWrapperPassPass(PassRegistry&);
 void initializeCGProfileLegacyPassPass(PassRegistry &);
 void initializeCallGraphDOTPrinterPass(PassRegistry&);
 void initializeCallGraphPrinterLegacyPassPass(PassRegistry&);
 void initializeCallGraphViewerPass(PassRegistry&);
 void initializeCallGraphWrapperPassPass(PassRegistry&);
 void initializeCallSiteSplittingLegacyPassPass(PassRegistry&);
 void initializeCalledValuePropagationLegacyPassPass(PassRegistry &);
+void initializeCheckDebugMachineModulePass(PassRegistry &);
 void initializeCodeGenPreparePass(PassRegistry&);
 void initializeConstantHoistingLegacyPassPass(PassRegistry&);
 void initializeConstantMergeLegacyPassPass(PassRegistry&);
 void initializeConstraintEliminationPass(PassRegistry &);
 void initializeControlHeightReductionLegacyPassPass(PassRegistry&);
 void initializeCorrelatedValuePropagationPass(PassRegistry&);
 void initializeCostModelAnalysisPass(PassRegistry&);
 void initializeCrossDSOCFIPass(PassRegistry&);

llvm/lib/CodeGen/CMakeLists.txt

add_llvm_component_library(LLVMCodeGen
   LowerEmuTLS.cpp
   MachineBasicBlock.cpp
   MachineBlockFrequencyInfo.cpp
   MachineBlockPlacement.cpp
   MachineBranchProbabilityInfo.cpp
   MachineCombiner.cpp
   MachineCopyPropagation.cpp
   MachineCSE.cpp
+  MachineCheckDebugify.cpp
   MachineDebugify.cpp
   MachineDominanceFrontier.cpp
   MachineDominators.cpp
   MachineFrameInfo.cpp
   MachineFunction.cpp
   MachineFunctionPass.cpp
   MachineFunctionPrinterPass.cpp
   MachineFunctionSplitter.cpp

llvm/lib/CodeGen/CodeGen.cpp

 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
 void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeAtomicExpandPass(Registry);
   initializeBasicBlockSectionsPass(Registry);
   initializeBranchFolderPassPass(Registry);
   initializeBranchRelaxationPass(Registry);
   initializeCFGuardLongjmpPass(Registry);
   initializeCFIInstrInserterPass(Registry);
+  initializeCheckDebugMachineModulePass(Registry);
   initializeCodeGenPreparePass(Registry);
   initializeDeadMachineInstructionElimPass(Registry);
   initializeDebugifyMachineModulePass(Registry);
   initializeDetectDeadLanesPass(Registry);
   initializeDwarfEHPreparePass(Registry);
   initializeEarlyIfConverterPass(Registry);
   initializeEarlyIfPredicatorPass(Registry);
   initializeEarlyMachineLICMPass(Registry);

llvm/lib/CodeGen/MachineCheckDebugify.cpp

+//===- MachineCheckDebugify.cpp - Check debug info ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file This checks debug info after mir-debugify (+ pass-to-test). Currently
+/// it simply checks the integrity of line info in DILocation and
+/// DILocalVariable which mir-debugifiy generated before.
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/IR/DebugInfo.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Transforms/Utils/Debugify.h"
+
+#define DEBUG_TYPE "mir-check-debugify"
+
+using namespace llvm;
+
+namespace {
+
+struct CheckDebugMachineModule : public ModulePass {
+  bool runOnModule(Module &M) override {
+    MachineModuleInfo &MMI =
+        getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
+
+    NamedMDNode *NMD = M.getNamedMetadata("llvm.mir.debugify");
+    if (!NMD) {
+      errs() << "WARNING: Please run mir-debugify to generate "
+                "llvm.mir.debugify metadata first.\n";
+      return false;
+    }
+
+    auto getDebugifyOperand = [&](unsigned Idx) -> unsigned {
+      return mdconst::extract<ConstantInt>(NMD->getOperand(Idx)->getOperand(0))
+          ->getZExtValue();
+    };
+    assert(NMD->getNumOperands() == 2 &&
+           "llvm.mir.debugify should have exactly 2 operands!");
+    unsigned NumLines = getDebugifyOperand(0);
+    unsigned NumVars = getDebugifyOperand(1);
+    BitVector MissingLines{NumLines, true};
+    BitVector MissingVars{NumVars, true};
+
+    for (Function &F : M.functions()) {
+      MachineFunction *MF = MMI.getMachineFunction(F);
+      if (!MF)
+        continue;
+      for (MachineBasicBlock &MBB : *MF) {
+        // Find missing lines.
+        // TODO: Avoid meta instructions other than dbg_val.
+        for (MachineInstr &MI : MBB) {
+          if (MI.isDebugValue())
+            continue;
+          const DebugLoc DL = MI.getDebugLoc();
+          if (DL && DL.getLine() != 0) {
+            MissingLines.reset(DL.getLine() - 1);
+            continue;
+          }
+
+          if (!DL) {
+            errs() << "WARNING: Instruction with empty DebugLoc in function ";
+            errs() << F.getName() << " --";
+            MI.print(errs());
+          }
+        }
+
+        // Find missing variables.
+        // TODO: Handle DBG_INSTR_REF which is under an experimental option now.
+        for (MachineInstr &MI : MBB) {
+          if (!MI.isDebugValue())
+            continue;
+          const DILocalVariable *LocalVar = MI.getDebugVariable();
+          unsigned Var = ~0U;
+
+          (void)to_integer(LocalVar->getName(), Var, 10);
+          assert(Var <= NumVars && "Unexpected name for DILocalVariable");
+          MissingVars.reset(Var - 1);
+        }
+      }
+    }
+
+    bool Fail = false;
+    for (unsigned Idx : MissingLines.set_bits()) {
+      errs() << "WARNING: Missing line " << Idx + 1 << "\n";
+      Fail = true;
+    }
+
+    for (unsigned Idx : MissingVars.set_bits()) {
+      errs() << "WARNING: Missing variable " << Idx + 1 << "\n";
+      Fail = true;
+    }
+    errs() << "Machine IR debug info check: ";
+    errs() << (Fail ? "FAIL" : "PASS") << "\n";
+
+    return false;
+  }
+
+  CheckDebugMachineModule() : ModulePass(ID) {}
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<MachineModuleInfoWrapperPass>();
+    AU.addPreserved<MachineModuleInfoWrapperPass>();
+    AU.setPreservesCFG();
+  }
+
+  static char ID; // Pass identification.
+};
+char CheckDebugMachineModule::ID = 0;
+
+} // end anonymous namespace
+
+INITIALIZE_PASS_BEGIN(CheckDebugMachineModule, DEBUG_TYPE,
+                      "Machine Check Debug Module", false, false)
+INITIALIZE_PASS_END(CheckDebugMachineModule, DEBUG_TYPE,
+                    "Machine Check Debug Module", false, false)
+
+ModulePass *llvm::createCheckDebugMachineModulePass() {
+  return new CheckDebugMachineModule();
+}

llvm/lib/CodeGen/MachineDebugify.cpp

 //===- MachineDebugify.cpp - Attach synthetic debug info to everything ----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file This pass attaches synthetic debug info to everything. It can be used
 /// to create targeted tests for debug info preservation, or test for CodeGen
 /// differences with vs. without debug info.
 ///
 /// This isn't intended to have feature parity with Debugify.
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DIBuilder.h"
bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
   unsigned NextLine = SP->getLine();
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
       // This will likely emit line numbers beyond the end of the imagined
       // source function and into subsequent ones. We don't do anything about
       // that as it doesn't really matter to the compiler where the line is in
       // the imaginary source code.
       MI.setDebugLoc(DILocation::get(Ctx, NextLine++, 1, SP));
     }
   }
 
   // Find local variables defined by debugify. No attempt is made to match up
   // MIR-level regs to the 'correct' IR-level variables: there isn't a simple
   // way to do that, and it isn't necessary to find interesting CodeGen bugs.
   // Instead, simply keep track of one variable per line. Later, we can insert
   // DBG_VALUE insts that point to these local variables. Emitting DBG_VALUEs
   // which cover a wide range of lines can help stress the debug info passes:
bool applyDebugifyMetadataToMachineFunction(MachineModuleInfo &MMI,
   }
   if (Line2Var.empty())
     return true;
 
   // Now, try to insert a DBG_VALUE instruction after each real instruction.
   // Do this by introducing debug uses of each register definition. If that is
   // not possible (e.g. we have a phi or a meta instruction), emit a constant.
   uint64_t NextImm = 0;
+  SmallSet<DILocalVariable *, 16> VarSet;
   const MCInstrDesc &DbgValDesc = TII.get(TargetOpcode::DBG_VALUE);
   for (MachineBasicBlock &MBB : MF) {
     MachineBasicBlock::iterator FirstNonPHIIt = MBB.getFirstNonPHI();
-    for (auto I = MBB.begin(), E = MBB.end(); I != E; ) {
+    for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
       MachineInstr &MI = *I;
       ++I;
 
       // `I` may point to a DBG_VALUE created in the previous loop iteration.
       if (MI.isDebugInstr())
         continue;
 
       // It's not allowed to insert DBG_VALUEs after a terminator.
       if (MI.isTerminator())
         continue;
 
       // Find a suitable insertion point for the DBG_VALUE.
       auto InsertBeforeIt = MI.isPHI() ? FirstNonPHIIt : I;
 
       // Find a suitable local variable for the DBG_VALUE.
       unsigned Line = MI.getDebugLoc().getLine();
       if (!Line2Var.count(Line))
         Line = EarliestDVI->getDebugLoc().getLine();
       DILocalVariable *LocalVar = Line2Var[Line];
       assert(LocalVar && "No variable for current line?");
+      VarSet.insert(LocalVar);
 
       // Emit DBG_VALUEs for register definitions.
       SmallVector<MachineOperand *, 4> RegDefs;
       for (MachineOperand &MO : MI.operands())
         if (MO.isReg() && MO.isDef() && MO.getReg())
           RegDefs.push_back(&MO);
       for (MachineOperand *MO : RegDefs)
         BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,
                 /*IsIndirect=*/false, *MO, LocalVar, Expr);
 
       // OK, failing that, emit a constant DBG_VALUE.
       if (RegDefs.empty()) {
         auto ImmOp = MachineOperand::CreateImm(NextImm++);
         BuildMI(MBB, InsertBeforeIt, MI.getDebugLoc(), DbgValDesc,
                 /*IsIndirect=*/false, ImmOp, LocalVar, Expr);
       }
     }
   }
 
+  // Here we save the number of lines and variables into "llvm.mir.debugify".
+  // It is useful for mir-check-debugify.
+  NamedMDNode *NMD = M.getNamedMetadata("llvm.mir.debugify");
+  IntegerType *Int32Ty = Type::getInt32Ty(Ctx);
+  if (!NMD) {
+    NMD = M.getOrInsertNamedMetadata("llvm.mir.debugify");
+    auto addDebugifyOperand = [&](unsigned N) {
+      NMD->addOperand(MDNode::get(
+          Ctx, ValueAsMetadata::getConstant(ConstantInt::get(Int32Ty, N))));
+    };
+    // Add number of lines.
+    addDebugifyOperand(NextLine - 1);
+    // Add number of variables.
+    addDebugifyOperand(VarSet.size());
+  } else {
+    assert(NMD->getNumOperands() == 2 &&
+           "llvm.mir.debugify should have exactly 2 operands!");
+    auto setDebugifyOperand = [&](unsigned Idx, unsigned N) {
+      NMD->setOperand(Idx, MDNode::get(Ctx, ValueAsMetadata::getConstant(
+                                                ConstantInt::get(Int32Ty, N))));
+    };
+    // Set number of lines.
+    setDebugifyOperand(0, NextLine - 1);
+    // Set number of variables.
+    setDebugifyOperand(1, VarSet.size());
+  }
+
   return true;
 }
 
 /// ModulePass for attaching synthetic debug info to everything, used with the
 /// legacy module pass manager.
 struct DebugifyMachineModule : public ModulePass {
   bool runOnModule(Module &M) override {
     MachineModuleInfo &MMI =

llvm/lib/CodeGen/TargetPassConfig.cpp

VerifyMachineCode("verify-machineinstrs", cl::Hidden,
                       cl::desc("Verify generated machine code"),
                       cl::ZeroOrMore);
 static cl::opt<cl::boolOrDefault> DebugifyAndStripAll(
     "debugify-and-strip-all-safe", cl::Hidden,
     cl::desc(
         "Debugify MIR before and Strip debug after "
         "each pass except those known to be unsafe when debug info is present"),
     cl::ZeroOrMore);
+static cl::opt<cl::boolOrDefault> DebugifyCheckAndStripAll(
+    "debugify-check-and-strip-all-safe", cl::Hidden,
+    cl::desc(
+        "Debugify MIR before, by checking and stripping the debug info after, "
+        "each pass except those known to be unsafe when debug info is present"),
+    cl::ZeroOrMore);
 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
 // Enable or disable the MachineOutliner.
 static cl::opt<RunOutliner> EnableMachineOutliner(
     "enable-machine-outliner", cl::desc("Enable the machine outliner"),
     cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
     cl::values(clEnumValN(AlwaysOutline, "always",
                           "Run on all functions guaranteed to be beneficial"),
                clEnumValN(NeverOutline, "never", "Disable all outlining"),

 void TargetPassConfig::addDebugifyPass() {
   PM->add(createDebugifyMachineModulePass());
 }
 
 void TargetPassConfig::addStripDebugPass() {
   PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
 }
 
+void TargetPassConfig::addCheckDebugPass() {
+  PM->add(createCheckDebugMachineModulePass());
+}
+
 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
-  if (AllowDebugify && DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
+  if (AllowDebugify && DebugifyIsSafe &&
+      (DebugifyAndStripAll == cl::BOU_TRUE ||
+       DebugifyCheckAndStripAll == cl::BOU_TRUE))
     addDebugifyPass();
 }
 
 void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
                                             bool AllowVerify, bool AllowStrip) {
-  if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
+  if (DebugifyIsSafe) {
+    if (DebugifyCheckAndStripAll == cl::BOU_TRUE) {
+      addCheckDebugPass();
+      addStripDebugPass();
+    } else if (DebugifyAndStripAll == cl::BOU_TRUE)
       addStripDebugPass();
+  }
   if (AllowVerify)
     addVerifyPass(Banner);
 }
 
 /// Add common target configurable passes that perform LLVM IR to IR transforms
 /// following machine independent optimization.
 void TargetPassConfig::addIRPasses() {
   // Before running any passes, run the verifier to determine if the input

llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -debugify-and-strip-all-safe=0 -run-pass=mir-debugify -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
 ...
 ---
 name:            fconstant_to_constant_s32
 alignment:       4
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    1
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: fconstant_to_constant_s32
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0, debug-location !10
-    ; CHECK: DBG_VALUE [[COPY]](p0), $noreg, !8, !DIExpression(), debug-location !10
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FA99999A0000000, debug-location !DILocation(line: 2, column: 1, scope: !5)
-    ; CHECK: DBG_VALUE [[C]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
-    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 524, debug-location !DILocation(line: 3, column: 1, scope: !5)
-    ; CHECK: DBG_VALUE [[C1]](s64), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !5)
-    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64), debug-location !DILocation(line: 4, column: 1, scope: !5)
-    ; CHECK: DBG_VALUE [[PTR_ADD]](p0), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
-    ; CHECK: G_STORE [[C]](s32), [[PTR_ADD]](p0), debug-location !DILocation(line: 5, column: 1, scope: !5) :: (store 4)
-    ; CHECK: DBG_VALUE 0, $noreg, !8, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
-    ; CHECK: RET_ReallyLR debug-location !DILocation(line: 6, column: 1, scope: !5)
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0, debug-location !11
+    ; CHECK: DBG_VALUE [[COPY]](p0), $noreg, !9, !DIExpression(), debug-location !11
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FA99999A0000000, debug-location !DILocation(line: 2, column: 1, scope: !6)
+    ; CHECK: DBG_VALUE [[C]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !6)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 524, debug-location !DILocation(line: 3, column: 1, scope: !6)
+    ; CHECK: DBG_VALUE [[C1]](s64), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !6)
+    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64), debug-location !DILocation(line: 4, column: 1, scope: !6)
+    ; CHECK: DBG_VALUE [[PTR_ADD]](p0), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !6)
+    ; CHECK: G_STORE [[C]](s32), [[PTR_ADD]](p0), debug-location !DILocation(line: 5, column: 1, scope: !6) :: (store 4)
+    ; CHECK: DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !6)
+    ; CHECK: RET_ReallyLR debug-location !DILocation(line: 6, column: 1, scope: !6)
     %0:_(p0) = COPY $x0
     %3:_(s32) = G_FCONSTANT float 0x3FA99999A0000000
     %1:_(s64) = G_CONSTANT i64 524
     %2:_(p0) = G_PTR_ADD %0, %1(s64)
     G_STORE %3(s32), %2(p0) :: (store 4)
     RET_ReallyLR
 ...

llvm/test/CodeGen/AArch64/GlobalISel/phi-mir-debugify.mir

registers:
   - { id: 9, class: _, preferred-register: '' }
   - { id: 10, class: _, preferred-register: '' }
 liveins:
 body:             |
   ; CHECK-LABEL: name: legalize_phi
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: $w0
-  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0, debug-location !10
-  ; CHECK:   DBG_VALUE [[COPY]](s32), $noreg, !8, !DIExpression(), debug-location !10
-  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0, debug-location !DILocation(line: 2, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[C]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
-  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1, debug-location !DILocation(line: 3, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[C1]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !5)
-  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 4, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[C2]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
-  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]], debug-location !DILocation(line: 5, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[ICMP]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
-  ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.1, debug-location !DILocation(line: 6, column: 1, scope: !5)
-  ; CHECK:   G_BR %bb.2, debug-location !DILocation(line: 7, column: 1, scope: !5)
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0, debug-location !11
+  ; CHECK:   DBG_VALUE [[COPY]](s32), $noreg, !9, !DIExpression(), debug-location !11
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0, debug-location !DILocation(line: 2, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[C]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !6)
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1, debug-location !DILocation(line: 3, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[C1]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !6)
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 4, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[C2]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !6)
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]], debug-location !DILocation(line: 5, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[ICMP]](s1), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !6)
+  ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.1, debug-location !DILocation(line: 6, column: 1, scope: !6)
+  ; CHECK:   G_BR %bb.2, debug-location !DILocation(line: 7, column: 1, scope: !6)
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]], debug-location !DILocation(line: 8, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[ADD]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 8, column: 1, scope: !5)
-  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ADD]](s32), debug-location !DILocation(line: 9, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[TRUNC]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 9, column: 1, scope: !5)
-  ; CHECK:   G_BR %bb.3, debug-location !DILocation(line: 10, column: 1, scope: !5)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]], debug-location !DILocation(line: 8, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[ADD]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 8, column: 1, scope: !6)
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ADD]](s32), debug-location !DILocation(line: 9, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[TRUNC]](s1), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 9, column: 1, scope: !6)
+  ; CHECK:   G_BR %bb.3, debug-location !DILocation(line: 10, column: 1, scope: !6)
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]], debug-location !DILocation(line: 11, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[ADD1]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 11, column: 1, scope: !5)
-  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ADD1]](s32), debug-location !DILocation(line: 12, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[TRUNC1]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 12, column: 1, scope: !5)
+  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]], debug-location !DILocation(line: 11, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[ADD1]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 11, column: 1, scope: !6)
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ADD1]](s32), debug-location !DILocation(line: 12, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[TRUNC1]](s1), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 12, column: 1, scope: !6)
   ; CHECK: bb.3:
-  ; CHECK:   [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 13, column: 1, scope: !5)
-  ; CHECK:   [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 14, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[PHI]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 13, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[PHI1]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 14, column: 1, scope: !5)
-  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s1), debug-location !DILocation(line: 15, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE [[ZEXT]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 15, column: 1, scope: !5)
-  ; CHECK:   $w0 = COPY [[ZEXT]](s32), debug-location !DILocation(line: 16, column: 1, scope: !5)
-  ; CHECK:   DBG_VALUE $w0, $noreg, !8, !DIExpression(), debug-location !DILocation(line: 16, column: 1, scope: !5)
-  ; CHECK:   RET_ReallyLR implicit $w0, debug-location !DILocation(line: 17, column: 1, scope: !5)
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 13, column: 1, scope: !6)
+  ; CHECK:   [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 14, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[PHI]](s1), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 13, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[PHI1]](s1), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 14, column: 1, scope: !6)
+  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s1), debug-location !DILocation(line: 15, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE [[ZEXT]](s32), $noreg, !9, !DIExpression(), debug-location !DILocation(line: 15, column: 1, scope: !6)
+  ; CHECK:   $w0 = COPY [[ZEXT]](s32), debug-location !DILocation(line: 16, column: 1, scope: !6)
+  ; CHECK:   DBG_VALUE $w0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 16, column: 1, scope: !6)
+  ; CHECK:   RET_ReallyLR implicit $w0, debug-location !DILocation(line: 17, column: 1, scope: !6)
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $w0
 
     %0(s32) = COPY $w0
     %1(s32) = G_CONSTANT i32 0
     %3(s32) = G_CONSTANT i32 1
     %6(s32) = G_CONSTANT i32 2

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir

+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=mir-check-debugify -o - %s 2>&1 | FileCheck %s
+--- |
+  ; ModuleID = 'check-line-and-variables.mir'
+  source_filename = "check-line-and-variables.c"
+
+  @ga = dso_local local_unnamed_addr global i32 2, align 4
+
+  ; Function Attrs: nofree norecurse nounwind uwtable writeonly
+  define dso_local i32 @foo(i32 %a, i32 %b) local_unnamed_addr #0 !dbg !9 {
+  entry:
+    %add = add nsw i32 %b, %a, !dbg !15
+    call void @llvm.dbg.value(metadata i32 %add, metadata !12, metadata !DIExpression()), !dbg !15
+    %mul = shl nsw i32 %add, 1, !dbg !16
+    call void @llvm.dbg.value(metadata i32 %mul, metadata !14, metadata !DIExpression()), !dbg !16
+    store i32 %mul, i32* @ga, align 4, !dbg !17
+    ret i32 %add, !dbg !18
+  }
+
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #1
+
+  !llvm.module.flags = !{!0, !1}
+  !llvm.ident = !{!2}
+  !llvm.dbg.cu = !{!3}
+  !llvm.mir.debugify = !{!6, !7}
+  !llvm.debugify = !{!8, !7}
+
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{i32 2, !"Debug Info Version", i32 3}
+  !2 = !{!"clang version 12.0.0 (https://github.com/llvm/llvm-project.git c0a922b3db2d39f36c0c01776cce90cc160a7d62)"}
+  !3 = distinct !DICompileUnit(language: DW_LANG_C, file: !4, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !5)
+  !4 = !DIFile(filename: "main.mir", directory: "/")
+  !5 = !{}
+  !6 = !{i32 6}
+  !7 = !{i32 2}
+  !8 = !{i32 4}
+  !9 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !4, line: 1, type: !10, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !3, retainedNodes: !11)
+  !10 = !DISubroutineType(types: !5)
+  !11 = !{!12, !14}
+  !12 = !DILocalVariable(name: "1", scope: !9, file: !4, line: 1, type: !13)
+  !13 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
+  !14 = !DILocalVariable(name: "2", scope: !9, file: !4, line: 2, type: !13)
+  !15 = !DILocation(line: 1, column: 1, scope: !9)
+  !16 = !DILocation(line: 2, column: 1, scope: !9)
+  !17 = !DILocation(line: 3, column: 1, scope: !9)
+  !18 = !DILocation(line: 4, column: 1, scope: !9)
+
+...
+---
+name:            foo
+body:             |
+  bb.0.entry:
+    liveins: $edi, $esi
+
+    %1:gr32 = COPY $esi, debug-location !15
+    DBG_VALUE %1, $noreg, !12, !DIExpression(), debug-location !15
+    ; Let it missing !14 and debug-location !16
+    ; %0:gr32 = COPY $edi, debug-location !16
+    ; DBG_VALUE %0, $noreg, !14, !DIExpression(), debug-location !16
+    %0:gr32 = COPY $edi
+    %2:gr32 = nsw ADD32rr %1, %0, implicit-def dead $eflags, debug-location !17
+    DBG_VALUE %2, $noreg, !12, !DIExpression(), debug-location !17
+    DBG_VALUE $eflags, $noreg, !12, !DIExpression(), debug-location !17
+    %3:gr32 = nsw ADD32rr %2, %2, implicit-def dead $eflags, debug-location !18
+    DBG_VALUE %3, $noreg, !12, !DIExpression(), debug-location !18
+    DBG_VALUE $eflags, $noreg, !12, !DIExpression(), debug-location !18
+    MOV32mr $rip, 1, $noreg, @ga, $noreg, killed %3, debug-location !DILocation(line: 5, column: 1, scope: !9) :: (store 4 into @ga, !tbaa !18)
+    DBG_VALUE 0, $noreg, !12, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !9)
+    ; Let it miss Line 6: Change "!DILocation(line: 6, ..." to "!DILocation(line: 5, ..."
+    $eax = COPY %2, debug-location !DILocation(line: 5, column: 1, scope: !9)
+    DBG_VALUE $eax, $noreg, !12, !DIExpression(), debug-location !DILocation(line: 6, column: 1, scope: !9)
+    RET 0, $eax, debug-location !DILocation(line: 7, column: 1, scope: !9)
+
+    ;CHECK:      WARNING: Instruction with empty DebugLoc in function foo --%1:gr32 = COPY $edi
+    ;CHECK-NEXT: WARNING: Missing line 2
+    ;CHECK-NEXT: WARNING: Missing line 6
+    ;CHECK-NEXT: WARNING: Missing variable 2
+    ;CHECK-NEXT: Machine IR debug info check: FAIL
+
+...

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.ll

+; RUN: llc -debugify-check-and-strip-all-safe -o - %s 2>&1 | FileCheck %s
+
+; ModuleID = 'main.c'
+source_filename = "main.c"
+
+@ga = dso_local global i32 2, align 4
+
+define dso_local i32 @foo(i32 %a, i32 %b) {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  store i32 %add, i32* %c, align 4
+  %2 = load i32, i32* %c, align 4
+  %mul = mul nsw i32 %2, 2
+  store i32 %mul, i32* @ga, align 4
+  %3 = load i32, i32* %c, align 4
+  ret i32 %3
+}
+
+; Different Back-Ends may have different number of passes, here we only
+; check two of them to make sure -debugify-check-and-strip-all-safe works.
+;CHECK: Machine IR debug info check: PASS
+;CHECK: Machine IR debug info check: PASS

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir

+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=mir-debugify,dead-mi-elimination,mir-check-debugify -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=mir-debugify,mir-check-debugify -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-PASS
+--- |
+  ; ModuleID = 'check-line-and-variables.mir'
+  source_filename = "check-line-and-variables.ll"
+
+  @ga = dso_local global i32 2, align 4
+
+  ; Function Attrs: noinline nounwind optnone uwtable
+  define dso_local i32 @foo(i32 %a, i32 %b) {
+  entry:
+    %a.addr = alloca i32, align 4
+    %b.addr = alloca i32, align 4
+    %c = alloca i32, align 4
+    store i32 %a, i32* %a.addr, align 4
+    store i32 %b, i32* %b.addr, align 4
+    %0 = load i32, i32* %a.addr, align 4
+    %1 = load i32, i32* %b.addr, align 4
+    %add = add nsw i32 %0, %1
+    store i32 %add, i32* %c, align 4
+    %2 = load i32, i32* %c, align 4
+    %mul = mul nsw i32 %2, 2
+    store i32 %mul, i32* @ga, align 4
+    %3 = load i32, i32* %c, align 4
+    ; dead-mi-elimination will remove %4 = ...
+    %4 = load i32, i32* %a.addr, align 4
+    ret i32 %3
+  }
+
+...
+---
+name:            foo
+alignment:       16
+stack:
+  - { id: 0, name: a.addr, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: b.addr, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: c, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0.entry:
+    liveins: $edi, $esi
+
+    %2:gr32 = COPY $esi
+    %0:gr32 = COPY $edi
+    %1:gr32 = COPY killed %0
+    %3:gr32 = COPY killed %2
+    MOV32mr %stack.0.a.addr, 1, $noreg, 0, $noreg, %1 :: (store 4 into %ir.a.addr)
+    MOV32mr %stack.1.b.addr, 1, $noreg, 0, $noreg, %3 :: (store 4 into %ir.b.addr)
+    %14:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg :: (load 4 from %ir.a.addr)
+    %13:gr32 = ADD32rm killed %14, %stack.1.b.addr, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load 4 from %ir.b.addr)
+    ; dead-mi-elimination will remove %15:gr32 = ...
+    %15:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg :: (load 4 from %ir.a.addr)
+    MOV32mr %stack.2.c, 1, $noreg, 0, $noreg, killed %13 :: (store 4 into %ir.c)
+    %9:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load 4 from %ir.c)
+    %8:gr32 = SHL32ri killed %9, 1, implicit-def $eflags
+    MOV32mr $noreg, 1, $noreg, @ga, $noreg, killed %8 :: (store 4 into @ga)
+    %5:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load 4 from %ir.c)
+    $eax = COPY %5
+    RETQ implicit $eax
+
+    ;CHECK:      WARNING: Missing line 9
+    ;CHECK-NEXT: Machine IR debug info check: FAIL
+    ;CHECK-PASS: Machine IR debug info check: PASS
+...

llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir

--- |
   ; VALUE-NEXT: call void @llvm.dbg.value(metadata i32 %add, metadata [[add:![0-9]+]], metadata !DIExpression()), !dbg [[L1]]
     %sub = sub i32 %add, %b
   ; ALL-NEXT: %sub = sub i32 %add, %b, !dbg [[L2:![0-9]+]]
   ; VALUE-NEXT: call void @llvm.dbg.value(metadata i32 %sub, metadata [[sub:![0-9]+]], metadata !DIExpression()), !dbg [[L2]]
   ; ALL-NEXT: ret i32 %sub, !dbg [[L3:![0-9]+]]
     ret i32 %sub
   }
 
-  ; ALL: !llvm.dbg.cu = !{!0}
+  ; ALL: !llvm.dbg.cu = !{![[CU:[0-9]+]]}
   ; ALL: !llvm.debugify =
   ; ALL: !llvm.module.flags = !{![[VERSION:[0-9]+]]}
-  ; ALL: !0 = distinct !DICompileUnit(
+  ; ALL: ![[CU]] = distinct !DICompileUnit(
   ; ALL: ![[VERSION]] = !{i32 2, !"Debug Info Version", i32 3}
   ; VALUE: [[VAR1:![0-9]+]] = !DILocalVariable(name: "1"
   ; VALUE: [[VAR2:![0-9]+]] = !DILocalVariable(name: "2"
 
 ...
 ---
 name:            test
 body:             |
   bb.1 (%ir-block.0):
     %0:_(s32) = IMPLICIT_DEF
     %1:_(s32) = IMPLICIT_DEF
     %2:_(s32) = G_CONSTANT i32 2
     %3:_(s32) = G_ADD %0, %2
     %4:_(s32) = G_SUB %3, %1
     ; There's no attempt to have the locations make sense as it's an imaginary
     ; source file anyway. These first three coincide with IR-level information
     ; and therefore use metadata references.
     ; ALL: %0:_(s32) = IMPLICIT_DEF debug-location [[L1]]
     ; VALUE: DBG_VALUE %0(s32), $noreg, [[VAR1]], !DIExpression(), debug-location [[L1]]
     ; ALL: %1:_(s32) = IMPLICIT_DEF debug-location [[L2]]
     ; VALUE: DBG_VALUE %1(s32), $noreg, [[VAR2]], !DIExpression(), debug-location [[L2]]
     ; ALL: %2:_(s32) = G_CONSTANT i32 2, debug-location [[L3]]
     ; VALUE: DBG_VALUE %2(s32), $noreg, [[VAR1]], !DIExpression(), debug-location [[L3]]
-    ; ALL: %3:_(s32) = G_ADD %0, %2, debug-location !DILocation(line: 4, column: 1, scope: !6)
+    ; ALL: %3:_(s32) = G_ADD %0, %2, debug-location !DILocation(line: 4, column: 1, scope: [[SP:![0-9]+]])
     ; VALUE: DBG_VALUE %3(s32), $noreg, [[VAR1]], !DIExpression(), debug-location !DILocation(line: 4
-    ; ALL: %4:_(s32) = G_SUB %3, %1, debug-location !DILocation(line: 5, column: 1, scope: !6)
+    ; ALL: %4:_(s32) = G_SUB %3, %1, debug-location !DILocation(line: 5, column: 1, scope: [[SP]])
     ; VALUE: DBG_VALUE %4(s32), $noreg, [[VAR1]], !DIExpression(), debug-location !DILocation(line: 5
 ...

llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn

sources = [
     "MIRPrinter.cpp",
     "MIRPrintingPass.cpp",
     "MIRVRegNamerUtils.cpp",
     "MachineBasicBlock.cpp",
     "MachineBlockFrequencyInfo.cpp",
     "MachineBlockPlacement.cpp",
     "MachineBranchProbabilityInfo.cpp",
     "MachineCSE.cpp",
+    "MachineCheckDebugify.cpp",
     "MachineCombiner.cpp",
     "MachineCopyPropagation.cpp",
     "MachineDebugify.cpp",
     "MachineDominanceFrontier.cpp",
     "MachineDominators.cpp",
     "MachineFrameInfo.cpp",
     "MachineFunction.cpp",
     "MachineFunctionPass.cpp",