Address Simon's comments.

In D128570#3621731, @RKSimon wrote:

Please pre-commit fshl-splat-undef.ll with current trunk codegen so that the patch commit shows the codegen change.

LGTM with a few minors

LGTM

Hi Friends, PLS can you accept this fix ? This is related to one of our Must Fix bug. Many thanks!

OK, let me add test coverage in APIntTest.cpp, many thanks!

In D128584#3614159, @LuoYuanke wrote:

In previous code, the tile register and shape register are allocated in the same pass. The shape config is processed before "virtregrewriter". Though when filling shape, it is still virtual register, but the virtual register has been split or spillied.

Add a test

I think the spill/split should still cover the shape regs:

Let me try create a small lit test for it. Thanks

LGTM

I think the idea of "split" special registers RA pass is good (especially for the registers who need to be config).
I notice all the "isVirtual<Register>" places need carefully to "exclude" the special registers.
Seems we may no need to do it if we can make sure that we handle these special registers before normal fast RA.
(because they have be allocated to physic registers)

LGTM

Mark some TODO for your planning.

Address pengfei's comment

Address pengfei's comment.

To generate zero value, ... may convert

>%0:vr128 = PXORrr undef %0, undef %0
>to %1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128.

It is not expected.

LGTM

Many thanks for your careful reviewing !!

Combine usually make sense. Not sure the case load/store has special attributes, e.g. volatile. The new amx load/store may miss them.

Use IsOneUse, let it more readable.

LGTM

Rebase

close with clang format at
commit 6454ff35e0e7b0c0762c640031aa6c2b5d1f16ec
[Clang Format] emmintrin.h smmintrin.h (NFC)

Thank you for your effort !!
Hi @RKSimon , a small question: do your local lit test can be checked by “make check-all” these 2 days ？
I ask it because I try to change the code and do make check-all to find out which tests will be affect. But I find we (out team) all meet “make check-all” problem these days. (Can not finish in very long time)

Rebased. Thank you!

In D123652#3461788, @RKSimon wrote:

please can you rebase?

In D124067#3461551, @RKSimon wrote:

OK - SSE2/SSE41 now have i386 coverage - please can you rebase and update the checks to use CHECK/X64/X86 ?

Add yuanke's test

In D123652#3458786, @LuoYuanke wrote:

Try this test case?

That is cool!

The small test case is easy to reproduced on llvm.14 PLS refer EY93Kc77E
it continue to do the combine ( gen vpsubb + vptest ) even there is more uses of the cmp result.

In D123652#3450748, @pengfei wrote:

Maybe use llvm-reduce to reduce the original IR? You can use llvm-extract --bb=FunctionName:DAGCombineBB YourIR.ll to get the bb first.

In D123652#3447672, @RKSimon wrote:

Please can you add test coverage - preferably for both cases?