[PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[ZarkoCA]

Summary

This patch is the initial patch for support of the AIX extended vector ABI. The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

Minor nit: align this with the first argument in the preceeding line.

4

I'm not sure the formatting we have adopted for the tests, but I think subsequent commands were to be indented by 2? @Xiangling_L or @DiggerLin might know better, I think it was on one of their reviews where I saw it mentioned.

20

A couple minor suggestions

1. Use only 2 or 3 callee saved vector registers as clobbers. It will show how we allocate stack space to store all vector registers from N to 31 where N is the lowest used csr vr, and make the test a bit more concise.
2. Have V12 as a clobber to show that it is not callee saved.

[sfertile]

More test coverage for this patch:

1. We should test spill/restore code when we have gpr/fpr/vr callee-saves all in the same function.
2. Extend at least one of the frame-pointer and base pointer tests to have a vector callee-saved clobbered.

See inline-asm-vsx-clobbers.ll. We should have a test which uses vsx registers to clobber fprs and vector registers and makes sure we allocate the right stack size, emit the right spills/restores. I think it should be a separate patch though as its testing the inline-asm implementation more, where the other test use inline-asm to test the frame-lowering. I can prepare this patch if you like.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

20

Ignore number 2. you already have that with v13, I should have paid more attention :(.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

The ABI mentioned AIX5.3 is the first AIX release to enable vector programming, and there are arch like pwr4 is not compatible with altivec. Since this is our first altivec patch, it looks it's the right place to add report_fatal_error for arch level which doesn't support altivec.

4

The original formatting comment is here: https://reviews.llvm.org/D78929#inline-740137

223

Could you also add a testcase showing how csr FPR/GPR interact with nonvolatile VR?

[ZarkoCA]

Added test case that includes FP and GP csrs along with the vector crs.
Reduced the number of clobbered VRs in the initial test case.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

While I think that's a good suggestion, none of the other PPC targets do anything similar. If you choose an arch that doesn't support altivec while selecting a CPU that doesn't support it they quietly don't generate the altivec instructions.

Also, as things are, we do have a report fatal error when ever someone tries using vector types in the front end and in the back end.

4

Thanks for info, I updated the RUN steps.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I see. The only reason why I raise it up is because XL gives an error when using altivec with unsupported arch.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I see a warning and xlc and xlclang:
1506-1162 (W) The altivec option is not supported for the target architecture and is ignored.
Additionally with xlclang we get from the altivec.h header included in xlclang if an unsupported arch is specified.

But this has me thinking that it is a good idea to follow through with your suggestion of an error.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

Since the extended ABI vector-enabled mode is not the safe default (certain call sequences involving functions compiled using the default ABI can bypass restoration of the non-volatile register values), we should report_fatal_error unless if the extended ABI is explicitly enabled.

Example:

[ uses non-volatile vector registers ]
vv   calls
[ not vector-extended ABI-aware ] -- calls setjmp
vv   calls
[ uses non-volatile vector registers ]
vv   calls
[ not vector-extended ABI-aware ] -- calls longjmp

This follows the precedent for the llc default for data sections: Even for llc, we do not enable the "unsafe" mode by default.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

55

minor nit: trailing space on line 54, 55, 57, 58, 60

82

Can we line up all comments?

82

I am suggesting to use things like [[REG1:[0-9]+]] to match registers, use {{[0-9]+}} to match numerical values if we need to. The same comments apply to all testcases.

121

Thank you for adding this testcase. I think it would be better if we also test`r13`/x14, f14, v20, then we can observe the padding added in.

[sfertile]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

220–221

Should we reformat this even though its ugly to avoid it cluttering other reviews that touch this file? Maybe if we delete the comment we will end up with a format that matches the 64-bit array more closely :shrug:

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

41

STXVD2X killed $v20, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)

Using $r{{[0-9]+}} for the second register in the r+r addressing is fine, but don't use a regex for r1/x1, its wothwhile to show that the addressing is based off he stack pointer.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

5

The comments here let me think should we also implement an equivalent option for llc to control which ABI to be enabled in addition to the frontend or driver option?

[ZarkoCA]

Added mvecnvol/mnovecnvol options in clang and vecnvol option in llc
Addressed other comments related to formatting and test case regex usage.
Updated test cases that fail when vecnvol is enabled.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I added the options to toggle between the two Altivec ABIs.

5

Yes, good point, I added that as well.

82

I'd rather not use any variables unless we need to use them later.

121

Good suggestion, I added.

[Xiangling_L]

I am wondering can we split the option related changes to a separate patch for reviews? That would make current patch a bit easier to review and faster to be committed as two small pieces.

If it's possible, I am thinking we can try to split it up to the following two pieces:

1. Add option in the frontend and backend to be able to turn on extended vector ABI
2. Do the frame lowing in the backend

clang/docs/ClangCommandLineReference.rst

2868

1. I am not sure if it's a good idea to put the supporting status also in the option description here. It looks a bit strange to me.

2. I would suggest something similar like this for the option description:

Only supported on AIX. Specifies whether to use both volatile and nonvolatile vector registers or volatile vector registers only. Defaults to `-mnovecnvol` when Altivec is enabled.

3. We missed a - before mnovecnvol.

clang/include/clang/Basic/DiagnosticDriverKinds.td

531

I would suggest:

The default Altivec ABI on AIX is not yet supported, use '-mvecnvol' for the extended Altivec ABI

clang/test/CodeGen/altivec.c

1

Can we also test how the driver react to these two options? It would serve as the LIT coverage for the code change in clang/lib/Driver/ToolChains/Clang.cpp.

llvm/include/llvm/Target/TargetOptions.h

177

Can we also use bitfield to indicate true and false here? The default value set to be false in ctor already, so we don't need assign 0 to it here.

unsigned AIXExtendedAltivecABI : 1;

[ZarkoCA]

Separated the option portion of the previous diff (now found here: https://reviews.llvm.org/D89684).
Addressed other comments.

[ZarkoCA]

Fixed typo in test case.

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

184–187

I suggest doing the error checking once before getting into the 32-bit/64-bit blocks.

[ZarkoCA]

Rebased and addressed comments.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

184–187

Thanks, good suggestion, I moved it up right at the beginning of the function.

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

225

CSR_64_AllRegs_Altivec_RegMask should be CSR_PPC64_Altivec_RegMask. FWIW I don't think this is testable without D86476. If that's the case, then it should go in that patch, not this patch.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

225

Are you suggesting that I also leave the error in if I were to move this change to D84676?

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

225

Can you still run the tests that are part of this commit with that error in? My understanding was that it didn't interfere, but I didn't verify that. If we can still run the tests then yes leave the error in. If we can't then it probably gives us a clue about how to test the change in this patch without needing D84676, in which case we can keep the change and simply add the testing that exercises it.

[ZarkoCA]

Rebase and remove regmask altivec change.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

225

No, you were right those changes can't be tested. Just needed some clarification, thanks.

[ZarkoCA]

Fixed failing test cases.

[sfertile]

LGTM.

[ZarkoCA]

Seems a few test cases require mattr=-altivec to pass with this patch.

clang/docs/ClangCommandLineReference.rst

 .. program:: clang
 
 Only supported on X86. Otherwise accepted for compatibility with GCC.
 
 .. option:: -mtvos-version-min=<arg>, -mappletvos-version-min=<arg>
 
 .. option:: -municode<arg>
 
+Specify usage of volatile and nonvolatile vector registers, the extended vector ABI on AIX (AIX only).  The default AIX vector ABI is not yet supported. 
+
+.. option:: -mvecnvol, mnovecnvol
+
 .. option:: -mvx, -mno-vx
 
 .. option:: -mwarn-nonportable-cfstrings, -mno-warn-nonportable-cfstrings
 
 .. option:: -mwatchos-version-min=<arg>
 
 .. option:: -mwavefrontsize64, -mno-wavefrontsize64
 

clang/include/clang/Basic/CodeGenOptions.def

 CODEGENOPT(RegisterGlobalDtorsWithAtExit, 1, 1) ///< Use atexit or __cxa_atexit to register global destructors.
 CODEGENOPT(CXXCtorDtorAliases, 1, 0) ///< Emit complete ctors/dtors as linker
                                      ///< aliases to base ctors when possible.
 CODEGENOPT(DataSections      , 1, 0) ///< Set when -fdata-sections is enabled.
 CODEGENOPT(UniqueSectionNames, 1, 1) ///< Set for -funique-section-names.
 CODEGENOPT(UniqueBasicBlockSectionNames, 1, 1) ///< Set for -funique-basic-block-section-names,
                                                ///< Produce unique section names with
                                                ///< basic block sections.
+CODEGENOPT(AIXExtendedAltivecABI, 1, 0) ///< Set for -mvecnvol. Enables the extended Altivec ABI on AIX.
 ENUM_CODEGENOPT(FramePointer, FramePointerKind, 2, FramePointerKind::None) /// frame-pointer: all,non-leaf,none
 
 CODEGENOPT(DisableFree       , 1, 0) ///< Don't free memory.
 CODEGENOPT(DiscardValueNames , 1, 0) ///< Discard Value Names from the IR (LLVMContext flag)
 CODEGENOPT(DisableGCov       , 1, 0) ///< Don't run the GCov pass, for testing.
 CODEGENOPT(DisableLLVMPasses , 1, 0) ///< Don't run any LLVM IR passes to get
                                      ///< the pristine IR generated by the
                                      ///< frontend.

clang/include/clang/Basic/DiagnosticDriverKinds.td

 def err_drv_cannot_mix_options : Error<"cannot specify '%1' along with '%0'">;
 
 def err_drv_invalid_object_mode : Error<"OBJECT_MODE setting %0 is not recognized and is not a valid setting.">;
 
 def err_drv_invalid_sve_vector_bits : Error<
   "'-msve-vector-bits' is not supported without SVE enabled">;
 
 def err_invalid_cxx_abi : Error<"invalid C++ ABI name '%0'">;
+
+def err_aix_default_altivec_abi : Error<
+  "The default Altivec ABI on AIX is not yet supported, use the extended ABI option '-mvecnvol'">;
+
+def err_aix_altivec : Error<"'-mvecnvol' and '-mnovecnvol' require '-maltivec'">; 
 }

clang/include/clang/Driver/Options.td

 def faltivec : Flag<["-"], "faltivec">, Group<f_Group>, Flags<[DriverOption]>;
 def fno_altivec : Flag<["-"], "fno-altivec">, Group<f_Group>, Flags<[DriverOption]>;
 def maltivec : Flag<["-"], "maltivec">, Group<m_ppc_Features_Group>;
 def mno_altivec : Flag<["-"], "mno-altivec">, Group<m_ppc_Features_Group>;
 def mpcrel: Flag<["-"], "mpcrel">, Group<m_ppc_Features_Group>;
 def mno_pcrel: Flag<["-"], "mno-pcrel">, Group<m_ppc_Features_Group>;
 def mspe : Flag<["-"], "mspe">, Group<m_ppc_Features_Group>;
 def mno_spe : Flag<["-"], "mno-spe">, Group<m_ppc_Features_Group>;
+def mvecnvol : Flag<["-"], "mvecnvol">, Group<m_Group>, Flags<[CC1Option]>, 
+  HelpText<"Enable the extended Altivec ABI on AIX (AIX only). Uses volatile and nonvolatile vector registers">;
+def mnovecnvol : Flag<["-"], "mnovecnvol">, Group<m_Group>, Flags<[CC1Option]>, 
+  HelpText<"Enable the default Altivec ABI on AIX (AIX only)">;
 def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
 def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
 def msecure_plt : Flag<["-"], "msecure-plt">, Group<m_ppc_Features_Group>;
 def mpower8_vector : Flag<["-"], "mpower8-vector">,
     Group<m_ppc_Features_Group>;
 def mno_power8_vector : Flag<["-"], "mno-power8-vector">,
     Group<m_ppc_Features_Group>;
 def mpower9_vector : Flag<["-"], "mpower9-vector">,

clang/lib/CodeGen/BackendUtil.cpp

static void initTargetOptions(DiagnosticsEngine &Diags,
   Options.TLSSize = CodeGenOpts.TLSSize;
   Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
   Options.ExplicitEmulatedTLS = CodeGenOpts.ExplicitEmulatedTLS;
   Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
   Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
   Options.EmitAddrsig = CodeGenOpts.Addrsig;
   Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection;
   Options.EmitCallSiteInfo = CodeGenOpts.EmitCallSiteInfo;
+  Options.AIXExtendedAltivecABI = CodeGenOpts.AIXExtendedAltivecABI; 
   Options.ValueTrackingVariableLocations =
       CodeGenOpts.ValueTrackingVariableLocations;
   Options.XRayOmitFunctionIndex = CodeGenOpts.XRayOmitFunctionIndex;
 
   Options.MCOptions.SplitDwarfFile = CodeGenOpts.SplitDwarfFile;
   Options.MCOptions.MCRelaxAll = CodeGenOpts.RelaxAll;
   Options.MCOptions.MCSaveTempLabels = CodeGenOpts.SaveTempLabels;
   Options.MCOptions.MCUseDwarfDirectory = !CodeGenOpts.NoDwarfDirectoryAsm;

clang/lib/Driver/ToolChains/Clang.cpp

for (const Arg *A : Args.filtered(options::OPT_frewrite_map_file,
       } else {
         CmdArgs.push_back("-frewrite-map-file");
         CmdArgs.push_back(A->getValue());
         A->claim();
       }
     }
   }
 
+  if (Arg *A =
+          Args.getLastArg(options::OPT_mvecnvol, options::OPT_mnovecnvol)) {
+
+    if (!RawTriple.isOSAIX())
+      D.Diag(diag::err_drv_unsupported_opt_for_target)
+          << A->getSpelling() << RawTriple.str();
+
+    bool haveMaltivec = false;
+
+    for (const Arg *A : Args) {
+      auto optID = A->getOption().getID();
+      switch (optID) {
+      default:
+        break;
+      case options::OPT_maltivec:
+        haveMaltivec = true;
+      }
+    }
+
+    if (A->getOption().matches(options::OPT_mnovecnvol) && haveMaltivec)
+      D.Diag(diag::err_aix_default_altivec_abi);
+    else if (A->getOption().matches(options::OPT_mvecnvol) && haveMaltivec)
+      CmdArgs.push_back("-mvecnvol");
+    else
+      D.Diag(diag::err_aix_default_altivec_abi);
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) {
     StringRef v = A->getValue();
     CmdArgs.push_back("-mllvm");
     CmdArgs.push_back(Args.MakeArgString("-warn-stack-size=" + v));
     A->claim();
   }
 
   if (!Args.hasFlag(options::OPT_fjump_tables, options::OPT_fno_jump_tables,

clang/lib/Frontend/CompilerInvocation.cpp

 //===- CompilerInvocation.cpp ---------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "clang/Frontend/CompilerInvocation.h"
 #include "TestModuleFileExtension.h"
 #include "clang/Basic/Builtins.h"
 #include "clang/Basic/CharInfo.h"
 #include "clang/Basic/CodeGenOptions.h"
 #include "clang/Basic/CommentOptions.h"
 #include "clang/Basic/DebugInfoOptions.h"
 #include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/DiagnosticIDs.h"
 #include "clang/Basic/DiagnosticOptions.h"
 #include "clang/Basic/FileSystemOptions.h"
 #include "clang/Basic/LLVM.h"
 #include "clang/Basic/LangOptions.h"
 #include "clang/Basic/LangStandard.h"
 #include "clang/Basic/ObjCRuntime.h"
 #include "clang/Basic/Sanitizers.h"
 #include "clang/Basic/SourceLocation.h"
if (O.matches(OPT_fpcc_struct_return) ||
       Opts.setStructReturnConvention(CodeGenOptions::SRCK_InRegs);
     }
   }
 
   if (T.isOSAIX() && (Args.hasArg(OPT_mignore_xcoff_visibility) ||
                       !Args.hasArg(OPT_fvisibility)))
     Opts.IgnoreXCOFFVisibility = 1;
 
+  if (Arg *A = Args.getLastArg(OPT_mnovecnvol, OPT_mvecnvol)) {
+    if (!T.isOSAIX())
+      Diags.Report(diag::err_drv_unsupported_opt_for_target)
+          << A->getSpelling() << T.str();
+
+    const Option &O = A->getOption();
+    if (O.matches(OPT_mnovecnvol))
+      Diags.Report(diag::err_aix_default_altivec_abi)
+          << A->getSpelling() << T.str();
+    else {
+      assert(O.matches(OPT_mvecnvol));
+      Opts.AIXExtendedAltivecABI = 1;
+    }
+  }
+
+
   Opts.DependentLibraries = Args.getAllArgValues(OPT_dependent_lib);
   Opts.LinkerOptions = Args.getAllArgValues(OPT_linker_option);
   bool NeedLocTracking = false;
 
   Opts.OptRecordFile = std::string(Args.getLastArgValue(OPT_opt_record_file));
   if (!Opts.OptRecordFile.empty())
     NeedLocTracking = true;
 

clang/test/CodeGen/altivec.c

 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -mvecnvol -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s
+// RUN: not %clang_cc1 -target-feature +altivec -mnovecnvol -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck --check-prefix=AIX-ERROR %s
+// RUN: not %clang_cc1 -target-feature +altivec -mnovecnvol -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck --check-prefix=AIX-ERROR %s
 
 // Check initialization
 
 vector int test0 = (vector int)(1);       // CHECK: @test0 = global <4 x i32> <i32 1, i32 1, i32 1, i32 1>
 vector float test1 = (vector float)(1.0); // CHECK: @test1 = global <4 x float> <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
 
 // CHECK: @v1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 2, i8 0, i8 0, i8 0, i8 3, i8 0, i8 0, i8 0, i8 4>
 vector char v1 = (vector char)((vector int)(1, 2, 3, 4));

 void test3() {
   vector int vi;
   vi++;                                    // CHECK: add <4 x i32> {{.*}} <i32 1, i32 1, i32 1, i32 1>
   vector unsigned int vui;
   --vui;                                   // CHECK: add <4 x i32> {{.*}} <i32 -1, i32 -1, i32 -1, i32 -1>
   vector float vf;
   vf++;                                    // CHECK: fadd <4 x float> {{.*}} <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
 }
+
+// AIX-ERROR:  error: The default Altivec ABI on AIX is not yet supported, use the extended ABI option '-mvecnvol'

llvm/include/llvm/CodeGen/CommandFlags.h

 llvm::FloatABI::ABIType getFloatABIForCalls();
 
 llvm::FPOpFusion::FPOpFusionMode getFuseFPOps();
 
 bool getDontPlaceZerosInBSS();
 
 bool getEnableGuaranteedTailCallOpt();
 
+bool getAIXExtendedAltivecABI();
+
 bool getDisableTailCalls();
 
 bool getStackSymbolOrdering();
 
 unsigned getOverrideStackAlignment();
 
 bool getStackRealign();
 

llvm/include/llvm/Target/TargetMachine.h

public:
   }
   void setSupportsDefaultOutlining(bool Enable) {
     Options.SupportsDefaultOutlining = Enable;
   }
   void setSupportsDebugEntryValues(bool Enable) {
     Options.SupportsDebugEntryValues = Enable;
   }
 
+  bool getAIXExtendedAltivecABI() const {
+    return Options.AIXExtendedAltivecABI;
+  }
+
   bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
 
   /// Return true if unique basic block section names must be generated.
   bool getUniqueBasicBlockSectionNames() const {
     return Options.UniqueBasicBlockSectionNames;
   }
 
   /// Return true if data objects should be emitted into their own section,

llvm/include/llvm/Target/TargetOptions.h

enum class GlobalISelAbortMode {
     DisableWithDiag // Disable the abort but emit a diagnostic on failure.
   };
 
   class TargetOptions {
   public:
     TargetOptions()
         : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
           NoTrappingFPMath(true), NoSignedZerosFPMath(false),
+          AIXExtendedAltivecABI(false),
           HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
           GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
           EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
           DisableIntegratedAS(false), RelaxELFRelocations(false),
           FunctionSections(false), DataSections(false),
           IgnoreXCOFFVisibility(false), UniqueSectionNames(true),
           UniqueBasicBlockSectionNames(false), TrapUnreachable(false),
           NoTrapAfterNoreturn(false), TLSSize(0), EmulatedTLS(false),
public:
     unsigned NoTrappingFPMath : 1;
 
     /// NoSignedZerosFPMath - This flag is enabled when the
     /// -enable-no-signed-zeros-fp-math is specified on the command line. This
     /// specifies that optimizations are allowed to treat the sign of a zero
     /// argument or result as insignificant.
     unsigned NoSignedZerosFPMath : 1;
 
+    /// AIXExtendedAltivecABI - This flag returns true when -mvecnvol is
+    /// specified. The code generator is then able to use both volatile and
+    /// nonvolitle vector regisers. When false, the code generator only uses
+    /// volatile vector registers which is the default setting on AIX.
+    unsigned AIXExtendedAltivecABI = 0;
+
     /// HonorSignDependentRoundingFPMath - This returns true when the
     /// -enable-sign-dependent-rounding-fp-math is specified.  If this returns
     /// false (the default), the code generator is allowed to assume that the
     /// rounding behavior is the default (round-to-zero for all floating point
     /// to integer conversions, and round-to-nearest for all other arithmetic
     /// truncations).  If this is enabled (set to true), the code generator must
     /// assume that the rounding mode may dynamically change.
     unsigned HonorSignDependentRoundingFPMathOption : 1;

llvm/lib/CodeGen/CommandFlags.cpp

 CGOPT(ExceptionHandling, ExceptionModel)
 CGOPT_EXP(CodeGenFileType, FileType)
 CGOPT(FramePointer::FP, FramePointerUsage)
 CGOPT(bool, EnableUnsafeFPMath)
 CGOPT(bool, EnableNoInfsFPMath)
 CGOPT(bool, EnableNoNaNsFPMath)
 CGOPT(bool, EnableNoSignedZerosFPMath)
 CGOPT(bool, EnableNoTrappingFPMath)
+CGOPT(bool, AIXExtendedAltivecABI)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
 CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math)
 CGOPT(bool, EnableHonorSignDependentRoundingFPMath)
 CGOPT(FloatABI::ABIType, FloatABIForCalls)
 CGOPT(FPOpFusion::FPOpFusionMode, FuseFPOps)
 CGOPT(bool, DontPlaceZerosInBSS)
 CGOPT(bool, EnableGuaranteedTailCallOpt)
 CGOPT(bool, DisableTailCalls)
#define CGBINDOPT(NAME)                                                        \
   CGBINDOPT(FuseFPOps);
 
   static cl::opt<bool> DontPlaceZerosInBSS(
       "nozero-initialized-in-bss",
       cl::desc("Don't place zero-initialized symbols into bss section"),
       cl::init(false));
   CGBINDOPT(DontPlaceZerosInBSS);
 
+  static cl::opt<bool> AIXExtendedAltivecABI(
+      "vecnvol",
+      cl::desc(
+          "Enable the AIX Extended Altivec ABI."),
+      cl::init(false));
+  CGBINDOPT(AIXExtendedAltivecABI);
+
   static cl::opt<bool> EnableGuaranteedTailCallOpt(
       "tailcallopt",
       cl::desc(
           "Turn fastcc calls into tail calls by (potentially) changing ABI."),
       cl::init(false));
   CGBINDOPT(EnableGuaranteedTailCallOpt);
 
   static cl::opt<bool> DisableTailCalls(
codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) {
 
   // FIXME: Should have separate input and output flags
   Options.setFPDenormalMode(DenormalMode(DenormKind, DenormKind));
 
   Options.HonorSignDependentRoundingFPMathOption =
       getEnableHonorSignDependentRoundingFPMath();
   if (getFloatABIForCalls() != FloatABI::Default)
     Options.FloatABIType = getFloatABIForCalls();
+  Options.AIXExtendedAltivecABI = getAIXExtendedAltivecABI();
   Options.NoZerosInBSS = getDontPlaceZerosInBSS();
   Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt();
   Options.StackAlignmentOverride = getOverrideStackAlignment();
   Options.StackSymbolOrdering = getStackSymbolOrdering();
   Options.UseInitArray = !getUseCtors();
   Options.RelaxELFRelocations = getRelaxELFRelocations();
   Options.DataSections =
       getExplicitDataSections().getValueOr(TheTriple.hasDefaultDataSections());

llvm/lib/Target/PowerPC/PPCCallingConv.td

 
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
                                      F19, F20, F21, F22, F23, F24, F25, F26,
                                      F27, F28, F29, F30, F31, CR2, CR3, CR4
                                 )>;
 
+def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;
+
 // Common CalleeSavedRegs for SVR4 and AIX.
 def CSR_PPC64   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
                                         X21, X22, X23, X24, X25, X26, X27, X28,
                                         X29, X30, X31, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
                                    )>;
 

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

#define CALLEE_SAVED_VRS \
   static const SpillSlot ELFOffsets64[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS64,
 
       // VRSAVE save area offset.
       {PPC::VRSAVE, -4},
       CALLEE_SAVED_VRS
   };
 
-  static const SpillSlot AIXOffsets32[] = {
-      CALLEE_SAVED_FPRS,
+  static const SpillSlot AIXOffsets32[] = {CALLEE_SAVED_FPRS,
                                            CALLEE_SAVED_GPRS32,
                                            // Add AIX's extra CSR.
                                            {PPC::R13, -76},
-      // TODO: Update when we add vector support for AIX.
-  };
+                                           CALLEE_SAVED_VRS};
 
   static const SpillSlot AIXOffsets64[] = {
-      CALLEE_SAVED_FPRS,
-      CALLEE_SAVED_GPRS64,
-      // TODO: Update when we add vector support for AIX.
-  };
+      CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS};
 
   if (Subtarget.is64BitELFABI()) {
     NumEntries = array_lengthof(ELFOffsets64);
     return ELFOffsets64;
   }
 
   if (Subtarget.is32BitELFABI()) {
     NumEntries = array_lengthof(ELFOffsets32);

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
                    CCState &State) {
 
   const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>(
       State.getMachineFunction().getSubtarget());
   const bool IsPPC64 = Subtarget.isPPC64();
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
+  if (ValVT.isVector() &&
+      !State.getMachineFunction().getTarget().Options.AIXExtendedAltivecABI)
+    report_fatal_error("the default Altivec AIX ABI is not yet supported.");
+
   assert((!ValVT.isInteger() ||
           (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
          "Integer argument exceeds register size: should have been legalized");
 
   if (ValVT == MVT::f128)
     report_fatal_error("f128 is unimplemented on AIX.");
 
   if (ArgFlags.isNest())

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
     if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
-    if (Subtarget.hasAltivec())
+    if (Subtarget.hasAltivec()) {
+      if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
+        report_fatal_error("the default AIX Altivec ABI is not yet "
+                           "supported.");
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                     : CSR_PPC64_Altivec_SaveList;
+    }
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
-  if (Subtarget.isAIXABI())
+  if (Subtarget.isAIXABI()) {
+    if (Subtarget.hasAltivec()) {
+        if (!TM.getAIXExtendedAltivecABI())
+          report_fatal_error("the default AIX Altivec ABI is not yet "
+                             "supported.");
+        return CSR_AIX32_Altivec_SaveList;
+      }
     return CSR_AIX32_SaveList;
+  }
+
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
   else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
 
 const uint32_t *
 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
-    assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
-    return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+    return TM.isPPC64()
+               ? (Subtarget.hasAltivec() ? CSR_64_AllRegs_Altivec_RegMask
+                                         : CSR_PPC64_RegMask)
+               : (Subtarget.hasAltivec() ? CSR_AIX32_Altivec_RegMask
+                                         : CSR_AIX32_RegMask);
   }
 
   if (CC == CallingConv::Cold) {
     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
                                                   : CSR_SVR64_ColdCC_RegMask)
                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
                                                   : (Subtarget.hasSPE()
                                                   ? CSR_SVR32_ColdCC_SPE_RegMask

llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
 @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }]
 @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @bar, i8* null }]
 
 define dso_local void @foo() {
 entry:
   ret void

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

+ RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vecnvol -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $v20, $v26, $v31
+
+; MIR32-DAG:     STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG:     STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG:     $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32:         BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $v20, $v26, $v31
+
+; MIR64-DAG:     STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG:     STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG:     $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64:         BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32:         li {{[0-9]+}}, -192
+; ASM32-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -16
+; ASM32-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32:         #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     lxvd2x 58, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -192
+; ASM32-DAG:     lxvd2x 52, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM32:         blr
+
+; ASM64-LABEL:   .vec_regs:
+
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -16
+; ASM64-DAG:     stxvd2x {{[0-9]+}}, 1, {{[0-9]+}}      # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x {{[0-9]+}}, 1, {{[0-9]+}}       # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     blr
+
+define dso_local void @fprs_gprs_vecregs() {
+  call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            fprs_gprs_vecregs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -240, size: 16, alignment: 16, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -416, size: 16, alignment: 16, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 6, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 7, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 8, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default, 
+; MIR32-NEXT:        callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '', 
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31
+
+; MIR32-DAG:     STW killed $r14, 232, $r1 :: (store 4 into %fixed-stack.8, align 8)
+; MIR32-DAG:     STW killed $r25, 276, $r1 :: (store 4 into %fixed-stack.7)
+; MIR32-DAG:     STW killed $r31, 300, $r1 :: (store 4 into %fixed-stack.6)
+; MIR32-DAG:     STFD killed $f14, 304, $r1 :: (store 8 into %fixed-stack.5, align 16)
+; MIR32-DAG:     STFD killed $f21, 360, $r1 :: (store 8 into %fixed-stack.4)
+; MIR32-DAG:     STFD killed $f31, 440, $r1 :: (store 8 into %fixed-stack.3)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 128
+; MIR32-DAG:     STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 208
+; MIR32-DAG:     STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+; MIR32-DAG:     $r1 = STWU $r1, -448, $r1
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $r14 = LWZ 232, $r1 :: (load 4 from %fixed-stack.8, align 8)
+; MIR32-DAG:     $r25 = LWZ 276, $r1 :: (load 4 from %fixed-stack.7)
+; MIR32-DAG:     $r31 = LWZ 300, $r1 :: (load 4 from %fixed-stack.6)
+; MIR32-DAG:     $f14 = LFD 304, $r1 :: (load 8 from %fixed-stack.5, align 16)
+; MIR32-DAG:     $f21 = LFD 360, $r1 :: (load 8 from %fixed-stack.4)
+; MIR32-DAG:     $f31 = LFD 440, $r1 :: (load 8 from %fixed-stack.3)
+; MIR32-DAG:     $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 128
+; MIR32-DAG:     $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 208
+; MIR32-DAG:     $r1 = ADDI $r1, 448
+; MIR32-DAG:     BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            fprs_gprs_vecregs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -480, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 6, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 7, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 8, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31
+
+; MIR64-DAG:     $x1 = STDU $x1, -544, $x1
+; MIR64-DAG:     STD killed $x14, 256, $x1 :: (store 8 into %fixed-stack.8, align 16)
+; MIR64-DAG:     STD killed $x25, 344, $x1 :: (store 8 into %fixed-stack.7)
+; MIR64-DAG:     STD killed $x31, 392, $x1 :: (store 8 into %fixed-stack.6)
+; MIR64-DAG:     STFD killed $f14, 400, $x1 :: (store 8 into %fixed-stack.5, align 16)
+; MIR64-DAG:     STFD killed $f21, 456, $x1 :: (store 8 into %fixed-stack.4)
+; MIR64-DAG:     STFD killed $f31, 536, $x1 :: (store 8 into %fixed-stack.3)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 160
+; MIR64-DAG:     STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 240
+; MIR64-DAG:     STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $x14 = LD 256, $x1 :: (load 8 from %fixed-stack.8, align 16)
+; MIR64-DAG:     $x25 = LD 344, $x1 :: (load 8 from %fixed-stack.7)
+; MIR64-DAG:     $x31 = LD 392, $x1 :: (load 8 from %fixed-stack.6)
+; MIR64-DAG:     $f14 = LFD 400, $x1 :: (load 8 from %fixed-stack.5, align 16)
+; MIR64-DAG:     $f21 = LFD 456, $x1 :: (load 8 from %fixed-stack.4)
+; MIR64-DAG:     $f31 = LFD 536, $x1 :: (load 8 from %fixed-stack.3)
+; MIR64-DAG:     $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 160
+; MIR64-DAG:     $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 240
+; MIR64-DAG:     $x1 = ADDI8 $x1, 544
+; MIR64-DAG:     BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL:   .fprs_gprs_vecregs:
+
+; ASM32:         stwu 1, -448(1)
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     stw 14, 232(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 14, 304(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, 128
+; ASM32-DAG:     stw 25, 276(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, 208
+; ASM32-DAG:     stw 31, 300(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 21, 360(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stfd 31, 440(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM32-DAG:     #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, 128
+; ASM32-DAG:     lfd 31, 440(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     lfd 21, 360(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM32-DAG:     lfd 14, 304(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lwz 31, 300(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     lwz 25, 276(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     lwz 14, 232(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     addi 1, 1, 448
+; ASM32:         blr
+ 
+; ASM64-LABEL    .fprs_gprs_vecregs:
+
+; ASM64:         stdu 1, -544(1)
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     std 14, 256(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 14, 400(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 52, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, 160
+; ASM64-DAG:     std 25, 344(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 58, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, 240
+; ASM64-DAG:     std 31, 392(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 21, 456(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stfd 31, 536(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 63, 1, {{[0-9]+}}               # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x 63, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, 160
+; ASM64-DAG:     lfd 31, 536(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lxvd2x 58, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     lfd 21, 456(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lxvd2x 52, 1, {{[0-9]+}}                # 16-byte Folded Reload
+; ASM64-DAG:     lfd 14, 400(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     ld 31, 392(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     ld 25, 344(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     ld 14, 256(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     addi 1, 1, 544
+; ASM64:         blr

llvm/test/CodeGen/PowerPC/aix-default-vec-abi.ll

+; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
+
+define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12, <4 x i32> %vec13, <4 x i32> %vec14) {
+  entry:
+    %add = add <4 x i32> %vec1, %vec2
+    %add1 = add <4 x i32> %add, %vec3
+    %add2 = add <4 x i32> %add1, %vec4
+    %add3 = add <4 x i32> %add2, %vec5
+    %add4 = add <4 x i32> %add3, %vec6
+    %add5 = add <4 x i32> %add4, %vec7
+    %add6 = add <4 x i32> %add5, %vec8
+    %add7 = add <4 x i32> %add6, %vec9
+    %add8 = add <4 x i32> %add7, %vec10
+    %add9 = add <4 x i32> %add8, %vec11
+    %add10 = add <4 x i32> %add9, %vec12
+    %add11 = add <4 x i32> %add10, %vec13
+    %add12 = add <4 x i32> %add11, %vec14
+    ret <4 x i32> %add12
+}
+
+; CHECK:  LLVM ERROR: the default Altivec AIX ABI is not yet supported.

llvm/test/CodeGen/PowerPC/aix-func-align.ll

 ; This test tries to verify if a csect containing code would have the correct alignment.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN:   FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 define i32 @foo()  align 32 {
 entry:

llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj  --symbols %t.o | FileCheck %s
 
 define void @foo() {
 entry:
   ret void
 }
 
 ; CHECK:      File: {{.*}}aix-func-dsc-gen.ll.tmp.o

llvm/test/CodeGen/PowerPC/aix-internal.ll

-; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4  \
+; RUN: llc -mtriple powerpc-ibm-aix -vecnvol -verify-machineinstrs -mcpu=pwr4  \
 ; RUN: -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck %s
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix -vecnvol -verify-machineinstrs -mcpu=pwr4 \
 ; RUN: -filetype=obj -o %t.o < %s 2>&1 | FileCheck --check-prefix=64-CHECK %s
 
 define internal i32 @foo() {
   ret i32 1
 }
 
 ; CHECK:  Symbol {
 ; CHECK:       Name: .foo

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 define void @foo() {
 entry:
   %tmp = alloca i64
   br label %__here
 
 __here:

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 define float @test_float() {
 entry:
   ret float 5.500000e+00
 }
 
 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %const.0, $r2 :: (load 4 from got)

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -code-model=small < %s | FileCheck \
 ; RUN: --check-prefixes=32SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -code-model=large < %s | FileCheck \
 ; RUN: --check-prefixes=32LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -code-model=small < %s | FileCheck \
 ; RUN: --check-prefixes=64SMALL-ASM,SMALL-ASM %s
 
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -code-model=large < %s | FileCheck \
 ; RUN: --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -function-sections < %s | FileCheck \
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -vecnvol -function-sections < %s | FileCheck \
 ; RUN: --check-prefixes=FUNC-ASM,CHECK %s
 
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -function-sections < %s | FileCheck \
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -function-sections < %s | FileCheck \
 ; RUN: --check-prefixes=FUNC-ASM,CHECK %s
 
   define i32 @jump_table(i32 %a) {
   entry:
     switch i32 %a, label %sw.epilog [
       i32 1, label %sw.bb
       i32 2, label %sw.bb1
       i32 3, label %sw.bb2

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
-; RUN:     -data-sections=false < %s | FileCheck %s
+; RUN:     -vecnvol -data-sections=false < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
-; RUN:     -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
+; RUN:     -vecnvol -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo
 declare void @foo(...)
 
 @bar_ptr1 = global void (...)* bitcast (void ()* @bar to void (...)*)
 define void @bar() {
 entry:
   ret void

llvm/test/CodeGen/PowerPC/aix-return55.ll

-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -vecnvol -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -vecnvol -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
 
-; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -vecnvol -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = global i64 320255973571806, align 8
 @d = global double 5.000000e+00, align 8
 @strA = private unnamed_addr constant [10 x i8] c"hellowor\0A\00", align 1
 
 define dso_local signext i32 @foo() {
 entry:
   ret i32 55
 ; CHECK-LABEL: .foo:
 ; CHECK: li 3, 55
 ; CHECK: blr
 }
 
 ;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:       0: 38 60 00 37                    li 3, 55
 ;CHECKOBJ-NEXT:       4: 4e 80 00 20                    blr{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1>:
+;CHECKOBJ-NEXT: 00000008 <.rodata.str1.1L..strA>:
 ;CHECKOBJ-NEXT:       8: 68 65 6c 6c                   xori 5, 3, 27756
 ;CHECKOBJ-NEXT:       c: 6f 77 6f 72 xoris 23, 27, 28530
 ;CHECKOBJ-NEXT:      10: 0a 00 00 00 tdlti 0, 0{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: Disassembly of section .data:{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: 00000018 <a>:
 ;CHECKOBJ-NEXT:      18: 00 01 23 45                   <unknown>
 ;CHECKOBJ-NEXT:      1c: 67 8a bc de                   oris 10, 28, 48350{{[[:space:]] *}}
 ;CHECKOBJ-NEXT: 00000020 <d>:

llvm/test/CodeGen/PowerPC/aix-space.ll

-; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 
 @a = common global double 0.000000e+00, align 8
 
 ; Get some constants into the constant pool that need spacing for alignment
 define void @e() {
 entry:
   %0 = load double, double* @a, align 8
   %mul = fmul double 1.500000e+00, %0
   store double %mul, double* @a, align 8
   %mul1 = fmul double 0x3F9C71C71C71C71C, %0
   store double %mul1, double* @a, align 8
   ret void
 }
 
 ; CHECK:      .space 4
 ; CHECK-NOT:  .zero

llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj \ 
+; RUN:     -data-sections -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 @ivar = local_unnamed_addr global i32 35, align 4
 @const_ivar = constant i32 35, align 4
 
 @a = common global i32 0, align 4
 @f = common local_unnamed_addr global i32 0, align 4

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s |\
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s |\
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 %struct.Merge_cnst32 = type { i64, i32, i64, i32 }
 %struct.Merge_cnst16 = type { i64, i32 }
 %struct.Merge_cnst8 = type { i32, i32 }
 %struct.Merge_cnst4 = type { i16, i8 }
 
 @__const.main.cnst32 = private unnamed_addr constant %struct.Merge_cnst32 { i64 4611686018427387954, i32 0, i64 0, i32 0 }
 @__const.main.cnst16 = private unnamed_addr constant %struct.Merge_cnst16 { i64 4611686018427387926, i32 0 }
 @__const.main.cnst8 = private unnamed_addr constant %struct.Merge_cnst8 { i32 1073741832, i32 0 }
 @__const.main.cnst4 = private unnamed_addr constant %struct.Merge_cnst4 { i16 16392, i8 0 }
 
 ; Function Attrs: noinline nounwind optnone
 define i32 @main() #0 {
 entry:
   ret i32 0
 }
 
-;CHECK:         .csect .rodata[RO],4
+;CHECK:         .csect .text[PR],2
 
-;CHECK-NEXT:         .align  4
-;CHECK-NEXT: L..__const.main.cnst32:
-;CHECK32-NEXT:         .vbyte 4, 1073741824
-;CHECK32-NEXT:         .vbyte 4, 50
-;CHECK64-NEXT:         .vbyte 8, 4611686018427387954
-;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
+;CHECK:      L..__const.main.cnst32[RO],4
+;CHECK-NEXT:           .align  4
+;CHECK32-NEXT:         .vbyte  4, 1073741824
+;CHECK32-NEXT:         .vbyte  4, 50
+;CHECK64-NEXT:         .vbyte  8, 4611686018427387954
+;CHECK-NEXT:           .vbyte  4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
-;CHECK32-NEXT:         .vbyte 4, 0
-;CHECK32-NEXT:         .vbyte 4, 0
-;CHECK64-NEXT:         .vbyte 8, 0
-;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
+;CHECK32-NEXT:         .vbyte  4, 0
+;CHECK32-NEXT:         .vbyte  4, 0
+;CHECK64-NEXT:         .vbyte  8, 0
+;CHECK-NEXT:           .vbyte  4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
 
+;CHECK-NEXT: L..__const.main.cnst16[RO],3
 ;CHECK-NEXT:           .align  3
-;CHECK-NEXT: L..__const.main.cnst16:
-;CHECK32-NEXT:         .vbyte 4, 1073741824
-;CHECK32-NEXT:         .vbyte 4, 22
-;CHECK64-NEXT:         .vbyte 8, 4611686018427387926
-;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
+;CHECK32-NEXT:         .vbyte  4, 1073741824
+;CHECK32-NEXT:         .vbyte  4, 22
+;CHECK64-NEXT:         .vbyte  8, 4611686018427387926
+;CHECK-NEXT:           .vbyte  4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
 
-;CHECK-NEXT:         .align  3
-;CHECK-NEXT: L..__const.main.cnst8:
-;CHECK-NEXT:         .vbyte 4, 1073741832              # 0x40000008
-;CHECK-NEXT:         .vbyte 4, 0                       # 0x0
+;CHECK-NEXT: L..__const.main.cnst8[RO],3
+;CHECK-NEXT:           .align  3
+;CHECK-NEXT:           .vbyte  4, 1073741832              # 0x40000008
+;CHECK-NEXT:           .vbyte  4, 0                       # 0x0
 
-;CHECK-NEXT:         .align  3
-;CHECK-NEXT: L..__const.main.cnst4:
-;CHECK-NEXT:         .vbyte 2, 16392                   # 0x4008
-;CHECK-NEXT:         .byte   0                       # 0x0
-;CHECK-NEXT:         .space  1
+;CHECK-NEXT: L..__const.main.cnst4[RO],3
+;CHECK-NEXT:           .align  3
+;CHECK-NEXT:           .vbyte  2, 16392                   # 0x4008
+;CHECK-NEXT:           .byte   0                          # 0x0
+;CHECK-NEXT:           .space  1
 
 
 ;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:        0: 38 60 00 00                    li 3, 0
 ;CHECKOBJ-NEXT:        4: 4e 80 00 20                    blr
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}
-;CHECKOBJ-NEXT: 00000010 <.rodata>:
+;CHECKOBJ-NEXT: 00000010 <L..__const.main.cnst32>:
 ;CHECKOBJ-NEXT:        10: 40 00 00 00
 ;CHECKOBJ-NEXT:        14: 00 00 00 32
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}
-;CHECKOBJ-SAME:       30: 40 00 00 00
+;CHECKOBJ-NEXT: 00000030 <L..__const.main.cnst16>:
+;CHECKOBJ-NEXT:       30: 40 00 00 00
 ;CHECKOBJ-NEXT:       34: 00 00 00 16
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}
-;CHECKOBJ-SAME:       40: 40 00 00 08
+;CHECKOBJ-NEXT: 00000040 <L..__const.main.cnst8>:
+;CHECKOBJ-NEXT:       40: 40 00 00 08
 ;CHECKOBJ-NEXT:       44: 00 00 00 00
-;CHECKOBJ-NEXT:       48: 40 08 00 00
 
+;CHECKOBJ:     00000048 <L..__const.main.cnst4>:
+;CHECKOBJ-NEXT:       48: 40 08 00 00
 
-;CHECKSYM:        Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: .rodata
-;CHECKSYM-NEXT:     Value (RelocatableAddress): 0x10
-;CHECKSYM-NEXT:     Section: .text
-;CHECKSYM-NEXT:     Type: 0x0
-;CHECKSYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
-;CHECKSYM-NEXT:     NumberOfAuxEntries: 1
-;CHECKSYM-NEXT:     CSECT Auxiliary Entry {
-;CHECKSYM-NEXT:       Index: [[#Index+1]]
-;CHECKSYM-NEXT:       SectionLen: 60
-;CHECKSYM-NEXT:       ParameterHashIndex: 0x0
-;CHECKSYM-NEXT:       TypeChkSectNum: 0x0
-;CHECKSYM-NEXT:       SymbolAlignmentLog2: 4
-;CHECKSYM-NEXT:       SymbolType: XTY_SD (0x1)
-;CHECKSYM-NEXT:       StorageMappingClass: XMC_RO (0x1)
-;CHECKSYM-NEXT:       StabInfoIndex: 0x0
-;CHECKSYM-NEXT:       StabSectNum: 0x0
-;CHECKSYM-NEXT:     }
-;CHECKSYM-NEXT:   }
+;CHECKSYM:        Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst32
+;CHECKSYM-NEXT:   Value (RelocatableAddress): 0x10
+;CHECKSYM-NEXT:   Section: .text
+;CHECKSYM-NEXT:   Type: 0x0
+;CHECKSYM-NEXT:   StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT:   NumberOfAuxEntries: 1
+;CHECKSYM-NEXT:   CSECT Auxiliary Entry {
+;CHECKSYM-NEXT:     Index: [[#Index+1]] 
+;CHECKSYM-NEXT:     SectionLen: 32
+;CHECKSYM-NEXT:     ParameterHashIndex: 0x0
+;CHECKSYM-NEXT:     TypeChkSectNum: 0x0
+;CHECKSYM-NEXT:     SymbolAlignmentLog2: 4
+;CHECKSYM-NEXT:     SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT:     StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT:     StabInfoIndex: 0x0
+;CHECKSYM-NEXT:     StabSectNum: 0x0
+;CHECKSYM-NEXT:        }
+;CHECKSYM-NEXT:  }
+
+;CHECKSYM:        Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst16
+;CHECKSYM-NEXT:   Value (RelocatableAddress): 0x30
+;CHECKSYM-NEXT:   Section: .text
+;CHECKSYM-NEXT:   Type: 0x0
+;CHECKSYM-NEXT:   StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT:   NumberOfAuxEntries: 1
+;CHECKSYM-NEXT:   CSECT Auxiliary Entry {
+;CHECKSYM-NEXT:     Index: [[#Index+1]] 
+;CHECKSYM-NEXT:     SectionLen: 16
+;CHECKSYM-NEXT:     ParameterHashIndex: 0x0
+;CHECKSYM-NEXT:     TypeChkSectNum: 0x0
+;CHECKSYM-NEXT:     SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT:     SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT:     StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT:     StabInfoIndex: 0x0
+;CHECKSYM-NEXT:     StabSectNum: 0x0
+;CHECKSYM-NEXT:        }
+;CHECKSYM-NEXT:  }
+
+;CHECKSYM:        Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst8
+;CHECKSYM-NEXT:   Value (RelocatableAddress): 0x40
+;CHECKSYM-NEXT:   Section: .text
+;CHECKSYM-NEXT:   Type: 0x0
+;CHECKSYM-NEXT:   StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT:   NumberOfAuxEntries: 1
+;CHECKSYM-NEXT:   CSECT Auxiliary Entry {
+;CHECKSYM-NEXT:     Index: [[#Index+1]] 
+;CHECKSYM-NEXT:     SectionLen: 8
+;CHECKSYM-NEXT:     ParameterHashIndex: 0x0
+;CHECKSYM-NEXT:     TypeChkSectNum: 0x0
+;CHECKSYM-NEXT:     SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT:     SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT:     StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT:     StabInfoIndex: 0x0
+;CHECKSYM-NEXT:     StabSectNum: 0x0
+;CHECKSYM-NEXT:        }
+;CHECKSYM-NEXT:  }
+  
+;CHECKSYM:        Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: L..__const.main.cnst4
+;CHECKSYM-NEXT:   Value (RelocatableAddress): 0x48
+;CHECKSYM-NEXT:   Section: .text
+;CHECKSYM-NEXT:   Type: 0x0
+;CHECKSYM-NEXT:   StorageClass: C_HIDEXT (0x6B)
+;CHECKSYM-NEXT:   NumberOfAuxEntries: 1
+;CHECKSYM-NEXT:   CSECT Auxiliary Entry {
+;CHECKSYM-NEXT:     Index: [[#Index+1]] 
+;CHECKSYM-NEXT:     SectionLen: 4
+;CHECKSYM-NEXT:     ParameterHashIndex: 0x0
+;CHECKSYM-NEXT:     TypeChkSectNum: 0x0
+;CHECKSYM-NEXT:     SymbolAlignmentLog2: 3
+;CHECKSYM-NEXT:     SymbolType: XTY_SD (0x1)
+;CHECKSYM-NEXT:     StorageMappingClass: XMC_RO (0x1)
+;CHECKSYM-NEXT:     StabInfoIndex: 0x0
+;CHECKSYM-NEXT:     StabSectNum: 0x0
+;CHECKSYM-NEXT:        }
+;CHECKSYM-NEXT:  }

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 ; This file tests the codegen of mergeable strings in AIX assembly only.
 ; Once the codegen of mergeable strings for XCOFF object files is supported
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
-; RUN:     -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 \
-; RUN:     -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
-
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol \
+; RUN:     -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol \
+; RUN:     -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff \ 
+; RUN:     -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
 @magic32 =  private unnamed_addr constant [4 x i32] [i32 464, i32 472, i32 413, i32 0], align 4
 @strA = private unnamed_addr constant [14 x i8] c"hello world!\0A\00", align 1
 @.str = private unnamed_addr constant [9 x i8] c"abcdefgh\00", align 1
 @p = global i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), align 4
 
 ; Function Attrs: noinline nounwind optnone
 define i8 @foo() #0 {
 entry:
   %0 = load i8*, i8** @p, align 4
   %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
-; CHECK:   .csect .rodata.str2.2[RO],2
-; CHECK-NEXT:   .align  1
-; CHECK-NEXT: L..magic16:
-; CHECK-NEXT:   .vbyte  2, 264                     # 0x108
-; CHECK-NEXT:   .vbyte  2, 272                     # 0x110
-; CHECK-NEXT:   .vbyte  2, 213                     # 0xd5
-; CHECK-NEXT:   .vbyte  2, 0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str4.4[RO],2
-; CHECK-NEXT:   .align  2
-; CHECK-NEXT: L..magic32:
-; CHECK-NEXT:   .vbyte  4, 464                     # 0x1d0
-; CHECK-NEXT:   .vbyte  4, 472                     # 0x1d8
-; CHECK-NEXT:   .vbyte  4, 413                     # 0x19d
-; CHECK-NEXT:   .vbyte  4, 0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str1.1[RO],2
-; CHECK-NEXT: L..strA:
-; CHECK-NEXT: .byte   'h,'e,'l,'l,'o,' ,'w,'o,'r,'l,'d,'!,0012,0000
-; CHECK-NEXT: L...str:
-; CHECK-NEXT: .byte   'a,'b,'c,'d,'e,'f,'g,'h,0000
+; CHECK:  .csect .rodata.str2.2L..magic16[RO],2
+; CHECK-NEXT:   .align  1
+; CHECK-NEXT:   .vbyte  2, 264                          # 0x108
+; CHECK-NEXT:   .vbyte  2, 272                          # 0x110
+; CHECK-NEXT:   .vbyte  2, 213                          # 0xd5
+; CHECK-NEXT:   .vbyte  2, 0                            # 0x0
+; CHECK-NEXT:   .csect .rodata.str4.4L..magic32[RO],2
+; CHECK-NEXT:   .align  2
+; CHECK-NEXT:   .vbyte  4, 464                          # 0x1d0
+; CHECK-NEXT:   .vbyte  4, 472                          # 0x1d8
+; CHECK-NEXT:   .vbyte  4, 413                          # 0x19d
+; CHECK-NEXT:   .vbyte  4, 0                            # 0x0
+; CHECK-NEXT:   .csect .rodata.str1.1L..strA[RO],2
+; CHECK-NEXT:   .byte 'h,'e,'l,'l,'o,' ,'w,'o,'r,'l,'d,'!,0012,0000
+; CHECK-NEXT:   .csect .rodata.str1.1L...str[RO],2
+; CHECK-NEXT:   .byte 'a,'b,'c,'d,'e,'f,'g,'h,0000
 
 ; CHECKOBJ:     00000010 <.rodata.str2.2>:
 ; CHECKOBJ-NEXT:       10: 01 08 01 10
 ; CHECKOBJ-NEXT:       14: 00 d5 00 00    {{.*}}{{[[:space:]] *}}
 ; CHECKOBJ-NEXT: 00000018 <.rodata.str4.4>:
 ; CHECKOBJ-NEXT:       18: 00 00 01 d0
 ; CHECKOBJ-NEXT:       1c: 00 00 01 d8
 ; CHECKOBJ-NEXT:       20: 00 00 01 9d
 ; CHECKOBJ-NEXT:       24: 00 00 00 00    {{.*}}{{[[:space:]] *}}
 ; CHECKOBJ-NEXT: 00000028 <.rodata.str1.1>:
 ; CHECKOBJ-NEXT:       28: 68 65 6c 6c
 ; CHECKOBJ-NEXT:       2c: 6f 20 77 6f
 ; CHECKOBJ-NEXT:       30: 72 6c 64 21
 ; CHECKOBJ-NEXT:       34: 0a 00 61 62
 ; CHECKOBJ-NEXT:       38: 63 64 65 66
 ; CHECKOBJ-NEXT:       3c: 67 68 00 00

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -filetype=obj -code-model=large -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @a = global i32 2, align 4
 @b = global i32 10, align 4
 @c = global i32 11, align 4
 

llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
 
 define i32 @foo() #0 {
 entry:
   ret i32 0
 }
 
 define i32 @foo1() #0 {

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

 ; This file tests TOC entry generation and undefined symbol generation.
 
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 
-; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -vecnvol -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
 ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = external global i32, align 4
 @b = external global i64, align 8
 @c = external global i16, align 2
 @globa = common global i32 0, align 4
 

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK
 
 ---
 name:            CRMultiSave
 alignment:       16
 tracksRegLiveness: true
 liveins:

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
 
 define i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0

llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
 
 @a = common global i32 0
 
 define zeroext i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0

llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll

-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -vecnvol \
 ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
 ; generated. And this testcase verifies that the operand expansion of `setcc`
 ; will not crash.

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
 # RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -vecnvol \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 ---
 name:            CRAllSave
 alignment:       16
 tracksRegLiveness: true
 liveins: