- User Since
- Dec 11 2018, 9:51 AM (102 w, 6 d)
Fri, Nov 27
Thu, Nov 26
Updated regex in test cases to check register correct usage.
Wed, Nov 25
Added regex and variable for function attribute
Removed passing vector parameters to the stack portion of patch, fixed test case and added test cases for errors.
Removed vector long error
Tue, Nov 24
Seems a few test cases require mattr=-altivec to pass with this patch.
Simplified option logic as per suggestion.
Removed stray isXCOFF reference.
Went back to old option selection logic as updated version did not emit an error when selecting 'maltivec` but not mabi=vec-extabi.
Mon, Nov 23
Addressed some of the comments.
Fri, Nov 20
Addressed comments and added a test to check whether the driver passes these options.
Thu, Nov 19
Fixed failing test cases.
Rebase and remove regmask altivec change.
Added and fixed test cases and changed option selection logic.
Wed, Nov 18
Fri, Nov 13
Rebase to reflect changes in parent revisions.
Rebased and addressed comments.
Oct 19 2020
Addressed comments and adding parent revisions.
Fixed typo in test case.
Separated the option portion of the previous diff (now found here: https://reviews.llvm.org/D89684).
Addressed other comments.
Oct 16 2020
Oct 15 2020
Rebased based on new changes in https://reviews.llvm.org/D88676.
Added error for vector long type.
Added mvecnvol/mnovecnvol options in clang and vecnvol option in llc
Addressed other comments related to formatting and test case regex usage.
Updated test cases that fail when vecnvol is enabled.
Oct 7 2020
Oct 6 2020
Added test case that includes FP and GP csrs along with the vector crs.
Reduced the number of clobbered VRs in the initial test case.
Oct 5 2020
This patch now only contains the ISel lowering portion of the previous version. Additionally, lowering on the callee side was implemented since with the work already contained in CC_AIX only the removal of the error in LowerCall_AIX() was required. Return vector types was also enabled. The test case checks the caller, callee and return assembly instructions.
Oct 1 2020
Sep 30 2020
Code changes didn't get included in last diff.
Used REG variables in 64Bit part of test case.
Sep 29 2020
Sep 28 2020
Sep 25 2020
Fixed register usage.
Sep 24 2020
Generated test case using update_llc_test_checks.py, added stores and used DAG instead of NEXT when appropriate.
Going to work on rebasing this patch.
Sep 23 2020
Thanks for doing the formatting changes.
Updated test case.
Sep 22 2020
Sep 21 2020
Moved !Subtarget.isPPC64() check earlier alongside other checks.
Sep 10 2020
Sep 2 2020
Aug 31 2020
Looks good with minor nit.
Aug 24 2020
Aug 14 2020
Jul 20 2020
LGTM but I will leave it up for a bit so other reviewers have a chance to look at it.
Jun 26 2020
I think this one is good. I wonder if there should be more tests to check corrected alignment of various allocations but that seems out of scope for the patch and the tests in https://reviews.llvm.org/D72454 covered that anyway.
Jun 25 2020
Jun 24 2020
Added High/Low Memory labels to diagram.
Addressed Sean's comments: