[PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[ZarkoCA]

Summary

This patch is the initial patch for support of the AIX extended vector ABI. The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

Minor nit: align this with the first argument in the preceeding line.

4

I'm not sure the formatting we have adopted for the tests, but I think subsequent commands were to be indented by 2? @Xiangling_L or @DiggerLin might know better, I think it was on one of their reviews where I saw it mentioned.

20

A couple minor suggestions

1. Use only 2 or 3 callee saved vector registers as clobbers. It will show how we allocate stack space to store all vector registers from N to 31 where N is the lowest used csr vr, and make the test a bit more concise.
2. Have V12 as a clobber to show that it is not callee saved.

[sfertile]

More test coverage for this patch:

1. We should test spill/restore code when we have gpr/fpr/vr callee-saves all in the same function.
2. Extend at least one of the frame-pointer and base pointer tests to have a vector callee-saved clobbered.

See inline-asm-vsx-clobbers.ll. We should have a test which uses vsx registers to clobber fprs and vector registers and makes sure we allocate the right stack size, emit the right spills/restores. I think it should be a separate patch though as its testing the inline-asm implementation more, where the other test use inline-asm to test the frame-lowering. I can prepare this patch if you like.

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

20

Ignore number 2. you already have that with v13, I should have paid more attention :(.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

The ABI mentioned AIX5.3 is the first AIX release to enable vector programming, and there are arch like pwr4 is not compatible with altivec. Since this is our first altivec patch, it looks it's the right place to add report_fatal_error for arch level which doesn't support altivec.

4

The original formatting comment is here: https://reviews.llvm.org/D78929#inline-740137

223

Could you also add a testcase showing how csr FPR/GPR interact with nonvolatile VR?

[ZarkoCA]

Added test case that includes FP and GP csrs along with the vector crs.
Reduced the number of clobbered VRs in the initial test case.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

While I think that's a good suggestion, none of the other PPC targets do anything similar. If you choose an arch that doesn't support altivec while selecting a CPU that doesn't support it they quietly don't generate the altivec instructions.

Also, as things are, we do have a report fatal error when ever someone tries using vector types in the front end and in the back end.

4

Thanks for info, I updated the RUN steps.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I see. The only reason why I raise it up is because XL gives an error when using altivec with unsupported arch.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I see a warning and xlc and xlclang:
1506-1162 (W) The altivec option is not supported for the target architecture and is ignored.
Additionally with xlclang we get from the altivec.h header included in xlclang if an unsupported arch is specified.

But this has me thinking that it is a good idea to follow through with your suggestion of an error.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

Since the extended ABI vector-enabled mode is not the safe default (certain call sequences involving functions compiled using the default ABI can bypass restoration of the non-volatile register values), we should report_fatal_error unless if the extended ABI is explicitly enabled.

Example:

[ uses non-volatile vector registers ]
vv   calls
[ not vector-extended ABI-aware ] -- calls setjmp
vv   calls
[ uses non-volatile vector registers ]
vv   calls
[ not vector-extended ABI-aware ] -- calls longjmp

This follows the precedent for the llc default for data sections: Even for llc, we do not enable the "unsafe" mode by default.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

54

minor nit: trailing space on line 54, 55, 57, 58, 60

81

Can we line up all comments?

81

I am suggesting to use things like [[REG1:[0-9]+]] to match registers, use {{[0-9]+}} to match numerical values if we need to. The same comments apply to all testcases.

120

Thank you for adding this testcase. I think it would be better if we also test`r13`/x14, f14, v20, then we can observe the padding added in.

[sfertile]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

221

Should we reformat this even though its ugly to avoid it cluttering other reviews that touch this file? Maybe if we delete the comment we will end up with a format that matches the 64-bit array more closely :shrug:

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

40

STXVD2X killed $v20, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)

Using $r{{[0-9]+}} for the second register in the r+r addressing is fine, but don't use a regex for r1/x1, its wothwhile to show that the addressing is based off he stack pointer.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

4

The comments here let me think should we also implement an equivalent option for llc to control which ABI to be enabled in addition to the frontend or driver option?

[ZarkoCA]

Added mvecnvol/mnovecnvol options in clang and vecnvol option in llc
Addressed other comments related to formatting and test case regex usage.
Updated test cases that fail when vecnvol is enabled.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

I added the options to toggle between the two Altivec ABIs.

4

Yes, good point, I added that as well.

81

I'd rather not use any variables unless we need to use them later.

120

Good suggestion, I added.

[Xiangling_L]

I am wondering can we split the option related changes to a separate patch for reviews? That would make current patch a bit easier to review and faster to be committed as two small pieces.

If it's possible, I am thinking we can try to split it up to the following two pieces:

1. Add option in the frontend and backend to be able to turn on extended vector ABI
2. Do the frame lowing in the backend

clang/docs/ClangCommandLineReference.rst

2868 ↗

(On Diff #298409)

1. I am not sure if it's a good idea to put the supporting status also in the option description here. It looks a bit strange to me.

2. I would suggest something similar like this for the option description:

Only supported on AIX. Specifies whether to use both volatile and nonvolatile vector registers or volatile vector registers only. Defaults to `-mnovecnvol` when Altivec is enabled.

3. We missed a - before mnovecnvol.

clang/include/clang/Basic/DiagnosticDriverKinds.td

531 ↗

(On Diff #298409)

I would suggest:

The default Altivec ABI on AIX is not yet supported, use '-mvecnvol' for the extended Altivec ABI

clang/test/CodeGen/altivec.c

1 ↗

(On Diff #298409)

Can we also test how the driver react to these two options? It would serve as the LIT coverage for the code change in clang/lib/Driver/ToolChains/Clang.cpp.

llvm/include/llvm/Target/TargetOptions.h

177 ↗

(On Diff #298409)

Can we also use bitfield to indicate true and false here? The default value set to be false in ctor already, so we don't need assign 0 to it here.

unsigned AIXExtendedAltivecABI : 1;

[ZarkoCA]

Separated the option portion of the previous diff (now found here: https://reviews.llvm.org/D89684).
Addressed other comments.

[ZarkoCA]

Fixed typo in test case.

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

184

I suggest doing the error checking once before getting into the 32-bit/64-bit blocks.

[ZarkoCA]

Rebased and addressed comments.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

184

Thanks, good suggestion, I moved it up right at the beginning of the function.

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

214

CSR_64_AllRegs_Altivec_RegMask should be CSR_PPC64_Altivec_RegMask. FWIW I don't think this is testable without D86476. If that's the case, then it should go in that patch, not this patch.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

214

Are you suggesting that I also leave the error in if I were to move this change to D84676?

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

214

Can you still run the tests that are part of this commit with that error in? My understanding was that it didn't interfere, but I didn't verify that. If we can still run the tests then yes leave the error in. If we can't then it probably gives us a clue about how to test the change in this patch without needing D84676, in which case we can keep the change and simply add the testing that exercises it.

[ZarkoCA]

Rebase and remove regmask altivec change.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

214

No, you were right those changes can't be tested. Just needed some clarification, thanks.

[ZarkoCA]

Fixed failing test cases.

[sfertile]

LGTM.

[ZarkoCA]

Seems a few test cases require mattr=-altivec to pass with this patch.

llvm/lib/Target/PowerPC/PPCCallingConv.td

 
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
                                      F19, F20, F21, F22, F23, F24, F25, F26,
                                      F27, F28, F29, F30, F31, CR2, CR3, CR4
                                 )>;
 
+def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;
+
 // Common CalleeSavedRegs for SVR4 and AIX.
 def CSR_PPC64   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
                                         X21, X22, X23, X24, X25, X26, X27, X28,
                                         X29, X30, X31, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
                                    )>;
 

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

static const SpillSlot ELFOffsets64[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS64,
 
       // VRSAVE save area offset.
       {PPC::VRSAVE, -4},
       CALLEE_SAVED_VRS
   };
 
   static const SpillSlot AIXOffsets32[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS32,
       // Add AIX's extra CSR.
       {PPC::R13, -76},
-      // TODO: Update when we add vector support for AIX.
+      CALLEE_SAVED_VRS
   };
 
   static const SpillSlot AIXOffsets64[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS64,
-      // TODO: Update when we add vector support for AIX.
+      CALLEE_SAVED_VRS
   };
 
   if (Subtarget.is64BitELFABI()) {
     NumEntries = array_lengthof(ELFOffsets64);
     return ELFOffsets64;
   }
 
   if (Subtarget.is32BitELFABI()) {

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
     if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
     if (Subtarget.hasAltivec())
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                     : CSR_PPC64_Altivec_SaveList;
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI())
-    return CSR_AIX32_SaveList;
+    return (Subtarget.hasAltivec()) ? CSR_AIX32_Altivec_SaveList
+                                    : CSR_AIX32_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
   else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
 
 const uint32_t *
 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
-    assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
-    return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+    return TM.isPPC64()
+               ? (Subtarget.hasAltivec() ? CSR_64_AllRegs_Altivec_RegMask
+                                         : CSR_PPC64_RegMask)
+               : (Subtarget.hasAltivec() ? CSR_AIX32_Altivec_RegMask
+                                         : CSR_AIX32_RegMask);
   }
 
   if (CC == CallingConv::Cold) {
     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
                                                   : CSR_SVR64_ColdCC_RegMask)
                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
                                                   : (Subtarget.hasSPE()
                                                   ? CSR_SVR32_ColdCC_SPE_RegMask

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM64 %s
+
+
+define dso_local void @vec_regs() {
+entry:
+  call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            vec_regs
+
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $v20, $v26, $v31
+
+; MIR32-DAG:     STXVD2X killed $v20, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR32-DAG:     STXVD2X killed $v26, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     STXVD2X killed $v31, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $v20 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR32-DAG:     $v26 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $v31 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32:         BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            vec_regs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default, 
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', 
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default, 
+; MIR64-NEXT:        callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', 
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default, 
+; MIR64-NEXT:        callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', 
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $v20, $v26, $v31
+
+; MIR64-DAG:     STXVD2X killed $v20, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2)
+; MIR64-DAG:     STXVD2X killed $v26, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     STXVD2X killed $v31, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $v20 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2)
+; MIR64-DAG:     $v26 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $v31 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64:         BLR8 implicit $lr8, implicit $rm
+
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32:         li {{[0-9]+}}, -192
+; ASM32-DAG:     stxvd2x 52, 1, {{[0-9]+}}                       # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     stxvd2x 58, 1, {{[0-9]+}}                       # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, -16
+; ASM32-DAG:     stxvd2x 63, 1, {{[0-9]+}}                       # 16-byte Folded Spill
+; ASM32:         #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -96
+; ASM32-DAG:     lxvd2x 58, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, -192
+; ASM32-DAG:     lxvd2x 52, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM32:         blr
+
+; ASM64-LABEL:   .vec_regs:
+
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     stxvd2x 52, 1, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     stxvd2x 58, 1, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, -16
+; ASM64-DAG:     stxvd2x 6{{[0-9]+}}, 1, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x 6{{[0-9]+}}, 1, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -96
+; ASM64-DAG:     lxvd2x 58, 1, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, -192
+; ASM64-DAG:     lxvd2x 52, 1, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64-DAG:     blr
+
+define dso_local void @fprs_gprs_vecregs() {
+  call void asm sideeffect "", "~{r25},~{r31},~{f21},~{f31},~{v21},~{v31}"()
+  ret void
+}
+
+; MIR32:         name:            fprs_gprs_vecregs
+; MIR32-LABEL:   fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -144, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$v21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 3, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 4, type: spill-slot, offset: -92, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 5, type: spill-slot, offset: -116, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    stack:
+
+; MIR32:         liveins: $r25, $r31, $f21, $f31, $v21, $v31
+
+; MIR32-DAG:     STFD killed $f31, 328, $r{{[0-9]+}} :: (store 8 into %fixed-stack.2)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     STXVD2X killed $v21, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 192
+; MIR32-DAG:     STXVD2X killed $v31, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR32:         INLINEASM
+
+; MIR32-DAG:     $r{{[0-9]+}} = LI 192
+; MIR32-DAG:     $v31 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR32-DAG:     $r{{[0-9]+}} = LI 32
+; MIR32-DAG:     $v21 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR32-DAG:     $f31 = LFD 328, $r{{[0-9]+}} :: (load 8 from %fixed-stack.2)
+; MIR32-DAG:     $f21 = LFD 248, $r{{[0-9]+}} :: (load 8 from %fixed-stack.3)
+; MIR32-DAG:     $r{{[0-9]+}}1 = LWZ 244, $r{{[0-9]+}} :: (load 4 from %fixed-stack.4)
+; MIR32-DAG:     $r25 = LWZ 220, $r{{[0-9]+}} :: (load 4 from %fixed-stack.5)
+; MIR32-DAG:     $r1 = ADDI $r1, 336
+; MIR32-DAG:     BLR implicit $lr, implicit $rm
+
+; MIR64:         name:            fprs_gprs_vecregs
+
+; MIR64-LABEL:   fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -160, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$v21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 3, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 4, type: spill-slot, offset: -96, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    stack:
+
+; MIR64:         liveins: $x25, $x31, $f21, $f31, $v21, $v31
+
+; MIR64-DAG:     $x1 = STDU $x1, -384, $x1
+; MIR64-DAG:     STD killed $x25, 240, $x{{[0-9]+}}  :: (store 8 into %fixed-stack.5)
+; MIR64-DAG:     STD killed $x31, 288, $x{{[0-9]+}}  :: (store 8 into %fixed-stack.4)
+; MIR64-DAG:     STFD killed $f21, 296, $x{{[0-9]+}}  :: (store 8 into %fixed-stack.3)
+; MIR64-DAG:     STFD killed $f31, 376, $x{{[0-9]+}}  :: (store 8 into %fixed-stack.2)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     STXVD2X killed $v21, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 224
+; MIR64-DAG:     STXVD2X killed $v31, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0)
+
+; MIR64:         INLINEASM
+
+; MIR64-DAG:     $x3 = LI8 224
+; MIR64-DAG:     $v31 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0)
+; MIR64-DAG:     $x{{[0-9]+}} = LI8 64
+; MIR64-DAG:     $v21 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1)
+; MIR64-DAG:     $f31 = LFD 376, $x{{[0-9]+}} :: (load 8 from %fixed-stack.2)
+; MIR64-DAG:     $f21 = LFD 296, $x{{[0-9]+}} :: (load 8 from %fixed-stack.3)
+; MIR64-DAG:     $x31 = LD 288, $x{{[0-9]+}} :: (load 8 from %fixed-stack.4)
+; MIR64-DAG:     $x25 = LD 240, $x{{[0-9]+}} :: (load 8 from %fixed-stack.5)
+; MIR64-DAG:     $x1 = ADDI8 $x1, 384
+; MIR64-DAG:     BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL:   .fprs_gprs_vecregs:
+
+; ASM32-DAG:     stwu 1, -336(1)
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     stw 25, 220(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 21, 248(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 53, {{[0-9]+}}, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM32-DAG:     li {{[0-9]+}}, 192
+; ASM32-DAG:     stw 31, 244(1)                          # 4-byte Folded Spill
+; ASM32-DAG:     stfd 31, 328(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stxvd2x 63, {{[0-9]+}}, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM32-DAG:     #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lxvd2x 63, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM32-DAG:     li {{[0-9]+}}, 32
+; ASM32-DAG:     lfd 31, 328(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lxvd2x 53, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM32-DAG:     lfd 21, 248(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lwz 31, 244(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     lwz 25, 220(1)                          # 4-byte Folded Reload
+; ASM32-DAG:     addi 1, 1, 336
+; ASM32-DAG:     blr
+
+; ASM64-LABEL:   .fprs_gprs_vecregs:
+
+; ASM64-DAG:     stdu 1, -384(1)
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     std 25, 240(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 21, 296(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 53, 1, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM64-DAG:     li {{[0-9]+}}, 224
+; ASM64-DAG:     std 31, 288(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     stfd 31, 376(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stxvd2x 63, 1, {{[0-9]+}}                        # 16-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lxvd2x 63, 1, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64-DAG:     li {{[0-9]+}}, 64
+; ASM64-DAG:     lfd 31, {{[0-9]+}}76(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lxvd2x 53, 1, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64-DAG:     lfd 21, 296(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     ld 31, 288(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     ld 25, 240(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     addi 1, 1, 384
+; ASM64-DAG:     blr