[AIX][XCOFF]emit extern linkage for the llvm intrinsic symbol

[DiggerLin]

Summary

1. when we call memset, memcopy,memmove etc(this are llvm intrinsic function) in the c source code. the llvm will generate IR

like call call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.S* @s to i8*), i8 %1, i32 %2, i1 false)
for c source code
bash> cat test_memset.call

struct S{
 int a;
 int b;
};
extern struct  S s;
void bar() {
  memset(&s, s.b, s.b);
}

like

%struct.S = type { i32, i32 }
@s = external global %struct.S, align 4
; Function Attrs: noinline nounwind optnone
define void @bar() #0 {
entry:
  %0 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
  %1 = trunc i32 %0 to i8
  %2 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
  call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.S* @s to i8*), i8 %1, i32 %2, i1 false)
  ret void
}
declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) #1

If we want to let the aix as assembly compile pass without -u
it need to has following assembly code.
.extern .memset
(we do not output extern linkage for llvm instrinsic function.
even if we output the extern linkage for llvm intrinsic function, we should not out .extern llvm.memset.p0i8.i32,
instead of we should emit .extern memset)

2. for other llvm buildin function floatdidf . even if we do not call these function floatdidf in the c source code(the generated IR also do not the call __floatdidf . the function call

was generated in the LLVM optimized.
the function is not in the functions list of Module, but we still need to emit extern .__floatdidf

The solution for it as :
We record all the lllvm intrinsic extern symbol when transformCallee(), and emit all these symbol in the AsmPrinter::doFinalization(Module &M)

[jasonliu]

llvm/include/llvm/MC/MCContext.h

105 ↗

(On Diff #260321)

Just a general comment on the data structure that's using here.
Have we thought about using using a SmallPtrSet so that you don't need to worry about inserting the duplicated value into the vector?

423 ↗

(On Diff #260321)

Is it necessary to have wrappers to the real data structure?
I feel like returning the actual data structure here is not that bad. And user of this data structure have much more freedom using something like range-based for loop, instead of the iterator interface.

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

20

nit: remove this Attr.

[DiggerLin]

llvm/include/llvm/MC/MCContext.h

105 ↗

(On Diff #260321)

/ SmallPtrSet - This class implements a set which is optimized for holding
/ SmallSize or less elements. This internally rounds up SmallSize to the next
/ power of two if it is not already a power of two. See the comments above
/ SmallPtrSetImplBase for details of the algorithm.
template<class PtrType, unsigned SmallSize>
class SmallPtrSet : public SmallPtrSetImpl<PtrType> {

// In small mode SmallPtrSet uses linear search for the elements, so it is
// not a good idea to choose this value too high. You may consider using a
// DenseSet<> instead if you expect many elements in the set.
static_assert(SmallSize <= 32, "SmallSize should be small");

There are hundreds llvm intrinsic function. I will use std::set

[DiggerLin]

address comment

[jasonliu]

llvm/include/llvm/MC/MCContext.h

105 ↗

(On Diff #260321)

There are hundreds of llvm intrinsic functions. But are you expecting every compilation will contain hundreds of llvm intrinsic functions? I would say most of the time, you would see those less than 8intrinsic functions in one compilation unit , except for some very heavy mathematic case.

[jasonliu]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1534 ↗

(On Diff #260740)

Ranged based for loop?

[hubert.reinterpretcast]

llvm/include/llvm/MC/MCContext.h

105 ↗

(On Diff #260321)

I agree with @jasonliu, and even if SmallPtrSet is too small, why not use DenseSet like the comments say?

[DiggerLin]

address comment

llvm/include/llvm/MC/MCContext.h

105 ↗

(On Diff #260321)

I think we can not guarantee the llvm intrinsic sysbols in a compilation unit is less than 32. I will use DenseSet.

[DiggerLin]

using SmallPtrSet as comment

[sfertile]

Have you considered not transforming ExternalSymbolSDNodes, but instead supporting them for AIX and then creating the symbol and emitting the linkage for the ExternalSymbol machine operand in the ASMPrinter? The approach this patch takes adds complexity to a target independent part of the MC infrastructure. The amount of complexity it adds is not unreasonable, but I think if we can contain the complexity to the PowerPC backend its worth considering strongly even if the implementation there is more difficult.

[DiggerLin]

upload wrong diff . discard previous diff

[jhenderson]

llvm/include/llvm/MC/MCContext.h

104 ↗

(On Diff #260934)

Nit: symbol's -> symbols' (or if you don't like that, try "the linkage of these symbols.")

I would write emiting as emitting, but I don't know if that's a British versus American English thing.

Here and in other comments, should "llvm" be "LLVM"?

[DiggerLin]

store llvm intrinsic symbols in the PPCAIXAsmPrinter

[jhenderson]

Please reupload the latest patch with context.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

152

Should it be spelt XCOFF?

1756

Don't use auto here. Also, should this really be a copy and not a const reference?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5284

Should this be const MCSymbolXCOFF *Sym?

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

3

Please don't break the lines up like this. I'd put -mattr=altivec on the same line as the rest of the llc line, but if you do want to break it onto a new line, split it roughly halfway through the arguments, and indent the second line, then put the FileCheck line on a new line. Same goes below.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1756

it store the a pointer of MCSymbol in the IntrinsicSymbols. I think return a copy of pointer is same efficient as const reference.

and the

bool MCXCOFFStreamer::emitSymbolAttribute(MCSymbol *Sym,
                                          MCSymbolAttr Attribute)

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5284

thanks

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

3

thanks

[DiggerLin]

address comment

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5384

If there exists a user-declared function whose name is the same as the
ExternalSymbol's, then we pick up the user-declared version.

How do we handle this scenario under the new logic? Are we still able to pick up the user-declared version without generating .extern for that function?

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5384

Please consider the case in llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1756

One issue with auto here is that it's not obvious that we have a pointer type (and even knowing how Sym is used does not rule out the possibility that it is merely convertible to the pointer type). Using auto * might not have caused the comment to be raised, but since the comment has been raised, please get rid of the auto.

[DiggerLin]

address comment

[jhenderson]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1756

By the way, there's a related style guide section on usage of auto: https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

3

One more related request: Indent the FileCheck directive by an extra two spaces to make it obvious it's a continuation of the previous line:

; RUN: llc ... | \
; RUN:   FileCheck ...

Same below.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1756

thanks for the information.

[jasonliu]

It's a bit awkward to use the emitInstruction function to record the special functions, as it is actually not doing anything related to "emit instruction".
But I'm not sure if there is any better way to do it if we want to hide the logic in PPCAsmPrinter instead of exposing it in target independent MCContext.
I will see what other people think.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5397

Could we have a lambda function to return a MCSymbolXCOFF with the correct name for it? Then replace the similar logic in getAIXFuncEntryPointSymbolSDNode with this lambda function call as well.
We should limit the places to do the "." + func_name dance.

[sfertile]

👍 Thanks for trying this out Digger, I think this approach is the right one to take. I've had an initial look and left a few comments inline. I'll need to spend some time understanding ExternalSymbolSDNodes a bit better before being able to review the patch thoroughly enough to approve.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

152

IIUC this isn't directly related to intrinsics, but to ExternalSymbolSD nodes, with the lowering of intrinsics being just one of the ways we can end up with an ExternalSymbolSDNodes. Intrinsic lowering might be the only way we expect to get one of these nodes on AIX right now but that can change in the future. The naming and comments need to reflect that this is explicitly for handling emitting the linkage of ExternalSymbolSDNodes.

1792

Choosing to implement this override and handle here instead of adding to the base classes emitInstruction makes this really nice and clean. Good job.

1799

What is the state of tail-calls on AIX? I know we can't tail call in many of the situations where we can on Linux, however if they aren't completely disabled we might need to add the tail-call opcodes here for similar transformation.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5385

I'm not too familiar with when we get ExternalSymbolSDNodes or what the semantic should be if we have an ExternalSymbolSDNode and a IR declaration for the same function, but it seems odd to treat the situation differently based on XCOFF vs ELF. @Xiangling_L Was aix-user-defined-memcpy.ll motivated by real code? If so I'd like to investigate it a bit more.

5396

Why not leave the name as is, and prepend the '.' when we create/lookup the symbol in the AsmPrinter?

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5385

It seems for real C code. If there is a user-provided memset/memcpy, clang would transform the call to that user-provided memset/memcpy instead of generating llvm.memset/memcpy intrinsic.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5396

if leave name as is, the branch will be
bl memset
not
bl .memset

if leave name as is , we want to generate bl .memset . we need to modify the operand(ExternalSymbol) of branch to generate correct bl .memset

[DiggerLin]

address comment

[sfertile]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

152

Sorry I wasn't more explicit in my previous comment. I don't think we should be using the name 'intrinsic' here at all.

/// Symbols lowered from ExternalSymbolSDNodes.
SmallPtrSet<MCSymbol *, 8> ExternalSymbols;

1800

We haven't implemented TLS on AIX yet, and I'm not sure which if any of these call pseudos will be used. How about adding them as a separate case with a report_fatal_error which can be revisited as part of TLS implementation on AIX.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5366

I'm don't think this is what Jason meant from his comment.

5396

Yes, which is why I said you would move where you prepend the '.' from here, to where you create the MCSymbol from the MO_ExternalSymbol in the ASM printer.

I think our handling of when there is deceleration in the IR matching the ExtrernalSymbol name is wrong, and it should either be done for all subtargets, or none (but I'm not 100% sure of that yet and investigating). If they are to be common-ed, then by moving modifying the symbols name too the ASMprinter, it lets us have identical code for all subtargets for transforming ExternalSymbolSDNode callees.

I'd say hold off on making this change until we better understand the IR Decl/ExternalSym situation though.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

152

thanks

1800

I will delete the TLS related opcode.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5366

thanks.

5396

Discussed with Sean offline, I will keep the implement.

[DiggerLin]

address comment

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5396

Expanding a bit: I though we could create the MCSymbol in PPCAIXAsmPrinter::emitInstruction and then create a new MCSymbol MachineOperand and change the operand to that. Digger explained how I was mistaken and we can not change the operand on the MachineInstr, so we have to stick with this approach.

[sfertile]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

153

Not all intrinsics get handled this way, and not all of these symbols necessarily come from lowering an intrinsic: so we shouldn't be using 'Intrinsic' in the naming. I suggested 'ExternalSymbols' above but that sprobably too generic.

1799

You have added PPC::TAILB so I am assuming that means we do support tail-calls on AIX. Why do we not need to add any of the other tail call pseudos. At the very least i would expect we need PPC::TAILB8 for 64-bit support if we expect TAILB for 32-bit. What about TAILBA[8] or TAILBCTR[8]?

[Xiangling_L]

Can you also please update the testcase aix-user-defined-memcpy.ll to include:
CHECK-NOT: .extern .memcpy

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5385

Just as a record. As we discussed offline, a real C code is like:

int memcpy ( void * destination, int num ) { return 3; }
typedef struct cpy_array {
  int array[20];
} cpy;
int main() {
  cpy A = {1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15,16};
  cpy B = A;
  return B.array[0];
}

And Clang FE will generate the following IR for AIX:

; Function Attrs: noinline nounwind optnone
define i32 @memcpy(i8* %destination, i32 %num) #0 {
entry:
  %destination.addr = alloca i8*, align 4
  %num.addr = alloca i32, align 4
  store i8* %destination, i8** %destination.addr, align 4
  store i32 %num, i32* %num.addr, align 4
  ret i32 3
}
; Function Attrs: noinline nounwind optnone
define i32 @main() #0 {
entry:
  %retval = alloca i32, align 4
  %A = alloca %struct.cpy_array, align 4
  %B = alloca %struct.cpy_array, align 4
  store i32 0, i32* %retval, align 4
  %0 = bitcast %struct.cpy_array* %A to i8*
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 bitcast (%struct.cpy_array* @__const.main.A to i8*), i32 80, i1 false)
  %1 = bitcast %struct.cpy_array* %B to i8*
  %2 = bitcast %struct.cpy_array* %A to i8*
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %2, i32 80, i1 false)
  %array = getelementptr inbounds %struct.cpy_array, %struct.cpy_array* %B, i32 0, i32 0
  %arrayidx = getelementptr inbounds [20 x i32], [20 x i32]* %array, i32 0, i32 0
  %3 = load i32, i32* %arrayidx, align 4
  ret i32 %3
}

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

91

Though unrelated to this patch, I am wondering if we can replace & to something more meaningful like extsym etc. like what we have for MCSymbol as mcsymbol?

[sfertile]

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

91

Good suggestion, send a quick email to the llvm-dev list and see if there interest for this, or any objections.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

153

thanks . change to "ExtSymSDNodeSymbols" as you discussed on the slack

1799

as discussed with Sean offline, since wo do not support tail call for the extern symbol now . I added a report_fatal_error("Tail call for extern symbol not yet implemented.");

[DiggerLin]

address comment

[jhenderson]

llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

11–12

I know this is what was done elsewhere in the test, but I don't think we should blindly copy bad practice here, and instead you should just reflow the line like I suggested in the other test. If you do think the llc line is too long and needs to broken up, I'd recommend the following:

; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
; RUN:     -mcpu=pwr4 -mattr=-altivec < %s | \
; RUN:   FileCheck %s

[jhenderson]

No more style/test comments from me now. I don't know enough about other things to further review this.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1800

Can we have an update on why the TLS call pseudos were simply removed instead of being tracked by report_fatal_error as @sfertile suggested? I think that leaving some breadcrumbs in the code would be useful.

1830

Please use the immediate base class name to refer to the base class implementation.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5341

Should the name be adjusted to match that of the function introduced by https://reviews.llvm.org/D80402? @jasonliu?

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

91

@sfertile, do we have further news on this?

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

9

We've been indenting options to line up with options on the previous line. That usually avoids indenting by only two spaces (which we may want to reserve for indentation after things like shell operators).

13

Same comment.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5341

Yeah, I think matching them would be useful for grepping.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

43

Start with COMMON-LABEL with this line and omit the lines above. The existence of the function descriptor is not the purpose of this test. After this, there would be no difference between 32-bit and 64-bit and we should be able to replace the prefix with plain CHECK.

46

I think the object code generation path test needs to verify that the relocation refers to the correct symbol table entry.

52

I think we should similarly omit the lines in this block before this last one.

75

I think we can omit the symbol table entries aside from the one for .memset.

[DiggerLin]

address comment

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5341

I do not think we can use MCSymbol *getFunctionEntryPointSymbol(const Function *F,const TargetMachine &TM) function , for the .memset or memcpy, we do not have Function object for it.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

5341

I don't think you can actually call that function, as the function is in TLOF and you do not have access to that from here.
Hubert and I are talking about matching the name.

[jhenderson]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

You can fold these two lines into one. No need for them to be separate:

; RUN: llvm-readobj --symbols --relocations --expand-relocs %t.o | \
; RUN:   FileCheck --check-prefix=SYMRELOC %s

[DiggerLin]

address comment

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

Thanks for your suggestion, but I think separating in two is based is more reasonable ,One test for test Symbol. other test for test relocation. it is more readable.

[jhenderson]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

I'm not sure how it's more readable. It's very clear from my suggested command-line that we want to test the symbols and relocations (otherwise the options wouldn't be present), and would reduce the amount of work required to figure out which checks below correspond to which FileCheck line.

It would also be more in keeping with most tests I've worked with, and would reduce the number of executable invocations from 4 to 2, improving test run time.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

I tried it with llvm-readobj --symbols --relocations --expand-relocs
it display the relocation information first and than symbol information.

in the test case we want to verify symbol first and than relocation.
I have to keep current test.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

@hubert.reinterpretcast , what is your option on combine the

llvm-readobj --symbols

and

llvm-readobj --relocations --expand-relocs

into

llvm-readobj --symbols --relocations --expand-relocs

and than verify relocation information first as

; SYMRELOC: Relocation {{[{][[:space:]] *}}Virtual Address: 0x18
; SYMRELOC-NEXT: Symbol: .memset (0)
; SYMRELOC-NEXT: IsSigned: Yes
; SYMRELOC-NEXT: FixupBitValue: 0
; SYMRELOC-NEXT: Length: 26
; SYMRELOC-NEXT: Type: R_RBR (0x1A)
; SYMRELOC-NEXT: }

; SYMRELOC: Symbol {
; SYMRELOC-NEXT: Index: 0
; SYMRELOC-NEXT: Name: .memset
; SYMRELOC-NEXT: Value (RelocatableAddress): 0x0
; SYMRELOC-NEXT: Section: N_UNDEF
; SYMRELOC-NEXT: Type: 0x0
; SYMRELOC-NEXT: StorageCl
......

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

I suggest using llvm-objdump -d --symbol-description for the relocation check. As it is, we can't tell whether the relocation we found is in the right place. This happens to make it so that we end up with two separate tool invocations.

33

I believe I requested CHECK-LABEL: here.

35

Please indent the instructions in relation to the label.

61

Moot point, but this should be aligned to match the closing brace.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

I think you meant: llvm-objdump -d -r --symbol-description

[jhenderson]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

It's moot, given the llvm-objdump suggestion, but I'm not sure it really matters which order symbols or relocations are printed in.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

10–12

because there is symbol index in the relocation information. we prefer to verify the symbol first and then relocation. otherwise, when we verified relocation, we have to go down the test file to search the symbol information.

[DiggerLin]

change test case based on comment

[sfertile]

Hey Digger, sorry for letting this sit for so long. Feel free to ping reviews periodically to get peoples attention back on them.

Other then a few minor nits, LGTM.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

152

Minor nit: Mention that we will need the emit extern linkage for them in the comment.

1861

nit: I would instead say 'not supported' or 'not expected'. The AIX ABI makes a tail-call to an external symbol really unexpected.

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

91

Not sure, I suggested @Xiangling_L send an email to the dev list to discuss, but never followed whether it happened or not. Either way I think its outside the scope of this patch.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

91

Sorry, I think there were some miscommunications. I thought you would send the email. Thanks for your suggestion and will do.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "PPCTargetStreamer.h"
 #include "TargetInfo/PowerPCTargetInfo.h"
 #include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/BinaryFormat/MachO.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/StackMaps.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/IR/Module.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSectionXCOFF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
public:
 
   void emitFunctionBodyStart() override;
   void emitFunctionBodyEnd() override;
   void emitInstruction(const MachineInstr *MI) override;
 };
 
 class PPCAIXAsmPrinter : public PPCAsmPrinter {
 private:
+  /// Symbols lowered from ExternalSymbolSDNodes, we will need to emit extern
+  /// linkage for them in AIX.
+  SmallPtrSet<MCSymbol *, 8> ExtSymSDNodeSymbols;
+
   static void ValidateGV(const GlobalVariable *GV);
 
 public:
   PPCAIXAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : PPCAsmPrinter(TM, std::move(Streamer)) {
     if (MAI->isLittleEndian())
       report_fatal_error(
           "cannot create AIX PPC Assembly Printer for a little-endian target");
   }
 
   StringRef getPassName() const override { return "AIX PPC Assembly Printer"; }
 
   bool doInitialization(Module &M) override;
 
   void SetupMachineFunction(MachineFunction &MF) override;
 
   void emitGlobalVariable(const GlobalVariable *GV) override;
 
   void emitFunctionDescriptor() override;
 
   void emitEndOfAsmFile(Module &) override;
 
   void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const override;
+
+  void emitInstruction(const MachineInstr *MI) override;
+
+  bool doFinalization(Module &M) override;
 };
 
 } // end anonymous namespace
 
 void PPCAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
                                        raw_ostream &O) {
   // Computing the address of a global symbol, not calling it.
   const GlobalValue *GV = MO.getGlobal();
const MCSymbol *TOCBaseSym =
       cast<MCSectionXCOFF>(getObjFileLowering().getTOCBaseSection())
           ->getQualNameSymbol();
   OutStreamer->emitValue(MCSymbolRefExpr::create(TOCBaseSym, OutContext),
                          PointerSize);
   // Emit a null environment pointer.
   OutStreamer->emitIntValue(0, PointerSize);
 
   OutStreamer->SwitchSection(Current.first, Current.second);
 }
 
 void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
   // If there are no functions in this module, we will never need to reference
   // the TOC base.
   if (M.empty())
     return;
 
   // Switch to section to emit TOC base.
for (auto &I : TOC) {
     OutStreamer->SwitchSection(TCEntry);
 
     OutStreamer->emitLabel(I.second);
     if (TS != nullptr)
       TS->emitTCEntry(*I.first);
   }
 }
 
 bool PPCAIXAsmPrinter::doInitialization(Module &M) {
   if (M.alias_size() > 0u)
     report_fatal_error(
         "module has aliases, which LLVM does not yet support for AIX");
 
   const bool Result = PPCAsmPrinter::doInitialization(M);
 
   auto setCsectAlignment = [this](const GlobalObject *GO) {
     // Declarations have 0 alignment which is set by default.
     if (GO->isDeclarationForLinker())
       return;
 
     SectionKind GOKind = getObjFileLowering().getKindForGlobal(GO, TM);
     MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(
         getObjFileLowering().SectionForGlobal(GO, GOKind, TM));
 
     Align GOAlign = getGVAlignment(GO, GO->getParent()->getDataLayout());
     if (GOAlign > Csect->getAlignment())
       Csect->setAlignment(GOAlign);
   };
 
   // We need to know, up front, the alignment of csects for the assembly path,
   // because once a .csect directive gets emitted, we could not change the
   // alignment value on it.
   for (const auto &G : M.globals())
     setCsectAlignment(&G);
 
   for (const auto &F : M)
     setCsectAlignment(&F);
 
   return Result;
 }
 
+void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
+  switch (MI->getOpcode()) {
+  default:
+    break;
+  case PPC::BL8:
+  case PPC::BL:
+  case PPC::BL8_NOP:
+  case PPC::BL_NOP: {
+    const MachineOperand &MO = MI->getOperand(0);
+    if (MO.isSymbol()) {
+      MCSymbolXCOFF *S =
+          cast<MCSymbolXCOFF>(OutContext.getOrCreateSymbol(MO.getSymbolName()));
+      if (!S->hasRepresentedCsectSet()) {
+        // On AIX, an undefined symbol needs to be associated with a
+        // MCSectionXCOFF to get the correct storage mapping class.
+        // In this case, XCOFF::XMC_PR.
+        MCSectionXCOFF *Sec = OutContext.getXCOFFSection(
+            S->getName(), XCOFF::XMC_PR, XCOFF::XTY_ER, XCOFF::C_EXT,
+            SectionKind::getMetadata());
+        S->setRepresentedCsect(Sec);
+      }
+      ExtSymSDNodeSymbols.insert(S);
+    }
+  } break;
+  case PPC::BL_TLS:
+  case PPC::BL8_TLS:
+  case PPC::BL8_TLS_:
+  case PPC::BL8_NOP_TLS:
+    report_fatal_error("TLS call not yet implemented");
+  case PPC::TAILB:
+  case PPC::TAILB8:
+  case PPC::TAILBA:
+  case PPC::TAILBA8:
+  case PPC::TAILBCTR:
+  case PPC::TAILBCTR8:
+    if (MI->getOperand(0).isSymbol())
+      report_fatal_error("Tail call for extern symbol not yet supported.");
+    break;
+  }
+  return PPCAsmPrinter::emitInstruction(MI);
+}
+
+bool PPCAIXAsmPrinter::doFinalization(Module &M) {
+  bool Ret = PPCAsmPrinter::doFinalization(M);
+  for (MCSymbol *Sym : ExtSymSDNodeSymbols)
+    OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);
+  return Ret;
+}
+
 /// createPPCAsmPrinterPass - Returns a pass that prints the PPC assembly code
 /// for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
 static AsmPrinter *
 createPPCAsmPrinterPass(TargetMachine &tm,
                         std::unique_ptr<MCStreamer> &&Streamer) {
   if (tm.getTargetTriple().isOSAIX())

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
 
   // This is a call through a function pointer.
   if (CFlags.IsIndirect) {
     // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
     // indirect calls. The save of the caller's TOC pointer to the stack will be
     // inserted into the DAG as part of call lowering. The restore of the TOC
     // pointer is modeled by using a pseudo instruction for the call opcode that
     // represents the 2 instruction sequence of an indirect branch and link,
     // immediately followed by a load of the TOC pointer from the the stack save
     // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
     // as it is not saved or used.
     return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
                                                : PPCISD::BCTRL;
   }
 
   if (Subtarget.isUsingPCRelativeCalls()) {
     assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.");
static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
   // built with secure-PLT.
   bool UsePlt =
       Subtarget.is32BitELFABI() && !isLocalCallee() &&
       Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
 
   // On AIX, direct function calls reference the symbol for the function's
   // entry point, which is named by prepending a "." before the function's
   // C-linkage name.
+  const auto getFunctionEntryPointSymbol = [&](StringRef SymName) {
+    auto &Context = DAG.getMachineFunction().getMMI().getContext();
+    return cast<MCSymbolXCOFF>(
+        Context.getOrCreateSymbol(Twine(".") + Twine(SymName)));
+  };
+
   const auto getAIXFuncEntryPointSymbolSDNode =
       [&](StringRef FuncName, bool IsDeclaration,
           const XCOFF::StorageClass &SC) {
-        auto &Context = DAG.getMachineFunction().getMMI().getContext();
+        MCSymbolXCOFF *S = getFunctionEntryPointSymbol(FuncName);
 
-        MCSymbolXCOFF *S = cast<MCSymbolXCOFF>(
-            Context.getOrCreateSymbol(Twine(".") + Twine(FuncName)));
+        auto &Context = DAG.getMachineFunction().getMMI().getContext();
 
         if (IsDeclaration && !S->hasRepresentedCsectSet()) {
           // On AIX, an undefined symbol needs to be associated with a
           // MCSectionXCOFF to get the correct storage mapping class.
           // In this case, XCOFF::XMC_PR.
           MCSectionXCOFF *Sec = Context.getXCOFFSection(
               S->getSymbolTableName(), XCOFF::XMC_PR, XCOFF::XTY_ER, SC,
               SectionKind::getMetadata());
           S->setRepresentedCsect(Sec);
         }
 
         MVT PtrVT =
             DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
         return DAG.getMCSymbol(S, PtrVT);
       };
 
   if (isFunctionGlobalAddress(Callee)) {
     const GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
     const GlobalValue *GV = G->getGlobal();
 
     if (!Subtarget.isAIXABI())
       return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
                                         UsePlt ? PPCII::MO_PLT : 0);
 
     assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.");
     const GlobalObject *GO = cast<GlobalObject>(GV);
     const XCOFF::StorageClass SC =
         TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
     return getAIXFuncEntryPointSymbolSDNode(GO->getName(), GO->isDeclaration(),
                                             SC);
   }
 
   if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     const char *SymName = S->getSymbol();
-    if (!Subtarget.isAIXABI())
-      return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
-                                         UsePlt ? PPCII::MO_PLT : 0);
-
+    if (Subtarget.isAIXABI()) {
       // If there exists a user-declared function whose name is the same as the
       // ExternalSymbol's, then we pick up the user-declared version.
       const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
       if (const Function *F =
               dyn_cast_or_null<Function>(Mod->getNamedValue(SymName))) {
         const XCOFF::StorageClass SC =
             TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(F);
-      return getAIXFuncEntryPointSymbolSDNode(F->getName(), F->isDeclaration(),
-                                              SC);
+        return getAIXFuncEntryPointSymbolSDNode(F->getName(),
+                                                F->isDeclaration(), SC);
       }
-
-    return getAIXFuncEntryPointSymbolSDNode(SymName, true, XCOFF::C_EXT);
+      SymName = getFunctionEntryPointSymbol(SymName)->getName().data();
+    }
+    return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
+                                       UsePlt ? PPCII::MO_PLT : 0);
   }
 
   // No transformation needed.
   assert(Callee.getNode() && "What no callee?");
   return Callee;
 }
 
 static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
           (BL tglobaladdr:$dst)>;
 
 def : Pat<(PPCcall (i32 texternalsym:$dst)),
           (BL texternalsym:$dst)>;
 
 // Calls for AIX only
 def : Pat<(PPCcall (i32 mcsym:$dst)),
           (BL mcsym:$dst)>;
+
 def : Pat<(PPCcall_nop (i32 mcsym:$dst)),
           (BL_NOP mcsym:$dst)>;
 
+def : Pat<(PPCcall_nop (i32 texternalsym:$dst)),
+          (BL_NOP texternalsym:$dst)>;
+
 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
           (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
           (TCRETURNdi texternalsym:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
           (TCRETURNri CTRRC:$dst, imm:$imm)>;

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

 ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %0:gprc = nuw ADDI $r1, 56
 ; 32BIT-NEXT:     %1:gprc = LWZtoc @gS256, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %2:gprc = LI 256
 ; 32BIT-DAG:      $r3 = COPY %0
 ; 32BIT-DAG:      $r4 = COPY %1
 ; 32BIT-DAG:      $r5 = COPY %2
-; 32BIT-NEXT:     BL_NOP <mcsymbol .memcpy>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 312, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r4 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}

 ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %1:g8rc = LDtoc @gS256, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:     %2:g8rc = LI8 256
 ; 64BIT-DAG:      $x3 = COPY %0
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %2
-; 64BIT-NEXT:     BL8_NOP <mcsymbol .memcpy>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT:     BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 368, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}

 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %0:gprc_and_gprc_nor0 = LWZtoc @gS57, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %1:gprc = nuw ADDI %0, 24
 ; 32BIT-NEXT:     %2:gprc = nuw ADDI $r1, 56
 ; 32BIT-NEXT:     %3:gprc = LI 33
 ; 32BIT-DAG:      $r3 = COPY %2
 ; 32BIT-DAG:      $r4 = COPY %1
 ; 32BIT-DAG:      $r5 = COPY %3
-; 32BIT-NEXT:     BL_NOP <mcsymbol .memcpy>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 92, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $f1 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}

 ; Confirm the expected memcpy call is independent of the call to test_byval_mem4.
 ; 32BIT:          ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:     %3:gprc = nuw ADDI $r1, 60
 ; 32BIT-NEXT:     %4:gprc = LWZtoc @gS256, $r2 :: (load 4 from got)
 ; 32BIT-NEXT:     %5:gprc = LI 256
 ; 32BIT-DAG:      $r3 = COPY %3
 ; 32BIT-DAG:      $r4 = COPY %4
 ; 32BIT-DAG:      $r5 = COPY %5
-; 32BIT-NEXT:     BL_NOP <mcsymbol .memcpy>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT:     BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
 ; 32BIT-NEXT:     ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT:          ADJCALLSTACKDOWN 316, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-DAG:      $r3 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r4 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r5 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}

 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc_and_g8rc_nox0 = LDtoc @gS256, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:     %1:g8rc = nuw ADDI8 %0, 24
 ; 64BIT-NEXT:     %2:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %3:g8rc = LI8 232
 ; 64BIT-DAG:      $x3 = COPY %2
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %3
-; 64BIT-NEXT:     BL8_NOP <mcsymbol .memcpy>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT:     BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 344, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}

llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll

 ; RUN: llc -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32BIT %s
 
 ; RUN: llc -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64BIT %s
 
 define double @call_ceil(double %n) {
 entry:
   %0 = call double @llvm.ceil.f64(double %n)
   ret double %0
 }
 
 declare double @llvm.ceil.f64(double)
 
-; 32BIT: BL_NOP <mcsymbol .ceil>
-; 64BIT: BL8_NOP <mcsymbol .ceil>
+; 32BIT: BL_NOP &.ceil
+; 64BIT: BL8_NOP &.ceil

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:   FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN:     -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
+; RUN: llvm-objdump -r -d --symbol-description %t.o | FileCheck --check-prefix=CHECKRELOC %s
+
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:                 -mattr=-altivec -filetype=obj -o %t.o 2>&1 < %s | \
+; RUN:   FileCheck --check-prefix=XCOFF64 %s
+; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
+
+%struct.S = type { i32, i32 }
+
+@s = external global %struct.S, align 4
+
+define void @bar() {
+entry:
+  %0 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
+  %1 = trunc i32 %0 to i8
+  %2 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
+  call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.S* @s to i8*), i8 %1, i32 %2, i1 false)
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg)
+
+; CHECK-LABEL: .bar:
+; CHECK-NEXT: # %bb.0:                                # %entry
+; CHECK-NEXT:         mflr 0
+
+; CHECK:              bl .memset
+
+; CHECK:              .extern .memset
+
+; CHECKSYM:      Symbol {
+; CHECKSYM-NEXT:     Index: 0
+; CHECKSYM-NEXT:     Name: .memset
+; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
+; CHECKSYM-NEXT:     Section: N_UNDEF
+; CHECKSYM-NEXT:     Type: 0x0
+; CHECKSYM-NEXT:     StorageClass: C_EXT (0x2)
+; CHECKSYM-NEXT:     NumberOfAuxEntries: 1
+; CHECKSYM-NEXT:     CSECT Auxiliary Entry {
+; CHECKSYM-NEXT:       Index: 1
+; CHECKSYM-NEXT:       SectionLen: 0
+; CHECKSYM-NEXT:       ParameterHashIndex: 0x0
+; CHECKSYM-NEXT:       TypeChkSectNum: 0x0
+; CHECKSYM-NEXT:       SymbolAlignmentLog2: 0
+; CHECKSYM-NEXT:       SymbolType: XTY_ER (0x0)
+; CHECKSYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; CHECKSYM-NEXT:       StabInfoIndex: 0x0
+; CHECKSYM-NEXT:       StabSectNum: 0x0
+; CHECKSYM-NEXT:     }
+; CHECKSYM-NEXT:   }
+
+; CHECKRELOC:      00000000 (idx: 6) .bar:
+; CHECKRELOC-NEXT:        0: 7c 08 02 a6                        mflr 0
+; CHECKRELOC-NEXT:        4: 90 01 00 08                        stw 0, 8(1)
+; CHECKRELOC-NEXT:        8: 94 21 ff c0                        stwu 1, -64(1)
+; CHECKRELOC-NEXT:        c: 80 62 00 00                        lwz 3, 0(2)
+; CHECKRELOC-NEXT:                      0000000e:  R_TOC        (idx: 12) s[TC]
+; CHECKRELOC-NEXT:       10: 80 83 00 04                        lwz 4, 4(3)
+; CHECKRELOC-NEXT:       14: 7c 85 23 78                        mr 5, 4
+; CHECKRELOC-NEXT:       18: 4b ff ff e9                        bl 0x0
+; CHECKRELOC-NEXT:                      00000018:  R_RBR        (idx: 0) .memset[PR]

llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
 
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=32-SYM %s
 
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck \
 ; RUN: --check-prefix=32-REL %s
 
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s
 
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:   FileCheck %s
+
 ; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -mcpu=pwr4 -mattr=-altivec -filetype=obj < %s 2>&1 | FileCheck \
 ; RUN: --check-prefix=64-CHECK %s
 
 ; Test verifies:
 ; If there exists a user-defined function whose name is the same as the
 ; "memcpy" ExternalSymbol's, we pick up the user-defined version, even if this
 ; may lead to some undefined behavior.

 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
 
 ; This test check
 ; 1. The symbol table for .o file to verify .memcpy is a defined external label.
 ; 2. There is no relocation associated with the call, since callee is defined.
 ; 3. Branch instruction in raw data is branching back to the right callee location.
 
+; CHECK-NOT: .extern .memcpy
+
 ; 32-SYM:      Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: .memcpy 
 ; 32-SYM-NEXT:    Value (RelocatableAddress): 0x0
 ; 32-SYM-NEXT:    Section: .text
 ; 32-SYM-NEXT:    Type: 0x0
 ; 32-SYM-NEXT:    StorageClass: C_EXT (0x2)
 ; 32-SYM-NEXT:    NumberOfAuxEntries: 1
 ; 32-SYM-NEXT:    CSECT Auxiliary Entry {
 ; 32-SYM-NEXT:      Index: 3