[MIRVRegNamer] MachineInstr StableHashing.

[plotfi]

Summary

Introducing Stable Hashing, based on Fowler–Noll–Vo hash function.
This hashing scheme has been useful out of tree, and I want to start experimenting with it.
Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner.

This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer).
We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner.

[lanza]

Other than the one comment LGTM.

llvm/lib/CodeGen/MachineStableHash.cpp

152

That seems kinda error prone. VRegRenamer::getInstructionOpcodeHash would just propagate forward a failure blindly.

[plotfi]

llvm/lib/CodeGen/MachineStableHash.cpp

152

The namer is resigned to handle collisions, but yeah I agree. If a hash comes out as 0 it should hit an assert.

[arsenm]

llvm/include/llvm/CodeGen/MachineStableHash.h

2

Extra blank line

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

66

Why substr?

[plotfi]

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

66

Mostly because the existing hash (see end of the function) is a 5 char substring. Thanks for reviewing this @arsenm You think this should be a 7 char hash?

[paquette]

Is there any way to test the hash itself on certain instructions?

e.g. verify that two instructions with different address spaces get a different hash?

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

62

Style nit: usually I've seen things like this formatted like below in the LLVM codebase:

/* HashVRegs = */ true, ...

llvm/lib/CodeGen/MachineStableHash.cpp

67

nit: somewhat shorter

183

static_cast for greppability?

[plotfi]

In D86952#2254859, @paquette wrote:

Is there any way to test the hash itself on certain instructions?

e.g. verify that two instructions with different address spaces get a different hash?

I think most of the tests where I added the -mir-vreg-namer-use-stable-hash line are checking for that. For instance the ; CHECK-NEXT: %bb0_{{[0-9]+}}__1: lines pretty much ensure that the __1 is there, which means there was not more than one collision.

[paquette]

Oh wait the tests already test what I was concerned about. LGTM with minor nits.

(although decoupling the tests from mir-canon would be nice, since this is supposed to be standalone)

[plotfi]

In D86952#2254880, @paquette wrote:

Oh wait the tests already test what I was concerned about. LGTM with minor nits.

(although decoupling the tests from mir-canon would be nice, since this is supposed to be standalone)

Cool. I am planning to write some tests for the MO types the MIRCanon tests aren't already covering.

llvm/include/llvm/CodeGen/MachineOperand.h

public:
 
   /// ChangeToRegister - Replace this operand with a new register operand of
   /// the specified value.  If an operand is known to be an register already,
   /// the setReg method should be used.
   void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
                         bool isKill = false, bool isDead = false,
                         bool isUndef = false, bool isDebug = false);
 
+  /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
+  /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
+  /// have a name. Asserts if MO is not a TargetIndex.
+  const char *getTargetIndexName() const;
+
   //===--------------------------------------------------------------------===//
   // Construction methods.
   //===--------------------------------------------------------------------===//
 
   static MachineOperand CreateImm(int64_t Val) {
     MachineOperand Op(MachineOperand::MO_Immediate);
     Op.setImm(Val);
     return Op;

llvm/include/llvm/CodeGen/MachineStableHash.h

+//===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Stable hashing for MachineInstr and MachineOperand. Useful or getting a
+// hash across runs, modules, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINESTABLEHASH_H
+#define LLVM_CODEGEN_MACHINESTABLEHASH_H
+
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/StableHashing.h"
+
+namespace llvm {
+stable_hash stableHashValue(const MachineOperand &MO);
+stable_hash stableHashValue(const MachineInstr &MI, bool HashVRegs = false,
+                            bool HashConstantPoolIndices = false,
+                            bool HashMemOperands = false);
+
+} // namespace llvm
+
+#endif

llvm/include/llvm/CodeGen/StableHashing.h

+//===- llvm/CodeGen/StableHashing.h - Utilities for stable hashing * C++ *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides types and functions for computing and combining stable
+// hashes. Stable hashes can be useful for hashing across different modules,
+// processes, or compiler runs.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_STABLEHASHING_H
+#define LLVM_CODEGEN_STABLEHASHING_H
+
+#include "llvm/ADT/StringRef.h"
+
+namespace llvm {
+
+/// An opaque object representing a stable hash code. It can be serialized,
+/// deserialized, and is stable across processes and executions.
+using stable_hash = uint64_t;
+
+// Implementation details
+namespace hashing {
+namespace detail {
+
+// Stable hashes are based on the 64-bit FNV-1 hash:
+// https://en.wikipedia.org/wiki/Fowler-Noll-Vo_hash_function
+
+const uint64_t FNV_PRIME_64 = 1099511628211u;
+const uint64_t FNV_OFFSET_64 = 14695981039346656037u;
+
+inline void stable_hash_append(stable_hash &Hash, const char Value) {
+  Hash = Hash ^ (Value & 0xFF);
+  Hash = Hash * FNV_PRIME_64;
+}
+
+inline void stable_hash_append(stable_hash &Hash, stable_hash Value) {
+  for (unsigned I = 0; I < 8; ++I) {
+    stable_hash_append(Hash, (const char)Value);
+    Value >>= 8;
+  }
+}
+
+} // namespace detail
+} // namespace hashing
+
+inline stable_hash stable_hash_combine(stable_hash A, stable_hash B) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  hashing::detail::stable_hash_append(Hash, A);
+  hashing::detail::stable_hash_append(Hash, B);
+  return Hash;
+}
+
+inline stable_hash stable_hash_combine(stable_hash A, stable_hash B,
+                                       stable_hash C) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  hashing::detail::stable_hash_append(Hash, A);
+  hashing::detail::stable_hash_append(Hash, B);
+  hashing::detail::stable_hash_append(Hash, C);
+  return Hash;
+}
+
+inline stable_hash stable_hash_combine(stable_hash A, stable_hash B,
+                                       stable_hash C, stable_hash D) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  hashing::detail::stable_hash_append(Hash, A);
+  hashing::detail::stable_hash_append(Hash, B);
+  hashing::detail::stable_hash_append(Hash, C);
+  hashing::detail::stable_hash_append(Hash, D);
+  return Hash;
+}
+
+/// Compute a stable_hash for a sequence of values.
+///
+/// This hashes a sequence of values. It produces the same stable_hash as
+/// 'stable_hash_combine(a, b, c, ...)', but can run over arbitrary sized
+/// sequences and is significantly faster given pointers and types which
+/// can be hashed as a sequence of bytes.
+template <typename InputIteratorT>
+stable_hash stable_hash_combine_range(InputIteratorT First,
+                                      InputIteratorT Last) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  for (auto I = First; I != Last; ++I)
+    hashing::detail::stable_hash_append(Hash, *I);
+  return Hash;
+}
+
+inline stable_hash stable_hash_combine_array(const stable_hash *P, size_t C) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  for (size_t I = 0; I < C; ++I)
+    hashing::detail::stable_hash_append(Hash, P[I]);
+  return Hash;
+}
+
+inline stable_hash stable_hash_combine_string(const StringRef &S) {
+  return stable_hash_combine_range(S.begin(), S.end());
+}
+
+inline stable_hash stable_hash_combine_string(const char *C) {
+  stable_hash Hash = hashing::detail::FNV_OFFSET_64;
+  while (*C)
+    hashing::detail::stable_hash_append(Hash, *(C++));
+  return Hash;
+}
+
+} // namespace llvm
+
+#endif

llvm/lib/CodeGen/CMakeLists.txt

add_llvm_component_library(LLVMCodeGen
   RegAllocFast.cpp
   RegAllocGreedy.cpp
   RegAllocPBQP.cpp
   RegisterClassInfo.cpp
   RegisterCoalescer.cpp
   RegisterPressure.cpp
   RegisterScavenging.cpp
   RenameIndependentSubregs.cpp
+  MachineStableHash.cpp
   MIRVRegNamerUtils.cpp
   MIRNamerPass.cpp
   MIRCanonicalizerPass.cpp
   RegisterUsageInfo.cpp
   RegUsageInfoCollector.cpp
   RegUsageInfoPropagate.cpp
   ResetMachineFunctionPass.cpp
   SafeStack.cpp

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

 //===---------- MIRVRegNamerUtils.cpp - MIR VReg Renaming Utilities -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MIRVRegNamerUtils.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineStableHash.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mir-vregnamer-utils"
 
+static cl::opt<bool>
+    UseStableNamerHash("mir-vreg-namer-use-stable-hash", cl::init(false),
+                       cl::Hidden,
+                       cl::desc("Use Stable Hashing for MIR VReg Renaming"));
+
 using VRegRenameMap = std::map<unsigned, unsigned>;
 
 bool VRegRenamer::doVRegRenaming(const VRegRenameMap &VRM) {
   bool Changed = false;
 
   for (const auto &E : VRM) {
     Changed = Changed || !MRI.reg_empty(E.first);
     MRI.replaceRegWith(E.first, E.second);
VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) {
   }
   return VRM;
 }
 
 std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
   std::string S;
   raw_string_ostream OS(S);
 
+  if (UseStableNamerHash) {
+    auto Hash = stableHashValue(MI, /* HashVRegs */ true,
+                                /* HashConstantPoolIndices */ true,
+                                /* HashMemOperands */ true);
+    assert(Hash && "Expected non-zero Hash");
+    return std::to_string(Hash).substr(0, 5);
+  }
+
   // Gets a hashable artifact from a given MachineOperand (ie an unsigned).
   auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
     switch (MO.getType()) {
     case MachineOperand::MO_CImmediate:
       return hash_combine(MO.getType(), MO.getTargetFlags(),
                           MO.getCImm()->getZExtValue());
     case MachineOperand::MO_FPImmediate:
       return hash_combine(

llvm/lib/CodeGen/MachineOperand.cpp

static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
     return I.first == Index;
   });
   if (Found != Indices.end())
     return Found->second;
   return nullptr;
 }
 
+const char *MachineOperand::getTargetIndexName() const {
+  const MachineFunction *MF = getMFIfAvailable(*this);
+  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
+}
+
 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
   for (const auto &I : Flags) {
     if (I.first == TF) {
       return I.second;
     }
   }
   return nullptr;
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
   case MachineOperand::MO_ConstantPoolIndex:
     OS << "%const." << getIndex();
     printOperandOffset(OS, getOffset());
     break;
   case MachineOperand::MO_TargetIndex: {
     OS << "target-index(";
     const char *Name = "<unknown>";
     if (const MachineFunction *MF = getMFIfAvailable(*this))
-      if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
+      if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
         Name = TargetIndexName;
     OS << Name << ')';
     printOperandOffset(OS, getOffset());
     break;
   }
   case MachineOperand::MO_JumpTableIndex:
     OS << printJumpTableEntryReference(getIndex());
     break;

llvm/lib/CodeGen/MachineStableHash.cpp

+//===- lib/CodeGen/MachineStableHash.cpp ----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Stable hashing for MachineInstr and MachineOperand. Useful or getting a
+// hash across runs, modules, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineStableHash.h"
+#include "llvm/ADT/FoldingSet.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Analysis/Loads.h"
+#include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/MIRFormatter.h"
+#include "llvm/CodeGen/MIRPrinter.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/StableHashing.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/Config/llvm-config.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/IRPrintingPasses.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/ModuleSlotTracker.h"
+#include "llvm/MC/MCDwarf.h"
+#include "llvm/Target/TargetIntrinsicInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+#define DEBUG_TYPE "machine-stable-hash"
+
+using namespace llvm;
+
+STATISTIC(StableHashBailingMachineBasicBlock,
+          "Number of encountered unsupported MachineOperands that were "
+          "MachineBasicBlocks while computing stable hashes");
+STATISTIC(StableHashBailingConstantPoolIndex,
+          "Number of encountered unsupported MachineOperands that were "
+          "ConstantPoolIndex while computing stable hashes");
+STATISTIC(StableHashBailingTargetIndexNoName,
+          "Number of encountered unsupported MachineOperands that were "
+          "TargetIndex with no name");
+STATISTIC(StableHashBailingGlobalAddress,
+          "Number of encountered unsupported MachineOperands that were "
+          "GlobalAddress while computing stable hashes");
+STATISTIC(StableHashBailingBlockAddress,
+          "Number of encountered unsupported MachineOperands that were "
+          "BlockAddress while computing stable hashes");
+STATISTIC(StableHashBailingMetadataUnsupported,
+          "Number of encountered unsupported MachineOperands that were "
+          "Metadata of an unsupported kind while computing stable hashes");
+
+stable_hash llvm::stableHashValue(const MachineOperand &MO) {
+  switch (MO.getType()) {
+  case MachineOperand::MO_Register:
+    if (Register::isVirtualRegister(MO.getReg())) {
+      const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
+      return MRI.getVRegDef(MO.getReg())->getOpcode();
+    }
+
+    // Register operands don't have target flags.
+    return stable_hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
+                               MO.isDef());
+  case MachineOperand::MO_Immediate:
+    return stable_hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
+  case MachineOperand::MO_CImmediate:
+  case MachineOperand::MO_FPImmediate: {
+    auto Val = MO.isCImm() ? MO.getCImm()->getValue()
+                           : MO.getFPImm()->getValueAPF().bitcastToAPInt();
+    auto ValHash =
+        stable_hash_combine_array(Val.getRawData(), Val.getNumWords());
+    return hash_combine(MO.getType(), MO.getTargetFlags(), ValHash);
+  }
+
+  case MachineOperand::MO_MachineBasicBlock:
+    StableHashBailingMachineBasicBlock++;
+    return 0;
+  case MachineOperand::MO_ConstantPoolIndex:
+    StableHashBailingConstantPoolIndex++;
+    return 0;
+  case MachineOperand::MO_BlockAddress:
+    StableHashBailingBlockAddress++;
+    return 0;
+  case MachineOperand::MO_Metadata:
+    StableHashBailingMetadataUnsupported++;
+    return 0;
+  case MachineOperand::MO_GlobalAddress:
+    StableHashBailingGlobalAddress++;
+    return 0;
+  case MachineOperand::MO_TargetIndex: {
+    if (const char *Name = MO.getTargetIndexName())
+      return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+                                 stable_hash_combine_string(Name),
+                                 MO.getOffset());
+    StableHashBailingTargetIndexNoName++;
+    return 0;
+  }
+
+  case MachineOperand::MO_FrameIndex:
+  case MachineOperand::MO_JumpTableIndex:
+    return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+                               MO.getIndex());
+
+  case MachineOperand::MO_ExternalSymbol:
+    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
+                        stable_hash_combine_string(MO.getSymbolName()));
+
+  case MachineOperand::MO_RegisterMask:
+  case MachineOperand::MO_RegisterLiveOut:
+    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
+
+  case MachineOperand::MO_ShuffleMask: {
+    std::vector<llvm::stable_hash> ShuffleMaskHashes;
+
+    llvm::transform(
+        MO.getShuffleMask(), std::back_inserter(ShuffleMaskHashes),
+        [](int S) -> llvm::stable_hash { return llvm::stable_hash(S); });
+
+    return hash_combine(MO.getType(), MO.getTargetFlags(),
+                        stable_hash_combine_array(ShuffleMaskHashes.data(),
+                                                  ShuffleMaskHashes.size()));
+  }
+  case MachineOperand::MO_MCSymbol: {
+    auto SymbolName = MO.getMCSymbol()->getName();
+    return hash_combine(MO.getType(), MO.getTargetFlags(),
+                        stable_hash_combine_string(SymbolName));
+  }
+  case MachineOperand::MO_CFIIndex:
+    return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+                               MO.getCFIIndex());
+  case MachineOperand::MO_IntrinsicID:
+    return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+                               MO.getIntrinsicID());
+  case MachineOperand::MO_Predicate:
+    return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
+                               MO.getPredicate());
+  }
+  llvm_unreachable("Invalid machine operand type");
+}
+
+/// A stable hash value for machine instructions.
+/// Returns 0 if no stable hash could be computed.
+/// The hashing and equality testing functions ignore definitions so this is
+/// useful for CSE, etc.
+stable_hash llvm::stableHashValue(const MachineInstr &MI, bool HashVRegs,
+                                  bool HashConstantPoolIndices,
+                                  bool HashMemOperands) {
+  // Build up a buffer of hash code components.
+  SmallVector<stable_hash, 16> HashComponents;
+  HashComponents.reserve(MI.getNumOperands() + MI.getNumMemOperands() + 2);
+  HashComponents.push_back(MI.getOpcode());
+  HashComponents.push_back(MI.getFlags());
+  for (const MachineOperand &MO : MI.operands()) {
+    if (!HashVRegs && MO.isReg() && MO.isDef() &&
+        Register::isVirtualRegister(MO.getReg()))
+      continue; // Skip virtual register defs.
+
+    if (MO.isCPI()) {
+      HashComponents.push_back(stable_hash_combine(
+          MO.getType(), MO.getTargetFlags(), MO.getIndex()));
+      continue;
+    }
+
+    stable_hash StableHash = stableHashValue(MO);
+    if (!StableHash)
+      return 0;
+    HashComponents.push_back(StableHash);
+  }
+
+  for (const auto *Op : MI.memoperands()) {
+    if (!HashMemOperands)
+      break;
+    HashComponents.push_back(static_cast<unsigned>(Op->getSize()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getFlags()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getOffset()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getOrdering()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getAddrSpace()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getSyncScopeID()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getBaseAlign().value()));
+    HashComponents.push_back(static_cast<unsigned>(Op->getFailureOrdering()));
+  }
+
+  return stable_hash_combine_range(HashComponents.begin(),
+                                   HashComponents.end());
+}

llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir

-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -o - %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
 
 --- |
 
   define void @addrspace_memoperands() {
     ret void
   }
 
 ...

llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir

 # RUN: llc -o - -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
 --- |
   target triple = "aarch64-unknown-unknown"
   define void @f() { unreachable }
 ...
 ---
 name: f
 constants:
   - id:              0

llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir

 # RUN: llc -run-pass mir-canonicalizer -verify-machineinstrs -mtriple aarch64-unknown-linux-gnu -o - %s | FileCheck %s
+# RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -mtriple aarch64-unknown-linux-gnu -o - %s | FileCheck %s
 ...
 ---
 name: foo
 alignment:       16
 jumpTable:
   kind:  block-address
   entries:
     - id:              0

llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir

 # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -mir-vreg-namer-use-stable-hash -run-pass mir-canonicalizer %s | FileCheck %s
 
 ...
 ---
 name: Proc8
 stack:
   - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       local-offset: -4, debug-info-variable: '', debug-info-expression: '',

llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir

 # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -mir-vreg-namer-use-stable-hash -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
 # These Idempotent instructions are sorted alphabetically (based on after the '=')
 # CHECK: %bb0_{{[0-9]+}}__1:gpr64 = MOVi64imm 4617315517961601024
 # CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 408
 # CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = MOVi32imm 408
 # CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr64all = IMPLICIT_DEF
 # CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 20
 # CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 112
 

llvm/test/CodeGen/MIR/AArch64/mirnamer.mir

-# RUN: llc -x mir -mtriple aarch64-apple-ios -run-pass mir-namer -verify-machineinstrs -o - < %s | FileCheck %s
+# RUN: llc -x mir -mtriple aarch64-apple-ios -run-pass mir-namer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - < %s | FileCheck %s
 
 ---
 name: foo
 body:             |
   bb.0:
 
     ;CHECK-LABEL: bb.0
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0

llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir

-# RUN: llc -o -  -march=amdgcn  -run-pass mir-canonicalizer  %s | FileCheck %s
+# RUN: llc -o -  -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o -  -march=amdgcn  -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
 
 # This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
 ...
 ---
 name: foo
 body:             |
   bb.0:
     ; CHECK-LABEL: name: foo

llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir

-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
 --- |
   target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
 
   define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %arg) {
     unreachable
   }
 ...
 ---

llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir

 # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
 # RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
+# RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
 
 # Previously getReservedRegs was called before parsing
 # machineFunctionInfo, but the AMDGPU implementation depends on
 # setting register fields to reserve there. $sgpr50 would then not be
 # reserved, resulting in a verifier error from an undefined register.
 
 ---
 # CHECK: machineFunctionInfo:

llvm/test/CodeGen/MIR/Generic/CFPImmMIRCanonHash.mir

-# RUN: llc -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# RUN: llc -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
 ---
 name: cimm_fpimm_hash_test
 body: |
   bb.0:
     ; CHECK: _1:_(s1) = G_CONSTANT i1 true
     ; CHECK: _1:_(s1) = G_CONSTANT i1 false
     ; CHECK: _1:_(s32) = G_FCONSTANT float
     ; CHECK: _1:_(s32) = G_FCONSTANT float
     %0:_(s1) = G_CONSTANT i1 true
     %1:_(s1) = G_CONSTANT i1 false
     %2:_(s32) = G_FCONSTANT float 1.0
     %3:_(s32) = G_FCONSTANT float 0.0
 ...

llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir

 # RUN: llc  -run-pass mir-namer -x mir -verify-machineinstrs %s -o - | FileCheck %s
 # RUN: llc  -run-pass mir-canonicalizer -x mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc  -run-pass mir-namer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc  -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
   target triple = "x86_64-unknown-linux-gnu"
   define i32 @_Z1fi(i32 %arg) {
     %tmp = alloca i32, align 4
     %tmp1 = alloca i32, align 4
     ret i32 %arg
   }

llvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir

 # RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s -o - | FileCheck %s
 
 ...
 ---
 name: f
 stack:
   - { id: 0, size: 4 }
   - { id: 1, size: 4 }
 fixedStack:

llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

-# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
 # The purpose of this test is to ensure that differing flags do in-fact cause
 # naming collisions with the new vreg renamers naming scheme.
 --- |
   target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
   define void @baz() { unreachable }
 ...
 ---
 name:            baz