[RISCV] Support libunwind for riscv32

[kamleshbhalui]

Summary

This patch adds support in libunwind for rv32 hard flaot and soft-float for both rv32 and rv64.
Tried to generalise as much possible with lesser code duplication.

[luismarques]

libunwind/include/__libunwind_config.h

133–134

This doesn't seem correct.

libunwind/src/Registers.hpp

3734–3738

If we go the generic route, why not just use unsigned long (or size_t, etc.) instead of these custom types? Also, these uncapitalized *_t names are generally typedefs, not preprocessor defines.

3979–3980

In the #else "branch" those variables aren't used, so presumably you still need those lines to avoid warnings about unused variables.

libunwind/src/UnwindRegistersRestore.S

1075

It might be a good idea to use instead __riscv_xlen == 32 || __riscv_xlen == 64, as that will correctly detect the case that riscv128 isn't handled.

1085–1116

If we are going to use a preprocessed instruction name (which I'm not sure we should) then at least the name should be ALL CAPS to make it obvious that it's a preprocessor definition, not a regular instruction.

libunwind/src/UnwindRegistersSave.S

1029

ditto 32 || 64.

[kamleshbhalui]

libunwind/include/__libunwind_config.h

133–134

OK so it appears that in principle we could have 4 combinations

ILP32 + "f" : xlen = 32, flen = 32
ILP32 + "fd" : xlen = 32, flen = 64
LP64 + "f" : xlen = 64, flen = 32
LP64 + "fd" : xlen = 64, flen = 64

So instead of having fixed size area for each kind of register thought of having packed size.
please point me where it can cause problem?

[kamleshbhalui]

libunwind/src/UnwindRegistersRestore.S

1085–1116

This is good idea.
thanks. will incorporate this.

[kamleshbhalui]

libunwind/src/UnwindRegistersRestore.S

1075

Since It is already handled at __libunwind_config.h:130
do we really need it at other places?

[kamleshbhalui]

addressed @luismarques comments.

[kamleshbhalui]

defined _LIBUNWIND_CURSOR_SIZE
for all these below variants
ILP32 + "f" : xlen = 32, flen = 32 ===> 39
ILP32 + "fd" : xlen = 32, flen = 64 ===>55
LP64 + "f" : xlen = 64, flen = 32 ====>60
LP64 + "fd" : xlen = 64, flen = 64 ====>76 (was already done.)

[ldionne]

@kamleshbhalui Just to be clear -- you need libunwind approval before you can submit a patch that touches libunwind. If you just wanted to iterate on this privately it's OK, but you'll need approval from the group before submitting.

[kamleshbhalui]

In D80690#2060505, @ldionne wrote:

@kamleshbhalui Just to be clear -- you need libunwind approval before you can submit a patch that touches libunwind. If you just wanted to iterate on this privately it's OK, but you'll need approval from the group before submitting.

Thanks @ldionne , wasn't aware of this. added the group as reviewer.

[ldionne]

In D80690#2060681, @kamleshbhalui wrote:

In D80690#2060505, @ldionne wrote:

@kamleshbhalui Just to be clear -- you need libunwind approval before you can submit a patch that touches libunwind. If you just wanted to iterate on this privately it's OK, but you'll need approval from the group before submitting.

Thanks @ldionne , wasn't aware of this. added the group as reviewer.

That's the reason why libunwind is added as a blocking reviewer to reviews that touch libunwind. At least one maintainer (or person familiar with the code base) needs to give you a thumbs up.

Changes in these runtimes components have very wide impact, and unfortunately they're usually not very well tested. That's why we have these requirements.

[kito-cheng]

libunwind/include/__libunwind_config.h

133–134

I am not family with libunwind and don't know what's _LIBUNWIND_CURSOR_SIZE , but I am curious about does here different value for xlen=32/flen=and xlen=64/flen=0?

And I think add an #else + #error to catch any unsupported value would be better, since the flen could be 128 (Q), although LLVM didn't implement yet, but in case we implemented in future we'll know we need fix here.

[luismarques]

libunwind/include/__libunwind_config.h

133–134

You are right that _LIBUNWIND_CONTEXT_SIZE is correctly defined.
Can you please add comments explaining the values for _LIBUNWIND_CURSOR_SIZE?
Personally, sometimes I also like to define constants as e.g. (32 + 32) instead of just 64, to make the structure behind the final value clear, so that may also be an option.

libunwind/src/Registers.hpp

3734–3738

I see you changed uintX_t to be #defined as unsigned long. That was not the point of my previous comment. Is there an advantage in introducing these X types, instead of using existing types like, say, size_t?

3792–3798

Since you're going for a generic approach, and you already define things like RISCV_FOFFSET, instead of using #if #elses here I guess you could check that sizeof(_registers) == RISCV_FOFFSET*8, or something like that. If you keep this approach then it's probably best to to add an #else branch to error out for other conditions (e.g. riscv128).

libunwind/src/UnwindRegistersRestore.S

1075

I think you're right, everything here is generic so we don't need to error out here on unhandled cases, only in the code that sets the preprocessor definitions this code uses.

libunwind/src/assembly.h

36

Isn't __riscv_xlen always defined when __riscv is defined? What's the point of this?

37–43

Better to put an #else branch here, to #error out on other cases (e.g. rv128).

53

Ditto #else, to #error out on other cases (e.g. quad-precision FP).

[kamleshbhalui]

addressed @luismarques concerns.
This patch extends soft float case .

[kamleshbhalui]

libunwind/include/__libunwind_config.h

133–134

I have generated values for _LIBUNWIND_CURSOR_SIZE from UnwindCursor class size for each configration so that checkfit function becomes true.
i.e.

static_assert((check_fit<UnwindCursor<A, R>, unw_cursor_t>::does_fit),
              "UnwindCursor<> does not fit in unw_cursor_t");

I tried to make sense of these values for commenting , but i could not.

[kamleshbhalui]

Rebased

[kamleshbhalui]

ping?

[mhorne]

@kamleshbhalui thanks for this, it looks to be shaping up well. I have only a couple of small comments first.

libunwind/include/__libunwind_config.h

133–134

I think the purpose is that they want instances of UnwindCursor to be allocated on the stack, and it must fit within unw_cursor_t to do so.

As you have seen the calculation is: _UNWIND_CONTEXT_SIZE + (size of other UnwindCursor members / sizeof(uint64_t))

For the 64-bit ISA this comes out to _UNWIND_CONTEXT_SIZE + 12, and _UNWIND_CONTEXT_SIZE + 7 for 32-bit.

146

I don't think you need the extra parentheses in this statement.

libunwind/src/Registers.hpp

3734–3738

Yep, I would also like to see this changed to a typedef before going in. Doing this as a define is very unusual.

3735

Could you please indent the nested #ifs to improve readability?

[kamleshbhalui]

thanks @mhorne for reviewing.
addressed your comments.

[kamleshbhalui]

rebased and cleaned up the diff.

[MaskRay]

libunwind/src/Registers.hpp

3735

See above.

The style is:

# + spaces + if

[mhorne]

libunwind/src/Registers.hpp

3744

Only the preprocessor directives need indentation, not the typedef.

3828

I don't think size_t is an appropriate type for this, although it would likely work in all cases. I think what you want is either an unsigned long or something like the following:

#if __riscv_xlen == 64
typedef uint64_t reg_t;
#elif __riscv_xlen == 32
typedef uint32_t reg_t;
#endif

[kamleshbhalui]

addressed @mhorne and @MaskRay concerns.

[kamleshbhalui]

ping?

[kamleshbhalui]

ping?

[mhorne]

Hi, sorry for the delay in review. It would be helpful if you could go through the inline comments and mark them as "done" if they have been addressed. I see there are still a few comments that have been ignored.

This patch is tricky because there are no consistent indentation rules for preprocessor directives. In general, I think the indentation is only necessary for blocks where it increases readability (such as where _LIBUNWIND_CURSOR_SIZE is defined, or the block where reg_t is defined). Otherwise, it's best to follow the existing convention of the file.

libunwind/include/__libunwind_config.h

148–154

Please look at this block again carefully. It should follow a rule of 1 space of indentation for each level of nesting.

libunwind/src/Registers.hpp

3744

Again, please fix these.

4001

(void)regNum;

libunwind/src/assembly.h

38

Everything inside this #if should have an additional space of indentation.

[kamleshbhalui]

addressed @mhorne comments.

[luismarques]

This seems roughly OK now. Does anyone with libunwind experience want to give it a thumbs up?
#libunwind people, does this LGTY?

libunwind/src/Registers.hpp

3751

Nit: supresing -> suppressing

[luismarques]

In D80690#2278727, @luismarques wrote:

This seems roughly OK now. Does anyone with libunwind experience want to give it a thumbs up?
#libunwind people, does this LGTY?

ping.

[luismarques]

In D80690#2375624, @luismarques wrote:

In D80690#2278727, @luismarques wrote:

This seems roughly OK now. Does anyone with libunwind experience want to give it a thumbs up?
#libunwind people, does this LGTY?

ping.

ping?

[kamleshbhalui]

rebased with the main branch. do not see any conflict.
@ldionne or @abdulras can you please have a look at this, this patch is in this state for a long time.
FYI, I have been using this patch in VxWorks.

[kamleshbhalui]

fixed a nit.

[compnerd]

This is fine for now, but in the future, for such changes, please split this up into a series of patches. The clean ups for the named constants and clean up for floating point handling could have been separate changes which would have reduced the overall size of the changes and focused the patch specifically to adding support for rv32.

[bkramer]

This breaks building libunwind with LIBUNWIND_ENABLE_CROSS_UNWINDING enabled

[thakis]

Hi,

this doesn't compile on our bots:

FAILED: obj/buildtools/third_party/libunwind/libunwind/libunwind.o 
/b/s/w/ir/cache/goma/client/gomacc ../../third_party/llvm-build/Release+Asserts/bin/clang++ -MMD -MF obj/buildtools/third_party/libunwind/libunwind/libunwind.o.d -D_LIBUNWIND_DISABLE_VISIBILITY_ANNOTATIONS -DDCHECK_ALWAYS_ON=1 -DUSE_AURA=1 -DUSE_OZONE=1 -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -DFUCHSIA_SDK_VERSION=2.20210302.1.1 -DCR_CLANG_REVISION=\"llvmorg-13-init-1559-g01b87444-3\" -D_LIBCPP_ABI_UNSTABLE -D_LIBCPP_DISABLE_VISIBILITY_ANNOTATIONS -D_LIBCXXABI_DISABLE_VISIBILITY_ANNOTATIONS -D_LIBCPP_ENABLE_NODISCARD -D_LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS -D_LIBCPP_NO_NATIVE_SEMAPHORES -D_LIBCPP_DEBUG=0 -DCR_LIBCXX_REVISION=8fa87946779682841e21e2da977eccfb6cb3bded -DNDEBUG -DNVALGRIND -DDYNAMIC_ANNOTATIONS_ENABLED=0 -I../../buildtools/third_party/libunwind/trunk/include -I../.. -Igen -fno-delete-null-pointer-checks -fno-ident -fno-strict-aliasing --param=ssp-buffer-size=4 -fstack-protector -funwind-tables -fPIC -fcolor-diagnostics -fmerge-all-constants -fcrash-diagnostics-dir=../../tools/clang/crashreports -mllvm -instcombine-lower-dbg-declare=0 -fcomplete-member-pointers --target=x86_64-fuchsia -m64 -march=x86-64 -msse3 -Wno-builtin-macro-redefined -D__DATE__= -D__TIME__= -D__TIMESTAMP__= -Xclang -fdebug-compilation-dir -Xclang . -no-canonical-prefixes -Oz -fdata-sections -ffunction-sections -fomit-frame-pointer -g1 -ftrivial-auto-var-init=pattern -fvisibility=hidden -Xclang -add-plugin -Xclang find-bad-constructs -Xclang -plugin-arg-find-bad-constructs -Xclang check-ipc -Wheader-hygiene -Wstring-conversion -Wtautological-overlap-compare -Werror -Wall -Wno-unused-variable -Wno-misleading-indentation -Wno-missing-field-initializers -Wno-unused-parameter -Wno-c++11-narrowing -Wno-unneeded-internal-declaration -Wno-undefined-var-template -Wno-psabi -Wno-ignored-pragma-optimize -Wno-implicit-int-float-conversion -Wno-final-dtor-non-final-class -Wno-builtin-assume-aligned-alignment -Wno-deprecated-copy -Wno-non-c-typedef-for-linkage -Wno-max-tokens -fstrict-aliasing -fPIC -Wno-unused-function -funwind-tables -std=c++14 -fno-trigraphs -Wno-trigraphs -nostdinc++ -isystem../../buildtools/third_party/libc++/trunk/include -isystem../../buildtools/third_party/libc++abi/trunk/include --sysroot=../../third_party/fuchsia-sdk/sdk/arch/x64/sysroot -fvisibility-inlines-hidden -fexceptions -frtti -c ../../buildtools/third_party/libunwind/trunk/src/libunwind.cpp -o obj/buildtools/third_party/libunwind/libunwind/libunwind.o
In file included from ../../buildtools/third_party/libunwind/trunk/src/libunwind.cpp:21:
In file included from ../../buildtools/third_party/libunwind/trunk/src/AddressSpace.hpp:23:
In file included from ../../buildtools/third_party/libunwind/trunk/src/EHHeaderParser.hpp:17:
In file included from ../../buildtools/third_party/libunwind/trunk/src/DwarfParser.hpp:22:
../../buildtools/third_party/libunwind/trunk/src/Registers.hpp:3739:4: error: "Unsupported __riscv_xlen"
#  error "Unsupported __riscv_xlen"
   ^

Does this assume that we pass any -D flags? Does this assume trunk clang?

[thakis]

libunwind/src/Registers.hpp

3739

I think you can't assume that __riscv stuff is defined down here. This is in a __LIBUNWIND_TARGET_RISCV block, which, if _LIBUNWIND_IS_NATIVE_ONLY is not defined (which it isn't in LIBUNWIND_ENABLE_CROSS_UNWINDING builds), is defined to 1.

libunwind/include/__libunwind_config.h

 #    error "Unsupported MIPS ABI and/or environment"
 #  endif
 #  define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
 # elif defined(__sparc__)
   #define _LIBUNWIND_TARGET_SPARC 1
   #define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
   #define _LIBUNWIND_CONTEXT_SIZE 16
   #define _LIBUNWIND_CURSOR_SIZE 23
 # elif defined(__riscv)
-#  if __riscv_xlen == 64
-#    define _LIBUNWIND_TARGET_RISCV 1
-#    define _LIBUNWIND_CONTEXT_SIZE 64
-#    define _LIBUNWIND_CURSOR_SIZE 76
+#  define _LIBUNWIND_TARGET_RISCV 1
+#  if defined(__riscv_flen)
+#   define RISCV_FLEN __riscv_flen
+#  else
+#   define RISCV_FLEN 0
+#  endif
+#  define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64)
+#  if __riscv_xlen == 32
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7)
+#  elif __riscv_xlen == 64
+#   define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12)
 #  else
-#    error "Unsupported RISC-V ABI"
+#   error "Unsupported RISC-V ABI"
 #  endif
 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
 # elif defined(__ve__)
 #  define _LIBUNWIND_TARGET_VE 1
 #  define _LIBUNWIND_CONTEXT_SIZE 67
 #  define _LIBUNWIND_CURSOR_SIZE 79
 #  define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE
 # else
 #  error "Unsupported architecture."
 # endif
 #else // !_LIBUNWIND_IS_NATIVE_ONLY
 # define _LIBUNWIND_TARGET_I386
 # define _LIBUNWIND_TARGET_X86_64 1
 # define _LIBUNWIND_TARGET_PPC 1
 # define _LIBUNWIND_TARGET_PPC64 1
 # define _LIBUNWIND_TARGET_AARCH64 1

libunwind/src/Registers.hpp

default:
     return "unknown register";
   }
 
 }
 #endif // _LIBUNWIND_TARGET_HEXAGON
 
 
 #if defined(_LIBUNWIND_TARGET_RISCV)
-/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
+/// Registers_riscv holds the register state of a thread in a RISC-V
 /// process.
+
+# if __riscv_xlen == 32
+typedef uint32_t reg_t;
+# elif __riscv_xlen == 64
+typedef uint64_t reg_t;
+# else
+#  error "Unsupported __riscv_xlen"
+# endif
+
+# if defined(__riscv_flen)
+#  if __riscv_flen == 64
+typedef double fp_t;
+#  elif __riscv_flen == 32
+typedef float fp_t;
+#  else
+#   error "Unsupported __riscv_flen"
+#  endif
+# else
+// This is just for supressing undeclared error of fp_t.
+typedef double fp_t;
+# endif
+
+/// Registers_riscv holds the register state of a thread.
 class _LIBUNWIND_HIDDEN Registers_riscv {
 public:
   Registers_riscv();
   Registers_riscv(const void *registers);
 
   bool        validRegister(int num) const;
-  uint64_t    getRegister(int num) const;
-  void        setRegister(int num, uint64_t value);
+  reg_t       getRegister(int num) const;
+  void        setRegister(int num, reg_t value);
   bool        validFloatRegister(int num) const;
-  double      getFloatRegister(int num) const;
-  void        setFloatRegister(int num, double value);
+  fp_t        getFloatRegister(int num) const;
+  void        setFloatRegister(int num, fp_t value);
   bool        validVectorRegister(int num) const;
   v128        getVectorRegister(int num) const;
   void        setVectorRegister(int num, v128 value);
   static const char *getRegisterName(int num);
   void        jumpto();
   static int  lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV; }
   static int  getArch() { return REGISTERS_RISCV; }
 
-  uint64_t  getSP() const         { return _registers[2]; }
-  void      setSP(uint64_t value) { _registers[2] = value; }
-  uint64_t  getIP() const         { return _registers[0]; }
-  void      setIP(uint64_t value) { _registers[0] = value; }
+  reg_t       getSP() const { return _registers[2]; }
+  void        setSP(reg_t value) { _registers[2] = value; }
+  reg_t       getIP() const { return _registers[0]; }
+  void        setIP(reg_t value) { _registers[0] = value; }
 
 private:
   // _registers[0] holds the pc
-  uint64_t _registers[32];
-  double   _floats[32];
+  reg_t _registers[32];
+# if defined(__riscv_flen)
+  fp_t _floats[32];
+# endif
 };
 
 inline Registers_riscv::Registers_riscv(const void *registers) {
   static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit),
                 "riscv registers do not fit into unw_context_t");
   memcpy(&_registers, registers, sizeof(_registers));
+# if __riscv_xlen == 32
+  static_assert(sizeof(_registers) == 0x80,
+                "expected float registers to be at offset 128");
+# elif __riscv_xlen == 64
   static_assert(sizeof(_registers) == 0x100,
                 "expected float registers to be at offset 256");
+# else
+# error "Unexpected float registers."
+# endif
+
+# if defined(__riscv_flen)
   memcpy(_floats,
          static_cast<const uint8_t *>(registers) + sizeof(_registers),
          sizeof(_floats));
+# endif
 }
 
 inline Registers_riscv::Registers_riscv() {
   memset(&_registers, 0, sizeof(_registers));
+# if defined(__riscv_flen)
   memset(&_floats, 0, sizeof(_floats));
+# endif
 }
 
 inline bool Registers_riscv::validRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return true;
   if (regNum == UNW_REG_SP)
     return true;
   if (regNum < 0)
     return false;
   if (regNum > UNW_RISCV_F31)
     return false;
   return true;
 }
 
-inline uint64_t Registers_riscv::getRegister(int regNum) const {
+inline reg_t Registers_riscv::getRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return _registers[0];
   if (regNum == UNW_REG_SP)
     return _registers[2];
   if (regNum == UNW_RISCV_X0)
     return 0;
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 
-inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
+inline void Registers_riscv::setRegister(int regNum, reg_t value) {
   if (regNum == UNW_REG_IP)
     _registers[0] = value;
   else if (regNum == UNW_REG_SP)
     _registers[2] = value;
   else if (regNum == UNW_RISCV_X0)
     /* x0 is hardwired to zero */
     return;
   else if ((regNum > 0) && (regNum < 32))
inline const char *Registers_riscv::getRegisterName(int regNum) {
   case UNW_RISCV_F31:
     return "ft11";
   default:
     return "unknown register";
   }
 }
 
 inline bool Registers_riscv::validFloatRegister(int regNum) const {
+# if defined(__riscv_flen)
   if (regNum < UNW_RISCV_F0)
     return false;
   if (regNum > UNW_RISCV_F31)
     return false;
   return true;
+# else
+  (void)regNum;
+  return false;
+# endif
 }
 
-inline double Registers_riscv::getFloatRegister(int regNum) const {
-#if defined(__riscv_flen) && __riscv_flen == 64
+inline fp_t Registers_riscv::getFloatRegister(int regNum) const {
+# if defined(__riscv_flen)
   assert(validFloatRegister(regNum));
   return _floats[regNum - UNW_RISCV_F0];
-#else
+# else
   (void)regNum;
   _LIBUNWIND_ABORT("libunwind not built with float support");
-#endif
+# endif
 }
 
-inline void Registers_riscv::setFloatRegister(int regNum, double value) {
-#if defined(__riscv_flen) && __riscv_flen == 64
+inline void Registers_riscv::setFloatRegister(int regNum, fp_t value) {
+# if defined(__riscv_flen)
   assert(validFloatRegister(regNum));
   _floats[regNum - UNW_RISCV_F0] = value;
-#else
+# else
   (void)regNum;
   (void)value;
   _LIBUNWIND_ABORT("libunwind not built with float support");
-#endif
+# endif
 }
 
 inline bool Registers_riscv::validVectorRegister(int) const {
   return false;
 }
 
 inline v128 Registers_riscv::getVectorRegister(int) const {
   _LIBUNWIND_ABORT("no riscv vector register support yet");

libunwind/src/UnwindRegistersRestore.S

DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
   ldd [%o0 + 96],  %i0
   ldd [%o0 + 104], %i2
   ldd [%o0 + 112], %i4
   ldd [%o0 + 120], %i6
   ld  [%o0 + 60],  %o7
   jmp %o7
    nop
 
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 
 //
 // void libunwind::Registers_riscv::jumpto()
 //
 // On entry:
 //  thread_state pointer is in a0
 //
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
-#if defined(__riscv_flen) && __riscv_flen == 64
-  fld    f0, (8 * 32 + 8 * 0)(a0)
-  fld    f1, (8 * 32 + 8 * 1)(a0)
-  fld    f2, (8 * 32 + 8 * 2)(a0)
-  fld    f3, (8 * 32 + 8 * 3)(a0)
-  fld    f4, (8 * 32 + 8 * 4)(a0)
-  fld    f5, (8 * 32 + 8 * 5)(a0)
-  fld    f6, (8 * 32 + 8 * 6)(a0)
-  fld    f7, (8 * 32 + 8 * 7)(a0)
-  fld    f8, (8 * 32 + 8 * 8)(a0)
-  fld    f9, (8 * 32 + 8 * 9)(a0)
-  fld    f10, (8 * 32 + 8 * 10)(a0)
-  fld    f11, (8 * 32 + 8 * 11)(a0)
-  fld    f12, (8 * 32 + 8 * 12)(a0)
-  fld    f13, (8 * 32 + 8 * 13)(a0)
-  fld    f14, (8 * 32 + 8 * 14)(a0)
-  fld    f15, (8 * 32 + 8 * 15)(a0)
-  fld    f16, (8 * 32 + 8 * 16)(a0)
-  fld    f17, (8 * 32 + 8 * 17)(a0)
-  fld    f18, (8 * 32 + 8 * 18)(a0)
-  fld    f19, (8 * 32 + 8 * 19)(a0)
-  fld    f20, (8 * 32 + 8 * 20)(a0)
-  fld    f21, (8 * 32 + 8 * 21)(a0)
-  fld    f22, (8 * 32 + 8 * 22)(a0)
-  fld    f23, (8 * 32 + 8 * 23)(a0)
-  fld    f24, (8 * 32 + 8 * 24)(a0)
-  fld    f25, (8 * 32 + 8 * 25)(a0)
-  fld    f26, (8 * 32 + 8 * 26)(a0)
-  fld    f27, (8 * 32 + 8 * 27)(a0)
-  fld    f28, (8 * 32 + 8 * 28)(a0)
-  fld    f29, (8 * 32 + 8 * 29)(a0)
-  fld    f30, (8 * 32 + 8 * 30)(a0)
-  fld    f31, (8 * 32 + 8 * 31)(a0)
-#endif
+# if defined(__riscv_flen)
+  FLOAD    f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0)
+  FLOAD    f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0)
+  FLOAD    f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0)
+  FLOAD    f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0)
+  FLOAD    f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0)
+  FLOAD    f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0)
+  FLOAD    f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0)
+  FLOAD    f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0)
+  FLOAD    f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0)
+  FLOAD    f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0)
+  FLOAD    f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0)
+  FLOAD    f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0)
+  FLOAD    f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0)
+  FLOAD    f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0)
+  FLOAD    f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0)
+  FLOAD    f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0)
+  FLOAD    f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0)
+  FLOAD    f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0)
+  FLOAD    f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0)
+  FLOAD    f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0)
+  FLOAD    f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0)
+  FLOAD    f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0)
+  FLOAD    f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0)
+  FLOAD    f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0)
+  FLOAD    f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0)
+  FLOAD    f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0)
+  FLOAD    f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0)
+  FLOAD    f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0)
+  FLOAD    f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0)
+  FLOAD    f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0)
+  FLOAD    f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0)
+  FLOAD    f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0)
+# endif
 
   // x0 is zero
-  ld    x1, (8 * 0)(a0) // restore pc into ra
-  ld    x2, (8 * 2)(a0)
-  ld    x3, (8 * 3)(a0)
-  ld    x4, (8 * 4)(a0)
-  ld    x5, (8 * 5)(a0)
-  ld    x6, (8 * 6)(a0)
-  ld    x7, (8 * 7)(a0)
-  ld    x8, (8 * 8)(a0)
-  ld    x9, (8 * 9)(a0)
+  ILOAD    x1, (RISCV_ISIZE * 0)(a0) // restore pc into ra
+  ILOAD    x2, (RISCV_ISIZE * 2)(a0)
+  ILOAD    x3, (RISCV_ISIZE * 3)(a0)
+  ILOAD    x4, (RISCV_ISIZE * 4)(a0)
+  ILOAD    x5, (RISCV_ISIZE * 5)(a0)
+  ILOAD    x6, (RISCV_ISIZE * 6)(a0)
+  ILOAD    x7, (RISCV_ISIZE * 7)(a0)
+  ILOAD    x8, (RISCV_ISIZE * 8)(a0)
+  ILOAD    x9, (RISCV_ISIZE * 9)(a0)
   // skip a0 for now
-  ld    x11, (8 * 11)(a0)
-  ld    x12, (8 * 12)(a0)
-  ld    x13, (8 * 13)(a0)
-  ld    x14, (8 * 14)(a0)
-  ld    x15, (8 * 15)(a0)
-  ld    x16, (8 * 16)(a0)
-  ld    x17, (8 * 17)(a0)
-  ld    x18, (8 * 18)(a0)
-  ld    x19, (8 * 19)(a0)
-  ld    x20, (8 * 20)(a0)
-  ld    x21, (8 * 21)(a0)
-  ld    x22, (8 * 22)(a0)
-  ld    x23, (8 * 23)(a0)
-  ld    x24, (8 * 24)(a0)
-  ld    x25, (8 * 25)(a0)
-  ld    x26, (8 * 26)(a0)
-  ld    x27, (8 * 27)(a0)
-  ld    x28, (8 * 28)(a0)
-  ld    x29, (8 * 29)(a0)
-  ld    x30, (8 * 30)(a0)
-  ld    x31, (8 * 31)(a0)
-  ld    x10, (8 * 10)(a0)   // restore a0
+  ILOAD    x11, (RISCV_ISIZE * 11)(a0)
+  ILOAD    x12, (RISCV_ISIZE * 12)(a0)
+  ILOAD    x13, (RISCV_ISIZE * 13)(a0)
+  ILOAD    x14, (RISCV_ISIZE * 14)(a0)
+  ILOAD    x15, (RISCV_ISIZE * 15)(a0)
+  ILOAD    x16, (RISCV_ISIZE * 16)(a0)
+  ILOAD    x17, (RISCV_ISIZE * 17)(a0)
+  ILOAD    x18, (RISCV_ISIZE * 18)(a0)
+  ILOAD    x19, (RISCV_ISIZE * 19)(a0)
+  ILOAD    x20, (RISCV_ISIZE * 20)(a0)
+  ILOAD    x21, (RISCV_ISIZE * 21)(a0)
+  ILOAD    x22, (RISCV_ISIZE * 22)(a0)
+  ILOAD    x23, (RISCV_ISIZE * 23)(a0)
+  ILOAD    x24, (RISCV_ISIZE * 24)(a0)
+  ILOAD    x25, (RISCV_ISIZE * 25)(a0)
+  ILOAD    x26, (RISCV_ISIZE * 26)(a0)
+  ILOAD    x27, (RISCV_ISIZE * 27)(a0)
+  ILOAD    x28, (RISCV_ISIZE * 28)(a0)
+  ILOAD    x29, (RISCV_ISIZE * 29)(a0)
+  ILOAD    x30, (RISCV_ISIZE * 30)(a0)
+  ILOAD    x31, (RISCV_ISIZE * 31)(a0)
+  ILOAD    x10, (RISCV_ISIZE * 10)(a0)   // restore a0
 
   ret                       // jump to ra
 
 #endif
 
 #endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
 
 NO_EXEC_STACK_DIRECTIVE
 

libunwind/src/UnwindRegistersSave.S

DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   std %l6, [%o0 +  88]
   std %i0, [%o0 +  96]
   std %i2, [%o0 + 104]
   std %i4, [%o0 + 112]
   std %i6, [%o0 + 120]
   jmp %o7
    clr %o0                   // return UNW_ESUCCESS
 
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 
 #
 # extern int __unw_getcontext(unw_context_t* thread_state)
 #
 # On entry:
 #  thread_state pointer is in a0
 #
 DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
-  sd    x1, (8 * 0)(a0) // store ra as pc
-  sd    x1, (8 * 1)(a0)
-  sd    x2, (8 * 2)(a0)
-  sd    x3, (8 * 3)(a0)
-  sd    x4, (8 * 4)(a0)
-  sd    x5, (8 * 5)(a0)
-  sd    x6, (8 * 6)(a0)
-  sd    x7, (8 * 7)(a0)
-  sd    x8, (8 * 8)(a0)
-  sd    x9, (8 * 9)(a0)
-  sd    x10, (8 * 10)(a0)
-  sd    x11, (8 * 11)(a0)
-  sd    x12, (8 * 12)(a0)
-  sd    x13, (8 * 13)(a0)
-  sd    x14, (8 * 14)(a0)
-  sd    x15, (8 * 15)(a0)
-  sd    x16, (8 * 16)(a0)
-  sd    x17, (8 * 17)(a0)
-  sd    x18, (8 * 18)(a0)
-  sd    x19, (8 * 19)(a0)
-  sd    x20, (8 * 20)(a0)
-  sd    x21, (8 * 21)(a0)
-  sd    x22, (8 * 22)(a0)
-  sd    x23, (8 * 23)(a0)
-  sd    x24, (8 * 24)(a0)
-  sd    x25, (8 * 25)(a0)
-  sd    x26, (8 * 26)(a0)
-  sd    x27, (8 * 27)(a0)
-  sd    x28, (8 * 28)(a0)
-  sd    x29, (8 * 29)(a0)
-  sd    x30, (8 * 30)(a0)
-  sd    x31, (8 * 31)(a0)
-
-#if defined(__riscv_flen) && __riscv_flen == 64
-  fsd    f0, (8 * 32 + 8 * 0)(a0)
-  fsd    f1, (8 * 32 + 8 * 1)(a0)
-  fsd    f2, (8 * 32 + 8 * 2)(a0)
-  fsd    f3, (8 * 32 + 8 * 3)(a0)
-  fsd    f4, (8 * 32 + 8 * 4)(a0)
-  fsd    f5, (8 * 32 + 8 * 5)(a0)
-  fsd    f6, (8 * 32 + 8 * 6)(a0)
-  fsd    f7, (8 * 32 + 8 * 7)(a0)
-  fsd    f8, (8 * 32 + 8 * 8)(a0)
-  fsd    f9, (8 * 32 + 8 * 9)(a0)
-  fsd    f10, (8 * 32 + 8 * 10)(a0)
-  fsd    f11, (8 * 32 + 8 * 11)(a0)
-  fsd    f12, (8 * 32 + 8 * 12)(a0)
-  fsd    f13, (8 * 32 + 8 * 13)(a0)
-  fsd    f14, (8 * 32 + 8 * 14)(a0)
-  fsd    f15, (8 * 32 + 8 * 15)(a0)
-  fsd    f16, (8 * 32 + 8 * 16)(a0)
-  fsd    f17, (8 * 32 + 8 * 17)(a0)
-  fsd    f18, (8 * 32 + 8 * 18)(a0)
-  fsd    f19, (8 * 32 + 8 * 19)(a0)
-  fsd    f20, (8 * 32 + 8 * 20)(a0)
-  fsd    f21, (8 * 32 + 8 * 21)(a0)
-  fsd    f22, (8 * 32 + 8 * 22)(a0)
-  fsd    f23, (8 * 32 + 8 * 23)(a0)
-  fsd    f24, (8 * 32 + 8 * 24)(a0)
-  fsd    f25, (8 * 32 + 8 * 25)(a0)
-  fsd    f26, (8 * 32 + 8 * 26)(a0)
-  fsd    f27, (8 * 32 + 8 * 27)(a0)
-  fsd    f28, (8 * 32 + 8 * 28)(a0)
-  fsd    f29, (8 * 32 + 8 * 29)(a0)
-  fsd    f30, (8 * 32 + 8 * 30)(a0)
-  fsd    f31, (8 * 32 + 8 * 31)(a0)
-#endif
+  ISTORE    x1, (RISCV_ISIZE * 0)(a0) // store ra as pc
+  ISTORE    x1, (RISCV_ISIZE * 1)(a0)
+  ISTORE    x2, (RISCV_ISIZE * 2)(a0)
+  ISTORE    x3, (RISCV_ISIZE * 3)(a0)
+  ISTORE    x4, (RISCV_ISIZE * 4)(a0)
+  ISTORE    x5, (RISCV_ISIZE * 5)(a0)
+  ISTORE    x6, (RISCV_ISIZE * 6)(a0)
+  ISTORE    x7, (RISCV_ISIZE * 7)(a0)
+  ISTORE    x8, (RISCV_ISIZE * 8)(a0)
+  ISTORE    x9, (RISCV_ISIZE * 9)(a0)
+  ISTORE    x10, (RISCV_ISIZE * 10)(a0)
+  ISTORE    x11, (RISCV_ISIZE * 11)(a0)
+  ISTORE    x12, (RISCV_ISIZE * 12)(a0)
+  ISTORE    x13, (RISCV_ISIZE * 13)(a0)
+  ISTORE    x14, (RISCV_ISIZE * 14)(a0)
+  ISTORE    x15, (RISCV_ISIZE * 15)(a0)
+  ISTORE    x16, (RISCV_ISIZE * 16)(a0)
+  ISTORE    x17, (RISCV_ISIZE * 17)(a0)
+  ISTORE    x18, (RISCV_ISIZE * 18)(a0)
+  ISTORE    x19, (RISCV_ISIZE * 19)(a0)
+  ISTORE    x20, (RISCV_ISIZE * 20)(a0)
+  ISTORE    x21, (RISCV_ISIZE * 21)(a0)
+  ISTORE    x22, (RISCV_ISIZE * 22)(a0)
+  ISTORE    x23, (RISCV_ISIZE * 23)(a0)
+  ISTORE    x24, (RISCV_ISIZE * 24)(a0)
+  ISTORE    x25, (RISCV_ISIZE * 25)(a0)
+  ISTORE    x26, (RISCV_ISIZE * 26)(a0)
+  ISTORE    x27, (RISCV_ISIZE * 27)(a0)
+  ISTORE    x28, (RISCV_ISIZE * 28)(a0)
+  ISTORE    x29, (RISCV_ISIZE * 29)(a0)
+  ISTORE    x30, (RISCV_ISIZE * 30)(a0)
+  ISTORE    x31, (RISCV_ISIZE * 31)(a0)
+
+# if defined(__riscv_flen)
+  FSTORE    f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0)
+  FSTORE    f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0)
+  FSTORE    f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0)
+  FSTORE    f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0)
+  FSTORE    f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0)
+  FSTORE    f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0)
+  FSTORE    f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0)
+  FSTORE    f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0)
+  FSTORE    f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0)
+  FSTORE    f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0)
+  FSTORE    f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0)
+  FSTORE    f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0)
+  FSTORE    f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0)
+  FSTORE    f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0)
+  FSTORE    f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0)
+  FSTORE    f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0)
+  FSTORE    f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0)
+  FSTORE    f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0)
+  FSTORE    f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0)
+  FSTORE    f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0)
+  FSTORE    f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0)
+  FSTORE    f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0)
+  FSTORE    f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0)
+  FSTORE    f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0)
+  FSTORE    f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0)
+  FSTORE    f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0)
+  FSTORE    f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0)
+  FSTORE    f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0)
+  FSTORE    f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0)
+  FSTORE    f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0)
+  FSTORE    f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0)
+  FSTORE    f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0)
+# endif
 
   li     a0, 0  // return UNW_ESUCCESS
   ret           // jump to ra
 #endif
 
   WEAK_ALIAS(__unw_getcontext, unw_getcontext)
 
 #endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
 
 NO_EXEC_STACK_DIRECTIVE

libunwind/src/assembly.h

 #define PPC64_OFFS_XER    280
 #define PPC64_OFFS_LR     288
 #define PPC64_OFFS_CTR    296
 #define PPC64_OFFS_VRSAVE 304
 #define PPC64_OFFS_FP     312
 #define PPC64_OFFS_V      824
 #elif defined(__APPLE__) && defined(__aarch64__)
 #define SEPARATOR %%
+#elif defined(__riscv)
+# define RISCV_ISIZE (__riscv_xlen / 8)
+# define RISCV_FOFFSET (RISCV_ISIZE * 32)
+# if defined(__riscv_flen)
+#  define RISCV_FSIZE (__riscv_flen / 8)
+# endif
+
+# if __riscv_xlen == 64
+#  define ILOAD ld
+#  define ISTORE sd
+# elif __riscv_xlen == 32
+#  define ILOAD lw
+#  define ISTORE sw
+# else
+#  error "Unsupported __riscv_xlen"
+# endif
+
+# if defined(__riscv_flen)
+#  if __riscv_flen == 64
+#   define FLOAD fld
+#   define FSTORE fsd
+#  elif __riscv_flen == 32
+#   define FLOAD flw
+#   define FSTORE fsw
+#  else
+#   error "Unsupported __riscv_flen"
+#  endif
+# endif
+# define SEPARATOR ;
 #else
 #define SEPARATOR ;
 #endif
 
 #if defined(__powerpc64__) && (!defined(_CALL_ELF) || _CALL_ELF == 1)
 #define PPC64_OPD1 .section .opd,"aw",@progbits SEPARATOR
 #define PPC64_OPD2 SEPARATOR \
   .p2align 3 SEPARATOR \

libunwind/src/libunwind.cpp

 #elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
 # define REGISTER_KIND Registers_mips_o32
 #elif defined(__mips64)
 # define REGISTER_KIND Registers_mips_newabi
 #elif defined(__mips__)
 # warning The MIPS architecture is not supported with this ABI and environment!
 #elif defined(__sparc__)
 # define REGISTER_KIND Registers_sparc
-#elif defined(__riscv) && __riscv_xlen == 64
+#elif defined(__riscv)
 # define REGISTER_KIND Registers_riscv
 #elif defined(__ve__)
 # define REGISTER_KIND Registers_ve
 #else
 # error Architecture not supported
 #endif
   // Use "placement new" to allocate UnwindCursor in the cursor buffer.
   new (reinterpret_cast<UnwindCursor<LocalAddressSpace, REGISTER_KIND> *>(cursor))