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[RISCV] fixes cross unwinding failure
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Authored by kamleshbhalui on Mar 2 2021, 3:37 AM.

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Summary

https://reviews.llvm.org/D80690 This introduced build failure when LIBUNWIND_ENABLE_CROSS_UNWINDING enabled.
This patch fixes that.

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Event Timeline

kamleshbhalui created this revision.Mar 2 2021, 3:37 AM
Herald added a reviewer: Restricted Project. · View Herald TranscriptMar 2 2021, 3:37 AM
kamleshbhalui requested review of this revision.Mar 2 2021, 3:37 AM
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compnerd accepted this revision.Mar 2 2021, 8:39 AM

Ah right, the !RISCV -> RISCV case. This makes sense to commit to fix the immediate issue.

Thinking about this more, ILP32 is not permitted on RISC-V 64 and ILP-64 is not permitted on RISC-V 32 (which for some reason I had backwards). I think that it would make sense to avoid using RISC-V macros entirely and use __SIZEOF_POINTER__ to select the register width (__SIZEOF_POINTER__ == 8 would mean that we should use uint64_t and a value of 4 would indicate uint32_t). Furthermore, we could then replace the use of __riscv_flen with __SIZEOF_DOUBLE__ to select between float and double for the fpret_t rather than the __riscv_flen. That would completely alleviate having to have 4 different configurations to worry about - {native, x-unwind} * {defined, undefined}.

This revision is now accepted and ready to land.Mar 2 2021, 8:39 AM
This revision was landed with ongoing or failed builds.Mar 2 2021, 3:08 PM
This revision was automatically updated to reflect the committed changes.