[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments

[david-arm]

Summary

In two instances of CreateStackTemporary we are sometimes promoting
alignments beyond the stack alignment. I have introduced a new function
called getReducedAlign that will return the alignment for the broken
down parts of illegal vector types. For example, on NEON a <32 x i8>
type is made up of two <16 x i8> types - in this case the sensible
alignment is 16 bytes, not 32.

In the legalization code wherever we create stack temporaries I have
started using the reduced alignments instead for illegal vector types.

I added a test to

CodeGen/AArch64/build-one-lane.ll

that tries to insert an element into an illegal fixed vector type
that involves creating a temporary stack object.

[arsenm]

See also D29810 and D28920. For AMDGPU there's only pain by using a stack object alignment > 4, so completely ignoring the ABI alignment for stack temporaries is a good option. The stack alignment is chosen to be higher to accommodate common types needing a higher ABI alignment

llvm/test/CodeGen/AMDGPU/scratch-simple.ll

30

I don't understand the new check. This should be either a register with a materialized register, or a constant. Did the total stack usage here increase?

[david-arm]

llvm/test/CodeGen/AMDGPU/scratch-simple.ll

30

I think the stack usage has dropped and the offsets were originally 0x200 and 0x400, but are now 0x80 and 0x280. The problem I found was that the instruction used seemed to differ for each RUN line. That's why my GCN-DAG lines look so horrible! I wasn't sure how best to fix the test, since it seems to be using the stack offsets as a convenient way to test instruction selection.

[david-arm]

ping

[efriedma]

I'm not sure we can really do this, at least not the way it's written.

The behavior of CreateStackTemporary(TypeSize Bytes, Align Alignment) is completely unambiguous; the caller has to decide the size and alignment, and generate other code consistent with that. For the other overloads, the alignment is computed implicitly. The callers then make some assumption about the alignment. If we change the alignment computation, we also have to change the code that uses it. I'm uncomfortable with assuming that a lower alignment is sufficient for all callers.

I recommend changing the six callers in type legalization (LegalizeVectorTypes.cpp, LegalizeTypesGeneric.cpp, LegalizeTypes.cpp, LegalizeIntegerTypes.cpp) to explicitly pass in the right size/alignment. That should be enough to solve the issue you care about without unpredictable side-effects on other code.

[david-arm]

Hi @efriedma, I hope I've addressed your previous comment! I've avoided changing CreateStackTemporary for now and tried to fix up the callers as you suggested.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

893 ↗

(On Diff #268110)

You changed the alignment of the stack temporary... but you still didn't change the alignment of the load or the store to that stack slot, so they're still wrong. (Same applies to other changes.)

[david-arm]

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

893 ↗

(On Diff #268110)

OK fair enough, but previously the code also didn't specify the same alignment chosen by CreateStackTemporary either. So I didn't realise I had to explicitly add the alignment to the loads/stores. My new NEON test now passes with an alignment of 16 bytes, whereas previously it was 32. Since it just worked I assumed that the StackPtr itself contained the alignment, but I can certainly take a look. I don't mind adding the alignments explicitly to the loads and stores at all if that's needed.

[david-arm]

I changed the loads/stores to use the alignment explicitly as it didn't change the behaviour in any way and it's clearer that way.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

893 ↗

(On Diff #268110)

When getStore() etc. is called without an explicit alignment, the alignment is inferred based on VT of the stored value, not the pointer.

If CreateStackTemporary() also computes the alignment based on the VT, it's fine: the resulting alignment is consistent. But if CreateStackTemporary() does something different, then it's inconsistent, and we might miscompile.

We're gradually moving towards deprecating the getStore() variants that don't explicitly specify the alignment because this is confusing.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

1474 ↗

(On Diff #268718)

It would be a good idea to explicitly specify the alignment to the getTruncStore, too. Probably it will be naturally aligned anyway, but better to be safe. Something like commonAlignment(SmallestAlign, EltVT.getSizeInBits() / 8).

2253 ↗

(On Diff #268718)

See above comment about getTruncStore.

[efriedma]

LGTM

[c-rhodes]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2013

NumRegs is producing an unused variable warning

llvm/include/llvm/CodeGen/SelectionDAG.h

public:
   }
 
   /// To be invoked on an SDNode that is slated to be erased. This
   /// function mirrors \c llvm::salvageDebugInfo.
   void salvageDebugInfo(SDNode &N);
 
   void dump() const;
 
+  /// In most cases this function returns the ABI alignment for a given type,
+  /// except for illegal vector types where the alignment exceeds that of the
+  /// stack. In such cases we attempt to break the vector down to a legal type
+  /// and return the ABI alignment for that instead.
+  Align getReducedABIAlign(EVT VT, Type *&Ty);
+
   /// Create a stack temporary based on the size in bytes and the alignment
   SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment);
 
   /// Create a stack temporary, suitable for holding the specified value type.
   /// If minAlign is specified, the slot size will have at least that alignment.
   SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);
 
   /// Create a stack temporary suitable for holding either of the specified

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/DebugInfoMetadata.h"

 }
 
 SDValue SelectionDAG::CreateStackTemporary(TypeSize Bytes, Align Alignment) {
   MachineFrameInfo &MFI = MF->getFrameInfo();
   int FrameIdx = MFI.CreateStackObject(Bytes, Alignment, false);
   return getFrameIndex(FrameIdx, TLI->getFrameIndexTy(getDataLayout()));
 }
 
+Align SelectionDAG::getReducedABIAlign(EVT VT, Type *&Ty) {
+  const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
+  const Align StackAlign = TFI->getStackAlign();
+  const DataLayout &DL = getDataLayout();
+
+  Ty = VT.getTypeForEVT(*getContext());
+  Align ABIAlign = DL.getABITypeAlign(Ty);
+
+  // See if we can choose a smaller ABI alignment in cases where it's an
+  // illegal vector type that will get broken down.
+  if (ABIAlign > StackAlign && VT.isVector() && !TLI->isTypeLegal(VT)) {
+    EVT IntermediateVT;
+    MVT RegisterVT;
+    unsigned NumIntermediates;
+    unsigned NumRegs = TLI->getVectorTypeBreakdown(
+        *getContext(), VT, IntermediateVT, NumIntermediates, RegisterVT);
+    Type *Ty2 = IntermediateVT.getTypeForEVT(*getContext());
+    Align ABIAlign2 = DL.getABITypeAlign(Ty2);
+    if (ABIAlign2 < ABIAlign) {
+      ABIAlign = ABIAlign2;
+      Ty = Ty2;
+    }
+  }
+
+  return ABIAlign;
+}
+
 SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
-  Type *Ty = VT.getTypeForEVT(*getContext());
-  Align StackAlign =
-      std::max(getDataLayout().getPrefTypeAlign(Ty), Align(minAlign));
-  return CreateStackTemporary(VT.getStoreSize(), StackAlign);
+  const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
+  TypeSize Bytes = VT.getStoreSize();
+  Type *Ty;
+
+  // This will return a reduced ABI alignment for vector types when the
+  // type is illegal and the alignment exceeds that of the stack. This
+  // reduces the amount of stack required and also ensures we don't
+  // exceed the permitted alignment for scalable vectors.
+  const Align ABIAlign = getReducedABIAlign(VT, Ty);
+
+  // The preferred alignment will use the reduced vector type returned
+  // from above.
+  const Align PrefAlign = getDataLayout().getPrefTypeAlign(Ty);
+
+  Align Alignment;
+
+  // We only permit preferred alignments if they exceed the ABI
+  // requirement, but do not exceed the stack alignment.
+  if (PrefAlign > ABIAlign && PrefAlign <= TFI->getStackAlign())
+    Alignment = PrefAlign;
+  else
+    Alignment = ABIAlign;
+  Alignment = std::max(Alignment, Align(minAlign));
+  return CreateStackTemporary(Bytes, Alignment);
 }
 
 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
   TypeSize Bytes = std::max(VT1.getStoreSize(), VT2.getStoreSize());
   Type *Ty1 = VT1.getTypeForEVT(*getContext());
   Type *Ty2 = VT2.getTypeForEVT(*getContext());
   const DataLayout &DL = getDataLayout();
   Align Align = std::max(DL.getPrefTypeAlign(Ty1), DL.getPrefTypeAlign(Ty2));

llvm/test/CodeGen/AArch64/build-one-lane.ll

define void @v2f64st(<2 x double>* %p, double %s) nounwind {
   store <2 x double> %v, <2 x double>* %p, align 16
   ret void
 
 ; CHECK-LABEL: v2f64st:
 ; CHECK: fmov v[[R:[0-9]+]].2d, #2.0
 ; CHECK: mov  v[[R]].d[1], v{{[0-9]+}}.d[0]
 ; CHECK: str  q[[R]], [x{{[0-9]+}}]
 }
+
+; In this test the illegal type has a ABI alignment greater than the
+; stack alignment, that gets reduced to the alignment of a broken down
+; legal type.
+define <32 x i8> @test_lanex_32xi8(<32 x i8> %a, i32 %x) {
+; CHECK-LABEL: test_lanex_32xi8
+; CHECK:       stp q0, q1, [sp, #-32]!
+; CHECK:       ldp q0, q1, [sp], #32
+  %b = insertelement <32 x i8> %a, i8 30, i32 %x
+  ret <32 x i8> %b
+}

llvm/test/CodeGen/AMDGPU/scratch-simple.ll

 ; VI-DAG: s_mov_b32 s3, 0xe80000
 ; GFX9-DAG: s_mov_b32 s3, 0xe00000
 ; GFX10_W32-DAG: s_mov_b32 s3, 0x31c16000
 ; GFX10_W64-DAG: s_mov_b32 s3, 0x31e16000
 ; GCN-DAG: v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0
 ; GCN-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, [[BYTES]]
 ; GCN-NOT: s_mov_b32 s0
 
-; GCN-DAG: v_or_b32_e32 [[LO_OFF:v[0-9]+]], 0x200, [[CLAMP_IDX]]
-; GCN-DAG: v_or_b32_e32 [[HI_OFF:v[0-9]+]], 0x400, [[CLAMP_IDX]]
+; GCN-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[HI_OFF:v[0-9]+]],{{.*}} 0x280, [[CLAMP_IDX]]
+; GCN-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]]
 
 ; GCN: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 ; GCN: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 define amdgpu_ps float @ps_main(i32 %idx) {
   %v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
   %v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
   %r = fadd float %v1, %v2
   ret float %r

llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

 ; SI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe8f000
 ; VI-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe80000
 ; GFX9-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe00000
 
 ; OFFREG is offset system SGPR
 ; GCN: buffer_store_dword {{v[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Spill
 ; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], 0 offset:{{[0-9]+}} ; 4-byte Folded Reload
 ; GCN: NumVgprs: 256
-; GCN: ScratchSize: 1536
+; GCN: ScratchSize: 768
 
 define amdgpu_vs void @main([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <4 x i32>] addrspace(4)* inreg %arg2, [34 x <8 x i32>] addrspace(4)* inreg %arg3, [16 x <4 x i32>] addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
 bb:
   %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i64 0, i64 0
   %tmp11 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, align 16, !tbaa !0
   %tmp12 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 0, i32 0)
   %tmp13 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 16, i32 0)
   %tmp14 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp11, i32 32, i32 0)

llvm/test/CodeGen/ARM/combine-vmovdrr.ll

define void @motivatingExample(<2 x i64>* %addr, <8 x i8>* %addr2) {
   %vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i)
   store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2
   ret void
 }
 
 ; Check that we do not perform the transformation for dynamic index.
 ; CHECK-LABEL: dynamicIndex:
 ; CHECK-NOT: mul
-; CHECK: pop
+; CHECK: add sp, #16
 define void @dynamicIndex(<2 x i64>* %addr, <8 x i8>* %addr2, i32 %index) {
   %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr
   %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2
   %shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 %index
   %shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1
   %tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8>
   %tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8>
   %vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i)

llvm/test/CodeGen/ARM/vdup.ll

 }
 
 ; Also make sure we don't barf on variable-index extractelts, where we almost
 ; could have generated a vdup.
 
 define <8 x i8> @check_i8_varidx(<16 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: check_i8_varidx:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    .save {r11}
-; CHECK-NEXT:    push {r11}
-; CHECK-NEXT:    .setfp r11, sp
-; CHECK-NEXT:    mov r11, sp
-; CHECK-NEXT:    .pad #28
-; CHECK-NEXT:    sub sp, sp, #28
-; CHECK-NEXT:    bic sp, sp, #15
-; CHECK-NEXT:    ldr r12, [r11, #4]
+; CHECK-NEXT:    .pad #16
+; CHECK-NEXT:    sub sp, sp, #16
+; CHECK-NEXT:    ldr r12, [sp, #16]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d16, r0, r1
 ; CHECK-NEXT:    mov r1, sp
 ; CHECK-NEXT:    and r0, r12, #15
-; CHECK-NEXT:    vst1.64 {d16, d17}, [r1:128], r0
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r1], r0
 ; CHECK-NEXT:    vld1.8 {d16[]}, [r1]
 ; CHECK-NEXT:    vmov r0, r1, d16
-; CHECK-NEXT:    mov sp, r11
-; CHECK-NEXT:    pop {r11}
+; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    mov pc, lr
   %x = extractelement <16 x i8> %v, i32 %idx
   %1 = insertelement  <8 x i8> undef, i8 %x, i32 0
   %2 = insertelement  <8 x i8> %1, i8 %x, i32 1
   ret <8 x i8> %2
 }

llvm/test/CodeGen/ARM/vstlane.ll

; CHECK-NEXT:    mov pc, lr
   ret void
 }
 
 ; Make sure this doesn't crash; PR10258
 define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
 ; CHECK-LABEL: variable_insertelement:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    push {r11, lr}
-; CHECK-NEXT:    mov r11, sp
-; CHECK-NEXT:    sub sp, sp, #24
-; CHECK-NEXT:    bic sp, sp, #15
-; CHECK-NEXT:    ldr lr, [r11, #12]
+; CHECK-NEXT:    sub sp, sp, #16
+; CHECK-NEXT:    ldr lr, [sp, #28]
 ; CHECK-NEXT:    vmov d17, r2, r3
 ; CHECK-NEXT:    vmov d16, r0, r1
 ; CHECK-NEXT:    mov r1, sp
 ; CHECK-NEXT:    and r0, lr, #7
 ; CHECK-NEXT:    mov r2, r1
-; CHECK-NEXT:    ldrh r12, [r11, #8]
+; CHECK-NEXT:    ldrh r12, [sp, #24]
 ; CHECK-NEXT:    lsl r0, r0, #1
-; CHECK-NEXT:    vst1.64 {d16, d17}, [r2:128], r0
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r2], r0
 ; CHECK-NEXT:    strh r12, [r2]
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r1]
 ; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    vmov r2, r3, d17
-; CHECK-NEXT:    mov sp, r11
+; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
     %r = insertelement <8 x i16> %a, i16 %b, i32 %c
     ret <8 x i16> %r
 }
 
 declare void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
 
 declare void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind

llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 
 define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
 ; CHECK:  lsls r[[ADDR:[0-9]+]], r[[ADDR]], #2
-; CHECK:  vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]:128], r[[ADDR]]
+; CHECK:  vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[SOURCE:[0-9]+]]], r[[ADDR]]
 ; CHECK:  vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32]
 ; CHECK:  vst1.32 {[[DREG]], [[DREG2]]}, [r0]
   %val = extractelement <4 x i32> %phitmp, i32 %lane
   %r1 = insertelement <4 x i32> undef, i32 %val, i32 1
   %r2 = insertelement <4 x i32> %r1, i32 %val, i32 2
   %r3 = insertelement <4 x i32> %r2, i32 %val, i32 3
   store <4 x i32> %r3, <4 x i32>* %p, align 4
   ret void
 }

llvm/test/CodeGen/Thumb2/mve-shuffle.ll

entry:
   %a = load half, half* %aa
   %res = insertelement <8 x half> undef, half %a, i32 0
   ret <8 x half> %res
 }
 
 define arm_aapcs_vfpcc <2 x double> @insert_f64(double %a) {
 ; CHECK-LABEL: insert_f64:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r6, r7, lr}
-; CHECK-NEXT:    push {r4, r6, r7, lr}
-; CHECK-NEXT:    .setfp r7, sp, #8
-; CHECK-NEXT:    add r7, sp, #8
 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
-; CHECK-NEXT:    mov r4, sp
-; CHECK-NEXT:    bfc r4, #0, #4
-; CHECK-NEXT:    mov sp, r4
-; CHECK-NEXT:    sub.w r4, r7, #8
 ; CHECK-NEXT:    vstr d0, [sp]
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    vldrw.u32 q0, [r0]
-; CHECK-NEXT:    mov sp, r4
-; CHECK-NEXT:    pop {r4, r6, r7, pc}
+; CHECK-NEXT:    add sp, #16
+; CHECK-NEXT:    bx lr
 entry:
   %res = insertelement <2 x double> undef, double %a, i32 0
   ret <2 x double> %res
 }
 
 define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
 ; CHECK-LABEL: scalar_to_vector_i32:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/X86/atomic-fp.ll

 ; X86-NOSSE-NEXT:    andl $-8, %esp
 ; X86-NOSSE-NEXT:    subl $32, %esp
 ; X86-NOSSE-NEXT:    movl 8(%ebp), %eax
 ; X86-NOSSE-NEXT:    fildll (%eax)
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    movl %ecx, (%esp)
+; X86-NOSSE-NEXT:    fldl (%esp)
 ; X86-NOSSE-NEXT:    faddl 12(%ebp)
 ; X86-NOSSE-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NOSSE-NEXT:    movl %ecx, (%esp)
+; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fildll (%esp)
+; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll (%eax)
 ; X86-NOSSE-NEXT:    movl %ebp, %esp
 ; X86-NOSSE-NEXT:    popl %ebp
 ; X86-NOSSE-NEXT:    retl
 ;
 ; X86-SSE1-LABEL: fadd_64r:
 ; X86-SSE1:       # %bb.0:
 ; X86-SSE1-NEXT:    pushl %ebp

 ; X86-SSE1-NEXT:    movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
 ; X86-SSE1-NEXT:    movlps %xmm0, (%eax)
 ; X86-SSE1-NEXT:    movl %ebp, %esp
 ; X86-SSE1-NEXT:    popl %ebp
 ; X86-SSE1-NEXT:    retl
 ;
 ; X86-SSE2-LABEL: fadd_64r:
 ; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    andl $-8, %esp
 ; X86-SSE2-NEXT:    subl $8, %esp
-; X86-SSE2-NEXT:    movl 8(%ebp), %eax
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT:    addsd 12(%ebp), %xmm0
+; X86-SSE2-NEXT:    addsd {{[0-9]+}}(%esp), %xmm0
 ; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, (%eax)
-; X86-SSE2-NEXT:    movl %ebp, %esp
-; X86-SSE2-NEXT:    popl %ebp
+; X86-SSE2-NEXT:    addl $8, %esp
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: fadd_64r:
 ; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    pushl %ebp
-; X86-AVX-NEXT:    movl %esp, %ebp
-; X86-AVX-NEXT:    andl $-8, %esp
 ; X86-AVX-NEXT:    subl $8, %esp
-; X86-AVX-NEXT:    movl 8(%ebp), %eax
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT:    vaddsd 12(%ebp), %xmm0, %xmm0
+; X86-AVX-NEXT:    vaddsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; X86-AVX-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, (%eax)
-; X86-AVX-NEXT:    movl %ebp, %esp
-; X86-AVX-NEXT:    popl %ebp
+; X86-AVX-NEXT:    addl $8, %esp
 ; X86-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: fadd_64r:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    addsd (%rdi), %xmm0
 ; X64-SSE-NEXT:    movsd %xmm0, (%rdi)
 ; X64-SSE-NEXT:    retq
 ;

 ; X86-NOSSE-NEXT:    movl %esp, %ebp
 ; X86-NOSSE-NEXT:    andl $-8, %esp
 ; X86-NOSSE-NEXT:    subl $32, %esp
 ; X86-NOSSE-NEXT:    fildll glob64
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    movl %eax, (%esp)
 ; X86-NOSSE-NEXT:    fld1
-; X86-NOSSE-NEXT:    faddl {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    faddl (%esp)
 ; X86-NOSSE-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NOSSE-NEXT:    movl %eax, (%esp)
+; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fildll (%esp)
+; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll glob64
 ; X86-NOSSE-NEXT:    movl %ebp, %esp
 ; X86-NOSSE-NEXT:    popl %ebp
 ; X86-NOSSE-NEXT:    retl
 ;
 ; X86-SSE1-LABEL: fadd_64g:
 ; X86-SSE1:       # %bb.0:
 ; X86-SSE1-NEXT:    pushl %ebp

 ; X86-SSE1-NEXT:    movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
 ; X86-SSE1-NEXT:    movlps %xmm0, glob64
 ; X86-SSE1-NEXT:    movl %ebp, %esp
 ; X86-SSE1-NEXT:    popl %ebp
 ; X86-SSE1-NEXT:    retl
 ;
 ; X86-SSE2-LABEL: fadd_64g:
 ; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    andl $-8, %esp
 ; X86-SSE2-NEXT:    subl $8, %esp
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    addsd {{\.LCPI.*}}, %xmm0
 ; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, glob64
-; X86-SSE2-NEXT:    movl %ebp, %esp
-; X86-SSE2-NEXT:    popl %ebp
+; X86-SSE2-NEXT:    addl $8, %esp
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: fadd_64g:
 ; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    pushl %ebp
-; X86-AVX-NEXT:    movl %esp, %ebp
-; X86-AVX-NEXT:    andl $-8, %esp
 ; X86-AVX-NEXT:    subl $8, %esp
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vaddsd {{\.LCPI.*}}, %xmm0, %xmm0
 ; X86-AVX-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, glob64
-; X86-AVX-NEXT:    movl %ebp, %esp
-; X86-AVX-NEXT:    popl %ebp
+; X86-AVX-NEXT:    addl $8, %esp
 ; X86-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: fadd_64g:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X64-SSE-NEXT:    addsd {{.*}}(%rip), %xmm0
 ; X64-SSE-NEXT:    movsd %xmm0, {{.*}}(%rip)
 ; X64-SSE-NEXT:    retq

 ; X86-NOSSE-NEXT:    movl %esp, %ebp
 ; X86-NOSSE-NEXT:    andl $-8, %esp
 ; X86-NOSSE-NEXT:    subl $32, %esp
 ; X86-NOSSE-NEXT:    fildll -559038737
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    movl %eax, (%esp)
 ; X86-NOSSE-NEXT:    fld1
-; X86-NOSSE-NEXT:    faddl {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    faddl (%esp)
 ; X86-NOSSE-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NOSSE-NEXT:    movl %eax, (%esp)
+; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fildll (%esp)
+; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll -559038737
 ; X86-NOSSE-NEXT:    movl %ebp, %esp
 ; X86-NOSSE-NEXT:    popl %ebp
 ; X86-NOSSE-NEXT:    retl
 ;
 ; X86-SSE1-LABEL: fadd_64imm:
 ; X86-SSE1:       # %bb.0:
 ; X86-SSE1-NEXT:    pushl %ebp

 ; X86-SSE1-NEXT:    movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
 ; X86-SSE1-NEXT:    movlps %xmm0, -559038737
 ; X86-SSE1-NEXT:    movl %ebp, %esp
 ; X86-SSE1-NEXT:    popl %ebp
 ; X86-SSE1-NEXT:    retl
 ;
 ; X86-SSE2-LABEL: fadd_64imm:
 ; X86-SSE2:       # %bb.0:
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    andl $-8, %esp
 ; X86-SSE2-NEXT:    subl $8, %esp
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    addsd {{\.LCPI.*}}, %xmm0
 ; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, -559038737
-; X86-SSE2-NEXT:    movl %ebp, %esp
-; X86-SSE2-NEXT:    popl %ebp
+; X86-SSE2-NEXT:    addl $8, %esp
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: fadd_64imm:
 ; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    pushl %ebp
-; X86-AVX-NEXT:    movl %esp, %ebp
-; X86-AVX-NEXT:    andl $-8, %esp
 ; X86-AVX-NEXT:    subl $8, %esp
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vaddsd {{\.LCPI.*}}, %xmm0, %xmm0
 ; X86-AVX-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, -559038737
-; X86-AVX-NEXT:    movl %ebp, %esp
-; X86-AVX-NEXT:    popl %ebp
+; X86-AVX-NEXT:    addl $8, %esp
 ; X86-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: fadd_64imm:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    movl $3735928559, %eax # imm = 0xDEADBEEF
 ; X64-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X64-SSE-NEXT:    addsd (%rax), %xmm0
 ; X64-SSE-NEXT:    movsd %xmm0, (%rax)

 ; X86-NOSSE-NEXT:    movl %esp, %ebp
 ; X86-NOSSE-NEXT:    andl $-8, %esp
 ; X86-NOSSE-NEXT:    subl $40, %esp
 ; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    movl %eax, (%esp)
 ; X86-NOSSE-NEXT:    fld1
-; X86-NOSSE-NEXT:    faddl {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    faddl (%esp)
 ; X86-NOSSE-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NOSSE-NEXT:    movl %eax, (%esp)
+; X86-NOSSE-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fildll (%esp)
+; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %ebp, %esp
 ; X86-NOSSE-NEXT:    popl %ebp
 ; X86-NOSSE-NEXT:    retl
 ;
 ; X86-SSE1-LABEL: fadd_64stack:
 ; X86-SSE1:       # %bb.0:
 ; X86-SSE1-NEXT:    pushl %ebp

 ; X86-SSE2-LABEL: fadd_64stack:
 ; X86-SSE2:       # %bb.0:
 ; X86-SSE2-NEXT:    pushl %ebp
 ; X86-SSE2-NEXT:    movl %esp, %ebp
 ; X86-SSE2-NEXT:    andl $-8, %esp
 ; X86-SSE2-NEXT:    subl $16, %esp
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    addsd {{\.LCPI.*}}, %xmm0
-; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
+; X86-SSE2-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
+; X86-SSE2-NEXT:    movlps %xmm0, (%esp)
 ; X86-SSE2-NEXT:    movl %ebp, %esp
 ; X86-SSE2-NEXT:    popl %ebp
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: fadd_64stack:
 ; X86-AVX:       # %bb.0:
 ; X86-AVX-NEXT:    pushl %ebp
 ; X86-AVX-NEXT:    movl %esp, %ebp
 ; X86-AVX-NEXT:    andl $-8, %esp
 ; X86-AVX-NEXT:    subl $16, %esp
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vaddsd {{\.LCPI.*}}, %xmm0, %xmm0
-; X86-AVX-NEXT:    vmovsd %xmm0, (%esp)
+; X86-AVX-NEXT:    vmovsd %xmm0, {{[0-9]+}}(%esp)
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
+; X86-AVX-NEXT:    vmovlps %xmm0, (%esp)
 ; X86-AVX-NEXT:    movl %ebp, %esp
 ; X86-AVX-NEXT:    popl %ebp
 ; X86-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: fadd_64stack:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X64-SSE-NEXT:    addsd -{{[0-9]+}}(%rsp), %xmm0

 ; X86-NOSSE-NEXT:    subl $40, %esp
 ; X86-NOSSE-NEXT:    movl 20(%ebp), %eax
 ; X86-NOSSE-NEXT:    movl 8(%ebp), %ecx
 ; X86-NOSSE-NEXT:    fildll (%ecx,%eax,8)
 ; X86-NOSSE-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NOSSE-NEXT:    movl %esi, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fldl {{[0-9]+}}(%esp)
+; X86-NOSSE-NEXT:    movl %edx, (%esp)
+; X86-NOSSE-NEXT:    fldl (%esp)
 ; X86-NOSSE-NEXT:    faddl 12(%ebp)
 ; X86-NOSSE-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-NOSSE-NEXT:    movl %edx, (%esp)
+; X86-NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    movl %esi, {{[0-9]+}}(%esp)
-; X86-NOSSE-NEXT:    fildll (%esp)
+; X86-NOSSE-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X86-NOSSE-NEXT:    fistpll (%ecx,%eax,8)
 ; X86-NOSSE-NEXT:    leal -4(%ebp), %esp
 ; X86-NOSSE-NEXT:    popl %esi
 ; X86-NOSSE-NEXT:    popl %ebp
 ; X86-NOSSE-NEXT:    retl
 ;
 ; X86-SSE1-LABEL: fadd_array:
 ; X86-SSE1:       # %bb.0: # %bb

 ; X86-SSE1-NEXT:    movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
 ; X86-SSE1-NEXT:    movlps %xmm0, (%ecx,%eax,8)
 ; X86-SSE1-NEXT:    movl %ebp, %esp
 ; X86-SSE1-NEXT:    popl %ebp
 ; X86-SSE1-NEXT:    retl
 ;
 ; X86-SSE2-LABEL: fadd_array:
 ; X86-SSE2:       # %bb.0: # %bb
-; X86-SSE2-NEXT:    pushl %ebp
-; X86-SSE2-NEXT:    movl %esp, %ebp
-; X86-SSE2-NEXT:    andl $-8, %esp
 ; X86-SSE2-NEXT:    subl $8, %esp
-; X86-SSE2-NEXT:    movl 20(%ebp), %eax
-; X86-SSE2-NEXT:    movl 8(%ebp), %ecx
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-NEXT:    addsd 12(%ebp), %xmm0
+; X86-SSE2-NEXT:    addsd {{[0-9]+}}(%esp), %xmm0
 ; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, (%ecx,%eax,8)
-; X86-SSE2-NEXT:    movl %ebp, %esp
-; X86-SSE2-NEXT:    popl %ebp
+; X86-SSE2-NEXT:    addl $8, %esp
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: fadd_array:
 ; X86-AVX:       # %bb.0: # %bb
-; X86-AVX-NEXT:    pushl %ebp
-; X86-AVX-NEXT:    movl %esp, %ebp
-; X86-AVX-NEXT:    andl $-8, %esp
 ; X86-AVX-NEXT:    subl $8, %esp
-; X86-AVX-NEXT:    movl 20(%ebp), %eax
-; X86-AVX-NEXT:    movl 8(%ebp), %ecx
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86-AVX-NEXT:    vaddsd 12(%ebp), %xmm0, %xmm0
+; X86-AVX-NEXT:    vaddsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; X86-AVX-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, (%ecx,%eax,8)
-; X86-AVX-NEXT:    movl %ebp, %esp
-; X86-AVX-NEXT:    popl %ebp
+; X86-AVX-NEXT:    addl $8, %esp
 ; X86-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: fadd_array:
 ; X64-SSE:       # %bb.0: # %bb
 ; X64-SSE-NEXT:    addsd (%rdi,%rsi,8), %xmm0
 ; X64-SSE-NEXT:    movsd %xmm0, (%rdi,%rsi,8)
 ; X64-SSE-NEXT:    retq
 ;

llvm/test/CodeGen/X86/atomic-load-store-wide.ll

 ; SSE42-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE42-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE42-NEXT:    movlps %xmm0, (%eax)
 ; SSE42-NEXT:    lock orl $0, (%esp)
 ; SSE42-NEXT:    retl
 ;
 ; NOSSE-LABEL: test1:
 ; NOSSE:       # %bb.0:
-; NOSSE-NEXT:    pushl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_offset 8
-; NOSSE-NEXT:    .cfi_offset %ebp, -8
-; NOSSE-NEXT:    movl %esp, %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_register %ebp
-; NOSSE-NEXT:    andl $-8, %esp
 ; NOSSE-NEXT:    subl $8, %esp
-; NOSSE-NEXT:    movl 8(%ebp), %eax
-; NOSSE-NEXT:    movl 12(%ebp), %ecx
-; NOSSE-NEXT:    movl 16(%ebp), %edx
+; NOSSE-NEXT:    .cfi_def_cfa_offset 12
+; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; NOSSE-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    movl %ecx, (%esp)
 ; NOSSE-NEXT:    fildll (%esp)
 ; NOSSE-NEXT:    fistpll (%eax)
 ; NOSSE-NEXT:    lock orl $0, (%esp)
-; NOSSE-NEXT:    movl %ebp, %esp
-; NOSSE-NEXT:    popl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa %esp, 4
+; NOSSE-NEXT:    addl $8, %esp
+; NOSSE-NEXT:    .cfi_def_cfa_offset 4
 ; NOSSE-NEXT:    retl
   store atomic i64 %val1, i64* %ptr seq_cst, align 8
   ret void
 }
 
 define i64 @test2(i64* %ptr) {
 ; SSE42-LABEL: test2:
 ; SSE42:       # %bb.0:
 ; SSE42-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE42-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; SSE42-NEXT:    movd %xmm0, %eax
 ; SSE42-NEXT:    pextrd $1, %xmm0, %edx
 ; SSE42-NEXT:    retl
 ;
 ; NOSSE-LABEL: test2:
 ; NOSSE:       # %bb.0:
-; NOSSE-NEXT:    pushl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_offset 8
-; NOSSE-NEXT:    .cfi_offset %ebp, -8
-; NOSSE-NEXT:    movl %esp, %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_register %ebp
-; NOSSE-NEXT:    andl $-8, %esp
 ; NOSSE-NEXT:    subl $8, %esp
-; NOSSE-NEXT:    movl 8(%ebp), %eax
+; NOSSE-NEXT:    .cfi_def_cfa_offset 12
+; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE-NEXT:    fildll (%eax)
 ; NOSSE-NEXT:    fistpll (%esp)
 ; NOSSE-NEXT:    movl (%esp), %eax
 ; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; NOSSE-NEXT:    movl %ebp, %esp
-; NOSSE-NEXT:    popl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa %esp, 4
+; NOSSE-NEXT:    addl $8, %esp
+; NOSSE-NEXT:    .cfi_def_cfa_offset 4
 ; NOSSE-NEXT:    retl
   %val = load atomic i64, i64* %ptr seq_cst, align 8
   ret i64 %val
 }
 
 ; Same as test2, but with noimplicitfloat.
 define i64 @test3(i64* %ptr) noimplicitfloat {
 ; CHECK-LABEL: test3:

 ; SSE42-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE42-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; SSE42-NEXT:    movd %xmm0, %eax
 ; SSE42-NEXT:    pextrd $1, %xmm0, %edx
 ; SSE42-NEXT:    retl
 ;
 ; NOSSE-LABEL: test4:
 ; NOSSE:       # %bb.0:
-; NOSSE-NEXT:    pushl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_offset 8
-; NOSSE-NEXT:    .cfi_offset %ebp, -8
-; NOSSE-NEXT:    movl %esp, %ebp
-; NOSSE-NEXT:    .cfi_def_cfa_register %ebp
-; NOSSE-NEXT:    andl $-8, %esp
 ; NOSSE-NEXT:    subl $8, %esp
-; NOSSE-NEXT:    movl 8(%ebp), %eax
+; NOSSE-NEXT:    .cfi_def_cfa_offset 12
+; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE-NEXT:    fildll (%eax)
 ; NOSSE-NEXT:    fistpll (%esp)
 ; NOSSE-NEXT:    movl (%esp), %eax
 ; NOSSE-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; NOSSE-NEXT:    movl %ebp, %esp
-; NOSSE-NEXT:    popl %ebp
-; NOSSE-NEXT:    .cfi_def_cfa %esp, 4
+; NOSSE-NEXT:    addl $8, %esp
+; NOSSE-NEXT:    .cfi_def_cfa_offset 4
 ; NOSSE-NEXT:    retl
   %val = load atomic volatile i64, i64* %ptr seq_cst, align 8
   ret i64 %val
 }

llvm/test/CodeGen/X86/atomic-mi.ll

 define void @store_atomic_imm_64(i64* %p) {
 ; X64-LABEL: store_atomic_imm_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq $42, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: store_atomic_imm_64:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $8, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 12
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl $42, (%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $8, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   These are implemented with a CAS loop on 32 bit architectures, and thus
 ;   cannot be optimized in the same way as the others.
   store atomic i64 42, i64* %p release, align 8
   ret void
 }
 
 ; If an immediate is too big to fit in 32 bits, it cannot be store in one mov,
 ; even on X64, one must use movabsq that can only target a register.
 define void @store_atomic_imm_64_big(i64* %p) {
 ; X64-LABEL: store_atomic_imm_64_big:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movabsq $100000000000, %rax # imm = 0x174876E800
 ; X64-NEXT:    movq %rax, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: store_atomic_imm_64_big:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $8, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 12
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl $23, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl $1215752192, (%esp) # imm = 0x4876E800
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $8, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
   store atomic i64 100000000000, i64* %p monotonic, align 8
   ret void
 }
 
 ; It would be incorrect to replace a lock xchgl by a movl
 define void @store_atomic_imm_32_seq_cst(i32* %p) {
 ; X64-LABEL: store_atomic_imm_32_seq_cst:

 define void @add_64i(i64* %p) {
 ; X64-LABEL: add_64i:
 ; X64:       # %bb.0:
 ; X64-NEXT:    addq $2, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: add_64i:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    addl $2, %ecx
 ; X32-NEXT:    adcl $0, %edx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'addq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = add i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 
 define void @add_64r(i64* %p, i64 %v) {
 ; X64-LABEL: add_64r:
 ; X64:       # %bb.0:
 ; X64-NEXT:    addq %rsi, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: add_64r:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    addl 12(%ebp), %ecx
-; X32-NEXT:    adcl 16(%ebp), %edx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    adcl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'addq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = add i64 %1, %v
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @sub_64r(i64* %p, i64 %v) {
 ; X64-LABEL: sub_64r:
 ; X64:       # %bb.0:
 ; X64-NEXT:    subq %rsi, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: sub_64r:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    subl 12(%ebp), %ecx
-; X32-NEXT:    sbbl 16(%ebp), %edx
+; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    sbbl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'subq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = sub i64 %1, %v
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @and_64i(i64* %p) {
 ; X64-LABEL: and_64i:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andq $2, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: and_64i:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    andl $2, %ecx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'andq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = and i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 
 define void @and_64r(i64* %p, i64 %v) {
 ; X64-LABEL: and_64r:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andq %rsi, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: and_64r:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    andl 16(%ebp), %edx
-; X32-NEXT:    andl 12(%ebp), %ecx
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    andl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'andq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = and i64 %1, %v
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @or_64i(i64* %p) {
 ; X64-LABEL: or_64i:
 ; X64:       # %bb.0:
 ; X64-NEXT:    orq $2, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: or_64i:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    orl $2, %ecx
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'orq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = or i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 
 define void @or_64r(i64* %p, i64 %v) {
 ; X64-LABEL: or_64r:
 ; X64:       # %bb.0:
 ; X64-NEXT:    orq %rsi, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: or_64r:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    orl 16(%ebp), %edx
-; X32-NEXT:    orl 12(%ebp), %ecx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'orq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = or i64 %1, %v
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @xor_64i(i64* %p) {
 ; X64-LABEL: xor_64i:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorq $2, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: xor_64i:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    xorl $2, %ecx
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'xorq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = xor i64 %1, 2
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 
 define void @xor_64r(i64* %p, i64 %v) {
 ; X64-LABEL: xor_64r:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorq %rsi, (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: xor_64r:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    xorl 16(%ebp), %edx
-; X32-NEXT:    xorl 12(%ebp), %ecx
+; X32-NEXT:    xorl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'xorq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = xor i64 %1, %v
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @inc_64(i64* %p) {
 ; FAST_INC-LABEL: inc_64:
 ; FAST_INC:       # %bb.0:
 ; FAST_INC-NEXT:    incq (%rdi)
 ; FAST_INC-NEXT:    retq
 ;
 ; X32-LABEL: inc_64:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    addl $1, %ecx
 ; X32-NEXT:    adcl $0, %edx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; SLOW_INC-LABEL: inc_64:
 ; SLOW_INC:       # %bb.0:
 ; SLOW_INC-NEXT:    addq $1, (%rdi)
 ; SLOW_INC-NEXT:    retq
 ;   We do not check X86-32 as it cannot do 'incq'.
   %1 = load atomic i64, i64* %p acquire, align 8

 define void @dec_64(i64* %p) {
 ; FAST_INC-LABEL: dec_64:
 ; FAST_INC:       # %bb.0:
 ; FAST_INC-NEXT:    decq (%rdi)
 ; FAST_INC-NEXT:    retq
 ;
 ; X32-LABEL: dec_64:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    addl $-1, %ecx
 ; X32-NEXT:    adcl $-1, %edx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; SLOW_INC-LABEL: dec_64:
 ; SLOW_INC:       # %bb.0:
 ; SLOW_INC-NEXT:    addq $-1, (%rdi)
 ; SLOW_INC-NEXT:    retq
 ;   We do not check X86-32 as it cannot do 'decq'.
   %1 = load atomic i64, i64* %p acquire, align 8

 define void @not_64(i64* %p) {
 ; X64-LABEL: not_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    notq (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: not_64:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    notl %edx
 ; X32-NEXT:    notl %ecx
 ; X32-NEXT:    movl %ecx, (%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do not check X86-32 as it cannot do 'notq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = xor i64 %1, -1
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

 define void @neg_64(i64* %p) {
 ; X64-LABEL: neg_64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    negq (%rdi)
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: neg_64:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    .cfi_def_cfa_offset 8
-; X32-NEXT:    .cfi_offset %ebp, -8
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    .cfi_def_cfa_register %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    .cfi_def_cfa_offset 20
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    fildll (%eax)
 ; X32-NEXT:    fistpll {{[0-9]+}}(%esp)
 ; X32-NEXT:    xorl %ecx, %ecx
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    sbbl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl %edx, (%esp)
 ; X32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll (%esp)
 ; X32-NEXT:    fistpll (%eax)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
-; X32-NEXT:    .cfi_def_cfa %esp, 4
+; X32-NEXT:    addl $16, %esp
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;   We do neg check X86-32 as it canneg do 'negq'.
   %1 = load atomic i64, i64* %p acquire, align 8
   %2 = sub i64 0, %1
   store atomic i64 %2, i64* %p release, align 8
   ret void
 }
 

llvm/test/CodeGen/X86/atomic64.ll

 ; X64-LABEL: atomic_fetch_swapf64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %xmm0, %rax
 ; X64-NEXT:    xchgq %rax, {{.*}}(%rip)
 ; X64-NEXT:    retq
 ;
 ; I486-LABEL: atomic_fetch_swapf64:
 ; I486:       # %bb.0:
-; I486-NEXT:    pushl %ebp
-; I486-NEXT:    movl %esp, %ebp
 ; I486-NEXT:    pushl %esi
-; I486-NEXT:    andl $-8, %esp
-; I486-NEXT:    subl $40, %esp
-; I486-NEXT:    fldl 8(%ebp)
+; I486-NEXT:    subl $28, %esp
+; I486-NEXT:    fldl {{[0-9]+}}(%esp)
 ; I486-NEXT:    leal fsc64, %eax
 ; I486-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; I486-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I486-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; I486-NEXT:    movl %esp, %esi
 ; I486-NEXT:    movl %edx, 8(%esi)
 ; I486-NEXT:    movl %ecx, 4(%esi)
 ; I486-NEXT:    movl $2, 12(%esi)
 ; I486-NEXT:    movl $fsc64, (%esi)
 ; I486-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; I486-NEXT:    calll __atomic_exchange_8
-; I486-NEXT:    leal -4(%ebp), %esp
+; I486-NEXT:    addl $28, %esp
 ; I486-NEXT:    popl %esi
-; I486-NEXT:    popl %ebp
 ; I486-NEXT:    retl
   %t1 = atomicrmw xchg double* @fsc64, double %x acquire
   ret void
 }

llvm/test/CodeGen/X86/avx512-insert-extract.ll

 define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
 ; KNL-LABEL: test_insertelement_variable_v96i1:
 ; KNL:       ## %bb.0:
 ; KNL-NEXT:    pushq %rbp
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
-; KNL-NEXT:    andq $-128, %rsp
-; KNL-NEXT:    subq $256, %rsp ## imm = 0x100
+; KNL-NEXT:    andq $-64, %rsp
+; KNL-NEXT:    subq $192, %rsp
 ; KNL-NEXT:    movl 744(%rbp), %eax
 ; KNL-NEXT:    andl $127, %eax
 ; KNL-NEXT:    vmovd %edi, %xmm0
 ; KNL-NEXT:    vpinsrb $1, %esi, %xmm0, %xmm0
 ; KNL-NEXT:    vpinsrb $2, %edx, %xmm0, %xmm0
 ; KNL-NEXT:    vpinsrb $3, %ecx, %xmm0, %xmm0
 ; KNL-NEXT:    vpinsrb $4, %r8d, %xmm0, %xmm0
 ; KNL-NEXT:    vpinsrb $5, %r9d, %xmm0, %xmm0

 ;
 ; SKX-LABEL: test_insertelement_variable_v96i1:
 ; SKX:       ## %bb.0:
 ; SKX-NEXT:    pushq %rbp
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    .cfi_offset %rbp, -16
 ; SKX-NEXT:    movq %rsp, %rbp
 ; SKX-NEXT:    .cfi_def_cfa_register %rbp
-; SKX-NEXT:    andq $-128, %rsp
-; SKX-NEXT:    subq $256, %rsp ## imm = 0x100
+; SKX-NEXT:    andq $-64, %rsp
+; SKX-NEXT:    subq $192, %rsp
 ; SKX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SKX-NEXT:    vpinsrb $1, 232(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $2, 240(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $3, 248(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $4, 256(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $5, 264(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $6, 272(%rbp), %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrb $7, 280(%rbp), %xmm0, %xmm0

 define i128 @test_insertelement_variable_v128i1(<128 x i8> %a, i8 %b, i32 %index) {
 ; KNL-LABEL: test_insertelement_variable_v128i1:
 ; KNL:       ## %bb.0:
 ; KNL-NEXT:    pushq %rbp
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    .cfi_offset %rbp, -16
 ; KNL-NEXT:    movq %rsp, %rbp
 ; KNL-NEXT:    .cfi_def_cfa_register %rbp
-; KNL-NEXT:    andq $-128, %rsp
-; KNL-NEXT:    subq $256, %rsp ## imm = 0x100
+; KNL-NEXT:    andq $-64, %rsp
+; KNL-NEXT:    subq $192, %rsp
 ; KNL-NEXT:    ## kill: def $esi killed $esi def $rsi
 ; KNL-NEXT:    vpxor %xmm2, %xmm2, %xmm2
 ; KNL-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm3
 ; KNL-NEXT:    vpternlogq $15, %zmm3, %zmm3, %zmm3
 ; KNL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0
 ; KNL-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm0
 ; KNL-NEXT:    vpternlogq $15, %zmm0, %zmm0, %zmm0
 ; KNL-NEXT:    vpcmpeqb %ymm2, %ymm1, %ymm4

 ;
 ; SKX-LABEL: test_insertelement_variable_v128i1:
 ; SKX:       ## %bb.0:
 ; SKX-NEXT:    pushq %rbp
 ; SKX-NEXT:    .cfi_def_cfa_offset 16
 ; SKX-NEXT:    .cfi_offset %rbp, -16
 ; SKX-NEXT:    movq %rsp, %rbp
 ; SKX-NEXT:    .cfi_def_cfa_register %rbp
-; SKX-NEXT:    andq $-128, %rsp
-; SKX-NEXT:    subq $256, %rsp ## imm = 0x100
+; SKX-NEXT:    andq $-64, %rsp
+; SKX-NEXT:    subq $192, %rsp
 ; SKX-NEXT:    ## kill: def $esi killed $esi def $rsi
 ; SKX-NEXT:    vptestmb %zmm0, %zmm0, %k0
 ; SKX-NEXT:    vptestmb %zmm1, %zmm1, %k1
 ; SKX-NEXT:    andl $127, %esi
 ; SKX-NEXT:    testb %dil, %dil
 ; SKX-NEXT:    vpmovm2b %k1, %zmm0
 ; SKX-NEXT:    vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
 ; SKX-NEXT:    vpmovm2b %k0, %zmm0

llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

entry:
   %or9.i = or <4 x i32> %shuffle8.i, %or7.i
   %vecext.i = extractelement <4 x i32> %or9.i, i32 0
   ret i32 %vecext.i
 }
 
 define double @test_mm512_reduce_add_pd(<8 x double> %__W) {
 ; X86-LABEL: test_mm512_reduce_add_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X86-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_reduce_add_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X64-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
entry:
   %add7.i = fadd <2 x double> %add4.i, %shuffle6.i
   %vecext.i = extractelement <2 x double> %add7.i, i32 0
   ret double %vecext.i
 }
 
 define double @test_mm512_reduce_mul_pd(<8 x double> %__W) {
 ; X86-LABEL: test_mm512_reduce_mul_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X86-NEXT:    vmulpd %ymm1, %ymm0, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vmulpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_reduce_mul_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X64-NEXT:    vmulpd %ymm1, %ymm0, %ymm0
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
entry:
   %mul8.i = fmul <4 x float> %mul6.i, %shuffle7.i
   %vecext.i = extractelement <4 x float> %mul8.i, i32 0
   ret float %vecext.i
 }
 
 define double @test_mm512_mask_reduce_add_pd(i8 zeroext %__M, <8 x double> %__W) {
 ; X86-LABEL: test_mm512_mask_reduce_add_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    movb 8(%ebp), %al
+; X86-NEXT:    .cfi_def_cfa_offset 12
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    kmovw %eax, %k1
 ; X86-NEXT:    vmovapd %zmm0, %zmm0 {%k1} {z}
 ; X86-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X86-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_mask_reduce_add_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovw %edi, %k1
 ; X64-NEXT:    vmovapd %zmm0, %zmm0 {%k1} {z}
 ; X64-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
entry:
   %add7.i = fadd <2 x double> %add4.i, %shuffle6.i
   %vecext.i = extractelement <2 x double> %add7.i, i32 0
   ret double %vecext.i
 }
 
 define double @test_mm512_mask_reduce_mul_pd(i8 zeroext %__M, <8 x double> %__W) {
 ; X86-LABEL: test_mm512_mask_reduce_mul_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    movb 8(%ebp), %al
+; X86-NEXT:    .cfi_def_cfa_offset 12
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    kmovw %eax, %k1
 ; X86-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; X86-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
 ; X86-NEXT:    vextractf64x4 $1, %zmm1, %ymm0
 ; X86-NEXT:    vmulpd %ymm0, %ymm1, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vmulpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_mask_reduce_mul_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovw %edi, %k1
 ; X64-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; X64-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
entry:
   %5 = select <8 x i1> %4, <8 x i64> %3, <8 x i64> %shuffle3.i
   %vecext.i = extractelement <8 x i64> %5, i32 0
   ret i64 %vecext.i
 }
 
 define double @test_mm512_reduce_max_pd(<8 x double> %__W) {
 ; X86-LABEL: test_mm512_reduce_max_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X86-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_reduce_max_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X64-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
entry:
   %5 = select <8 x i1> %4, <8 x i64> %3, <8 x i64> %shuffle3.i
   %vecext.i = extractelement <8 x i64> %5, i32 0
   ret i64 %vecext.i
 }
 
 define double @test_mm512_reduce_min_pd(<8 x double> %__W) {
 ; X86-LABEL: test_mm512_reduce_min_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X86-NEXT:    vminpd %ymm1, %ymm0, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vminpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vminsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_reduce_min_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
 ; X64-NEXT:    vminpd %ymm1, %ymm0, %ymm0
 ; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
entry:
   %7 = select <8 x i1> %6, <8 x i64> %5, <8 x i64> %shuffle4.i
   %vecext.i = extractelement <8 x i64> %7, i32 0
   ret i64 %vecext.i
 }
 
 define double @test_mm512_mask_reduce_max_pd(i8 zeroext %__M, <8 x double> %__W) {
 ; X86-LABEL: test_mm512_mask_reduce_max_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    movb 8(%ebp), %al
+; X86-NEXT:    .cfi_def_cfa_offset 12
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    kmovw %eax, %k1
 ; X86-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [-Inf,-Inf,-Inf,-Inf,-Inf,-Inf,-Inf,-Inf]
 ; X86-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
 ; X86-NEXT:    vextractf64x4 $1, %zmm1, %ymm0
 ; X86-NEXT:    vmaxpd %ymm0, %ymm1, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_mask_reduce_max_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovw %edi, %k1
 ; X64-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [-Inf,-Inf,-Inf,-Inf,-Inf,-Inf,-Inf,-Inf]
 ; X64-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
entry:
   %7 = select <8 x i1> %6, <8 x i64> %5, <8 x i64> %shuffle5.i
   %vecext.i = extractelement <8 x i64> %7, i32 0
   ret i64 %vecext.i
 }
 
 define double @test_mm512_mask_reduce_min_pd(i8 zeroext %__M, <8 x double> %__W) {
 ; X86-LABEL: test_mm512_mask_reduce_min_pd:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    .cfi_offset %ebp, -8
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    .cfi_def_cfa_register %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    movb 8(%ebp), %al
+; X86-NEXT:    .cfi_def_cfa_offset 12
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    kmovw %eax, %k1
 ; X86-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [+Inf,+Inf,+Inf,+Inf,+Inf,+Inf,+Inf,+Inf]
 ; X86-NEXT:    vmovapd %zmm0, %zmm1 {%k1}
 ; X86-NEXT:    vextractf64x4 $1, %zmm1, %ymm0
 ; X86-NEXT:    vminpd %ymm0, %ymm1, %ymm0
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; X86-NEXT:    vminpd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; X86-NEXT:    vminsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
-; X86-NEXT:    .cfi_def_cfa %esp, 4
+; X86-NEXT:    addl $8, %esp
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm512_mask_reduce_min_pd:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    kmovw %edi, %k1
 ; X64-NEXT:    vbroadcastsd {{.*#+}} zmm1 = [+Inf,+Inf,+Inf,+Inf,+Inf,+Inf,+Inf,+Inf]
 ; X64-NEXT:    vmovapd %zmm0, %zmm1 {%k1}

llvm/test/CodeGen/X86/cmov-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=i686-- -mcpu pentium4 < %s | FileCheck %s -check-prefix=SSE
 ; RUN: llc -mtriple=i686-- -mcpu pentium3 < %s | FileCheck %s -check-prefix=NOSSE2
 ; RUN: llc -mtriple=i686-- -mcpu pentium2 < %s | FileCheck %s -check-prefix=NOSSE1
 ; RUN: llc -mtriple=i686-- -mcpu pentium < %s | FileCheck %s -check-prefix=NOCMOV
 ; PR14035
 
 define double @test1(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test1:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    ja .LBB0_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB0_3
 ; SSE-NEXT:  .LBB0_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB0_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test1:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    flds {{\.LCPI.*}}
; NOCMOV-NEXT:    retl
   %cmp = icmp ugt i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test2(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test2:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jae .LBB1_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB1_3
 ; SSE-NEXT:  .LBB1_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB1_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test2:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    flds {{\.LCPI.*}}
; NOCMOV-NEXT:    retl
   %cmp = icmp uge i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test3(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test3:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jb .LBB2_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB2_3
 ; SSE-NEXT:  .LBB2_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB2_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test3:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    flds {{\.LCPI.*}}
; NOCMOV-NEXT:    retl
   %cmp = icmp ult i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test4(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test4:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jbe .LBB3_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB3_3
 ; SSE-NEXT:  .LBB3_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB3_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test4:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    flds {{\.LCPI.*}}
; NOCMOV-NEXT:    retl
   %cmp = icmp ule i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test5(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test5:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jg .LBB4_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB4_3
 ; SSE-NEXT:  .LBB4_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB4_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test5:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    setg %al
; NOCMOV-NEXT:    retl
   %cmp = icmp sgt i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test6(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test6:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jge .LBB5_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB5_3
 ; SSE-NEXT:  .LBB5_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB5_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test6:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    setge %al
; NOCMOV-NEXT:    retl
   %cmp = icmp sge i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test7(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test7:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jl .LBB6_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB6_3
 ; SSE-NEXT:  .LBB6_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB6_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test7:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    setl %al
; NOCMOV-NEXT:    retl
   %cmp = icmp slt i32 %a, %b
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 }
 
 define double @test8(i32 %a, i32 %b, double %x) nounwind {
 ; SSE-LABEL: test8:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushl %ebp
-; SSE-NEXT:    movl %esp, %ebp
-; SSE-NEXT:    andl $-8, %esp
 ; SSE-NEXT:    subl $8, %esp
-; SSE-NEXT:    movl 8(%ebp), %eax
-; SSE-NEXT:    cmpl 12(%ebp), %eax
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    jle .LBB7_1
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    jmp .LBB7_3
 ; SSE-NEXT:  .LBB7_1:
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:  .LBB7_3:
 ; SSE-NEXT:    movsd %xmm0, (%esp)
 ; SSE-NEXT:    fldl (%esp)
-; SSE-NEXT:    movl %ebp, %esp
-; SSE-NEXT:    popl %ebp
+; SSE-NEXT:    addl $8, %esp
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test8:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldl {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOSSE2-NEXT:    setle %al

llvm/test/CodeGen/X86/deopt-bundles.ll

define void @f_0(i64 %n) {
   call void @g_0(i64* %vl) [ "deopt"(i64* %s) ]
   ret void
 }
 
 declare void @g_0(i64* %vl)
 
 define void @vector_deopt_bundle(<32 x i64 addrspace(1)*> %val) {
 ; CHECK-LABEL: _vector_deopt_bundle:
-; CHECK: movaps  16(%rbp), %xmm8
-; CHECK-NEXT: movaps  32(%rbp), %xmm9
-; CHECK-NEXT: movaps  48(%rbp), %xmm10
-; CHECK-NEXT: movaps  64(%rbp), %xmm11
-; CHECK-NEXT: movaps  80(%rbp), %xmm12
-; CHECK-NEXT: movaps  96(%rbp), %xmm13
-; CHECK-NEXT: movaps  112(%rbp), %xmm14
-; CHECK-NEXT: movaps  128(%rbp), %xmm15
+; CHECK: movaps  272(%rsp), %xmm8
+; CHECK-NEXT: movaps  288(%rsp), %xmm9
+; CHECK-NEXT: movaps  304(%rsp), %xmm10
+; CHECK-NEXT: movaps  320(%rsp), %xmm11
+; CHECK-NEXT: movaps  336(%rsp), %xmm12
+; CHECK-NEXT: movaps  352(%rsp), %xmm13
+; CHECK-NEXT: movaps  368(%rsp), %xmm14
+; CHECK-NEXT: movaps  384(%rsp), %xmm15
 ; CHECK-NEXT: movaps  %xmm15, 240(%rsp)
 ; CHECK-NEXT: movaps  %xmm14, 224(%rsp)
 ; CHECK-NEXT: movaps  %xmm13, 208(%rsp)
 ; CHECK-NEXT: movaps  %xmm12, 192(%rsp)
 ; CHECK-NEXT: movaps  %xmm11, 176(%rsp)
 ; CHECK-NEXT: movaps  %xmm10, 160(%rsp)
 ; CHECK-NEXT: movaps  %xmm9, 144(%rsp)
 ; CHECK-NEXT: movaps  %xmm8, 128(%rsp)

llvm/test/CodeGen/X86/extractelement-fp.ll

 ; X64-NEXT:    vmovddup {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
 ; X64-NEXT:    # xmm1 = mem[0,0]
 ; X64-NEXT:    vxorps %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fneg_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vmovddup {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0]
 ; X86-NEXT:    # xmm1 = mem[0,0]
 ; X86-NEXT:    vxorps %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovlps %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = fneg <4 x double> %x
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fadd_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: fadd_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fadd_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = fadd <4 x double> %x, %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fsub_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: fsub_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fsub_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = fsub <4 x double> %x, %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fmul_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: fmul_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fmul_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = fmul <4 x double> %x, %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fdiv_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: fdiv_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fdiv_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = fdiv <4 x double> %x, %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @frem_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: fsqrt_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fsqrt_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fsin_v4f32(<4 x float> %x) nounwind {

 ; X64:       # %bb.0:
 ; X64-NEXT:    vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; X64-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fma_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vfmadd213sd {{.*#+}} xmm1 = (xmm0 * xmm1) + xmm2
 ; X86-NEXT:    vmovsd %xmm1, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %z)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fabs_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: fabs_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fabs_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vandps {{\.LCPI.*}}, %xmm0, %xmm0
 ; X86-NEXT:    vmovlps %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fmaxnum_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-NEXT:    vmaxsd %xmm0, %xmm1, %xmm2
 ; X64-NEXT:    vcmpunordsd %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fmaxnum_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vmaxsd %xmm0, %xmm1, %xmm2
 ; X86-NEXT:    vcmpunordsd %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
 ; X86-NEXT:    vmovlpd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %x, <4 x double> %y)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @fminnum_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-NEXT:    vminsd %xmm0, %xmm1, %xmm2
 ; X64-NEXT:    vcmpunordsd %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: fminnum_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vminsd %xmm0, %xmm1, %xmm2
 ; X86-NEXT:    vcmpunordsd %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
 ; X86-NEXT:    vmovlpd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.minnum.v4f64(<4 x double> %x, <4 x double> %y)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 ;define float @fmaximum_v4f32(<4 x float> %x, <4 x float> %y) nounwind {

 ; X64-LABEL: maxpd_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: maxpd_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %cmp = fcmp ogt <4 x double> %x, %y
   %v = select <4 x i1> %cmp, <4 x double> %x, <4 x double> %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 

 ; X64-LABEL: minpd_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vminsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: minpd_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vminsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %cmp = fcmp olt <4 x double> %x, %y
   %v = select <4 x i1> %cmp, <4 x double> %x, <4 x double> %y
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 

 ; X64-NEXT:    vandps {{.*}}(%rip), %xmm1, %xmm1
 ; X64-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
 ; X64-NEXT:    vorps %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: copysign_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vandps {{\.LCPI.*}}, %xmm1, %xmm1
 ; X86-NEXT:    vandps {{\.LCPI.*}}, %xmm0, %xmm0
 ; X86-NEXT:    vorps %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vmovlps %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %y)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @floor_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: floor_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: floor_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.floor.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @ceil_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: ceil_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: ceil_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @trunc_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: trunc_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: trunc_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.trunc.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @rint_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: rint_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: rint_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.rint.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @nearbyint_v4f32(<4 x float> %x) nounwind {

 ; X64-LABEL: nearbyint_v4f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: nearbyint_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @round_v4f32(<4 x float> %x) nounwind {

 ; X64-NEXT:    vorpd %xmm1, %xmm2, %xmm1
 ; X64-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: round_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
 ; X86-NEXT:    vandpd {{\.LCPI.*}}, %xmm0, %xmm1
 ; X86-NEXT:    vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
 ; X86-NEXT:    # xmm2 = mem[0,0]
 ; X86-NEXT:    vorpd %xmm1, %xmm2, %xmm1
 ; X86-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; X86-NEXT:    vmovsd %xmm0, (%esp)
 ; X86-NEXT:    fldl (%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
   %v = call <4 x double> @llvm.round.v4f64(<4 x double> %x)
   %r = extractelement <4 x double> %v, i32 0
   ret double %r
 }
 
 define float @rcp_v4f32(<4 x float> %x) nounwind {

llvm/test/CodeGen/X86/extractelement-index.ll

 ; AVX-NEXT:    retq
   %b = extractelement <16 x i8> %a, i256 %i
   ret i8 %b
 }
 
 define i8 @extractelement_v32i8_var(<32 x i8> %a, i256 %i) nounwind {
 ; SSE-LABEL: extractelement_v32i8_var:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    andl $31, %edi
-; SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movaps %xmm0, (%rsp)
-; SSE-NEXT:    movb (%rsp,%rdi), %al
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movb -40(%rsp,%rdi), %al
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v32i8_var:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    pushq %rbp
 ; AVX-NEXT:    movq %rsp, %rbp
 ; AVX-NEXT:    andq $-32, %rsp
 ; AVX-NEXT:    subq $64, %rsp

 ; AVX-NEXT:    retq
   %b = extractelement <8 x i16> %a, i256 %i
   ret i16 %b
 }
 
 define i16 @extractelement_v16i16_var(<16 x i16> %a, i256 %i) nounwind {
 ; SSE-LABEL: extractelement_v16i16_var:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    andl $15, %edi
-; SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movaps %xmm0, (%rsp)
-; SSE-NEXT:    movzwl (%rsp,%rdi,2), %eax
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movzwl -40(%rsp,%rdi,2), %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v16i16_var:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    pushq %rbp
 ; AVX-NEXT:    movq %rsp, %rbp
 ; AVX-NEXT:    andq $-32, %rsp
 ; AVX-NEXT:    subq $64, %rsp

 ; AVX-NEXT:    retq
   %b = extractelement <4 x i32> %a, i256 %i
   ret i32 %b
 }
 
 define i32 @extractelement_v8i32_var(<8 x i32> %a, i256 %i) nounwind {
 ; SSE-LABEL: extractelement_v8i32_var:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    andl $7, %edi
-; SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movaps %xmm0, (%rsp)
-; SSE-NEXT:    movl (%rsp,%rdi,4), %eax
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movl -40(%rsp,%rdi,4), %eax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v8i32_var:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    pushq %rbp
 ; AVX-NEXT:    movq %rsp, %rbp
 ; AVX-NEXT:    andq $-32, %rsp
 ; AVX-NEXT:    subq $64, %rsp

 ; AVX-NEXT:    retq
   %b = extractelement <2 x i64> %a, i256 %i
   ret i64 %b
 }
 
 define i64 @extractelement_v4i64_var(<4 x i64> %a, i256 %i) nounwind {
 ; SSE-LABEL: extractelement_v4i64_var:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    andl $3, %edi
-; SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movaps %xmm0, (%rsp)
-; SSE-NEXT:    movq (%rsp,%rdi,8), %rax
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE-NEXT:    movq -40(%rsp,%rdi,8), %rax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v4i64_var:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    pushq %rbp
 ; AVX-NEXT:    movq %rsp, %rbp
 ; AVX-NEXT:    andq $-32, %rsp
 ; AVX-NEXT:    subq $64, %rsp

llvm/test/CodeGen/X86/fast-isel-fneg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 | FileCheck %s
 ; RUN: llc < %s -fast-isel -mtriple=i686-- -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
 
 define double @doo(double %x) nounwind {
 ; CHECK-LABEL: doo:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movq %xmm0, %rax
 ; CHECK-NEXT:    movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
 ; CHECK-NEXT:    xorq %rax, %rcx
 ; CHECK-NEXT:    movq %rcx, %xmm0
 ; CHECK-NEXT:    retq
 ;
 ; SSE2-LABEL: doo:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pushl %ebp
-; SSE2-NEXT:    movl %esp, %ebp
-; SSE2-NEXT:    andl $-8, %esp
 ; SSE2-NEXT:    subl $8, %esp
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2-NEXT:    xorps {{\.LCPI.*}}, %xmm0
 ; SSE2-NEXT:    movlps %xmm0, (%esp)
 ; SSE2-NEXT:    fldl (%esp)
-; SSE2-NEXT:    movl %ebp, %esp
-; SSE2-NEXT:    popl %ebp
+; SSE2-NEXT:    addl $8, %esp
 ; SSE2-NEXT:    retl
   %y = fsub double -0.0, %x
   ret double %y
 }
 
 define float @foo(float %x) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       ## %bb.0:

 ; CHECK-NEXT:    movq %xmm0, %rax
 ; CHECK-NEXT:    movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
 ; CHECK-NEXT:    xorq %rax, %rcx
 ; CHECK-NEXT:    movq %rcx, %xmm0
 ; CHECK-NEXT:    retq
 ;
 ; SSE2-LABEL: too:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pushl %ebp
-; SSE2-NEXT:    movl %esp, %ebp
-; SSE2-NEXT:    andl $-8, %esp
 ; SSE2-NEXT:    subl $8, %esp
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2-NEXT:    xorps {{\.LCPI.*}}, %xmm0
 ; SSE2-NEXT:    movlps %xmm0, (%esp)
 ; SSE2-NEXT:    fldl (%esp)
-; SSE2-NEXT:    movl %ebp, %esp
-; SSE2-NEXT:    popl %ebp
+; SSE2-NEXT:    addl $8, %esp
 ; SSE2-NEXT:    retl
   %y = fneg double %x
   ret double %y
 }
 
 define float @zoo(float %x) nounwind {
 ; CHECK-LABEL: zoo:
 ; CHECK:       ## %bb.0:

llvm/test/CodeGen/X86/fast-isel-int-float-conversion.ll

 ;
 ; AVX-LABEL: int_to_double_rr:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; SSE2_X86-LABEL: int_to_double_rr:
 ; SSE2_X86:       # %bb.0: # %entry
-; SSE2_X86-NEXT:    pushl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE2_X86-NEXT:    .cfi_offset %ebp, -8
-; SSE2_X86-NEXT:    movl %esp, %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE2_X86-NEXT:    andl $-8, %esp
 ; SSE2_X86-NEXT:    subl $8, %esp
-; SSE2_X86-NEXT:    cvtsi2sdl 8(%ebp), %xmm0
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE2_X86-NEXT:    cvtsi2sdl {{[0-9]+}}(%esp), %xmm0
 ; SSE2_X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE2_X86-NEXT:    fldl (%esp)
-; SSE2_X86-NEXT:    movl %ebp, %esp
-; SSE2_X86-NEXT:    popl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE2_X86-NEXT:    addl $8, %esp
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE2_X86-NEXT:    retl
 ;
 ; AVX_X86-LABEL: int_to_double_rr:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    vcvtsi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = sitofp i32 %a to double
   ret double %0
 }
 
 define double @int_to_double_rm(i32* %a) {
 ; SSE2-LABEL: int_to_double_rm:
 ; SSE2:       # %bb.0: # %entry
 ; SSE2-NEXT:    cvtsi2sdl (%rdi), %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: int_to_double_rm:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtsi2sdl (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; SSE2_X86-LABEL: int_to_double_rm:
 ; SSE2_X86:       # %bb.0: # %entry
-; SSE2_X86-NEXT:    pushl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE2_X86-NEXT:    .cfi_offset %ebp, -8
-; SSE2_X86-NEXT:    movl %esp, %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE2_X86-NEXT:    andl $-8, %esp
 ; SSE2_X86-NEXT:    subl $8, %esp
-; SSE2_X86-NEXT:    movl 8(%ebp), %eax
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE2_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE2_X86-NEXT:    cvtsi2sdl (%eax), %xmm0
 ; SSE2_X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE2_X86-NEXT:    fldl (%esp)
-; SSE2_X86-NEXT:    movl %ebp, %esp
-; SSE2_X86-NEXT:    popl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE2_X86-NEXT:    addl $8, %esp
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE2_X86-NEXT:    retl
 ;
 ; AVX_X86-LABEL: int_to_double_rm:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    movl 8(%ebp), %eax
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX_X86-NEXT:    vcvtsi2sdl (%eax), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = load i32, i32* %a
   %1 = sitofp i32 %0 to double
   ret double %1
 }
 
 define double @int_to_double_rm_optsize(i32* %a) optsize {
 ; SSE2-LABEL: int_to_double_rm_optsize:
 ; SSE2:       # %bb.0: # %entry
 ; SSE2-NEXT:    cvtsi2sdl (%rdi), %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: int_to_double_rm_optsize:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtsi2sdl (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; SSE2_X86-LABEL: int_to_double_rm_optsize:
 ; SSE2_X86:       # %bb.0: # %entry
-; SSE2_X86-NEXT:    pushl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE2_X86-NEXT:    .cfi_offset %ebp, -8
-; SSE2_X86-NEXT:    movl %esp, %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE2_X86-NEXT:    andl $-8, %esp
 ; SSE2_X86-NEXT:    subl $8, %esp
-; SSE2_X86-NEXT:    movl 8(%ebp), %eax
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE2_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE2_X86-NEXT:    cvtsi2sdl (%eax), %xmm0
 ; SSE2_X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE2_X86-NEXT:    fldl (%esp)
-; SSE2_X86-NEXT:    movl %ebp, %esp
-; SSE2_X86-NEXT:    popl %ebp
-; SSE2_X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE2_X86-NEXT:    addl $8, %esp
+; SSE2_X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE2_X86-NEXT:    retl
 ;
 ; AVX_X86-LABEL: int_to_double_rm_optsize:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    movl 8(%ebp), %eax
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX_X86-NEXT:    vcvtsi2sdl (%eax), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = load i32, i32* %a
   %1 = sitofp i32 %0 to double
   ret double %1
 }
 
 define float @int_to_float_rr(i32 %a) {

llvm/test/CodeGen/X86/fast-isel-uint-float-conversion.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
 ; RUN: llc -verify-machineinstrs -mtriple=i686-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX_X86
 
 
 define double @int_to_double_rr(i32 %a) {
 ; AVX-LABEL: int_to_double_rr:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtusi2sd %edi, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; AVX_X86-LABEL: int_to_double_rr:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    vcvtusi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    vcvtusi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = uitofp i32 %a to double
   ret double %0
 }
 
 define double @int_to_double_rm(i32* %a) {
 ; AVX-LABEL: int_to_double_rm:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtusi2sdl (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; AVX_X86-LABEL: int_to_double_rm:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    movl 8(%ebp), %eax
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX_X86-NEXT:    vcvtusi2sdl (%eax), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = load i32, i32* %a
   %1 = uitofp i32 %0 to double
   ret double %1
 }
 
 define double @int_to_double_rm_optsize(i32* %a) optsize {
 ; AVX-LABEL: int_to_double_rm_optsize:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vcvtusi2sdl (%rdi), %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
 ; AVX_X86-LABEL: int_to_double_rm_optsize:
 ; AVX_X86:       # %bb.0: # %entry
-; AVX_X86-NEXT:    pushl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX_X86-NEXT:    .cfi_offset %ebp, -8
-; AVX_X86-NEXT:    movl %esp, %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX_X86-NEXT:    andl $-8, %esp
 ; AVX_X86-NEXT:    subl $8, %esp
-; AVX_X86-NEXT:    movl 8(%ebp), %eax
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX_X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX_X86-NEXT:    vcvtusi2sdl (%eax), %xmm0, %xmm0
 ; AVX_X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX_X86-NEXT:    fldl (%esp)
-; AVX_X86-NEXT:    movl %ebp, %esp
-; AVX_X86-NEXT:    popl %ebp
-; AVX_X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX_X86-NEXT:    addl $8, %esp
+; AVX_X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX_X86-NEXT:    retl
 entry:
   %0 = load i32, i32* %a
   %1 = uitofp i32 %0 to double
   ret double %1
 }
 
 define float @int_to_float_rr(i32 %a) {

llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll

%result = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret float %result
 }
 
 define double @sitofp_i8tof64(i8 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i8tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movsbl 8(%ebp), %eax
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i8tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movsbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i8tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    movsbl 8(%ebp), %eax
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i8tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movsbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
%result = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @sitofp_i16tof64(i16 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i16tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movswl 8(%ebp), %eax
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i16tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movswl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i16tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    movswl 8(%ebp), %eax
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i16tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movswl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
%result = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @sitofp_i32tof64(i32 %x) #0 {
 ; SSE-X86-LABEL: sitofp_i32tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    cvtsi2sdl 8(%ebp), %xmm0
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    cvtsi2sdl {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: sitofp_i32tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    cvtsi2sd %edi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: sitofp_i32tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    vcvtsi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: sitofp_i32tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: sitofp_i32tof64:
%result = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i1tof64(i1 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i1tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movb 8(%ebp), %al
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; SSE-X86-NEXT:    andb $1, %al
 ; SSE-X86-NEXT:    movzbl %al, %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i1tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    andl $1, %edi
 ; SSE-X64-NEXT:    cvtsi2sd %edi, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i1tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    movb 8(%ebp), %al
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; AVX-X86-NEXT:    andb $1, %al
 ; AVX-X86-NEXT:    movzbl %al, %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i1tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    andl $1, %edi
 ; AVX-X64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
%result = call double @llvm.experimental.constrained.uitofp.f64.i1(i1 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i8tof64(i8 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i8tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movzbl 8(%ebp), %eax
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i8tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzbl %dil, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i8tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    movzbl 8(%ebp), %eax
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i8tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzbl %dil, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
%result = call double @llvm.experimental.constrained.uitofp.f64.i8(i8 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i16tof64(i16 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i16tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
-; SSE-X86-NEXT:    movzwl 8(%ebp), %eax
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
+; SSE-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; SSE-X86-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i16tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movzwl %di, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %eax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i16tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
-; AVX-X86-NEXT:    movzwl 8(%ebp), %eax
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX-X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; AVX-X86-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: uitofp_i16tof64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    movzwl %di, %eax
 ; AVX-X64-NEXT:    vcvtsi2sd %eax, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
%result = call double @llvm.experimental.constrained.uitofp.f64.i16(i16 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i32tof64(i32 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i32tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-X86-NEXT:    orpd %xmm0, %xmm1
 ; SSE-X86-NEXT:    subsd %xmm0, %xmm1
 ; SSE-X86-NEXT:    movsd %xmm1, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i32tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movl %edi, %eax
 ; SSE-X64-NEXT:    cvtsi2sd %rax, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX1-X86-LABEL: uitofp_i32tof64:
 ; AVX1-X86:       # %bb.0:
-; AVX1-X86-NEXT:    pushl %ebp
-; AVX1-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX1-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX1-X86-NEXT:    movl %esp, %ebp
-; AVX1-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX1-X86-NEXT:    andl $-8, %esp
 ; AVX1-X86-NEXT:    subl $8, %esp
+; AVX1-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX1-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX1-X86-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; AVX1-X86-NEXT:    vorpd %xmm0, %xmm1, %xmm1
 ; AVX1-X86-NEXT:    vsubsd %xmm0, %xmm1, %xmm0
 ; AVX1-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX1-X86-NEXT:    fldl (%esp)
 ; AVX1-X86-NEXT:    wait
-; AVX1-X86-NEXT:    movl %ebp, %esp
-; AVX1-X86-NEXT:    popl %ebp
-; AVX1-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX1-X86-NEXT:    addl $8, %esp
+; AVX1-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX1-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i32tof64:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    movl %edi, %eax
 ; AVX1-X64-NEXT:    vcvtsi2sd %rax, %xmm0, %xmm0
 ; AVX1-X64-NEXT:    retq
 ;
 ; AVX512-X86-LABEL: uitofp_i32tof64:
 ; AVX512-X86:       # %bb.0:
-; AVX512-X86-NEXT:    pushl %ebp
-; AVX512-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX512-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX512-X86-NEXT:    movl %esp, %ebp
-; AVX512-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX512-X86-NEXT:    andl $-8, %esp
 ; AVX512-X86-NEXT:    subl $8, %esp
-; AVX512-X86-NEXT:    vcvtusi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX512-X86-NEXT:    .cfi_def_cfa_offset 12
+; AVX512-X86-NEXT:    vcvtusi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512-X86-NEXT:    fldl (%esp)
 ; AVX512-X86-NEXT:    wait
-; AVX512-X86-NEXT:    movl %ebp, %esp
-; AVX512-X86-NEXT:    popl %ebp
-; AVX512-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX512-X86-NEXT:    addl $8, %esp
+; AVX512-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512-X86-NEXT:    retl
 ;
 ; AVX512-X64-LABEL: uitofp_i32tof64:
 ; AVX512-X64:       # %bb.0:
 ; AVX512-X64-NEXT:    vcvtusi2sd %edi, %xmm0, %xmm0
 ; AVX512-X64-NEXT:    retq
 ;
 ; X87-LABEL: uitofp_i32tof64:
%result = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret double %result
 }
 
 define double @uitofp_i64tof64(i64 %x) #0 {
 ; SSE-X86-LABEL: uitofp_i64tof64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; SSE-X86-NEXT:    subpd {{\.LCPI.*}}, %xmm0
 ; SSE-X86-NEXT:    movapd %xmm0, %xmm1
 ; SSE-X86-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; SSE-X86-NEXT:    addpd %xmm0, %xmm1
 ; SSE-X86-NEXT:    movlpd %xmm1, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $8, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: uitofp_i64tof64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    movq %rdi, %xmm1
 ; SSE-X64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
 ; SSE-X64-NEXT:    subpd {{.*}}(%rip), %xmm1
 ; SSE-X64-NEXT:    movapd %xmm1, %xmm0
 ; SSE-X64-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
 ; SSE-X64-NEXT:    addpd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: uitofp_i64tof64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX-X86-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; AVX-X86-NEXT:    vaddpd %xmm0, %xmm1, %xmm0
 ; AVX-X86-NEXT:    vmovlpd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX1-X64-LABEL: uitofp_i64tof64:
 ; AVX1-X64:       # %bb.0:
 ; AVX1-X64-NEXT:    vmovq %rdi, %xmm0
 ; AVX1-X64-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX1-X64-NEXT:    vsubpd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX1-X64-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]

llvm/test/CodeGen/X86/fp-strict-scalar-round.ll

; AVX-X64-NEXT:    retq
   %res = call float @llvm.experimental.constrained.ceil.f32(
                         float %f, metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @fceilf64(double %f) #0 {
 ; SSE41-X86-LABEL: fceilf64:
 ; SSE41-X86:       # %bb.0:
-; SSE41-X86-NEXT:    pushl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE41-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE41-X86-NEXT:    movl %esp, %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $10, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
 ; SSE41-X86-NEXT:    wait
-; SSE41-X86-NEXT:    movl %ebp, %esp
-; SSE41-X86-NEXT:    popl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE41-X86-NEXT:    addl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fceilf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $10, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fceilf64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fceilf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $10, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.ceil.f64(
                         double %f, metadata !"fpexcept.strict")
; AVX-X64-NEXT:    retq
   %res = call float @llvm.experimental.constrained.floor.f32(
                         float %f, metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @ffloorf64(double %f) #0 {
 ; SSE41-X86-LABEL: ffloorf64:
 ; SSE41-X86:       # %bb.0:
-; SSE41-X86-NEXT:    pushl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE41-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE41-X86-NEXT:    movl %esp, %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $9, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
 ; SSE41-X86-NEXT:    wait
-; SSE41-X86-NEXT:    movl %ebp, %esp
-; SSE41-X86-NEXT:    popl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE41-X86-NEXT:    addl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ffloorf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $9, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ffloorf64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ffloorf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $9, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.floor.f64(
                         double %f, metadata !"fpexcept.strict")
; AVX-X64-NEXT:    retq
   %res = call float @llvm.experimental.constrained.trunc.f32(
                         float %f, metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @ftruncf64(double %f) #0 {
 ; SSE41-X86-LABEL: ftruncf64:
 ; SSE41-X86:       # %bb.0:
-; SSE41-X86-NEXT:    pushl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE41-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE41-X86-NEXT:    movl %esp, %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $11, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
 ; SSE41-X86-NEXT:    wait
-; SSE41-X86-NEXT:    movl %ebp, %esp
-; SSE41-X86-NEXT:    popl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE41-X86-NEXT:    addl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: ftruncf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $11, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: ftruncf64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: ftruncf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.trunc.f64(
                         double %f, metadata !"fpexcept.strict")
%res = call float @llvm.experimental.constrained.rint.f32(
                         float %f,
                         metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @frintf64(double %f) #0 {
 ; SSE41-X86-LABEL: frintf64:
 ; SSE41-X86:       # %bb.0:
-; SSE41-X86-NEXT:    pushl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE41-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE41-X86-NEXT:    movl %esp, %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $4, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
 ; SSE41-X86-NEXT:    wait
-; SSE41-X86-NEXT:    movl %ebp, %esp
-; SSE41-X86-NEXT:    popl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE41-X86-NEXT:    addl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: frintf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $4, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: frintf64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: frintf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $4, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.rint.f64(
                         double %f,
%res = call float @llvm.experimental.constrained.nearbyint.f32(
                         float %f,
                         metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %res
 }
 
 define double @fnearbyintf64(double %f) #0 {
 ; SSE41-X86-LABEL: fnearbyintf64:
 ; SSE41-X86:       # %bb.0:
-; SSE41-X86-NEXT:    pushl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE41-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE41-X86-NEXT:    movl %esp, %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE41-X86-NEXT:    andl $-8, %esp
 ; SSE41-X86-NEXT:    subl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 12
 ; SSE41-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE41-X86-NEXT:    roundsd $12, %xmm0, %xmm0
 ; SSE41-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE41-X86-NEXT:    fldl (%esp)
 ; SSE41-X86-NEXT:    wait
-; SSE41-X86-NEXT:    movl %ebp, %esp
-; SSE41-X86-NEXT:    popl %ebp
-; SSE41-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE41-X86-NEXT:    addl $8, %esp
+; SSE41-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE41-X86-NEXT:    retl
 ;
 ; SSE41-X64-LABEL: fnearbyintf64:
 ; SSE41-X64:       # %bb.0:
 ; SSE41-X64-NEXT:    roundsd $12, %xmm0, %xmm0
 ; SSE41-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fnearbyintf64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_offset 8
-; AVX-X86-NEXT:    .cfi_offset %ebp, -8
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa_register %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 12
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
-; AVX-X86-NEXT:    .cfi_def_cfa %esp, 4
+; AVX-X86-NEXT:    addl $8, %esp
+; AVX-X86-NEXT:    .cfi_def_cfa_offset 4
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fnearbyintf64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vroundsd $12, %xmm0, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
   %res = call double @llvm.experimental.constrained.nearbyint.f64(
                         double %f,
                         metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret double %res
 }
 
 attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fp-strict-scalar.ll

 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
 
 define double @fadd_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fadd_f64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    addsd 16(%ebp), %xmm0
+; SSE-X86-NEXT:    addsd {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
+; SSE-X86-NEXT:    addl $8, %esp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fadd_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    addsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fadd_f64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-X86-NEXT:    vaddsd 16(%ebp), %xmm0, %xmm0
+; AVX-X86-NEXT:    vaddsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
+; AVX-X86-NEXT:    addl $8, %esp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fadd_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fadd_f64:
%ret = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fsub_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fsub_f64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    subsd 16(%ebp), %xmm0
+; SSE-X86-NEXT:    subsd {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
+; SSE-X86-NEXT:    addl $8, %esp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fsub_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    subsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fsub_f64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-X86-NEXT:    vsubsd 16(%ebp), %xmm0, %xmm0
+; AVX-X86-NEXT:    vsubsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
+; AVX-X86-NEXT:    addl $8, %esp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fsub_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fsub_f64:
%ret = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fmul_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fmul_f64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    mulsd 16(%ebp), %xmm0
+; SSE-X86-NEXT:    mulsd {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
+; SSE-X86-NEXT:    addl $8, %esp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fmul_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    mulsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fmul_f64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-X86-NEXT:    vmulsd 16(%ebp), %xmm0, %xmm0
+; AVX-X86-NEXT:    vmulsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
+; AVX-X86-NEXT:    addl $8, %esp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fmul_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fmul_f64:
%ret = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b,
                                                             metadata !"round.dynamic",
                                                             metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fdiv_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fdiv_f64:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT:    divsd 16(%ebp), %xmm0
+; SSE-X86-NEXT:    divsd {{[0-9]+}}(%esp), %xmm0
 ; SSE-X86-NEXT:    movsd %xmm0, (%esp)
 ; SSE-X86-NEXT:    fldl (%esp)
 ; SSE-X86-NEXT:    wait
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
+; SSE-X86-NEXT:    addl $8, %esp
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: fdiv_f64:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    divsd %xmm1, %xmm0
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fdiv_f64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-X86-NEXT:    vdivsd 16(%ebp), %xmm0, %xmm0
+; AVX-X86-NEXT:    vdivsd {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX-X86-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
+; AVX-X86-NEXT:    addl $8, %esp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fdiv_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fdiv_f64:

 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    pushq %rax
 ; SSE-X64-NEXT:    callq fma
 ; SSE-X64-NEXT:    popq %rax
 ; SSE-X64-NEXT:    retq
 ;
 ; AVX-X86-LABEL: fma_f64:
 ; AVX-X86:       # %bb.0:
-; AVX-X86-NEXT:    pushl %ebp
-; AVX-X86-NEXT:    movl %esp, %ebp
-; AVX-X86-NEXT:    andl $-8, %esp
 ; AVX-X86-NEXT:    subl $8, %esp
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX-X86-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
 ; AVX-X86-NEXT:    vfmadd213sd {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
 ; AVX-X86-NEXT:    vmovsd %xmm1, (%esp)
 ; AVX-X86-NEXT:    fldl (%esp)
 ; AVX-X86-NEXT:    wait
-; AVX-X86-NEXT:    movl %ebp, %esp
-; AVX-X86-NEXT:    popl %ebp
+; AVX-X86-NEXT:    addl $8, %esp
 ; AVX-X86-NEXT:    retl
 ;
 ; AVX-X64-LABEL: fma_f64:
 ; AVX-X64:       # %bb.0:
 ; AVX-X64-NEXT:    vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX-X64-NEXT:    retq
 ;
 ; X87-LABEL: fma_f64:

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

%ret = call float @llvm.experimental.constrained.fptrunc.f32.x86_fp80(x86_fp80 %a,
                                                                         metadata !"round.dynamic",
                                                                         metadata !"fpexcept.strict") #0
   ret float %ret
 }
 
 define double @fptrunc_fp80_to_f64(x86_fp80 %a) nounwind strictfp {
 ; X86-LABEL: fptrunc_fp80_to_f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
 ; X86-NEXT:    subl $8, %esp
-; X86-NEXT:    fldt 8(%ebp)
+; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fstpl (%esp)
 ; X86-NEXT:    fldl (%esp)
 ; X86-NEXT:    wait
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fptrunc_fp80_to_f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fstpl -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    wait
 ; X64-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero

llvm/test/CodeGen/X86/i64-mem-copy.ll

 }
 
 ; PR23476
 ; Handle extraction from a non-simple / pre-legalization type.
 
 define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) nounwind {
 ; X64-LABEL: PR23476:
 ; X64:       # %bb.0:
-; X64-NEXT:    pushq %rbp
-; X64-NEXT:    movq %rsp, %rbp
-; X64-NEXT:    andq $-64, %rsp
-; X64-NEXT:    subq $128, %rsp
 ; X64-NEXT:    movq %rsi, %xmm0
 ; X64-NEXT:    movq %rdi, %xmm1
 ; X64-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
 ; X64-NEXT:    movq %rcx, %xmm0
 ; X64-NEXT:    movq %rdx, %xmm2
 ; X64-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
-; X64-NEXT:    movl 16(%rbp), %eax
+; X64-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    andl $7, %eax
 ; X64-NEXT:    movq %r8, %xmm0
-; X64-NEXT:    movdqa %xmm0, {{[0-9]+}}(%rsp)
-; X64-NEXT:    movdqa %xmm2, {{[0-9]+}}(%rsp)
-; X64-NEXT:    movdqa %xmm1, (%rsp)
-; X64-NEXT:    movq (%rsp,%rax,8), %rax
+; X64-NEXT:    movdqa %xmm0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movdqa %xmm2, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movdqa %xmm1, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movq -72(%rsp,%rax,8), %rax
 ; X64-NEXT:    movq %rax, (%r9)
-; X64-NEXT:    movq %rbp, %rsp
-; X64-NEXT:    popq %rbp
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: PR23476:
 ; X32:       # %bb.0:
 ; X32-NEXT:    pushl %ebp
 ; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    andl $-64, %esp
-; X32-NEXT:    subl $128, %esp
+; X32-NEXT:    andl $-16, %esp
+; X32-NEXT:    subl $80, %esp
 ; X32-NEXT:    movl 52(%ebp), %eax
 ; X32-NEXT:    andl $7, %eax
 ; X32-NEXT:    movl 48(%ebp), %ecx
 ; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X32-NEXT:    movups 8(%ebp), %xmm1
 ; X32-NEXT:    movups 24(%ebp), %xmm2
 ; X32-NEXT:    movaps %xmm2, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movaps %xmm1, (%esp)
 ; X32-NEXT:    movaps %xmm0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X32-NEXT:    movsd %xmm0, (%ecx)
 ; X32-NEXT:    movl %ebp, %esp
 ; X32-NEXT:    popl %ebp
 ; X32-NEXT:    retl
 ;
 ; X32AVX-LABEL: PR23476:
 ; X32AVX:       # %bb.0:
 ; X32AVX-NEXT:    pushl %ebp
 ; X32AVX-NEXT:    movl %esp, %ebp
-; X32AVX-NEXT:    andl $-64, %esp
-; X32AVX-NEXT:    subl $128, %esp
+; X32AVX-NEXT:    andl $-32, %esp
+; X32AVX-NEXT:    subl $96, %esp
 ; X32AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X32AVX-NEXT:    movl 52(%ebp), %eax
 ; X32AVX-NEXT:    andl $7, %eax
 ; X32AVX-NEXT:    movl 48(%ebp), %ecx
 ; X32AVX-NEXT:    vmovups 8(%ebp), %ymm1
 ; X32AVX-NEXT:    vmovaps %ymm1, (%esp)
 ; X32AVX-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero

llvm/test/CodeGen/X86/insertelement-var-index.ll

; AVX-NEXT:    retq
   %x = load double, double* %p
   %ins = insertelement <2 x double> undef, double %x, i32 %y
   ret <2 x double> %ins
 }
 
 define <32 x i8> @arg_i8_v32i8(i8 %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_i8_v32i8:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    andl $31, %esi
-; SSE-NEXT:    movb %dil, (%rsp,%rsi)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movb %dil, -40(%rsp,%rsi)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_i8_v32i8:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovd %edi, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_i8_v32i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovd %edi, %xmm0
 ; AVX2-NEXT:    vpbroadcastb %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <32 x i8> undef, i8 %x, i32 %y
   ret <32 x i8> %ins
 }
 
 define <16 x i16> @arg_i16_v16i16(i16 %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_i16_v16i16:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    andl $15, %esi
-; SSE-NEXT:    movw %di, (%rsp,%rsi,2)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movw %di, -40(%rsp,%rsi,2)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_i16_v16i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovd %edi, %xmm0
 ; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_i16_v16i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovd %edi, %xmm0
 ; AVX2-NEXT:    vpbroadcastw %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <16 x i16> undef, i16 %x, i32 %y
   ret <16 x i16> %ins
 }
 
 define <8 x i32> @arg_i32_v8i32(i32 %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_i32_v8i32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    andl $7, %esi
-; SSE-NEXT:    movl %edi, (%rsp,%rsi,4)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movl %edi, -40(%rsp,%rsi,4)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_i32_v8i32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovd %edi, %xmm0
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_i32_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovd %edi, %xmm0
 ; AVX2-NEXT:    vpbroadcastd %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <8 x i32> undef, i32 %x, i32 %y
   ret <8 x i32> %ins
 }
 
 define <4 x i64> @arg_i64_v4i64(i64 %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_i64_v4i64:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    andl $3, %esi
-; SSE-NEXT:    movq %rdi, (%rsp,%rsi,8)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movq %rdi, -40(%rsp,%rsi,8)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_i64_v4i64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovq %rdi, %xmm0
 ; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_i64_v4i64:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovq %rdi, %xmm0
 ; AVX2-NEXT:    vpbroadcastq %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <4 x i64> undef, i64 %x, i32 %y
   ret <4 x i64> %ins
 }
 
 define <8 x float> @arg_f32_v8f32(float %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_f32_v8f32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $edi killed $edi def $rdi
 ; SSE-NEXT:    andl $7, %edi
-; SSE-NEXT:    movss %xmm0, (%rsp,%rdi,4)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movss %xmm0, -40(%rsp,%rdi,4)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_f32_v8f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_f32_v8f32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vbroadcastss %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <8 x float> undef, float %x, i32 %y
   ret <8 x float> %ins
 }
 
 define <4 x double> @arg_f64_v4f64(double %x, i32 %y) nounwind {
 ; SSE-LABEL: arg_f64_v4f64:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $edi killed $edi def $rdi
 ; SSE-NEXT:    andl $3, %edi
-; SSE-NEXT:    movsd %xmm0, (%rsp,%rdi,8)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movsd %xmm0, -40(%rsp,%rdi,8)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: arg_f64_v4f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: arg_f64_v4f64:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vbroadcastsd %xmm0, %ymm0
 ; AVX2-NEXT:    retq
   %ins = insertelement <4 x double> undef, double %x, i32 %y
   ret <4 x double> %ins
 }
 
 define <32 x i8> @load_i8_v32i8(i8* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_i8_v32i8:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movb (%rdi), %al
 ; SSE-NEXT:    andl $31, %esi
-; SSE-NEXT:    movb %al, (%rsp,%rsi)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movb %al, -40(%rsp,%rsi)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: load_i8_v32i8:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    movzbl (%rdi), %eax
 ; AVX1-NEXT:    vmovd %eax, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: load_i8_v32i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpbroadcastb (%rdi), %ymm0
 ; AVX2-NEXT:    retq
   %x = load i8, i8* %p
   %ins = insertelement <32 x i8> undef, i8 %x, i32 %y
   ret <32 x i8> %ins
 }
 
 define <16 x i16> @load_i16_v16i16(i16* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_i16_v16i16:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movzwl (%rdi), %eax
 ; SSE-NEXT:    andl $15, %esi
-; SSE-NEXT:    movw %ax, (%rsp,%rsi,2)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movw %ax, -40(%rsp,%rsi,2)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: load_i16_v16i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    movzwl (%rdi), %eax
 ; AVX1-NEXT:    vmovd %eax, %xmm0
 ; AVX1-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7]
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: load_i16_v16i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpbroadcastw (%rdi), %ymm0
 ; AVX2-NEXT:    retq
   %x = load i16, i16* %p
   %ins = insertelement <16 x i16> undef, i16 %x, i32 %y
   ret <16 x i16> %ins
 }
 
 define <8 x i32> @load_i32_v8i32(i32* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_i32_v8i32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movl (%rdi), %eax
 ; SSE-NEXT:    andl $7, %esi
-; SSE-NEXT:    movl %eax, (%rsp,%rsi,4)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movl %eax, -40(%rsp,%rsi,4)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: load_i32_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vbroadcastss (%rdi), %ymm0
 ; AVX-NEXT:    retq
   %x = load i32, i32* %p
   %ins = insertelement <8 x i32> undef, i32 %x, i32 %y
   ret <8 x i32> %ins
 }
 
 define <4 x i64> @load_i64_v4i64(i64* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_i64_v4i64:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movq (%rdi), %rax
 ; SSE-NEXT:    andl $3, %esi
-; SSE-NEXT:    movq %rax, (%rsp,%rsi,8)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movq %rax, -40(%rsp,%rsi,8)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: load_i64_v4i64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; AVX-NEXT:    retq
   %x = load i64, i64* %p
   %ins = insertelement <4 x i64> undef, i64 %x, i32 %y
   ret <4 x i64> %ins
 }
 
 define <8 x float> @load_f32_v8f32(float* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_f32_v8f32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-NEXT:    andl $7, %esi
-; SSE-NEXT:    movss %xmm0, (%rsp,%rsi,4)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movss %xmm0, -40(%rsp,%rsi,4)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: load_f32_v8f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vbroadcastss (%rdi), %ymm0
 ; AVX-NEXT:    retq
   %x = load float, float* %p
   %ins = insertelement <8 x float> undef, float %x, i32 %y
   ret <8 x float> %ins
 }
 
 define <4 x double> @load_f64_v4f64(double* %p, i32 %y) nounwind {
 ; SSE-LABEL: load_f64_v4f64:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    pushq %rbp
-; SSE-NEXT:    movq %rsp, %rbp
-; SSE-NEXT:    andq $-32, %rsp
-; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    # kill: def $esi killed $esi def $rsi
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    andl $3, %esi
-; SSE-NEXT:    movsd %xmm0, (%rsp,%rsi,8)
-; SSE-NEXT:    movaps (%rsp), %xmm0
-; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; SSE-NEXT:    movq %rbp, %rsp
-; SSE-NEXT:    popq %rbp
+; SSE-NEXT:    movsd %xmm0, -40(%rsp,%rsi,8)
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; SSE-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: load_f64_v4f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vbroadcastsd (%rdi), %ymm0
 ; AVX-NEXT:    retq
   %x = load double, double* %p
   %ins = insertelement <4 x double> undef, double %x, i32 %y

llvm/test/CodeGen/X86/mmx-fold-zero.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X64
 
 define double @mmx_zero(double, double, double, double) nounwind {
 ; X86-LABEL: mmx_zero:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %ebp
-; X86-NEXT:    movl %esp, %ebp
-; X86-NEXT:    andl $-8, %esp
-; X86-NEXT:    subl $16, %esp
-; X86-NEXT:    movq 8(%ebp), %mm0
-; X86-NEXT:    movq 16(%ebp), %mm5
+; X86-NEXT:    subl $20, %esp
+; X86-NEXT:    movq {{[0-9]+}}(%esp), %mm0
+; X86-NEXT:    movq {{[0-9]+}}(%esp), %mm5
 ; X86-NEXT:    movq %mm5, (%esp) # 8-byte Spill
 ; X86-NEXT:    movq %mm0, %mm3
 ; X86-NEXT:    paddd %mm5, %mm3
 ; X86-NEXT:    pxor %mm1, %mm1
 ; X86-NEXT:    movq %mm3, %mm6
 ; X86-NEXT:    pmuludq %mm1, %mm6
-; X86-NEXT:    movq 24(%ebp), %mm4
+; X86-NEXT:    movq {{[0-9]+}}(%esp), %mm4
 ; X86-NEXT:    movq %mm6, %mm2
 ; X86-NEXT:    paddd %mm4, %mm2
 ; X86-NEXT:    paddw %mm2, %mm0
 ; X86-NEXT:    movq %mm5, %mm1
 ; X86-NEXT:    paddw %mm0, %mm1
-; X86-NEXT:    movq 32(%ebp), %mm5
+; X86-NEXT:    movq {{[0-9]+}}(%esp), %mm5
 ; X86-NEXT:    movq %mm1, %mm7
 ; X86-NEXT:    pmuludq %mm5, %mm7
 ; X86-NEXT:    paddw %mm4, %mm7
 ; X86-NEXT:    paddw %mm7, %mm5
 ; X86-NEXT:    paddw %mm5, %mm2
 ; X86-NEXT:    paddw %mm2, %mm0
 ; X86-NEXT:    paddw %mm6, %mm0
 ; X86-NEXT:    pmuludq %mm3, %mm0
 ; X86-NEXT:    paddw {{\.LCPI.*}}, %mm0
 ; X86-NEXT:    paddw %mm1, %mm0
 ; X86-NEXT:    pmuludq %mm7, %mm0
 ; X86-NEXT:    pmuludq (%esp), %mm0 # 8-byte Folded Reload
 ; X86-NEXT:    paddw %mm5, %mm0
 ; X86-NEXT:    paddw %mm2, %mm0
 ; X86-NEXT:    movq2dq %mm0, %xmm0
 ; X86-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldl {{[0-9]+}}(%esp)
-; X86-NEXT:    movl %ebp, %esp
-; X86-NEXT:    popl %ebp
+; X86-NEXT:    addl $20, %esp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: mmx_zero:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movdq2q %xmm0, %mm0
 ; X64-NEXT:    movdq2q %xmm1, %mm5
-; X64-NEXT:    movq %mm5, -{{[0-9]+}}(%rsp) # 8-byte Spill
+; X64-NEXT:    movq %mm5, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; X64-NEXT:    movq %mm0, %mm3
 ; X64-NEXT:    paddd %mm5, %mm3
 ; X64-NEXT:    pxor %mm1, %mm1
 ; X64-NEXT:    movq %mm3, %mm6
 ; X64-NEXT:    pmuludq %mm1, %mm6
 ; X64-NEXT:    movdq2q %xmm2, %mm4
 ; X64-NEXT:    movq %mm6, %mm2
 ; X64-NEXT:    paddd %mm4, %mm2
 ; X64-NEXT:    paddw %mm2, %mm0
 ; X64-NEXT:    movq %mm5, %mm1
 ; X64-NEXT:    paddw %mm0, %mm1
 ; X64-NEXT:    movdq2q %xmm3, %mm5
 ; X64-NEXT:    movq %mm1, %mm7
 ; X64-NEXT:    pmuludq %mm5, %mm7
 ; X64-NEXT:    paddw %mm4, %mm7
 ; X64-NEXT:    paddw %mm7, %mm5
 ; X64-NEXT:    paddw %mm5, %mm2
 ; X64-NEXT:    paddw %mm2, %mm0
 ; X64-NEXT:    paddw %mm6, %mm0
 ; X64-NEXT:    pmuludq %mm3, %mm0
 ; X64-NEXT:    paddw {{\.LCPI.*}}, %mm0
 ; X64-NEXT:    paddw %mm1, %mm0
 ; X64-NEXT:    pmuludq %mm7, %mm0
-; X64-NEXT:    pmuludq -{{[0-9]+}}(%rsp), %mm0 # 8-byte Folded Reload
+; X64-NEXT:    pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
 ; X64-NEXT:    paddw %mm5, %mm0
 ; X64-NEXT:    paddw %mm2, %mm0
 ; X64-NEXT:    movq2dq %mm0, %xmm0
 ; X64-NEXT:    retq
   %5 = bitcast double %0 to x86_mmx
   %6 = bitcast double %1 to x86_mmx
   %7 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %5, x86_mmx %6)
   %8 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %7, x86_mmx bitcast (double 0.000000e+00 to x86_mmx))

llvm/test/CodeGen/X86/neg_fp.ll

entry:
   ret float %neg
 }
 
 ; This may infinite loop if isNegatibleForFree and getNegatedExpression are conflicted.
 
 define double @negation_propagation(double* %arg, double %arg1, double %arg2) nounwind {
 ; CHECK-LABEL: negation_propagation:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushl %ebp
-; CHECK-NEXT:    movl %esp, %ebp
-; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    divsd 12(%ebp), %xmm0
+; CHECK-NEXT:    divsd {{[0-9]+}}(%esp), %xmm0
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    mulsd %xmm0, %xmm1
 ; CHECK-NEXT:    movapd %xmm0, %xmm2
 ; CHECK-NEXT:    mulsd %xmm0, %xmm2
 ; CHECK-NEXT:    mulsd %xmm0, %xmm2
 ; CHECK-NEXT:    subsd %xmm2, %xmm1
 ; CHECK-NEXT:    movsd %xmm1, (%esp)
 ; CHECK-NEXT:    fldl (%esp)
-; CHECK-NEXT:    movl %ebp, %esp
-; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    addl $8, %esp
 ; CHECK-NEXT:    retl
   %t = fdiv double 1.0, %arg1
   %t7 = fmul double %t, %arg2
   %t10 = fneg double %t7
   %t11 = fmul double %t, %t
   %t13 = fsub double %t11, %t
   %t14 = fneg double %t
   %t15 = fmul double %t, %t14

llvm/test/CodeGen/X86/powi.ll

 ; X86-X87-NEXT:    fmul %st, %st(0)
 ; X86-X87-NEXT:    fmul %st, %st(1)
 ; X86-X87-NEXT:    fmul %st, %st(0)
 ; X86-X87-NEXT:    fmulp %st, %st(1)
 ; X86-X87-NEXT:    retl
 ;
 ; X86-SSE-LABEL: pow_wrapper:
 ; X86-SSE:       # %bb.0:
-; X86-SSE-NEXT:    pushl %ebp
-; X86-SSE-NEXT:    movl %esp, %ebp
-; X86-SSE-NEXT:    andl $-8, %esp
 ; X86-SSE-NEXT:    subl $8, %esp
 ; X86-SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    movapd %xmm0, %xmm1
 ; X86-SSE-NEXT:    mulsd %xmm0, %xmm1
 ; X86-SSE-NEXT:    mulsd %xmm1, %xmm0
 ; X86-SSE-NEXT:    mulsd %xmm1, %xmm1
 ; X86-SSE-NEXT:    mulsd %xmm1, %xmm0
 ; X86-SSE-NEXT:    mulsd %xmm1, %xmm1
 ; X86-SSE-NEXT:    mulsd %xmm0, %xmm1
 ; X86-SSE-NEXT:    movsd %xmm1, (%esp)
 ; X86-SSE-NEXT:    fldl (%esp)
-; X86-SSE-NEXT:    movl %ebp, %esp
-; X86-SSE-NEXT:    popl %ebp
+; X86-SSE-NEXT:    addl $8, %esp
 ; X86-SSE-NEXT:    retl
 ;
 ; X64-LABEL: pow_wrapper:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movapd %xmm0, %xmm1
 ; X64-NEXT:    mulsd %xmm0, %xmm1
 ; X64-NEXT:    mulsd %xmm1, %xmm0
 ; X64-NEXT:    mulsd %xmm1, %xmm1

llvm/test/CodeGen/X86/scalar-int-to-fp.ll

 ; X87-NEXT:    retl
   %r = sitofp i32 %a to float
   ret float %r
 }
 
 define double @u32_to_d(i32 %a) nounwind {
 ; AVX512_32-LABEL: u32_to_d:
 ; AVX512_32:       # %bb.0:
-; AVX512_32-NEXT:    pushl %ebp
-; AVX512_32-NEXT:    movl %esp, %ebp
-; AVX512_32-NEXT:    andl $-8, %esp
 ; AVX512_32-NEXT:    subl $8, %esp
-; AVX512_32-NEXT:    vcvtusi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX512_32-NEXT:    vcvtusi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512_32-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512_32-NEXT:    fldl (%esp)
-; AVX512_32-NEXT:    movl %ebp, %esp
-; AVX512_32-NEXT:    popl %ebp
+; AVX512_32-NEXT:    addl $8, %esp
 ; AVX512_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: u32_to_d:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtusi2sd %edi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; SSE2_32-LABEL: u32_to_d:
 ; SSE2_32:       # %bb.0:
-; SSE2_32-NEXT:    pushl %ebp
-; SSE2_32-NEXT:    movl %esp, %ebp
-; SSE2_32-NEXT:    andl $-8, %esp
 ; SSE2_32-NEXT:    subl $8, %esp
 ; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2_32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE2_32-NEXT:    orpd %xmm0, %xmm1
 ; SSE2_32-NEXT:    subsd %xmm0, %xmm1
 ; SSE2_32-NEXT:    movsd %xmm1, (%esp)
 ; SSE2_32-NEXT:    fldl (%esp)
-; SSE2_32-NEXT:    movl %ebp, %esp
-; SSE2_32-NEXT:    popl %ebp
+; SSE2_32-NEXT:    addl $8, %esp
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: u32_to_d:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    movl %edi, %eax
 ; SSE2_64-NEXT:    cvtsi2sd %rax, %xmm0
 ; SSE2_64-NEXT:    retq
 ;

 ; X87-NEXT:    retl
   %r = uitofp i32 %a to double
   ret double %r
 }
 
 define double @s32_to_d(i32 %a) nounwind {
 ; AVX512_32-LABEL: s32_to_d:
 ; AVX512_32:       # %bb.0:
-; AVX512_32-NEXT:    pushl %ebp
-; AVX512_32-NEXT:    movl %esp, %ebp
-; AVX512_32-NEXT:    andl $-8, %esp
 ; AVX512_32-NEXT:    subl $8, %esp
-; AVX512_32-NEXT:    vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
+; AVX512_32-NEXT:    vcvtsi2sdl {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; AVX512_32-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512_32-NEXT:    fldl (%esp)
-; AVX512_32-NEXT:    movl %ebp, %esp
-; AVX512_32-NEXT:    popl %ebp
+; AVX512_32-NEXT:    addl $8, %esp
 ; AVX512_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: s32_to_d:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; SSE2_32-LABEL: s32_to_d:
 ; SSE2_32:       # %bb.0:
-; SSE2_32-NEXT:    pushl %ebp
-; SSE2_32-NEXT:    movl %esp, %ebp
-; SSE2_32-NEXT:    andl $-8, %esp
 ; SSE2_32-NEXT:    subl $8, %esp
-; SSE2_32-NEXT:    cvtsi2sdl 8(%ebp), %xmm0
+; SSE2_32-NEXT:    cvtsi2sdl {{[0-9]+}}(%esp), %xmm0
 ; SSE2_32-NEXT:    movsd %xmm0, (%esp)
 ; SSE2_32-NEXT:    fldl (%esp)
-; SSE2_32-NEXT:    movl %ebp, %esp
-; SSE2_32-NEXT:    popl %ebp
+; SSE2_32-NEXT:    addl $8, %esp
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: s32_to_d:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    cvtsi2sd %edi, %xmm0
 ; SSE2_64-NEXT:    retq
 ;
 ; SSE1_32-LABEL: s32_to_d:
; X87-NEXT:    retl
   %a1 = add i64 %a, 5
   %r = sitofp i64 %a1 to float
   ret float %r
 }
 
 define double @u64_to_d(i64 %a) nounwind {
 ; AVX512DQVL_32-LABEL: u64_to_d:
 ; AVX512DQVL_32:       # %bb.0:
-; AVX512DQVL_32-NEXT:    pushl %ebp
-; AVX512DQVL_32-NEXT:    movl %esp, %ebp
-; AVX512DQVL_32-NEXT:    andl $-8, %esp
 ; AVX512DQVL_32-NEXT:    subl $8, %esp
 ; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQVL_32-NEXT:    vcvtuqq2pd %ymm0, %ymm0
 ; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQVL_32-NEXT:    fldl (%esp)
-; AVX512DQVL_32-NEXT:    movl %ebp, %esp
-; AVX512DQVL_32-NEXT:    popl %ebp
+; AVX512DQVL_32-NEXT:    addl $8, %esp
 ; AVX512DQVL_32-NEXT:    vzeroupper
 ; AVX512DQVL_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: u64_to_d:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtusi2sd %rdi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; AVX512DQ_32-LABEL: u64_to_d:
 ; AVX512DQ_32:       # %bb.0:
-; AVX512DQ_32-NEXT:    pushl %ebp
-; AVX512DQ_32-NEXT:    movl %esp, %ebp
-; AVX512DQ_32-NEXT:    andl $-8, %esp
 ; AVX512DQ_32-NEXT:    subl $8, %esp
 ; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQ_32-NEXT:    vcvtuqq2pd %zmm0, %zmm0
 ; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQ_32-NEXT:    fldl (%esp)
-; AVX512DQ_32-NEXT:    movl %ebp, %esp
-; AVX512DQ_32-NEXT:    popl %ebp
+; AVX512DQ_32-NEXT:    addl $8, %esp
 ; AVX512DQ_32-NEXT:    vzeroupper
 ; AVX512DQ_32-NEXT:    retl
 ;
 ; AVX512F_32-LABEL: u64_to_d:
 ; AVX512F_32:       # %bb.0:
-; AVX512F_32-NEXT:    pushl %ebp
-; AVX512F_32-NEXT:    movl %esp, %ebp
-; AVX512F_32-NEXT:    andl $-8, %esp
 ; AVX512F_32-NEXT:    subl $8, %esp
 ; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512F_32-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX512F_32-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX512F_32-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
 ; AVX512F_32-NEXT:    vaddsd %xmm0, %xmm1, %xmm0
 ; AVX512F_32-NEXT:    vmovsd %xmm0, (%esp)
 ; AVX512F_32-NEXT:    fldl (%esp)
-; AVX512F_32-NEXT:    movl %ebp, %esp
-; AVX512F_32-NEXT:    popl %ebp
+; AVX512F_32-NEXT:    addl $8, %esp
 ; AVX512F_32-NEXT:    retl
 ;
 ; SSE2_32-LABEL: u64_to_d:
 ; SSE2_32:       # %bb.0:
-; SSE2_32-NEXT:    pushl %ebp
-; SSE2_32-NEXT:    movl %esp, %ebp
-; SSE2_32-NEXT:    andl $-8, %esp
 ; SSE2_32-NEXT:    subl $8, %esp
 ; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2_32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; SSE2_32-NEXT:    subpd {{\.LCPI.*}}, %xmm0
 ; SSE2_32-NEXT:    movapd %xmm0, %xmm1
 ; SSE2_32-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; SSE2_32-NEXT:    addsd %xmm0, %xmm1
 ; SSE2_32-NEXT:    movsd %xmm1, (%esp)
 ; SSE2_32-NEXT:    fldl (%esp)
-; SSE2_32-NEXT:    movl %ebp, %esp
-; SSE2_32-NEXT:    popl %ebp
+; SSE2_32-NEXT:    addl $8, %esp
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: u64_to_d:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    movq %rdi, %xmm1
 ; SSE2_64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
 ; SSE2_64-NEXT:    subpd {{.*}}(%rip), %xmm1
 ; SSE2_64-NEXT:    movapd %xmm1, %xmm0

 ; X87-NEXT:    retl
   %r = uitofp i64 %a to double
   ret double %r
 }
 
 define double @u64_to_d_optsize(i64 %a) nounwind optsize {
 ; AVX512DQVL_32-LABEL: u64_to_d_optsize:
 ; AVX512DQVL_32:       # %bb.0:
-; AVX512DQVL_32-NEXT:    pushl %ebp
-; AVX512DQVL_32-NEXT:    movl %esp, %ebp
-; AVX512DQVL_32-NEXT:    andl $-8, %esp
 ; AVX512DQVL_32-NEXT:    subl $8, %esp
 ; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQVL_32-NEXT:    vcvtuqq2pd %ymm0, %ymm0
 ; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQVL_32-NEXT:    fldl (%esp)
-; AVX512DQVL_32-NEXT:    movl %ebp, %esp
-; AVX512DQVL_32-NEXT:    popl %ebp
+; AVX512DQVL_32-NEXT:    addl $8, %esp
 ; AVX512DQVL_32-NEXT:    vzeroupper
 ; AVX512DQVL_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: u64_to_d_optsize:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtusi2sd %rdi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; AVX512DQ_32-LABEL: u64_to_d_optsize:
 ; AVX512DQ_32:       # %bb.0:
-; AVX512DQ_32-NEXT:    pushl %ebp
-; AVX512DQ_32-NEXT:    movl %esp, %ebp
-; AVX512DQ_32-NEXT:    andl $-8, %esp
 ; AVX512DQ_32-NEXT:    subl $8, %esp
 ; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQ_32-NEXT:    vcvtuqq2pd %zmm0, %zmm0
 ; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQ_32-NEXT:    fldl (%esp)
-; AVX512DQ_32-NEXT:    movl %ebp, %esp
-; AVX512DQ_32-NEXT:    popl %ebp
+; AVX512DQ_32-NEXT:    addl $8, %esp
 ; AVX512DQ_32-NEXT:    vzeroupper
 ; AVX512DQ_32-NEXT:    retl
 ;
 ; AVX512F_32-LABEL: u64_to_d_optsize:
 ; AVX512F_32:       # %bb.0:
-; AVX512F_32-NEXT:    pushl %ebp
-; AVX512F_32-NEXT:    movl %esp, %ebp
-; AVX512F_32-NEXT:    andl $-8, %esp
 ; AVX512F_32-NEXT:    subl $8, %esp
 ; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512F_32-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; AVX512F_32-NEXT:    vsubpd {{\.LCPI.*}}, %xmm0, %xmm0
 ; AVX512F_32-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
 ; AVX512F_32-NEXT:    vmovlpd %xmm0, (%esp)
 ; AVX512F_32-NEXT:    fldl (%esp)
-; AVX512F_32-NEXT:    movl %ebp, %esp
-; AVX512F_32-NEXT:    popl %ebp
+; AVX512F_32-NEXT:    addl $8, %esp
 ; AVX512F_32-NEXT:    retl
 ;
 ; SSE2_32-LABEL: u64_to_d_optsize:
 ; SSE2_32:       # %bb.0:
-; SSE2_32-NEXT:    pushl %ebp
-; SSE2_32-NEXT:    movl %esp, %ebp
-; SSE2_32-NEXT:    andl $-8, %esp
 ; SSE2_32-NEXT:    subl $8, %esp
 ; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE2_32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
 ; SSE2_32-NEXT:    subpd {{\.LCPI.*}}, %xmm0
 ; SSE2_32-NEXT:    movapd %xmm0, %xmm1
 ; SSE2_32-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
 ; SSE2_32-NEXT:    addsd %xmm0, %xmm1
 ; SSE2_32-NEXT:    movsd %xmm1, (%esp)
 ; SSE2_32-NEXT:    fldl (%esp)
-; SSE2_32-NEXT:    movl %ebp, %esp
-; SSE2_32-NEXT:    popl %ebp
+; SSE2_32-NEXT:    addl $8, %esp
 ; SSE2_32-NEXT:    retl
 ;
 ; SSE2_64-LABEL: u64_to_d_optsize:
 ; SSE2_64:       # %bb.0:
 ; SSE2_64-NEXT:    movq %rdi, %xmm1
 ; SSE2_64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
 ; SSE2_64-NEXT:    subpd {{.*}}(%rip), %xmm1
 ; SSE2_64-NEXT:    movapd %xmm1, %xmm0

 ; X87-NEXT:    retl
   %r = uitofp i64 %a to double
   ret double %r
 }
 
 define double @s64_to_d(i64 %a) nounwind {
 ; AVX512DQVL_32-LABEL: s64_to_d:
 ; AVX512DQVL_32:       # %bb.0:
-; AVX512DQVL_32-NEXT:    pushl %ebp
-; AVX512DQVL_32-NEXT:    movl %esp, %ebp
-; AVX512DQVL_32-NEXT:    andl $-8, %esp
 ; AVX512DQVL_32-NEXT:    subl $8, %esp
 ; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQVL_32-NEXT:    vcvtqq2pd %ymm0, %ymm0
 ; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQVL_32-NEXT:    fldl (%esp)
-; AVX512DQVL_32-NEXT:    movl %ebp, %esp
-; AVX512DQVL_32-NEXT:    popl %ebp
+; AVX512DQVL_32-NEXT:    addl $8, %esp
 ; AVX512DQVL_32-NEXT:    vzeroupper
 ; AVX512DQVL_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: s64_to_d:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; AVX512DQ_32-LABEL: s64_to_d:
 ; AVX512DQ_32:       # %bb.0:
-; AVX512DQ_32-NEXT:    pushl %ebp
-; AVX512DQ_32-NEXT:    movl %esp, %ebp
-; AVX512DQ_32-NEXT:    andl $-8, %esp
 ; AVX512DQ_32-NEXT:    subl $8, %esp
 ; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; AVX512DQ_32-NEXT:    vcvtqq2pd %zmm0, %zmm0
 ; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQ_32-NEXT:    fldl (%esp)
-; AVX512DQ_32-NEXT:    movl %ebp, %esp
-; AVX512DQ_32-NEXT:    popl %ebp
+; AVX512DQ_32-NEXT:    addl $8, %esp
 ; AVX512DQ_32-NEXT:    vzeroupper
 ; AVX512DQ_32-NEXT:    retl
 ;
 ; AVX512F_32-LABEL: s64_to_d:
 ; AVX512F_32:       # %bb.0:
 ; AVX512F_32-NEXT:    pushl %ebp
 ; AVX512F_32-NEXT:    movl %esp, %ebp
 ; AVX512F_32-NEXT:    andl $-8, %esp

 ; X87-NEXT:    retl
   %r = sitofp i64 %a to double
   ret double %r
 }
 
 define double @s64_to_d_2(i64 %a) nounwind {
 ; AVX512DQVL_32-LABEL: s64_to_d_2:
 ; AVX512DQVL_32:       # %bb.0:
-; AVX512DQVL_32-NEXT:    pushl %ebp
-; AVX512DQVL_32-NEXT:    movl %esp, %ebp
-; AVX512DQVL_32-NEXT:    andl $-8, %esp
 ; AVX512DQVL_32-NEXT:    subl $8, %esp
-; AVX512DQVL_32-NEXT:    movl 8(%ebp), %eax
-; AVX512DQVL_32-NEXT:    movl 12(%ebp), %ecx
+; AVX512DQVL_32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX512DQVL_32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; AVX512DQVL_32-NEXT:    addl $5, %eax
 ; AVX512DQVL_32-NEXT:    adcl $0, %ecx
 ; AVX512DQVL_32-NEXT:    vmovd %eax, %xmm0
 ; AVX512DQVL_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512DQVL_32-NEXT:    vcvtqq2pd %ymm0, %ymm0
 ; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQVL_32-NEXT:    fldl (%esp)
-; AVX512DQVL_32-NEXT:    movl %ebp, %esp
-; AVX512DQVL_32-NEXT:    popl %ebp
+; AVX512DQVL_32-NEXT:    addl $8, %esp
 ; AVX512DQVL_32-NEXT:    vzeroupper
 ; AVX512DQVL_32-NEXT:    retl
 ;
 ; AVX512_64-LABEL: s64_to_d_2:
 ; AVX512_64:       # %bb.0:
 ; AVX512_64-NEXT:    addq $5, %rdi
 ; AVX512_64-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
 ; AVX512_64-NEXT:    retq
 ;
 ; AVX512DQ_32-LABEL: s64_to_d_2:
 ; AVX512DQ_32:       # %bb.0:
-; AVX512DQ_32-NEXT:    pushl %ebp
-; AVX512DQ_32-NEXT:    movl %esp, %ebp
-; AVX512DQ_32-NEXT:    andl $-8, %esp
 ; AVX512DQ_32-NEXT:    subl $8, %esp
-; AVX512DQ_32-NEXT:    movl 8(%ebp), %eax
-; AVX512DQ_32-NEXT:    movl 12(%ebp), %ecx
+; AVX512DQ_32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX512DQ_32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; AVX512DQ_32-NEXT:    addl $5, %eax
 ; AVX512DQ_32-NEXT:    adcl $0, %ecx
 ; AVX512DQ_32-NEXT:    vmovd %eax, %xmm0
 ; AVX512DQ_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
 ; AVX512DQ_32-NEXT:    vcvtqq2pd %zmm0, %zmm0
 ; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
 ; AVX512DQ_32-NEXT:    fldl (%esp)
-; AVX512DQ_32-NEXT:    movl %ebp, %esp
-; AVX512DQ_32-NEXT:    popl %ebp
+; AVX512DQ_32-NEXT:    addl $8, %esp
 ; AVX512DQ_32-NEXT:    vzeroupper
 ; AVX512DQ_32-NEXT:    retl
 ;
 ; AVX512F_32-LABEL: s64_to_d_2:
 ; AVX512F_32:       # %bb.0:
 ; AVX512F_32-NEXT:    pushl %ebp
 ; AVX512F_32-NEXT:    movl %esp, %ebp
 ; AVX512F_32-NEXT:    andl $-8, %esp

llvm/test/CodeGen/X86/sse-fcopysign.ll

 ; X64-NEXT:    retq
   %tmp = tail call float @llvm.copysign.f32( float %b, float %a )
   ret float %tmp
 }
 
 define double @int2(double %a, float %b, float %c) nounwind {
 ; X32-LABEL: int2:
 ; X32:       # %bb.0:
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $8, %esp
 ; X32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT:    addss 20(%ebp), %xmm0
+; X32-NEXT:    addss {{[0-9]+}}(%esp), %xmm0
 ; X32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; X32-NEXT:    andps {{\.LCPI.*}}, %xmm1
 ; X32-NEXT:    cvtss2sd %xmm0, %xmm0
 ; X32-NEXT:    andps {{\.LCPI.*}}, %xmm0
 ; X32-NEXT:    orps %xmm1, %xmm0
 ; X32-NEXT:    movlps %xmm0, (%esp)
 ; X32-NEXT:    fldl (%esp)
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
+; X32-NEXT:    addl $8, %esp
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: int2:
 ; X64:       # %bb.0:
 ; X64-NEXT:    addss %xmm2, %xmm1
 ; X64-NEXT:    cvtss2sd %xmm1, %xmm1
 ; X64-NEXT:    andps {{.*}}(%rip), %xmm1
 ; X64-NEXT:    andps {{.*}}(%rip), %xmm0

llvm/test/CodeGen/X86/sse-load-ret.ll

 ; CHECK-NEXT:    retl
         ret double 1.234560e+03
 }
 
 
 define double @test3(i1 %B) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    pushl %ebp
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:    .cfi_offset %ebp, -8
-; CHECK-NEXT:    movl %esp, %ebp
-; CHECK-NEXT:    .cfi_def_cfa_register %ebp
-; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $8, %esp
-; CHECK-NEXT:    testb $1, 8(%ebp)
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    testb $1, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    jne .LBB2_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    jmp .LBB2_3
 ; CHECK-NEXT:  .LBB2_1:
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:  .LBB2_3:
 ; CHECK-NEXT:    movsd %xmm0, (%esp)
 ; CHECK-NEXT:    fldl (%esp)
-; CHECK-NEXT:    movl %ebp, %esp
-; CHECK-NEXT:    popl %ebp
-; CHECK-NEXT:    .cfi_def_cfa %esp, 4
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
   %C = select i1 %B, double 123.412, double 523.01123123
   ret double %C
 }
 

llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll

; AVX512-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
   %ext = shufflevector <4 x float> %a0, <4 x float> %a0, <2 x i32> <i32 0, i32 1>
   %res = fpext <2 x float> %ext to <2 x double>
   ret <2 x double> %res
 }
 
 define double @test_mm_cvtsd_f64(<2 x double> %a0) nounwind {
 ; X86-SSE-LABEL: test_mm_cvtsd_f64:
 ; X86-SSE:       # %bb.0:
-; X86-SSE-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-SSE-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-SSE-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-SSE-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
 ; X86-SSE-NEXT:    movlps %xmm0, (%esp) # encoding: [0x0f,0x13,0x04,0x24]
 ; X86-SSE-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-SSE-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-SSE-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-SSE-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-SSE-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX1-LABEL: test_mm_cvtsd_f64:
 ; X86-AVX1:       # %bb.0:
-; X86-AVX1-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-AVX1-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-AVX1-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-AVX1-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
 ; X86-AVX1-NEXT:    vmovlps %xmm0, (%esp) # encoding: [0xc5,0xf8,0x13,0x04,0x24]
 ; X86-AVX1-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-AVX1-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-AVX1-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-AVX1-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-AVX1-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX512-LABEL: test_mm_cvtsd_f64:
 ; X86-AVX512:       # %bb.0:
-; X86-AVX512-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-AVX512-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-AVX512-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-AVX512-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
 ; X86-AVX512-NEXT:    vmovlps %xmm0, (%esp) # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x13,0x04,0x24]
 ; X86-AVX512-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-AVX512-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-AVX512-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-AVX512-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-AVX512-NEXT:    retl # encoding: [0xc3]
 ;
 ; X64-LABEL: test_mm_cvtsd_f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    retq # encoding: [0xc3]
   %res = extractelement <2 x double> %a0, i32 0
   ret double %res
 }
; AVX512-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
   ret <2 x double> %ins
 }
 declare double @llvm.sqrt.f64(double) nounwind readnone
 
 ; This doesn't match a clang test, but helps with fast-isel coverage.
 define double @test_mm_sqrt_sd_scalar(double %a0) nounwind {
 ; X86-SSE-LABEL: test_mm_sqrt_sd_scalar:
 ; X86-SSE:       # %bb.0:
-; X86-SSE-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-SSE-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-SSE-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-SSE-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
-; X86-SSE-NEXT:    movsd 8(%ebp), %xmm0 # encoding: [0xf2,0x0f,0x10,0x45,0x08]
+; X86-SSE-NEXT:    movsd {{[0-9]+}}(%esp), %xmm0 # encoding: [0xf2,0x0f,0x10,0x44,0x24,0x0c]
 ; X86-SSE-NEXT:    # xmm0 = mem[0],zero
 ; X86-SSE-NEXT:    sqrtsd %xmm0, %xmm0 # encoding: [0xf2,0x0f,0x51,0xc0]
 ; X86-SSE-NEXT:    movsd %xmm0, (%esp) # encoding: [0xf2,0x0f,0x11,0x04,0x24]
 ; X86-SSE-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-SSE-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-SSE-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-SSE-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-SSE-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX1-LABEL: test_mm_sqrt_sd_scalar:
 ; X86-AVX1:       # %bb.0:
-; X86-AVX1-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-AVX1-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-AVX1-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-AVX1-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
-; X86-AVX1-NEXT:    vmovsd 8(%ebp), %xmm0 # encoding: [0xc5,0xfb,0x10,0x45,0x08]
+; X86-AVX1-NEXT:    vmovsd {{[0-9]+}}(%esp), %xmm0 # encoding: [0xc5,0xfb,0x10,0x44,0x24,0x0c]
 ; X86-AVX1-NEXT:    # xmm0 = mem[0],zero
 ; X86-AVX1-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xfb,0x51,0xc0]
 ; X86-AVX1-NEXT:    vmovsd %xmm0, (%esp) # encoding: [0xc5,0xfb,0x11,0x04,0x24]
 ; X86-AVX1-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-AVX1-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-AVX1-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-AVX1-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-AVX1-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX512-LABEL: test_mm_sqrt_sd_scalar:
 ; X86-AVX512:       # %bb.0:
-; X86-AVX512-NEXT:    pushl %ebp # encoding: [0x55]
-; X86-AVX512-NEXT:    movl %esp, %ebp # encoding: [0x89,0xe5]
-; X86-AVX512-NEXT:    andl $-8, %esp # encoding: [0x83,0xe4,0xf8]
 ; X86-AVX512-NEXT:    subl $8, %esp # encoding: [0x83,0xec,0x08]
-; X86-AVX512-NEXT:    vmovsd 8(%ebp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x45,0x08]
+; X86-AVX512-NEXT:    vmovsd {{[0-9]+}}(%esp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x44,0x24,0x0c]
 ; X86-AVX512-NEXT:    # xmm0 = mem[0],zero
 ; X86-AVX512-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0]
 ; X86-AVX512-NEXT:    vmovsd %xmm0, (%esp) # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x04,0x24]
 ; X86-AVX512-NEXT:    fldl (%esp) # encoding: [0xdd,0x04,0x24]
-; X86-AVX512-NEXT:    movl %ebp, %esp # encoding: [0x89,0xec]
-; X86-AVX512-NEXT:    popl %ebp # encoding: [0x5d]
+; X86-AVX512-NEXT:    addl $8, %esp # encoding: [0x83,0xc4,0x08]
 ; X86-AVX512-NEXT:    retl # encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_mm_sqrt_sd_scalar:
 ; X64-SSE:       # %bb.0:
 ; X64-SSE-NEXT:    sqrtsd %xmm0, %xmm0 # encoding: [0xf2,0x0f,0x51,0xc0]
 ; X64-SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX1-LABEL: test_mm_sqrt_sd_scalar:

llvm/test/CodeGen/X86/var-permute-128.ll

; AVX-NEXT:    retq
   %ret15 = insertelement <16 x i8> %ret14, i8 %v15, i32 15
   ret <16 x i8> %ret15
 }
 
 define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %indices) nounwind {
 ; SSE3-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
 ; SSE3:       # %bb.0:
 ; SSE3-NEXT:    pushq %rbp
-; SSE3-NEXT:    movq %rsp, %rbp
 ; SSE3-NEXT:    pushq %r15
 ; SSE3-NEXT:    pushq %r14
 ; SSE3-NEXT:    pushq %r13
 ; SSE3-NEXT:    pushq %r12
 ; SSE3-NEXT:    pushq %rbx
-; SSE3-NEXT:    andq $-32, %rsp
-; SSE3-NEXT:    subq $608, %rsp # imm = 0x260
-; SSE3-NEXT:    movaps %xmm2, {{[0-9]+}}(%rsp)
+; SSE3-NEXT:    subq $424, %rsp # imm = 0x1A8
+; SSE3-NEXT:    movaps %xmm2, -{{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
-; SSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r11d
-; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r14d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r10d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r15d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r11d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r12d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r14d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r13d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r15d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r12d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r8d
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r13d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %edi
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r9d
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %esi
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ebx
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %ecx
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %edi
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %edx
-; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r9d
-; SSE3-NEXT:    andl $31, %r9d
-; SSE3-NEXT:    movzbl 64(%rsp,%r9), %ebx
-; SSE3-NEXT:    movd %ebx, %xmm8
-; SSE3-NEXT:    andl $31, %eax
-; SSE3-NEXT:    movzbl 96(%rsp,%rax), %eax
-; SSE3-NEXT:    movd %eax, %xmm15
+; SSE3-NEXT:    movaps %xmm0, (%rsp)
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ecx
+; SSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %edx
+; SSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ebp
+; SSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r8d
+; SSE3-NEXT:    andl $31, %r8d
+; SSE3-NEXT:    movzbl -96(%rsp,%r8), %esi
+; SSE3-NEXT:    movd %esi, %xmm8
+; SSE3-NEXT:    andl $31, %ebp
+; SSE3-NEXT:    movzbl -64(%rsp,%rbp), %esi
+; SSE3-NEXT:    movd %esi, %xmm15
 ; SSE3-NEXT:    andl $31, %edx
-; SSE3-NEXT:    movzbl 128(%rsp,%rdx), %eax
-; SSE3-NEXT:    movd %eax, %xmm9
+; SSE3-NEXT:    movzbl -32(%rsp,%rdx), %edx
+; SSE3-NEXT:    movd %edx, %xmm9
 ; SSE3-NEXT:    andl $31, %ecx
-; SSE3-NEXT:    movzbl 160(%rsp,%rcx), %eax
-; SSE3-NEXT:    movd %eax, %xmm3
-; SSE3-NEXT:    andl $31, %esi
-; SSE3-NEXT:    movzbl 192(%rsp,%rsi), %eax
+; SSE3-NEXT:    movzbl (%rsp,%rcx), %ecx
+; SSE3-NEXT:    movd %ecx, %xmm3
+; SSE3-NEXT:    andl $31, %eax
+; SSE3-NEXT:    movzbl 32(%rsp,%rax), %eax
 ; SSE3-NEXT:    movd %eax, %xmm10
 ; SSE3-NEXT:    andl $31, %edi
-; SSE3-NEXT:    movzbl 224(%rsp,%rdi), %eax
+; SSE3-NEXT:    movzbl 64(%rsp,%rdi), %eax
 ; SSE3-NEXT:    movd %eax, %xmm7
-; SSE3-NEXT:    andl $31, %r8d
-; SSE3-NEXT:    movzbl 256(%rsp,%r8), %eax
+; SSE3-NEXT:    andl $31, %ebx
+; SSE3-NEXT:    movzbl 96(%rsp,%rbx), %eax
 ; SSE3-NEXT:    movd %eax, %xmm11
-; SSE3-NEXT:    andl $31, %r10d
-; SSE3-NEXT:    movzbl 288(%rsp,%r10), %eax
+; SSE3-NEXT:    andl $31, %r9d
+; SSE3-NEXT:    movzbl 128(%rsp,%r9), %eax
 ; SSE3-NEXT:    movd %eax, %xmm6
 ; SSE3-NEXT:    andl $31, %r13d
-; SSE3-NEXT:    movzbl 320(%rsp,%r13), %eax
+; SSE3-NEXT:    movzbl 160(%rsp,%r13), %eax
 ; SSE3-NEXT:    movd %eax, %xmm12
 ; SSE3-NEXT:    andl $31, %r12d
-; SSE3-NEXT:    movzbl 352(%rsp,%r12), %eax
+; SSE3-NEXT:    movzbl 192(%rsp,%r12), %eax
 ; SSE3-NEXT:    movd %eax, %xmm5
 ; SSE3-NEXT:    andl $31, %r15d
-; SSE3-NEXT:    movzbl 384(%rsp,%r15), %eax
+; SSE3-NEXT:    movzbl 224(%rsp,%r15), %eax
 ; SSE3-NEXT:    movd %eax, %xmm13
 ; SSE3-NEXT:    andl $31, %r14d
-; SSE3-NEXT:    movzbl 416(%rsp,%r14), %eax
+; SSE3-NEXT:    movzbl 256(%rsp,%r14), %eax
 ; SSE3-NEXT:    movd %eax, %xmm4
 ; SSE3-NEXT:    andl $31, %r11d
-; SSE3-NEXT:    movzbl 448(%rsp,%r11), %eax
+; SSE3-NEXT:    movzbl 288(%rsp,%r11), %eax
 ; SSE3-NEXT:    movd %eax, %xmm14
-; SSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; SSE3-NEXT:    andl $31, %eax
-; SSE3-NEXT:    movzbl 480(%rsp,%rax), %eax
+; SSE3-NEXT:    andl $31, %r10d
+; SSE3-NEXT:    movzbl 320(%rsp,%r10), %eax
 ; SSE3-NEXT:    movd %eax, %xmm1
 ; SSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; SSE3-NEXT:    andl $31, %eax
-; SSE3-NEXT:    movzbl 512(%rsp,%rax), %eax
+; SSE3-NEXT:    movzbl 352(%rsp,%rax), %eax
 ; SSE3-NEXT:    movd %eax, %xmm2
 ; SSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; SSE3-NEXT:    andl $31, %eax
-; SSE3-NEXT:    movzbl 544(%rsp,%rax), %eax
+; SSE3-NEXT:    movzbl 384(%rsp,%rax), %eax
 ; SSE3-NEXT:    movd %eax, %xmm0
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],xmm10[1],xmm7[2],xmm10[2],xmm7[3],xmm10[3],xmm7[4],xmm10[4],xmm7[5],xmm10[5],xmm7[6],xmm10[6],xmm7[7],xmm10[7]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],xmm11[1],xmm6[2],xmm11[2],xmm6[3],xmm11[3],xmm6[4],xmm11[4],xmm6[5],xmm11[5],xmm6[6],xmm11[6],xmm6[7],xmm11[7]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3]
 ; SSE3-NEXT:    punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],xmm12[1],xmm5[2],xmm12[2],xmm5[3],xmm12[3],xmm5[4],xmm12[4],xmm5[5],xmm12[5],xmm5[6],xmm12[6],xmm5[7],xmm12[7]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],xmm13[1],xmm4[2],xmm13[2],xmm4[3],xmm13[3],xmm4[4],xmm13[4],xmm4[5],xmm13[5],xmm4[6],xmm13[6],xmm4[7],xmm13[7]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
 ; SSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
 ; SSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
-; SSE3-NEXT:    leaq -40(%rbp), %rsp
+; SSE3-NEXT:    addq $424, %rsp # imm = 0x1A8
 ; SSE3-NEXT:    popq %rbx
 ; SSE3-NEXT:    popq %r12
 ; SSE3-NEXT:    popq %r13
 ; SSE3-NEXT:    popq %r14
 ; SSE3-NEXT:    popq %r15
 ; SSE3-NEXT:    popq %rbp
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
 ; SSSE3:       # %bb.0:
 ; SSSE3-NEXT:    pushq %rbp
-; SSSE3-NEXT:    movq %rsp, %rbp
 ; SSSE3-NEXT:    pushq %r15
 ; SSSE3-NEXT:    pushq %r14
 ; SSSE3-NEXT:    pushq %r13
 ; SSSE3-NEXT:    pushq %r12
 ; SSSE3-NEXT:    pushq %rbx
-; SSSE3-NEXT:    andq $-32, %rsp
-; SSSE3-NEXT:    subq $608, %rsp # imm = 0x260
-; SSSE3-NEXT:    movaps %xmm2, {{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    subq $424, %rsp # imm = 0x1A8
+; SSSE3-NEXT:    movaps %xmm2, -{{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
-; SSSE3-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r11d
-; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r14d
-; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r15d
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r10d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r12d
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r11d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r13d
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r14d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r15d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r8d
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r12d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %edi
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r13d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %esi
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r9d
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %ecx
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ebx
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %edx
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %edi
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax
 ; SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSSE3-NEXT:    movzbl {{[0-9]+}}(%rsp), %r9d
-; SSSE3-NEXT:    andl $31, %r9d
-; SSSE3-NEXT:    movzbl 64(%rsp,%r9), %ebx
-; SSSE3-NEXT:    movd %ebx, %xmm8
-; SSSE3-NEXT:    andl $31, %eax
-; SSSE3-NEXT:    movzbl 96(%rsp,%rax), %eax
-; SSSE3-NEXT:    movd %eax, %xmm15
+; SSSE3-NEXT:    movaps %xmm0, (%rsp)
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ecx
+; SSSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %edx
+; SSSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %ebp
+; SSSE3-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSSE3-NEXT:    movzbl -{{[0-9]+}}(%rsp), %r8d
+; SSSE3-NEXT:    andl $31, %r8d
+; SSSE3-NEXT:    movzbl -96(%rsp,%r8), %esi
+; SSSE3-NEXT:    movd %esi, %xmm8
+; SSSE3-NEXT:    andl $31, %ebp
+; SSSE3-NEXT:    movzbl -64(%rsp,%rbp), %esi
+; SSSE3-NEXT:    movd %esi, %xmm15
 ; SSSE3-NEXT:    andl $31, %edx
-; SSSE3-NEXT:    movzbl 128(%rsp,%rdx), %eax
-; SSSE3-NEXT:    movd %eax, %xmm9
+; SSSE3-NEXT:    movzbl -32(%rsp,%rdx), %edx
+; SSSE3-NEXT:    movd %edx, %xmm9
 ; SSSE3-NEXT:    andl $31, %ecx
-; SSSE3-NEXT:    movzbl 160(%rsp,%rcx), %eax
-; SSSE3-NEXT:    movd %eax, %xmm3
-; SSSE3-NEXT:    andl $31, %esi
-; SSSE3-NEXT:    movzbl 192(%rsp,%rsi), %eax
+; SSSE3-NEXT:    movzbl (%rsp,%rcx), %ecx
+; SSSE3-NEXT:    movd %ecx, %xmm3
+; SSSE3-NEXT:    andl $31, %eax
+; SSSE3-NEXT:    movzbl 32(%rsp,%rax), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm10
 ; SSSE3-NEXT:    andl $31, %edi
-; SSSE3-NEXT:    movzbl 224(%rsp,%rdi), %eax
+; SSSE3-NEXT:    movzbl 64(%rsp,%rdi), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm7
-; SSSE3-NEXT:    andl $31, %r8d
-; SSSE3-NEXT:    movzbl 256(%rsp,%r8), %eax
+; SSSE3-NEXT:    andl $31, %ebx
+; SSSE3-NEXT:    movzbl 96(%rsp,%rbx), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm11
-; SSSE3-NEXT:    andl $31, %r10d
-; SSSE3-NEXT:    movzbl 288(%rsp,%r10), %eax
+; SSSE3-NEXT:    andl $31, %r9d
+; SSSE3-NEXT:    movzbl 128(%rsp,%r9), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm6
 ; SSSE3-NEXT:    andl $31, %r13d
-; SSSE3-NEXT:    movzbl 320(%rsp,%r13), %eax
+; SSSE3-NEXT:    movzbl 160(%rsp,%r13), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm12
 ; SSSE3-NEXT:    andl $31, %r12d
-; SSSE3-NEXT:    movzbl 352(%rsp,%r12), %eax
+; SSSE3-NEXT:    movzbl 192(%rsp,%r12), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm5
 ; SSSE3-NEXT:    andl $31, %r15d
-; SSSE3-NEXT:    movzbl 384(%rsp,%r15), %eax
+; SSSE3-NEXT:    movzbl 224(%rsp,%r15), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm13
 ; SSSE3-NEXT:    andl $31, %r14d
-; SSSE3-NEXT:    movzbl 416(%rsp,%r14), %eax
+; SSSE3-NEXT:    movzbl 256(%rsp,%r14), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm4
 ; SSSE3-NEXT:    andl $31, %r11d
-; SSSE3-NEXT:    movzbl 448(%rsp,%r11), %eax
+; SSSE3-NEXT:    movzbl 288(%rsp,%r11), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm14
-; SSSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; SSSE3-NEXT:    andl $31, %eax
-; SSSE3-NEXT:    movzbl 480(%rsp,%rax), %eax
+; SSSE3-NEXT:    andl $31, %r10d
+; SSSE3-NEXT:    movzbl 320(%rsp,%r10), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm1
 ; SSSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; SSSE3-NEXT:    andl $31, %eax
-; SSSE3-NEXT:    movzbl 512(%rsp,%rax), %eax
+; SSSE3-NEXT:    movzbl 352(%rsp,%rax), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm2
 ; SSSE3-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
 ; SSSE3-NEXT:    andl $31, %eax
-; SSSE3-NEXT:    movzbl 544(%rsp,%rax), %eax
+; SSSE3-NEXT:    movzbl 384(%rsp,%rax), %eax
 ; SSSE3-NEXT:    movd %eax, %xmm0
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],xmm10[1],xmm7[2],xmm10[2],xmm7[3],xmm10[3],xmm7[4],xmm10[4],xmm7[5],xmm10[5],xmm7[6],xmm10[6],xmm7[7],xmm10[7]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],xmm11[1],xmm6[2],xmm11[2],xmm6[3],xmm11[3],xmm6[4],xmm11[4],xmm6[5],xmm11[5],xmm6[6],xmm11[6],xmm6[7],xmm11[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1],xmm6[2],xmm7[2],xmm6[3],xmm7[3]
 ; SSSE3-NEXT:    punpckldq {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],xmm12[1],xmm5[2],xmm12[2],xmm5[3],xmm12[3],xmm5[4],xmm12[4],xmm5[5],xmm12[5],xmm5[6],xmm12[6],xmm5[7],xmm12[7]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],xmm13[1],xmm4[2],xmm13[2],xmm4[3],xmm13[3],xmm4[4],xmm13[4],xmm4[5],xmm13[5],xmm4[6],xmm13[6],xmm4[7],xmm13[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],xmm14[1],xmm1[2],xmm14[2],xmm1[3],xmm14[3],xmm1[4],xmm14[4],xmm1[5],xmm14[5],xmm1[6],xmm14[6],xmm1[7],xmm14[7]
 ; SSSE3-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
 ; SSSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
 ; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
-; SSSE3-NEXT:    leaq -40(%rbp), %rsp
+; SSSE3-NEXT:    addq $424, %rsp # imm = 0x1A8
 ; SSSE3-NEXT:    popq %rbx
 ; SSSE3-NEXT:    popq %r12
 ; SSSE3-NEXT:    popq %r13
 ; SSSE3-NEXT:    popq %r14
 ; SSSE3-NEXT:    popq %r15
 ; SSSE3-NEXT:    popq %rbp
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pushq %rbp
-; SSE41-NEXT:    movq %rsp, %rbp
-; SSE41-NEXT:    andq $-32, %rsp
-; SSE41-NEXT:    subq $544, %rsp # imm = 0x220
+; SSE41-NEXT:    subq $392, %rsp # imm = 0x188
 ; SSE41-NEXT:    movd %xmm2, %eax
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    andl $31, %eax
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)

 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE41-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    movaps %xmm0, (%rsp)
-; SSE41-NEXT:    movzbl 480(%rsp,%rax), %eax
+; SSE41-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; SSE41-NEXT:    movzbl 352(%rsp,%rax), %eax
 ; SSE41-NEXT:    movd %eax, %xmm0
 ; SSE41-NEXT:    pextrb $1, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $1, 448(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $1, 320(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $2, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $2, 416(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $2, 288(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $3, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $3, 384(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $3, 256(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $4, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $4, 352(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $4, 224(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $5, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $5, 320(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $5, 192(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $6, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $6, 288(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $6, 160(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $7, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $7, 256(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $7, 128(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $8, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $8, 224(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $8, 96(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $9, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $9, 192(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $9, 64(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $10, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $10, 160(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $10, 32(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $11, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $11, 128(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $11, (%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $12, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $12, 96(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $12, -32(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $13, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $13, 64(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $13, -64(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $14, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $14, 32(%rsp,%rax), %xmm0
+; SSE41-NEXT:    pinsrb $14, -96(%rsp,%rax), %xmm0
 ; SSE41-NEXT:    pextrb $15, %xmm2, %eax
 ; SSE41-NEXT:    andl $31, %eax
-; SSE41-NEXT:    pinsrb $15, (%rsp,%rax), %xmm0
-; SSE41-NEXT:    movq %rbp, %rsp
-; SSE41-NEXT:    popq %rbp
+; SSE41-NEXT:    pinsrb $15, -128(%rsp,%rax), %xmm0
+; SSE41-NEXT:    addq $392, %rsp # imm = 0x188
 ; SSE41-NEXT:    retq
 ;
 ; XOP-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; XOP-NEXT:    vpperm %xmm1, %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vzeroupper
 ; XOP-NEXT:    retq

llvm/test/CodeGen/X86/vec-strict-128.ll

%res = call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c,
                                                                    metadata !"round.dynamic",
                                                                    metadata !"fpexcept.strict") #0
   ret <4 x float> %res
 }
 
 define <2 x double> @f14(<2 x double> %a, <2 x double> %b, <2 x double> %c) #0 {
 ; SSE-X86-LABEL: f14:
 ; SSE-X86:       # %bb.0:
-; SSE-X86-NEXT:    pushl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_offset 8
-; SSE-X86-NEXT:    .cfi_offset %ebp, -8
-; SSE-X86-NEXT:    movl %esp, %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa_register %ebp
-; SSE-X86-NEXT:    andl $-16, %esp
-; SSE-X86-NEXT:    subl $112, %esp
-; SSE-X86-NEXT:    movaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
-; SSE-X86-NEXT:    movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
-; SSE-X86-NEXT:    movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; SSE-X86-NEXT:    subl $108, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 112
+; SSE-X86-NEXT:    movups %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; SSE-X86-NEXT:    movups %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; SSE-X86-NEXT:    movups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
 ; SSE-X86-NEXT:    movlps %xmm2, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movlps %xmm1, {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    movlps %xmm0, (%esp)
 ; SSE-X86-NEXT:    calll fma
-; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
-; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, {{[0-9]+}}(%esp)
-; SSE-X86-NEXT:    movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-X86-NEXT:    movups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
 ; SSE-X86-NEXT:    movhps %xmm0, (%esp)
 ; SSE-X86-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    calll fma
 ; SSE-X86-NEXT:    fstpl {{[0-9]+}}(%esp)
 ; SSE-X86-NEXT:    wait
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
-; SSE-X86-NEXT:    movl %ebp, %esp
-; SSE-X86-NEXT:    popl %ebp
-; SSE-X86-NEXT:    .cfi_def_cfa %esp, 4
+; SSE-X86-NEXT:    addl $108, %esp
+; SSE-X86-NEXT:    .cfi_def_cfa_offset 4
 ; SSE-X86-NEXT:    retl
 ;
 ; SSE-X64-LABEL: f14:
 ; SSE-X64:       # %bb.0:
 ; SSE-X64-NEXT:    subq $72, %rsp
 ; SSE-X64-NEXT:    .cfi_def_cfa_offset 80
 ; SSE-X64-NEXT:    movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
 ; SSE-X64-NEXT:    movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill

llvm/test/CodeGen/X86/vec_insert-4.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-apple-darwin9.2.2 -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9.2.2 -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64
 
 define <8 x float> @f(<8 x float> %a, i32 %b) nounwind  {
 ; X32-LABEL: f:
 ; X32:       ## %bb.0: ## %entry
-; X32-NEXT:    pushl %ebp
-; X32-NEXT:    movl %esp, %ebp
-; X32-NEXT:    andl $-32, %esp
-; X32-NEXT:    subl $64, %esp
-; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    subl $44, %esp
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    andl $7, %eax
 ; X32-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movaps %xmm0, (%esp)
 ; X32-NEXT:    movl $1084227584, (%esp,%eax,4) ## imm = 0x40A00000
 ; X32-NEXT:    movaps (%esp), %xmm0
 ; X32-NEXT:    movaps {{[0-9]+}}(%esp), %xmm1
-; X32-NEXT:    movl %ebp, %esp
-; X32-NEXT:    popl %ebp
+; X32-NEXT:    addl $44, %esp
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: f:
 ; X64:       ## %bb.0: ## %entry
-; X64-NEXT:    pushq %rbp
-; X64-NEXT:    movq %rsp, %rbp
-; X64-NEXT:    andq $-32, %rsp
-; X64-NEXT:    subq $64, %rsp
 ; X64-NEXT:    ## kill: def $edi killed $edi def $rdi
-; X64-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
-; X64-NEXT:    movaps %xmm0, (%rsp)
+; X64-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    andl $7, %edi
-; X64-NEXT:    movl $1084227584, (%rsp,%rdi,4) ## imm = 0x40A00000
-; X64-NEXT:    movaps (%rsp), %xmm0
-; X64-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
-; X64-NEXT:    movq %rbp, %rsp
-; X64-NEXT:    popq %rbp
+; X64-NEXT:    movl $1084227584, -40(%rsp,%rdi,4) ## imm = 0x40A00000
+; X64-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm0
+; X64-NEXT:    movaps -{{[0-9]+}}(%rsp), %xmm1
 ; X64-NEXT:    retq
 entry:
   %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b
   ret <8 x float> %vecins
 }

llvm/test/CodeGen/X86/vector-extend-inreg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2   | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X64-SSE
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2   | FileCheck %s --check-prefix=ALL --check-prefix=X32-AVX
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X64-AVX
 
 define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) nounwind {
 ; X32-SSE-LABEL: extract_any_extend_vector_inreg_v16i64:
 ; X32-SSE:       # %bb.0:
 ; X32-SSE-NEXT:    pushl %ebp
 ; X32-SSE-NEXT:    movl %esp, %ebp
-; X32-SSE-NEXT:    andl $-128, %esp
-; X32-SSE-NEXT:    subl $384, %esp # imm = 0x180
+; X32-SSE-NEXT:    andl $-16, %esp
+; X32-SSE-NEXT:    subl $272, %esp # imm = 0x110
 ; X32-SSE-NEXT:    movl 88(%ebp), %ecx
 ; X32-SSE-NEXT:    movdqa 72(%ebp), %xmm0
 ; X32-SSE-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
 ; X32-SSE-NEXT:    xorps %xmm1, %xmm1
 ; X32-SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
 ; X32-SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
 ; X32-SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
 ; X32-SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)

 ; X32-SSE-NEXT:    andl $31, %ecx
 ; X32-SSE-NEXT:    movl (%esp,%ecx,4), %edx
 ; X32-SSE-NEXT:    movl %ebp, %esp
 ; X32-SSE-NEXT:    popl %ebp
 ; X32-SSE-NEXT:    retl
 ;
 ; X64-SSE-LABEL: extract_any_extend_vector_inreg_v16i64:
 ; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    pushq %rbp
-; X64-SSE-NEXT:    movq %rsp, %rbp
-; X64-SSE-NEXT:    andq $-128, %rsp
-; X64-SSE-NEXT:    subq $256, %rsp # imm = 0x100
+; X64-SSE-NEXT:    pushq %rax
 ; X64-SSE-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-SSE-NEXT:    psrldq {{.*#+}} xmm7 = xmm7[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
 ; X64-SSE-NEXT:    xorps %xmm0, %xmm0
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; X64-SSE-NEXT:    movaps %xmm0, (%rsp)
-; X64-SSE-NEXT:    movdqa %xmm7, {{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-SSE-NEXT:    movdqa %xmm7, -{{[0-9]+}}(%rsp)
 ; X64-SSE-NEXT:    andl $15, %edi
-; X64-SSE-NEXT:    movq (%rsp,%rdi,8), %rax
-; X64-SSE-NEXT:    movq %rbp, %rsp
-; X64-SSE-NEXT:    popq %rbp
+; X64-SSE-NEXT:    movq -128(%rsp,%rdi,8), %rax
+; X64-SSE-NEXT:    popq %rcx
 ; X64-SSE-NEXT:    retq
 ;
 ; X32-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
 ; X32-AVX:       # %bb.0:
 ; X32-AVX-NEXT:    pushl %ebp
 ; X32-AVX-NEXT:    movl %esp, %ebp
-; X32-AVX-NEXT:    andl $-128, %esp
-; X32-AVX-NEXT:    subl $384, %esp # imm = 0x180
+; X32-AVX-NEXT:    andl $-32, %esp
+; X32-AVX-NEXT:    subl $288, %esp # imm = 0x120
 ; X32-AVX-NEXT:    movl 40(%ebp), %ecx
 ; X32-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X32-AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
 ; X32-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)
 ; X32-AVX-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%esp)
 ; X32-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%esp)

 ; X32-AVX-NEXT:    popl %ebp
 ; X32-AVX-NEXT:    vzeroupper
 ; X32-AVX-NEXT:    retl
 ;
 ; X64-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
 ; X64-AVX:       # %bb.0:
 ; X64-AVX-NEXT:    pushq %rbp
 ; X64-AVX-NEXT:    movq %rsp, %rbp
-; X64-AVX-NEXT:    andq $-128, %rsp
-; X64-AVX-NEXT:    subq $256, %rsp # imm = 0x100
+; X64-AVX-NEXT:    andq $-32, %rsp
+; X64-AVX-NEXT:    subq $160, %rsp
 ; X64-AVX-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-AVX-NEXT:    vpermq {{.*#+}} ymm0 = ymm3[3,1,2,3]
 ; X64-AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
 ; X64-AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
 ; X64-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%rsp)
 ; X64-AVX-NEXT:    vmovaps %ymm1, (%rsp)
 ; X64-AVX-NEXT:    vmovdqa %ymm0, {{[0-9]+}}(%rsp)