[globalisel] Add lost debug locations verifier

[dsanders]

Summary

This verifier tries to ensure that DebugLoc's don't just disappear as
we transform the MIR. It observes the instructions created, erased, and
changed and at checkpoints chosen by the client algorithm verifies the
locations affected by those changes.

In particular, it verifies that:

• Every DebugLoc for an erased/changing instruction is still present on at least one new/changed instruction
• Failing that, that there is a line-0 location in the new/changed instructions. It's not possible to confirm which locations were merged so it conservatively assumes all unaccounted for locations are accounted for by any line-0 location to avoid false positives.

If that fails, it prints the lost locations in the debug output along with
the instructions that should have accounted for them.

In theory, this is usable by the legalizer, combiner, selector and any other
pass that performs incremental changes to the MIR. However, it has so far
only really been tested on the legalizer (not including the artifact
combiner) where it has caught lots of lost locations, particularly in Custom
legalizations. The tests in this patch are those the verifier detected a problem in after applying it to all the .mir tests for AArch64 and AMDGPU.

Depends on D77575, D77446

[dsanders]

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

169

The addition of this argument is rather unfortunate given the AuxObservers list. The reason is the LocObserver needs to be more tightly integrated into the algorithm than most observers. The fewer changes that are made between checkpoints, the more accurately it can detect lossage, particularly given the conservative behaviour for line-0 locations.

In the end I settled on a separate argument over finding the observer within the AuxObservers list as we currently don't have isa/dyn_cast support in observers

[paquette]

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

369

Can this use NV?

E.g. something like

R << "lost " << NV("NumLostDebugLocs", LocObserver.getNumLostDebugLocs()) << " debug locations during pass";

I think that would make optimization records easier to parse, if you choose to save them.

It would also be nice to have a testcase for the remarks.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LostDebugLocObserver.h

1

Missing C++ mode comment

36–39

Defined to no-op calls in debug build?

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

64

Missing static const?

370

Missing newline?

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

3

Do we really need to double the number of run lines in every test?

[paquette]

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

369

Although that being said, any testcase that exposes this is a bug we should fix, so... maybe it's not reasonable to test it. :)

It would be nice to know what the opt remark output looks like though.

[vsk]

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

3

There are some alternatives:

• Get rid of the non-mir debugify check lines. This is fine by me, but some pass authors might not like this.
• Run the tests with llvm-lit -Dopt='opt -debugify -Dllc='llc -run-pass=mir-debugify'`. That means only a subset of users/bots are test with debug info.

[dsanders]

llvm/include/llvm/CodeGen/GlobalISel/LostDebugLocObserver.h

36–39

I assume you mean the non-debug build.

I suppose we could do as there's a small code-size saving from it. It shouldn't affect execution time though as we just decline to install the observer for that case

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

369

Can this use NV?

I didn't know about NV. Fixed in my working copy

It would also be nice to have a testcase for the remarks.

A test case is tricky because as you say, we should fix all the cases where this actually happens.

It would be nice to know what the opt remark output looks like though.

I'll add an example in a comment

370

As far as I know, it's not needed for remarks. The other two above don't have a newline at least

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

3

Do we really need to double the number of run lines in every test?

I kept it to the ones that actually reveal something but I agree it's not great to have the extra run lines. Not least because they don't actually do anything different to the main ones on non-asserts builds because the LostDebugLocObserver doesn't get installed. For that build, they're just wasting time.

I want to end up at a -verify-mir-debug-locations similar to -verify-machineinstrs (however that spelling is a bit misleading because each pass must cooperate to verify anything) or -mir-debugify-before-all -mir-strip-debug-after-all or something along those lines. At that point injecting the options via lit makes a lot of sense.

[dsanders]

C++ mode comment
Use ore::NV
Fix build errors in legalizer unit test

[dsanders]

Removed test changes, now covered by llvm-lit -Dllc='llc --debugify-and-strip-all-safe --debugify-level=locations'

[vsk]

llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp

44

Why not delete HasUnseenLineZeroLoc and return early here?

84

Please have this return early, ideally like 'if (MI.isConstant()) return;'

I don't mean to suggest that you make tangential changes, it's just that it seems like there's a need for such a predicate (e.g. https://llvm.org/doxygen/AMDGPUInstructionSelector_8cpp_source.html#l01470 defines isConstant for MIs but leaves out G_FCONSTANT).

92

Ditto.

[dsanders]

Add missing opcodes that never have locations
Predicate
Early returns

llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp

84

I looked at this again and found I'd missed G_IMPLICIT_DEF and G_GLOBAL_VALUE which also have their debug locations removed by the IRTranslator to avoid 'jumpy' behaviour in the debugger. I've added a predicate so we don't have two copies of the code in this file but it's not really meaningful for other code.

[vsk]

I think this is in good shape overall, but I'll defer to someone with more GISel experience to lgtm this patch.

llvm/include/llvm/CodeGen/GlobalISel/LostDebugLocObserver.h

29

Can analyzeDebugLocations be private?

33

The checkpoint method could use some doxygen (when exactly should clients call it, and when should CheckDebugLocs be false)?

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

64

This is still missing.

[dsanders]

static const
Doxygen comment
Make a function private

[aprantl]

llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp

2

Please don't put -*- C++ -*- markers into .cpp files, that's redundant. They are only needed for .h files, where it is ambiguous whether it's C or C++.

[paquette]

After you address @aprantl's comment, I think that this looks fine.

[qcolombet]

Hi Daniel,

What is the compile time impact of this change?

Is there a way to make the callers agnostic to the kind of observers we are dealing with?

Basically, I like the observer idea for checking the debug information, but I don't like that:

1. We have to add a bunch of checkpoint calls all over the place
2. We have to specifically carry this observer around instead of having it being with the other observers (AuxObservers argument)

Bottom line, it feels intrusive and if we have to do that everywhere I am afraid we won't be able to scale.

I am fine with moving forward with that patch for the time being, but I think we have to rethink our strategy long term.

Cheers,
-Quentin

[dsanders]

In D77576#1978914, @qcolombet wrote:

Hi Daniel,

What is the compile time impact of this change?

That depends on VerifyDebugLocs. When it's None (default for release), there shouldn't be a measurable impact as the observer doesn't get installed. I haven't measured it for Locations (current default for asserts) yet as I've been more focused on fixing the bugs it finds in our out-of-tree target so far. I don't expect it to be noticable as it's a fairly simple matcher on small search spaces but if it is we can change the default to None at the cost of needing to use an extra option in out llvm-lit -Dllc='llc ...' command.

Is there a way to make the callers agnostic to the kind of observers we are dealing with?

In general, not really as each observer implementation will have different requirements depending on what they're for. That said, two of the three observers so far wrap logical changes (transactions except we don't really have that concept) to the IR and the third just follows the events as they happen. So while we can't really solve it in general, we could add another event to observer interface. There's no guarantee we won't need something else in the future though that causes the observers to diverge again though.

Basically, I like the observer idea for checking the debug information, but I don't like that:

1. We have to add a bunch of checkpoint calls all over the place

There's not really any avoiding these calls. The verifier needs to check often to minimize the times it just gives up but not so often that it checks while the IR is expected to be in a broken state. Only the algorithm knows when it's safe to have the verifier check the locations. Maybe a transaction-complete style event is common enough that we can add it to the observer interface and leave it very vague as to what a transaction is.

2. We have to specifically carry this observer around instead of having it being with the other observers (AuxObservers argument)

FWIW, it's 'as well as it being with the other observers' but that makes no real difference to your point. I dislike this too both because AuxObservers is trying to force common behaviour where it doesn't really exist but also because if it's going to be there then there shouldn't need to be separate arguments as well. It's possible to fix this but only if we design the observer interface to suit the observers that exist today rather than what they are in principle.

[dsanders]

One more last-minute fix: If there was a line-0 location in the input
and the output it was matching them up. If another location folded
into that line-0 location it would falsely be considered lost despite
being handled correctly because the code to treat line-0 locations
as covering everything was not reached.

[dsanders]

In D77576#1979013, @dsanders wrote:

In D77576#1978914, @qcolombet wrote:

Hi Daniel,

What is the compile time impact of this change?

That depends on VerifyDebugLocs. When it's None (default for release), there shouldn't be a measurable impact as the observer doesn't get installed. I haven't measured it for Locations (current default for asserts) yet as I've been more focused on fixing the bugs it finds in our out-of-tree target so far. I don't expect it to be noticable as it's a fairly simple matcher on small search spaces but if it is we can change the default to None at the cost of needing to use an extra option in out llvm-lit -Dllc='llc ...' command.

Running CTMark with -j20 (because I'm not looking at individual tests, just the rough total), I get:

• X86 -fglobal-isel -g: 3215s without this patch, 3209s with it
• X86 -fglobal-isel: 3133s without this patch, 3133s with it
• AArch64 -fglobal-isel -g: 3065s without this patch, 3053s with it
• AArch64 -fglobal-isel: 2972s without this patch, 2979s with it

So I'd say that leaving it on by default for asserts has no significant impact on compile time

I did run into an interesting issue in some other testing I was doing though. A verifier failure can cause GlobalISel to fall back on DAGISel when fallbacks are enabled, changing codegen. I'm going to have to tweak how failures are reported to fix that

llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h

 //== llvm/CodeGen/GlobalISel/Legalizer.h ---------------- -*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #define LLVM_CODEGEN_GLOBALISEL_LEGALIZEMACHINEIRPASS_H
 
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 
 namespace llvm {
 
 class MachineRegisterInfo;
+class LostDebugLocObserver;
 
 class Legalizer : public MachineFunctionPass {
 public:
   static char ID;
 
   struct MFResult {
     bool Changed;
     const MachineInstr *FailedOn;
public:
   bool combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,
                        const TargetInstrInfo &TII);
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   static MFResult
   legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
                           ArrayRef<GISelChangeObserver *> AuxObservers,
+                          LostDebugLocObserver &LocObserver,
                           MachineIRBuilder &MIRBuilder);
 };
 } // End namespace llvm.
 
 #endif

llvm/include/llvm/CodeGen/GlobalISel/LostDebugLocObserver.h

+//===----- llvm/CodeGen/GlobalISel/LostDebugLocObserver.h -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// Tracks DebugLocs between checkpoints and verifies that they are transferred.
+//
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_CODEGEN_GLOBALISEL_LOSTDEBUGLOCOBSERVER_H
+#define LLVM_CODEGEN_GLOBALISEL_LOSTDEBUGLOCOBSERVER_H
+
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+
+namespace llvm {
+class LostDebugLocObserver : public GISelChangeObserver {
+  StringRef DebugType;
+  SmallSet<DebugLoc, 4> LostDebugLocs;
+  SmallPtrSet<MachineInstr *, 4> PotentialMIsForDebugLocs;
+  unsigned NumLostDebugLocs = 0;
+
+public:
+  LostDebugLocObserver(StringRef DebugType) : DebugType(DebugType) {}
+
+  void analyzeDebugLocations();
+
+  unsigned getNumLostDebugLocs() const {
+    return NumLostDebugLocs;
+  }
+
+  void checkpoint(bool CheckDebugLocs = true);
+
+  void createdInstr(MachineInstr &MI) override;
+  void erasingInstr(MachineInstr &MI) override;
+  void changingInstr(MachineInstr &MI) override;
+  void changedInstr(MachineInstr &MI) override;
+};
+
+} // namespace llvm
+#endif // ifndef LLVM_CODEGEN_GLOBALISEL_LOSTDEBUGLOCOBSERVER_H

llvm/lib/CodeGen/GlobalISel/CMakeLists.txt

add_llvm_component_library(LLVMGlobalISel
         InstructionSelect.cpp
         InstructionSelector.cpp
         LegalityPredicates.cpp
         LegalizeMutations.cpp
         Legalizer.cpp
         LegalizerHelper.cpp
         LegalizerInfo.cpp
         Localizer.cpp
+        LostDebugLocObserver.cpp
         MachineIRBuilder.cpp
         RegBankSelect.cpp
         RegisterBank.cpp
         RegisterBankInfo.cpp
         Utils.cpp
 
         DEPENDS
         intrinsics_gen
   )

llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

 //===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file This file implements the LegalizerHelper class to legalize individual
 /// instructions and the LegalizePass wrapper pass for the primary
 /// legalization.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
 #include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
 #include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
 #include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Target/TargetMachine.h"
 
 #include <iterator>
 
 #define DEBUG_TYPE "legalizer"
 
 using namespace llvm;
 
 static cl::opt<bool>
     EnableCSEInLegalizer("enable-cse-in-legalizer",
                          cl::desc("Should enable CSE in Legalizer"),
                          cl::Optional, cl::init(false));
 
+enum class DebugLocVerifyLevel {
+  None,
+  Legalizations,
+  LegalizationsAndArtifactCombiners,
+};
+#ifndef NDEBUG
+static cl::opt<DebugLocVerifyLevel> VerifyDebugLocs(
+    "verify-legalizer-debug-locs",
+    cl::desc("Verify that debug locations are handled"),
+    cl::values(clEnumVal(DebugLocVerifyLevel::None, "No verification"),
+               clEnumVal(DebugLocVerifyLevel::Legalizations,
+                         "Verify legalizations"),
+               clEnumVal(DebugLocVerifyLevel::LegalizationsAndArtifactCombiners,
+                         "Verify legalizations and artifact combines")),
+    cl::init(DebugLocVerifyLevel::Legalizations));
+#else
+// Always disable it for release builds by preventing the observer from being
+// installed.
+DebugLocVerifyLevel VerifyDebugLocs = DebugLocVerifyLevel::None;
+#endif
+
 char Legalizer::ID = 0;
 INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
                       "Legalize the Machine IR a function's Machine IR", false,
                       false)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
 INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
                     "Legalize the Machine IR a function's Machine IR", false,
void changedInstr(MachineInstr &MI) override {
     createdOrChangedInstr(MI);
   }
 };
 } // namespace
 
 Legalizer::MFResult
 Legalizer::legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
                                    ArrayRef<GISelChangeObserver *> AuxObservers,
+                                   LostDebugLocObserver &LocObserver,
                                    MachineIRBuilder &MIRBuilder) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   // Populate worklists.
   InstListTy InstList;
   ArtifactListTy ArtifactList;
   ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
   // Perform legalization bottom up so we can DCE as we legalize.
do {
     unsigned NumArtifacts = ArtifactList.size();
     while (!InstList.empty()) {
       MachineInstr &MI = *InstList.pop_back_val();
       assert(isPreISelGenericOpcode(MI.getOpcode()) &&
              "Expecting generic opcode");
       if (isTriviallyDead(MI, MRI)) {
         LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
         MI.eraseFromParentAndMarkDBGValuesForRemoval();
+        LocObserver.checkpoint();
         continue;
       }
 
       // Do the legalization for this instruction.
       auto Res = Helper.legalizeInstrStep(MI);
       // Error out if we couldn't legalize this instruction. We may want to
       // fall back to DAG ISel instead in the future.
       if (Res == LegalizerHelper::UnableToLegalize) {
while (!InstList.empty()) {
           (void)NumArtifacts;
           RetryList.push_back(&MI);
           continue;
         }
         Helper.MIRBuilder.stopObservingChanges();
         return {Changed, &MI};
       }
       WorkListObserver.printNewInstrs();
+      LocObserver.checkpoint();
       Changed |= Res == LegalizerHelper::Legalized;
     }
     // Try to combine the instructions in RetryList again if there
     // are new artifacts. If not, stop legalizing.
     if (!RetryList.empty()) {
       if (!ArtifactList.empty()) {
         while (!RetryList.empty())
           ArtifactList.insert(RetryList.pop_back_val());
       } else {
         LLVM_DEBUG(dbgs() << "No new artifacts created, not retrying!\n");
         Helper.MIRBuilder.stopObservingChanges();
         return {Changed, RetryList.front()};
       }
     }
+    LocObserver.checkpoint();
     while (!ArtifactList.empty()) {
       MachineInstr &MI = *ArtifactList.pop_back_val();
       assert(isPreISelGenericOpcode(MI.getOpcode()) &&
              "Expecting generic opcode");
       if (isTriviallyDead(MI, MRI)) {
         LLVM_DEBUG(dbgs() << MI << "Is dead\n");
         RemoveDeadInstFromLists(&MI);
         MI.eraseFromParentAndMarkDBGValuesForRemoval();
+        LocObserver.checkpoint();
         continue;
       }
       SmallVector<MachineInstr *, 4> DeadInstructions;
       LLVM_DEBUG(dbgs() << "Trying to combine: " << MI);
       if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions,
                                             WrapperObserver)) {
         WorkListObserver.printNewInstrs();
+        LocObserver.checkpoint(
+            VerifyDebugLocs ==
+            DebugLocVerifyLevel::LegalizationsAndArtifactCombiners);
         for (auto *DeadMI : DeadInstructions) {
           LLVM_DEBUG(dbgs() << *DeadMI << "Is dead\n");
           RemoveDeadInstFromLists(DeadMI);
           DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
         }
+        LocObserver.checkpoint();
         Changed = true;
         continue;
       }
       // If this was not an artifact (that could be combined away), this might
       // need special handling. Add it to InstList, so when it's processed
       // there, it has to be legal or specially handled.
       else {
         LLVM_DEBUG(dbgs() << ".. Not combined, moving to instructions list\n");
if (EnableCSE) {
     MIRBuilder = std::make_unique<MachineIRBuilder>();
 
   SmallVector<GISelChangeObserver *, 1> AuxObservers;
   if (EnableCSE && CSEInfo) {
     // We want CSEInfo in addition to WorkListObserver to observe all changes.
     AuxObservers.push_back(CSEInfo);
   }
   assert(!CSEInfo || !errorToBool(CSEInfo->verify()));
+  LostDebugLocObserver LocObserver(DEBUG_TYPE);
+  if (VerifyDebugLocs > DebugLocVerifyLevel::None)
+    AuxObservers.push_back(&LocObserver);
 
   const LegalizerInfo &LI = *MF.getSubtarget().getLegalizerInfo();
-  MFResult Result = legalizeMachineFunction(MF, LI, AuxObservers, *MIRBuilder);
+  MFResult Result =
+      legalizeMachineFunction(MF, LI, AuxObservers, LocObserver, *MIRBuilder);
 
   if (Result.FailedOn) {
     reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
                        "unable to legalize instruction", *Result.FailedOn);
     return false;
   }
   // For now don't support if new blocks are inserted - we would need to fix the
   // outer loop for that.
   if (MF.size() != NumBlocks) {
     MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
                                       MF.getFunction().getSubprogram(),
                                       /*MBB=*/nullptr);
     R << "inserting blocks is not supported yet";
     reportGISelFailure(MF, TPC, MORE, R);
     return false;
   }
+
+  if (LocObserver.getNumLostDebugLocs()) {
+    MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
+                                      MF.getFunction().getSubprogram(),
+                                      /*MBB=*/&*MF.begin());
+    R << "lost " << std::to_string(LocObserver.getNumLostDebugLocs())
+      << " debug locations during pass";
+    reportGISelFailure(MF, TPC, MORE, R);
+  }
+
   // If for some reason CSE was not enabled, make sure that we invalidate the
   // CSEInfo object (as we currently declare that the analysis is preserved).
   // The next time get on the wrapper is called, it will force it to recompute
   // the analysis.
   if (!EnableCSE)
     Wrapper.setComputed(false);
   return Result.Changed;
 }

llvm/lib/CodeGen/GlobalISel/LostDebugLocObserver.cpp

+//===----- llvm/CodeGen/GlobalISel/LostDebugLocObserver.h -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// Tracks DebugLocs between checkpoints and verifies that they are transferred.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
+
+using namespace llvm;
+
+#define LOC_DEBUG(X) DEBUG_WITH_TYPE(DebugType.str().c_str(), X)
+
+void LostDebugLocObserver::analyzeDebugLocations() {
+  if (LostDebugLocs.empty()) {
+    LOC_DEBUG(dbgs() << ".. No debug info was present\n");
+    return;
+  }
+  if (PotentialMIsForDebugLocs.empty()) {
+    LOC_DEBUG(
+        dbgs() << ".. No instructions to carry debug info (dead code?)\n");
+    return;
+  }
+
+  LOC_DEBUG(dbgs() << ".. Searching " << PotentialMIsForDebugLocs.size()
+                   << " instrs for " << LostDebugLocs.size() << " locations\n");
+  SmallPtrSet<MachineInstr *, 4> FoundIn;
+  bool HasUnseenLineZeroLoc = false;
+  for (MachineInstr *MI : PotentialMIsForDebugLocs) {
+    if (!MI->getDebugLoc())
+      continue;
+    if (LostDebugLocs.erase(MI->getDebugLoc())) {
+      LOC_DEBUG(dbgs() << ".. .. found " << MI->getDebugLoc() << " in " << *MI);
+      FoundIn.insert(MI);
+      continue;
+    }
+    if (MI->getDebugLoc().getLine() == 0)
+      HasUnseenLineZeroLoc = true;
+  }
+  if (LostDebugLocs.empty())
+    return;
+  if (HasUnseenLineZeroLoc) {
+    LOC_DEBUG(dbgs() << ".. Assuming line-0 location covers remainder\n");
+    return;
+  }
+
+  NumLostDebugLocs += LostDebugLocs.size();
+  LOC_DEBUG({
+    dbgs() << ".. Lost locations:\n";
+    for (const DebugLoc &Loc : LostDebugLocs) {
+      dbgs() << ".. .. ";
+      Loc.print(dbgs());
+      dbgs() << "\n";
+    }
+    dbgs() << ".. MIs with matched locations:\n";
+    for (MachineInstr *MI : FoundIn)
+      if (PotentialMIsForDebugLocs.erase(MI))
+        dbgs() << ".. .. " << *MI;
+    dbgs() << ".. Remaining MIs with unmatched/no locations:\n";
+    for (const MachineInstr *MI : PotentialMIsForDebugLocs)
+      dbgs() << ".. .. " << *MI;
+  });
+}
+
+void LostDebugLocObserver::checkpoint(bool CheckDebugLocs) {
+  if (CheckDebugLocs)
+    analyzeDebugLocations();
+  PotentialMIsForDebugLocs.clear();
+  LostDebugLocs.clear();
+}
+
+void LostDebugLocObserver::createdInstr(MachineInstr &MI) {
+  PotentialMIsForDebugLocs.insert(&MI);
+}
+
+void LostDebugLocObserver::erasingInstr(MachineInstr &MI) {
+  if (MI.getOpcode() != TargetOpcode::G_CONSTANT &&
+      MI.getOpcode() != TargetOpcode::G_FCONSTANT) {
+    PotentialMIsForDebugLocs.erase(&MI);
+    if (MI.getDebugLoc())
+      LostDebugLocs.insert(MI.getDebugLoc());
+  }
+}
+
+void LostDebugLocObserver::changingInstr(MachineInstr &MI) {
+  if (MI.getOpcode() != TargetOpcode::G_CONSTANT &&
+      MI.getOpcode() != TargetOpcode::G_FCONSTANT) {
+    PotentialMIsForDebugLocs.erase(&MI);
+    if (MI.getDebugLoc())
+      LostDebugLocs.insert(MI.getDebugLoc());
+  }
+}
+
+void LostDebugLocObserver::changedInstr(MachineInstr &MI) {
+  PotentialMIsForDebugLocs.insert(&MI);
+}

llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -march=aarch64 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            test_memcpy
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $w2, $x0, $x1
 
     ; CHECK-LABEL: name: test_memcpy

llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
+# RUN: llc -O0 -run-pass=mir-debugify,legalizer %s -o - -global-isel-abort=1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test_vaarg() { ret void }
 ...
 
 ---

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_add_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_add_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=VI %s
 # RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=GFX9 %s
 # RUN: llc -march=amdgcn -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI %s
+# RUN: llc -march=amdgcn -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=SI %s
 
 ---
 name: test_addrspacecast_p0_to_p1
 machineFunctionInfo:
   argumentInfo:
     queuePtr: { reg: '$sgpr4_sgpr5' }
 
 body: |

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=WAVE64 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=WAVE32 %s
 
 ---
 name: test_wavefrontsize
 body: |
   bb.0:
 
     ; WAVE64-LABEL: name: test_wavefrontsize
     ; WAVE64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
     ; WAVE64: $vgpr0 = COPY [[C]](s32)
     ; WAVE32-LABEL: name: test_wavefrontsize
     ; WAVE32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
     ; WAVE32: $vgpr0 = COPY [[C]](s32)
     %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wavefrontsize)
     $vgpr0 = COPY %0
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: atomic_cmpxchg_local_i32
 
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $sgpr2
     ; CHECK-LABEL: name: atomic_cmpxchg_local_i32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=WAVE64 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=WAVE32 %s
 
 ---
 name: legal_brcond_vcc
 body:             |
   ; WAVE64-LABEL: name: legal_brcond_vcc
   ; WAVE64: bb.0:
   ; WAVE64:   successors: %bb.1(0x80000000)
   ; WAVE64:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX8 %s
 
 ---
 name: bswap_s8
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX7-LABEL: name: bswap_s8

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: legal_v2s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     ; CHECK-LABEL: name: legal_v2s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: extract_vector_elt_0_v2i32
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s  | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=VI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fcos_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; SI-LABEL: name: test_fcos_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0  %s -o - | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  %s -o - | FileCheck -check-prefix=VI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0  %s -o - | FileCheck -check-prefix=VI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -enable-unsafe-fp-math -o - %s | FileCheck -check-prefix=GFX9-UNSAFE %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -enable-unsafe-fp-math -o - %s | FileCheck -check-prefix=GFX9-UNSAFE %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fdiv_s16
 machineFunctionInfo:
   mode:
     fp32-input-denormals: true
     fp32-output-denormals: true
     fp64-fp16-input-denormals: true

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck  -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck  -check-prefix=GFX9 %s
 
 ---
 name: test_fexp_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX6-LABEL: name: test_fexp_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=VI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_ffloor_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; SI-LABEL: name: test_ffloor_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: test_flog_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: test_flog10_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_flog10_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fmad_s16_flush
 machineFunctionInfo:
   mode:
     fp64-fp16-input-denormals: false
     fp64-fp16-output-denormals: false
 

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fmad_s32_flush
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
     fp32-output-denormals: false
 

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=VI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fminnum_s32_ieee_mode_on
 machineFunctionInfo:
   mode:
     ieee: true
 body: |
   bb.0:

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=VI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fminnum_s32_ieee_mode_on
 machineFunctionInfo:
   mode:
     ieee: true
 body: |
   bb.0:

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_fpow_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_fpow_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=SI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=VI %s
 
 ---
 name: test_fptosi_s32_to_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; SI-LABEL: name: test_fptosi_s32_to_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=SI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=VI %s
 
 ---
 name: test_fptoui_s32_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; SI-LABEL: name: test_fptoui_s32_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -global-isel %s -o - | FileCheck %s
 
 ---
 name: test_fptrunc_s64_to_s32
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_fptrunc_s64_to_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s  | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=VI %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s  | FileCheck -check-prefix=GFX9  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s  | FileCheck -check-prefix=GFX9  %s
 
 ---
 name: test_fsin_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; SI-LABEL: name: test_fsin_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: insert_vector_elt_0_v2s32
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2
     ; CHECK-LABEL: name: insert_vector_elt_0_v2s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: test_amdgcn_fdiv_fast
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_amdgcn_fdiv_fast

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_mul_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_mul_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck %s
 
 ---
 name: test_saddo_s7
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_saddo_s7

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: shufflevector_v2s16_v2s16_undef_undef
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX8 %s
 
 ---
 name: test_sitofp_s32_to_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX6-LABEL: name: test_sitofp_s32_to_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck %s
 
 ---
 name: test_ssubo_s7
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_ssubo_s7

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_sub_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_sub_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: test_uaddo_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_uaddo_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_udiv_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_udiv_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck -check-prefix=GFX8 %s
 
 ---
 name: test_uitofp_s32_to_s32
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX6-LABEL: name: test_uitofp_s32_to_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck %s
 
 ---
 name: test_unmerge_s32_s64
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_unmerge_s32_s64
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX8 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 name: test_urem_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; GFX6-LABEL: name: test_urem_s32

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=mir-debugify,legalizer -mir-debug-loc=0 %s -o - | FileCheck %s
 
 ---
 name: test_usubo_s32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_usubo_s32