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Differential D76283

[IRBuilder] Use preferred target type for len argument of memory intrinsic functions
Needs RevisionPublic

Authored by kschwarz on Mar 17 2020, 7:02 AM.

Details

Reviewers
rjmccall
gchatelet
aemerson
arsenm
Summary

The IR builder hard-coded the type of the len argument of the memory function instrinsics to i64 for several builder functions.

During instruction selection of these intrinsics to the corresponding C library functions SelectionDAG ignores the type of the len argument and uses the targets preferred type.
GlobalISel however translates these calls using the actual types of the intrinsic, which will miscompile on 32-bit architectures.

Using the preferred type when creating the intrinsic call in the first place fixes this issue.

Diff Detail

Event Timeline

kschwarz created this revision.Mar 17 2020, 7:02 AM
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kschwarz added a subscriber: llvm-commits.Mar 17 2020, 7:25 AM
lebedev.ri added a subscriber: lebedev.ri.Mar 17 2020, 7:34 AM

So what happens if i manually create such IR, or create such IR without using IRBuilder?
It will again compile fine via SelectionDAG and will be miscompiled via GlobalISel, correct?
Don't you then want to harden -verify to barf on such mismatch, too?

Harbormaster failed remote builds in B49422: Diff 250743!Mar 17 2020, 7:58 AM
kschwarz added a comment.Mar 17 2020, 8:36 AM

Correct, it will still miscompile even with this change.
I see two options: either 1) extend GlobalISel to select to the appropriate type, or 2) declare this as illegal LLVM IR in the first place.

  1. will introduce an implicit truncation of the i64 argument (same as SelectionDAG does today). In practice this seems to work, but it feels broken
  2. I'm not sure whether it should be illegal to create an i64 version of the llvm.mem* intrinsics on 32-bit architectures.

Thoughts?

gargaroff added a subscriber: gargaroff.Mar 17 2020, 8:42 AM
lebedev.ri added a comment.Mar 17 2020, 10:03 AM

llvm-dev might be a better place for that question, wider coverage.

rjmccall added a comment.Mar 17 2020, 10:15 AM

I guess the logical rule would be that the bit-width of the size has to match the minimum of the bit-widths of the address spaces used with the intrinsic. (Note that llvm.memcpy etc. can take pointers into two different address spaces, potentially of different widths.) That might be pretty disruptive for existing code, though.

kschwarz updated this revision to Diff 269789.Jun 10 2020, 4:09 AM

Brining this up again

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kschwarz added a reviewer: arsenm.Jun 10 2020, 4:09 AM
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kschwarz added a comment.Jun 10 2020, 4:20 AM

I brought this to the mailing list (http://lists.llvm.org/pipermail/llvm-dev/2020-March/140032.html) but didn't get an answer there.

@arsenm, have you any comments regarding @rjmccall's last comment regarding the sizes of pointers in different address spaces?

gchatelet added a comment.Jun 10 2020, 4:35 AM

I would harden the verifier and declare the i64 versions of mem intrinsics illegal on 32 bits architectures.
Also the intrinsic sections of LangRef should be updated accordingly.

Harbormaster failed remote builds in B59771: Diff 269789!Jun 10 2020, 5:25 AM
arsenm added a comment.Jun 10 2020, 5:48 AM
In D76283#2084627, @kschwarz wrote:

I brought this to the mailing list (http://lists.llvm.org/pipermail/llvm-dev/2020-March/140032.html) but didn't get an answer there.

@arsenm, have you any comments regarding @rjmccall's last comment regarding the sizes of pointers in different address spaces?

I've always use the minimum of the two sizes, so I agree

gargaroff mentioned this in D85199: GlobalISel: Add generic instructions for memory intrinsics.Aug 4 2020, 6:01 AM
arsenm requested changes to this revision.Aug 17 2023, 3:56 PM

I think any size type should be valid for the intrinsic. Legalization should have to cast the type to the target libcall if that's how it chooses to implement the lowering

This revision now requires changes to proceed.Aug 17 2023, 3:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 17 2023, 3:56 PM
arsenm added inline comments.Aug 17 2023, 3:56 PM
llvm/include/llvm/IR/IRBuilder.h
427–435

This change on its own might be ok but in the context of what you are trying to solve it is not

Revision Contents

PathSize
clang/
test/
CodeGen/
10 lines
10 lines
28 lines
CodeGenCXX/
2 lines
2 lines
llvm/
include/
llvm/
IR/
24 lines
test/
Transforms/
MemCpyOpt/
26 lines

Diff 250743

clang/test/CodeGen/c11atomics-ios.c

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
// CHECK-NEXT: [[X:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: [[X:%.*]] = alloca [[APS]], align 8
// CHECK-NEXT: [[F:%.*]] = alloca [[PS:%.*]], align 2 // CHECK-NEXT: [[F:%.*]] = alloca [[PS:%.*]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = alloca [[APS]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8
// CHECK-NEXT: store [[APS]]* // CHECK-NEXT: store [[APS]]*
// CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]]
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8* // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8*
// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[T0]], i8 0, i64 8, i1 false) // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false)
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0 // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8 // CHECK-NEXT: store i16 1, i16* [[T1]], align 8
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2
// CHECK-NEXT: store i16 3, i16* [[T1]], align 4 // CHECK-NEXT: store i16 3, i16* [[T1]], align 4
__c11_atomic_init(fp, (PS){1,2,3}); __c11_atomic_init(fp, (PS){1,2,3});
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  __c11_atomic_init(fp, (PS){1,2,3});
+__c11_atomic_init(fp, (PS){1, 2, 3});
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __c11_atomic_init(fp, (PS){1,2,3})…
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8* // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8*
// CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false) // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false)
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0 // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8 // CHECK-NEXT: store i16 1, i16* [[T1]], align 8
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesvoid test_promoted_store(_Atomic(PS) *addr, PS *val) {
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4 // CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8* // CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8* // CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64* // CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8 // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8
// CHECK: store atomic i64 [[VAL64]], i64* [[ADDR64]] seq_cst, align 8 // CHECK: store atomic i64 [[VAL64]], i64* [[ADDR64]] seq_cst, align 8
__c11_atomic_store(addr, *val, 5); __c11_atomic_store(addr, *val, 5);
} }
PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) {
// CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val)
// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
// CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4
// CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2
// CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
// CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4 // CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4 // CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8* // CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8* // CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64* // CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
// CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64* // CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64*
// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8 // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8
// CHECK: [[RES:%.*]] = atomicrmw xchg i64* [[ADDR64]], i64 [[VAL64]] seq_cst // CHECK: [[RES:%.*]] = atomicrmw xchg i64* [[ADDR64]], i64 [[VAL64]] seq_cst
// CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8 // CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8
// CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS* // CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS*
// CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8* // CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8*
// CHECK: [[ATOMIC_RES8:%.*]] = bitcast %struct.PS* [[ATOMIC_RES_STRUCT]] to i8* // CHECK: [[ATOMIC_RES8:%.*]] = bitcast %struct.PS* [[ATOMIC_RES_STRUCT]] to i8*
Show All 17 Lines_Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) {
// CHECK: [[DESIRED:%.*]] = load %struct.PS*, %struct.PS** [[DESIRED_ARG]], align 4 // CHECK: [[DESIRED:%.*]] = load %struct.PS*, %struct.PS** [[DESIRED_ARG]], align 4
// CHECK: [[NEW:%.*]] = load %struct.PS*, %struct.PS** [[NEW_ARG]], align 4 // CHECK: [[NEW:%.*]] = load %struct.PS*, %struct.PS** [[NEW_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[NEW8:%.*]] = bitcast %struct.PS* [[NEW]] to i8* // CHECK: [[NEW8:%.*]] = bitcast %struct.PS* [[NEW]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[NEW8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[NEW8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i8* // CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i8*
// CHECK: [[DESIRED8:%.*]] = bitcast %struct.PS* [[DESIRED]] to i8* // CHECK: [[DESIRED8:%.*]] = bitcast %struct.PS* [[DESIRED]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_DESIRED8]], i8* align 2 [[DESIRED8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_DESIRED8]], i8* align 2 [[DESIRED8]], i32 6, i1 false)
// CHECK: [[ATOMIC_DESIRED64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i64* // CHECK: [[ATOMIC_DESIRED64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i64*
// CHECK: [[ATOMIC_NEW8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i8* // CHECK: [[ATOMIC_NEW8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_NEW8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_NEW8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_NEW64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i64* // CHECK: [[ATOMIC_NEW64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i64*
// CHECK: [[ATOMIC_DESIRED_VAL64:%.*]] = load i64, i64* [[ATOMIC_DESIRED64]], align 8 // CHECK: [[ATOMIC_DESIRED_VAL64:%.*]] = load i64, i64* [[ATOMIC_DESIRED64]], align 8
// CHECK: [[ATOMIC_NEW_VAL64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 8 // CHECK: [[ATOMIC_NEW_VAL64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 8
// CHECK: [[RES:%.*]] = cmpxchg i64* [[ADDR64]], i64 [[ATOMIC_DESIRED_VAL64]], i64 [[ATOMIC_NEW_VAL64]] seq_cst seq_cst // CHECK: [[RES:%.*]] = cmpxchg i64* [[ADDR64]], i64 [[ATOMIC_DESIRED_VAL64]], i64 [[ATOMIC_NEW_VAL64]] seq_cst seq_cst
// CHECK: [[RES_VAL64:%.*]] = extractvalue { i64, i1 } [[RES]], 0 // CHECK: [[RES_VAL64:%.*]] = extractvalue { i64, i1 } [[RES]], 0
// CHECK: [[RES_BOOL:%.*]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: [[RES_BOOL:%.*]] = extractvalue { i64, i1 } [[RES]], 1
// CHECK: br i1 [[RES_BOOL]], label {{%.*}}, label {{%.*}} // CHECK: br i1 [[RES_BOOL]], label {{%.*}}, label {{%.*}}
Show All 27 Lines

clang/test/CodeGen/c11atomics.c

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines
// CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8
// CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[TMP2:%.*]] = alloca %struct.PS, align 2 // CHECK-NEXT: [[TMP2:%.*]] = alloca %struct.PS, align 2
// CHECK-NEXT: [[TMP3:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = alloca [[APS]], align 8
// CHECK-NEXT: store [[APS]]* // CHECK-NEXT: store [[APS]]*
// CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]]
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8* // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8*
// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[T0]], i8 0, i64 8, i1 false) // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false)
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0 // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8 // CHECK-NEXT: store i16 1, i16* [[T1]], align 8
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2
// CHECK-NEXT: store i16 3, i16* [[T1]], align 4 // CHECK-NEXT: store i16 3, i16* [[T1]], align 4
__c11_atomic_init(fp, (PS){1,2,3}); __c11_atomic_init(fp, (PS){1,2,3});
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  __c11_atomic_init(fp, (PS){1,2,3});
+__c11_atomic_init(fp, (PS){1, 2, 3});
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __c11_atomic_init(fp, (PS){1,2,3})…
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8* // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8*
// CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false) // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 8 [[T0]], i8 0, i32 8, i1 false)
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0 // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8 // CHECK-NEXT: store i16 1, i16* [[T1]], align 8
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesvoid test_promoted_store(_Atomic(PS) *addr, PS *val) {
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4 // CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8* // CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8* // CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64* // CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
// CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2 // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2
// CHECK: call arm_aapcscc void @__atomic_store_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5) // CHECK: call arm_aapcscc void @__atomic_store_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5)
__c11_atomic_store(addr, *val, 5); __c11_atomic_store(addr, *val, 5);
} }
PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) {
// CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val)
// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
// CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4
// CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2
// CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
// CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4 // CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 // CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4 // CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8* // CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[VAL8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8* // CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_VAL8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64* // CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
// CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64* // CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64*
// CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2 // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2
// CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_exchange_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5) // CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_exchange_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5)
// CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8 // CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8
// CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS* // CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS*
// CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8* // CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8*
Show All 17 Lines_Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) {
// CHECK: [[DESIRED:%.*]]= load %struct.PS*, %struct.PS** [[DESIRED_ARG]], align 4 // CHECK: [[DESIRED:%.*]]= load %struct.PS*, %struct.PS** [[DESIRED_ARG]], align 4
// CHECK: [[NEW:%.*]] = load %struct.PS*, %struct.PS** [[NEW_ARG]], align 4 // CHECK: [[NEW:%.*]] = load %struct.PS*, %struct.PS** [[NEW_ARG]], align 4
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: [[NEW8:%.*]] = bitcast %struct.PS* [[NEW]] to i8* // CHECK: [[NEW8:%.*]] = bitcast %struct.PS* [[NEW]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[NEW8]], i32 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[NONATOMIC_TMP8]], i8* align 2 [[NEW8]], i32 6, i1 false)
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
// CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED]] to i8* // CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED]] to i8*
// CHECK: [[DESIRED8:%.*]] = bitcast %struct.PS* [[DESIRED]]to i8* // CHECK: [[DESIRED8:%.*]] = bitcast %struct.PS* [[DESIRED]]to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_DESIRED8]], i8* align 2 [[DESIRED8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_DESIRED8]], i8* align 2 [[DESIRED8]], i32 6, i1 false)
// CHECK: [[ATOMIC_DESIRED64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED]] to i64* // CHECK: [[ATOMIC_DESIRED64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED]] to i64*
// CHECK: [[ATOMIC_NEW8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i8* // CHECK: [[ATOMIC_NEW8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i8*
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8* // CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[ATOMIC_NEW8]], i8* align 2 [[NONATOMIC_TMP8]], i64 6, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[ATOMIC_NEW8]], i8* align 2 [[NONATOMIC_TMP8]], i32 6, i1 false)
// CHECK: [[ATOMIC_NEW64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i64* // CHECK: [[ATOMIC_NEW64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i64*
// CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
// CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast i64* [[ATOMIC_DESIRED64]] to i8* // CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast i64* [[ATOMIC_DESIRED64]] to i8*
// CHECK: [[NEW64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 2 // CHECK: [[NEW64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 2
// CHECK: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_compare_exchange_8(i8* [[ADDR8]], i8* [[ATOMIC_DESIRED8]], i64 [[NEW64]], i32 5, i32 5) // CHECK: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_compare_exchange_8(i8* [[ADDR8]], i8* [[ATOMIC_DESIRED8]], i64 [[NEW64]], i32 5, i32 5)
// CHECK: ret i1 [[RES]] // CHECK: ret i1 [[RES]]
return __c11_atomic_compare_exchange_strong(addr, desired, *new, 5, 5); return __c11_atomic_compare_exchange_strong(addr, desired, *new, 5, 5);
} }
Show All 14 Lines

clang/test/CodeGen/x86-atomic-long_double.c

Show All 40 Lineslong double testinc(_Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[INC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]], // CHECK32: [[INC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lineslong double testdec(_Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[DEC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]], // CHECK32: [[DEC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lineslong double testcompassign(_Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[INC_VALUE:%.+]] = fsub x86_fp80 [[OLD_VALUE]], // CHECK32: [[INC_VALUE:%.+]] = fsub x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
Show All 16 Lineslong double testassign(_Atomic long double *addr) {
// CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128* // CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128*
// CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16 // CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
// CHECK: store atomic i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: store atomic i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16
// CHECK32-LABEL: @testassign // CHECK32-LABEL: @testassign
// CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[STORE_TEMP_VOID_PTR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[STORE_TEMP_VOID_PTR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4
// CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8*
// CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5)
*addr = 115; *addr = 115;
// CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
// CHECK: [[INT_VAL:%.+]] = load atomic i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_VAL:%.+]] = load atomic i128, i128* [[ADDR_INT]] seq_cst, align 16
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lineslong double test_volatile_inc(volatile _Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[INC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]], // CHECK32: [[INC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lineslong double test_volatile_dec(volatile _Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[DEC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]], // CHECK32: [[DEC_VALUE:%.+]] = fadd x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lineslong double test_volatile_compassign(volatile _Atomic long double *addr) {
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]] // CHECK32: [[ATOMIC_OP]]
// CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ]
// CHECK32: [[INC_VALUE:%.+]] = fsub x86_fp80 [[OLD_VALUE]], // CHECK32: [[INC_VALUE:%.+]] = fsub x86_fp80 [[OLD_VALUE]],
// CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8* // CHECK32: [[OLD_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[OLD_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8* // CHECK32: [[DESIRED_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[DESIRED_VALUE_VOID_ADDR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4 // CHECK32: store x86_fp80 [[INC_VALUE]], x86_fp80* [[DESIRED_VALUE_ADDR]], align 4
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ATOMIC_CONT]]
Show All 16 Lineslong double test_volatile_assign(volatile _Atomic long double *addr) {
// CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128* // CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128*
// CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16 // CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
// CHECK: store atomic volatile i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: store atomic volatile i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16
// CHECK32-LABEL: @test_volatile_assign // CHECK32-LABEL: @test_volatile_assign
// CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8*
// CHECK32: call void @llvm.memset.p0i8.i64(i8* align 4 [[STORE_TEMP_VOID_PTR]], i8 0, i64 12, i1 false) // CHECK32: call void @llvm.memset.p0i8.i32(i8* align 4 [[STORE_TEMP_VOID_PTR]], i8 0, i32 12, i1 false)
// CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4
// CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8*
// CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5)
*addr = 115; *addr = 115;
// CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
// CHECK: [[INT_VAL:%.+]] = load atomic volatile i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_VAL:%.+]] = load atomic volatile i128, i128* [[ADDR_INT]] seq_cst, align 16
Show All 13 Lines

clang/test/CodeGenCXX/pod-member-memcpys.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
// CHECK-LABEL: define linkonce_odr void @_ZN13PackedMembersC2ERKS_(%struct.PackedMembers* %this, %struct.PackedMembers* dereferenceable({{[0-9]+}}) %0) // CHECK-LABEL: define linkonce_odr void @_ZN13PackedMembersC2ERKS_(%struct.PackedMembers* %this, %struct.PackedMembers* dereferenceable({{[0-9]+}}) %0)
// CHECK: call void @_ZN6NonPODC1ERKS_ // CHECK: call void @_ZN6NonPODC1ERKS_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64({{.*}} align 1 {{.*}} align 1 {{.*}}i64 16, i1 {{.*}}) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64({{.*}} align 1 {{.*}} align 1 {{.*}}i64 16, i1 {{.*}})
// CHECK: ret void // CHECK: ret void
CALL_CC(BitfieldMember2) CALL_CC(BitfieldMember2)
// BitfieldMember2 copy-constructor: // BitfieldMember2 copy-constructor:
// CHECK-2-LABEL: define linkonce_odr void @_ZN15BitfieldMember2C2ERKS_(%struct.BitfieldMember2* %this, %struct.BitfieldMember2* dereferenceable({{[0-9]+}}) %0) // CHECK-2-LABEL: define linkonce_odr void @_ZN15BitfieldMember2C2ERKS_(%struct.BitfieldMember2* %this, %struct.BitfieldMember2* dereferenceable({{[0-9]+}}) %0)
// CHECK-2: call void @llvm.memcpy.p0i8.p0i8.i64({{.*}} align 4 {{.*}} align 4 {{.*}}i64 16, i1 false) // CHECK-2: call void @llvm.memcpy.p0i8.p0i8.i32({{.*}} align 4 {{.*}} align 4 {{.*}}i32 16, i1 false)
// CHECK-2: call void @_ZN6NonPODC1ERKS_ // CHECK-2: call void @_ZN6NonPODC1ERKS_
// CHECK-2: ret void // CHECK-2: ret void
CALL_CC(BitfieldMember3) CALL_CC(BitfieldMember3)
// BitfieldMember3 copy-constructor: // BitfieldMember3 copy-constructor:
// CHECK-LABEL: define linkonce_odr void @_ZN15BitfieldMember3C2ERKS_(%struct.BitfieldMember3* %this, %struct.BitfieldMember3* dereferenceable({{[0-9]+}}) %0) // CHECK-LABEL: define linkonce_odr void @_ZN15BitfieldMember3C2ERKS_(%struct.BitfieldMember3* %this, %struct.BitfieldMember3* dereferenceable({{[0-9]+}}) %0)
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64({{.*}} align 8 {{.*}} align 8 {{.*}}i64 8, i1 false) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64({{.*}} align 8 {{.*}} align 8 {{.*}}i64 8, i1 false)
// CHECK: ret void // CHECK: ret void
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

clang/test/CodeGenCXX/pr20897.cpp

// RUN: %clang_cc1 -triple i686-windows-msvc -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s | FileCheck %s // RUN: %clang_cc1 -triple i686-windows-msvc -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s | FileCheck %s
struct Base {}; struct Base {};
// __declspec(dllexport) causes us to export the implicit constructor. // __declspec(dllexport) causes us to export the implicit constructor.
struct __declspec(dllexport) Derived : virtual Base { struct __declspec(dllexport) Derived : virtual Base {
// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived* @"??0Derived@@QAE@ABU0@@Z" // CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived* @"??0Derived@@QAE@ABU0@@Z"
Lint: Pre-merge checks
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clang-format: please reformat the code

-// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived* @"??0Derived@@QAE@ABU0@@Z"
-// CHECK:      %[[this:.*]] = load %struct.Derived*, %struct.Derived** {{.*}}
-// CHECK-NEXT: store %struct.Derived* %[[this]], %struct.Derived** %[[retval:.*]]
-// CHECK:      %[[dest_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[this]], i32 0, i32 1
-// CHECK-NEXT: %[[src_load:.*]]   = load %struct.Derived*, %struct.Derived** {{.*}}
-// CHECK-NEXT: %[[src_a_gep:.*]]  = getelementptr inbounds %struct.Derived, %struct.Derived* %[[src_load:.*]], i32 0, i32 1
-// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %[[dest_a_gep]], i8* align 4 %[[src_a_gep]], i32 1, i1 false)
-// CHECK-NEXT: %[[dest_this:.*]] = load %struct.Derived*, %struct.Derived** %[[retval]]
-// CHECK-NEXT: ret %struct.Derived* %[[dest_this]]
+  // CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived* @"??0Derived@@QAE@ABU0@@Z"

8 diff lines are omitted. See full diff.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -// CHECK-LABEL: define weak_odr dso_local dllexport…
// CHECK: %[[this:.*]] = load %struct.Derived*, %struct.Derived** {{.*}} // CHECK: %[[this:.*]] = load %struct.Derived*, %struct.Derived** {{.*}}
// CHECK-NEXT: store %struct.Derived* %[[this]], %struct.Derived** %[[retval:.*]] // CHECK-NEXT: store %struct.Derived* %[[this]], %struct.Derived** %[[retval:.*]]
// CHECK: %[[dest_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[this]], i32 0, i32 1 // CHECK: %[[dest_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[this]], i32 0, i32 1
// CHECK-NEXT: %[[src_load:.*]] = load %struct.Derived*, %struct.Derived** {{.*}} // CHECK-NEXT: %[[src_load:.*]] = load %struct.Derived*, %struct.Derived** {{.*}}
// CHECK-NEXT: %[[src_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[src_load:.*]], i32 0, i32 1 // CHECK-NEXT: %[[src_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[src_load:.*]], i32 0, i32 1
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[dest_a_gep]], i8* align 4 %[[src_a_gep]], i64 1, i1 false) // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %[[dest_a_gep]], i8* align 4 %[[src_a_gep]], i32 1, i1 false)
// CHECK-NEXT: %[[dest_this:.*]] = load %struct.Derived*, %struct.Derived** %[[retval]] // CHECK-NEXT: %[[dest_this:.*]] = load %struct.Derived*, %struct.Derived** %[[retval]]
// CHECK-NEXT: ret %struct.Derived* %[[dest_this]] // CHECK-NEXT: ret %struct.Derived* %[[dest_this]]
bool a : 1; bool a : 1;
bool b : 1; bool b : 1;
}; };
// __declspec(dllexport) causes us to export the implicit copy constructor. // __declspec(dllexport) causes us to export the implicit copy constructor.
struct __declspec(dllexport) Derived2 : virtual Base { struct __declspec(dllexport) Derived2 : virtual Base {
Show All 13 Lines

llvm/include/llvm/IR/IRBuilder.h

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines ConstantInt *getIntN(unsigned N, uint64_t C) {
return ConstantInt::get(getIntNTy(N), C); return ConstantInt::get(getIntNTy(N), C);
} }
/// Get a constant integer value. /// Get a constant integer value.
ConstantInt *getInt(const APInt &AI) { ConstantInt *getInt(const APInt &AI) {
return ConstantInt::get(Context, AI); return ConstantInt::get(Context, AI);
} }
ConstantInt *getIntPtrSize(Value *Ptr, uint64_t Size) {
assert(BB && "Must have a basic block to retrieve the module!");
Module *M = BB->getParent()->getParent();
auto *PtrType = Ptr->getType();
unsigned PtrSize = M->getDataLayout().getPointerSizeInBits(
PtrType->getPointerAddressSpace());
return getIntN(PtrSize, Size);
}
arsenmUnsubmitted
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This change on its own might be ok but in the context of what you are trying to solve it is not

arsenm: This change on its own might be ok but in the context of what you are trying to solve it is not
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Type creation methods // Type creation methods
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// Fetch the type representing a single bit /// Fetch the type representing a single bit
IntegerType *getInt1Ty() { IntegerType *getInt1Ty() {
return Type::getInt1Ty(Context); return Type::getInt1Ty(Context);
} }
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linespublic:
/// ///
/// If the pointer isn't an i8*, it will be converted. If a TBAA tag is /// If the pointer isn't an i8*, it will be converted. If a TBAA tag is
/// specified, it will be added to the instruction. Likewise with alias.scope /// specified, it will be added to the instruction. Likewise with alias.scope
/// and noalias tags. /// and noalias tags.
CallInst *CreateMemSet(Value *Ptr, Value *Val, uint64_t Size, CallInst *CreateMemSet(Value *Ptr, Value *Val, uint64_t Size,
MaybeAlign Align, bool isVolatile = false, MaybeAlign Align, bool isVolatile = false,
MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr, MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr) { MDNode *NoAliasTag = nullptr) {
return CreateMemSet(Ptr, Val, getInt64(Size), Align, isVolatile, return CreateMemSet(Ptr, Val, getIntPtrSize(Ptr, Size), Align, isVolatile,
TBAATag, ScopeTag, NoAliasTag); TBAATag, ScopeTag, NoAliasTag);
} }
CallInst *CreateMemSet(Value *Ptr, Value *Val, Value *Size, MaybeAlign Align, CallInst *CreateMemSet(Value *Ptr, Value *Val, Value *Size, MaybeAlign Align,
bool isVolatile = false, MDNode *TBAATag = nullptr, bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr, MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr); MDNode *NoAliasTag = nullptr);
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines LLVM_ATTRIBUTE_DEPRECATED(
CallInst *CreateMemCpy(Value *Dst, unsigned DstAlign, Value *Src, CallInst *CreateMemCpy(Value *Dst, unsigned DstAlign, Value *Src,
unsigned SrcAlign, uint64_t Size, unsigned SrcAlign, uint64_t Size,
bool isVolatile = false, MDNode *TBAATag = nullptr, bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr, MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr, MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr), MDNode *NoAliasTag = nullptr),
"Use the version that takes MaybeAlign instead") { "Use the version that takes MaybeAlign instead") {
return CreateMemCpy(Dst, MaybeAlign(DstAlign), Src, MaybeAlign(SrcAlign), return CreateMemCpy(Dst, MaybeAlign(DstAlign), Src, MaybeAlign(SrcAlign),
getInt64(Size), isVolatile, TBAATag, TBAAStructTag, getIntPtrSize(Dst, Size), isVolatile, TBAATag,
ScopeTag, NoAliasTag); TBAAStructTag, ScopeTag, NoAliasTag);
} }
CallInst *CreateMemCpy(Value *Dst, MaybeAlign DstAlign, Value *Src, CallInst *CreateMemCpy(Value *Dst, MaybeAlign DstAlign, Value *Src,
MaybeAlign SrcAlign, uint64_t Size, MaybeAlign SrcAlign, uint64_t Size,
bool isVolatile = false, MDNode *TBAATag = nullptr, bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr, MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr, MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr) { MDNode *NoAliasTag = nullptr) {
return CreateMemCpy(Dst, DstAlign, Src, SrcAlign, getInt64(Size), return CreateMemCpy(Dst, DstAlign, Src, SrcAlign, getIntPtrSize(Dst, Size),
isVolatile, TBAATag, TBAAStructTag, ScopeTag, isVolatile, TBAATag, TBAAStructTag, ScopeTag,
NoAliasTag); NoAliasTag);
} }
/// FIXME: Remove this function once transition to Align is over. /// FIXME: Remove this function once transition to Align is over.
/// Use the version that takes MaybeAlign instead of this one. /// Use the version that takes MaybeAlign instead of this one.
LLVM_ATTRIBUTE_DEPRECATED( LLVM_ATTRIBUTE_DEPRECATED(
CallInst *CreateMemCpy(Value *Dst, unsigned DstAlign, Value *Src, CallInst *CreateMemCpy(Value *Dst, unsigned DstAlign, Value *Src,
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linespublic:
/// Use the version that takes MaybeAlign instead of this one. /// Use the version that takes MaybeAlign instead of this one.
LLVM_ATTRIBUTE_DEPRECATED( LLVM_ATTRIBUTE_DEPRECATED(
CallInst *CreateMemMove( CallInst *CreateMemMove(
Value *Dst, unsigned DstAlign, Value *Src, unsigned SrcAlign, Value *Dst, unsigned DstAlign, Value *Src, unsigned SrcAlign,
uint64_t Size, bool isVolatile = false, MDNode *TBAATag = nullptr, uint64_t Size, bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr), MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr),
"Use the version that takes MaybeAlign") { "Use the version that takes MaybeAlign") {
return CreateMemMove(Dst, MaybeAlign(DstAlign), Src, MaybeAlign(SrcAlign), return CreateMemMove(Dst, MaybeAlign(DstAlign), Src, MaybeAlign(SrcAlign),
getInt64(Size), isVolatile, TBAATag, ScopeTag, getIntPtrSize(Dst, Size), isVolatile, TBAATag,
NoAliasTag); ScopeTag, NoAliasTag);
} }
CallInst *CreateMemMove(Value *Dst, MaybeAlign DstAlign, Value *Src, CallInst *CreateMemMove(Value *Dst, MaybeAlign DstAlign, Value *Src,
MaybeAlign SrcAlign, uint64_t Size, MaybeAlign SrcAlign, uint64_t Size,
bool isVolatile = false, MDNode *TBAATag = nullptr, bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr, MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr) { MDNode *NoAliasTag = nullptr) {
return CreateMemMove(Dst, DstAlign, Src, SrcAlign, getInt64(Size), return CreateMemMove(Dst, DstAlign, Src, SrcAlign, getIntPtrSize(Dst, Size),
isVolatile, TBAATag, ScopeTag, NoAliasTag); isVolatile, TBAATag, ScopeTag, NoAliasTag);
} }
/// FIXME: Remove this function once transition to Align is over. /// FIXME: Remove this function once transition to Align is over.
/// Use the version that takes MaybeAlign instead of this one. /// Use the version that takes MaybeAlign instead of this one.
LLVM_ATTRIBUTE_DEPRECATED( LLVM_ATTRIBUTE_DEPRECATED(
CallInst *CreateMemMove( CallInst *CreateMemMove(
Value *Dst, unsigned DstAlign, Value *Src, unsigned SrcAlign, Value *Dst, unsigned DstAlign, Value *Src, unsigned SrcAlign,
Value *Size, bool isVolatile = false, MDNode *TBAATag = nullptr, Value *Size, bool isVolatile = false, MDNode *TBAATag = nullptr,
▲ Show 20 Lines • Show All 2,341 Lines • Show Last 20 Lines

llvm/test/Transforms/MemCpyOpt/form-memset.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesentry:
%tmp69 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 17 ; <i8*> [#uses=1] %tmp69 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 17 ; <i8*> [#uses=1]
store i8 %c, i8* %tmp69, align 1 store i8 %c, i8* %tmp69, align 1
%tmp73 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 18 ; <i8*> [#uses=1] %tmp73 = getelementptr [19 x i8], [19 x i8]* %x, i32 0, i32 18 ; <i8*> [#uses=1]
store i8 %c, i8* %tmp73, align 1 store i8 %c, i8* %tmp73, align 1
%tmp76 = call i32 (...) @bar( [19 x i8]* %x ) nounwind %tmp76 = call i32 (...) @bar( [19 x i8]* %x ) nounwind
ret void ret void
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64 ; CHECK: call void @llvm.memset.p0i8.i32
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: ret ; CHECK: ret
} }
declare i32 @bar(...) declare i32 @bar(...)
%struct.MV = type { i16, i16 } %struct.MV = type { i16, i16 }
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
store i16 0, i16* %tmp249, align 2 store i16 0, i16* %tmp249, align 2
%up_mvd252 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 0 ; <%struct.MV*> [#uses=1] %up_mvd252 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %up_mvd, i32 0, i32 0 ; <%struct.MV*> [#uses=1]
%left_mvd253 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 0 ; <%struct.MV*> [#uses=1] %left_mvd253 = getelementptr [8 x %struct.MV], [8 x %struct.MV]* %left_mvd, i32 0, i32 0 ; <%struct.MV*> [#uses=1]
call void @foo( %struct.MV* %up_mvd252, %struct.MV* %left_mvd253, i8* %tmp41 ) nounwind call void @foo( %struct.MV* %up_mvd252, %struct.MV* %left_mvd253, i8* %tmp41 ) nounwind
ret void ret void
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %tmp41, i8 -1, i64 8, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 1 %tmp41, i8 -1, i32 8, i1 false)
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 32, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 8 %0, i8 0, i32 32, i1 false)
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %1, i8 0, i64 32, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 8 %1, i8 0, i32 32, i1 false)
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: ret ; CHECK: ret
} }
declare void @foo(%struct.MV*, %struct.MV*, i8*) declare void @foo(%struct.MV*, %struct.MV*, i8*)
; Store followed by memset. ; Store followed by memset.
define void @test3(i32* nocapture %P) nounwind ssp { define void @test3(i32* nocapture %P) nounwind ssp {
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %P, i64 1 %arrayidx = getelementptr inbounds i32, i32* %P, i64 1
store i32 0, i32* %arrayidx, align 4 store i32 0, i32* %arrayidx, align 4
%add.ptr = getelementptr inbounds i32, i32* %P, i64 2 %add.ptr = getelementptr inbounds i32, i32* %P, i64 2
%0 = bitcast i32* %add.ptr to i8* %0 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false)
ret void ret void
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 15, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %1, i8 0, i32 15, i1 false)
} }
; store followed by memset, different offset scenario ; store followed by memset, different offset scenario
define void @test4(i32* nocapture %P) nounwind ssp { define void @test4(i32* nocapture %P) nounwind ssp {
entry: entry:
store i32 0, i32* %P, align 4 store i32 0, i32* %P, align 4
%add.ptr = getelementptr inbounds i32, i32* %P, i64 1 %add.ptr = getelementptr inbounds i32, i32* %P, i64 1
%0 = bitcast i32* %add.ptr to i8* %0 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false)
ret void ret void
; CHECK-LABEL: @test4( ; CHECK-LABEL: @test4(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 15, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %1, i8 0, i32 15, i1 false)
} }
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
; Memset followed by store. ; Memset followed by store.
define void @test5(i32* nocapture %P) nounwind ssp { define void @test5(i32* nocapture %P) nounwind ssp {
entry: entry:
%add.ptr = getelementptr inbounds i32, i32* %P, i64 2 %add.ptr = getelementptr inbounds i32, i32* %P, i64 2
%0 = bitcast i32* %add.ptr to i8* %0 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false)
%arrayidx = getelementptr inbounds i32, i32* %P, i64 1 %arrayidx = getelementptr inbounds i32, i32* %P, i64 1
store i32 0, i32* %arrayidx, align 4 store i32 0, i32* %arrayidx, align 4
ret void ret void
; CHECK-LABEL: @test5( ; CHECK-LABEL: @test5(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 15, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %1, i8 0, i32 15, i1 false)
} }
;; Memset followed by memset. ;; Memset followed by memset.
define void @test6(i32* nocapture %P) nounwind ssp { define void @test6(i32* nocapture %P) nounwind ssp {
entry: entry:
%0 = bitcast i32* %P to i8* %0 = bitcast i32* %P to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 12, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 12, i1 false)
%add.ptr = getelementptr inbounds i32, i32* %P, i64 3 %add.ptr = getelementptr inbounds i32, i32* %P, i64 3
%1 = bitcast i32* %add.ptr to i8* %1 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 12, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 12, i1 false)
ret void ret void
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* %2, i8 0, i32 24, i1 false)
} }
; More aggressive heuristic ; More aggressive heuristic
; rdar://9892684 ; rdar://9892684
define void @test7(i32* nocapture %c) nounwind optsize { define void @test7(i32* nocapture %c) nounwind optsize {
store i32 -1, i32* %c, align 4 store i32 -1, i32* %c, align 4
%1 = getelementptr inbounds i32, i32* %c, i32 1 %1 = getelementptr inbounds i32, i32* %c, i32 1
store i32 -1, i32* %1, align 4 store i32 -1, i32* %1, align 4
%2 = getelementptr inbounds i32, i32* %c, i32 2 %2 = getelementptr inbounds i32, i32* %c, i32 2
store i32 -1, i32* %2, align 4 store i32 -1, i32* %2, align 4
%3 = getelementptr inbounds i32, i32* %c, i32 3 %3 = getelementptr inbounds i32, i32* %c, i32 3
store i32 -1, i32* %3, align 4 store i32 -1, i32* %3, align 4
%4 = getelementptr inbounds i32, i32* %c, i32 4 %4 = getelementptr inbounds i32, i32* %c, i32 4
store i32 -1, i32* %4, align 4 store i32 -1, i32* %4, align 4
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %5, i8 -1, i64 20, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %5, i8 -1, i32 20, i1 false)
ret void ret void
} }
%struct.test8 = type { [4 x i32] } %struct.test8 = type { [4 x i32] }
define void @test8() { define void @test8() {
entry: entry:
%memtmp = alloca %struct.test8, align 16 %memtmp = alloca %struct.test8, align 16
Show All 20 Linesdefine void @test9() nounwind {
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 10), align 2 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 10), align 2
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 11), align 1 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 11), align 1
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 12), align 4 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 12), align 4
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 13), align 1 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 13), align 1
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 14), align 2 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 14), align 2
store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 15), align 1 store i8 -1, i8* getelementptr (i8, i8* bitcast ([16 x i64]* @test9buf to i8*), i64 15), align 1
ret void ret void
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 16 bitcast ([16 x i64]* @test9buf to i8*), i8 -1, i64 16, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 16 bitcast ([16 x i64]* @test9buf to i8*), i8 -1, i32 16, i1 false)
} }
; PR19092 ; PR19092
define void @test10(i8* nocapture %P) nounwind { define void @test10(i8* nocapture %P) nounwind {
tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 42, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 42, i1 false)
tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 23, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 23, i1 false)
ret void ret void
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NOT: memset ; CHECK-NOT: memset
; CHECK: call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 42, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* %P, i8 0, i32 42, i1 false)
; CHECK-NOT: memset ; CHECK-NOT: memset
; CHECK: ret void ; CHECK: ret void
} }
; Memset followed by odd store. ; Memset followed by odd store.
define void @test11(i32* nocapture %P) nounwind ssp { define void @test11(i32* nocapture %P) nounwind ssp {
entry: entry:
%add.ptr = getelementptr inbounds i32, i32* %P, i64 3 %add.ptr = getelementptr inbounds i32, i32* %P, i64 3
%0 = bitcast i32* %add.ptr to i8* %0 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 1, i64 11, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 1, i64 11, i1 false)
%arrayidx = getelementptr inbounds i32, i32* %P, i64 0 %arrayidx = getelementptr inbounds i32, i32* %P, i64 0
%arrayidx.cast = bitcast i32* %arrayidx to i96* %arrayidx.cast = bitcast i32* %arrayidx to i96*
store i96 310698676526526814092329217, i96* %arrayidx.cast, align 4 store i96 310698676526526814092329217, i96* %arrayidx.cast, align 4
ret void ret void
; CHECK-LABEL: @test11( ; CHECK-LABEL: @test11(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 1, i64 23, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %1, i8 1, i32 23, i1 false)
} }
; Alignment should be preserved when there is a store with default align ; Alignment should be preserved when there is a store with default align
define void @test12(i32* nocapture %P) nounwind ssp { define void @test12(i32* nocapture %P) nounwind ssp {
entry: entry:
store i32 0, i32* %P store i32 0, i32* %P
%add.ptr = getelementptr inbounds i32, i32* %P, i64 1 %add.ptr = getelementptr inbounds i32, i32* %P, i64 1
%0 = bitcast i32* %add.ptr to i8* %0 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i1 false)
ret void ret void
; CHECK-LABEL: @test12( ; CHECK-LABEL: @test12(
; CHECK-NOT: store ; CHECK-NOT: store
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 15, i1 false) ; CHECK: call void @llvm.memset.p0i8.i32(i8* align 4 %1, i8 0, i32 15, i1 false)
} }