This patch adds a virtual method getCPUCacheLineSize() to TargetInfo. Currently, I've only (partially) implemented the method in X86TargetInfo. It's extremely important that each CPU's cache line size correct (e.g., we can't just define it as 64 across the board) so, it has been a little slow getting to this point. There are still quite a few CPUs I haven't been able to find the cache line size of yet; for those, I'm returning zero so that the caller of this method can propagate an error. See the commented table above X86TargetInfo::getCPUCacheLineSize to check my sources for each CPU.
I'll work on the ARM CPUs next, but that will probably come later in a different patch.
Also, I updated the current uses of cache line sizes in the compiler to use this API when possible. The only one (that I could find) that I didn't update is in TargetTransformInfo. Updating that would require a more significant API change, which would be out of scope for this patch. It would be nice if that also used this API (to keep everything in one place), so I'll try to update that too at some point.