[DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)

[steven.zhang]

Summary

This is a positive combination as long as the NEG is NOT free, as we are reducing the number of NEG from two to one.

[merge_guards_bot]

Unit tests: pass. 61273 tests passed, 0 failed and 736 were skipped.

clang-tidy: pass.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[steven.zhang]

Format the patch.

[lebedev.ri]

Seems reasonable to me, but i'll leave review to someone more FP-familiar.

[RKSimon]

Wouldn't it be better to make use of the TargetLowering::isNegatibleForFree/getNegatedExpression mechanism?

[steven.zhang]

This is really a good suggestion. I will go with that mechanism, though it seems that, it didn't respect the TLI.isFNegFree() and UnsafeFPMath which didn't make sense. (When it is FNEG opcode, we just return 2 to indicate that it is profitable. What if some target is free for FNEG operations ...)

[steven.zhang]

Use the isNegatibleForFree/getNegatibleExpression mechanism.

[RKSimon]

LGTM - cheers

[xbolva00]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12659

It would be better if this function returns enum constant to improve readability.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12659

Yeah, thats been a pet peeve of mine as well for a long time - I'll take a look (might be after the release though)

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (UnsafeFPMath) {
 
     // (fma x, c, (fneg x)) -> (fmul x, (c-1))
     if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
       return DAG.getNode(ISD::FMUL, DL, VT, N0,
                          DAG.getNode(ISD::FADD, DL, VT, N1,
                                      DAG.getConstantFP(-1.0, DL, VT), Flags),
                          Flags);
     }
+
+    if (N2.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) {
+      // (fma (fneg x), y, (fneg z)) -> fneg (fma x, y, z)
+      if (N0.getOpcode() == ISD::FNEG && (N2.hasOneUse() || N0.hasOneUse()))
+        return DAG.getNode(ISD::FNEG, DL, VT,
+                           DAG.getNode(ISD::FMA, DL, VT, N0.getOperand(0), N1,
+                                       N2.getOperand(0), Flags), Flags);
+
+      // (fma x, (fneg y), (fneg z)) -> fneg (fma x, y, z)
+      if (N1.getOpcode() == ISD::FNEG && (N2.hasOneUse() || N1.hasOneUse()))
+        return DAG.getNode(ISD::FNEG, DL, VT,
+                           DAG.getNode(ISD::FMA, DL, VT, N0, N1.getOperand(0),
+                                       N2.getOperand(0), Flags), Flags);
+    }
   }
 
   return SDValue();
 }
 
 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
 // reciprocal.
 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
 // Notice that this is not always beneficial. One reason is different targets
 // may have different costs for FDIV and FMUL, so sometimes the cost of two
 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
 SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
   // TODO: Limit this transform based on optsize/minsize - it always creates at

llvm/test/CodeGen/PowerPC/fma-combine.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -enable-unsafe-fp-math  < %s | FileCheck -check-prefix=CHECK-FAST %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -enable-unsafe-fp-math -mattr=-vsx < %s | FileCheck -check-prefix=CHECK-FAST-NOVSX %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define double @fma_combine1(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine1:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
-; CHECK-FAST-NEXT:    xsmsubadp 1, 0, 2
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine1:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    fmsub 1, 0, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 3, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %fneg1 = fneg double %c
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define double @fma_combine2(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine2:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
-; CHECK-FAST-NEXT:    xsmsubadp 1, 2, 0
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 2, 3
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine2:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    fmsub 1, 2, 0, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 2, 3, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 2, 0
 ; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
entry:
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define double @fma_combine_one_use(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_one_use:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
+; CHECK-FAST-NEXT:    xsnegdp 0, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NEXT:    xsnegdp 3, 1
-; CHECK-FAST-NEXT:    xsmsubadp 1, 0, 2
-; CHECK-FAST-NEXT:    stfd 3, v@toc@l(3)
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
+; CHECK-FAST-NEXT:    stfd 0, v@toc@l(3)
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_one_use:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmsub 0, 0, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 0, 3, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    fmr 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    stfd 2, v@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_one_use:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    addis 3, 2, v@toc@ha