[DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)

[steven.zhang]

Summary

This is a positive combination as long as the NEG is NOT free, as we are reducing the number of NEG from two to one.

[merge_guards_bot]

Unit tests: pass. 61273 tests passed, 0 failed and 736 were skipped.

clang-tidy: pass.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[steven.zhang]

Format the patch.

[lebedev.ri]

Seems reasonable to me, but i'll leave review to someone more FP-familiar.

[RKSimon]

Wouldn't it be better to make use of the TargetLowering::isNegatibleForFree/getNegatedExpression mechanism?

[steven.zhang]

This is really a good suggestion. I will go with that mechanism, though it seems that, it didn't respect the TLI.isFNegFree() and UnsafeFPMath which didn't make sense. (When it is FNEG opcode, we just return 2 to indicate that it is profitable. What if some target is free for FNEG operations ...)

[steven.zhang]

Use the isNegatibleForFree/getNegatibleExpression mechanism.

[RKSimon]

LGTM - cheers

[xbolva00]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12645

It would be better if this function returns enum constant to improve readability.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12645

Yeah, thats been a pet peeve of mine as well for a long time - I'll take a look (might be after the release though)

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (UnsafeFPMath) {
     if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
       return DAG.getNode(ISD::FMUL, DL, VT, N0,
                          DAG.getNode(ISD::FADD, DL, VT, N1,
                                      DAG.getConstantFP(-1.0, DL, VT), Flags),
                          Flags);
     }
   }
 
+  // fold ((fma (fneg X), Y, (fneg Z)) -> fneg (fma X, Y, Z))
+  // fold ((fma X, (fneg Y), (fneg Z)) -> fneg (fma X, Y, Z))
+  if (!TLI.isFNegFree(VT) &&
+      TLI.isNegatibleForFree(SDValue(N, 0), DAG, LegalOperations,
+                             ForCodeSize) == 2)
+    return DAG.getNode(ISD::FNEG, DL, VT,
+                       TLI.getNegatedExpression(SDValue(N, 0), DAG,
+                                                LegalOperations, ForCodeSize),
+                       Flags);
   return SDValue();
 }
 
 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
 // reciprocal.
 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
 // Notice that this is not always beneficial. One reason is different targets
 // may have different costs for FDIV and FMUL, so sometimes the cost of two

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 ; Infinite loop identified in D62963.
 define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {
 ; CHECK-LABEL: fneg_fdiv_splat:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; CHECK-NEXT:    xxspltd 0, 1, 0
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; CHECK-NEXT:    lxvd2x 1, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; CHECK-NEXT:    xvredp 2, 0
-; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; CHECK-NEXT:    xxswapd 1, 1
-; CHECK-NEXT:    xvnmsubadp 1, 0, 2
-; CHECK-NEXT:    xvmaddadp 2, 2, 1
-; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    xxswapd 1, 1
+; CHECK-NEXT:    xxlor 3, 1, 1
+; CHECK-NEXT:    xvmaddadp 3, 0, 2
+; CHECK-NEXT:    xvnmsubadp 2, 2, 3
 ; CHECK-NEXT:    xvmaddadp 1, 0, 2
 ; CHECK-NEXT:    xvmsubadp 2, 2, 1
 ; CHECK-NEXT:    xvmuldp 34, 34, 2
 ; CHECK-NEXT:    xvmuldp 35, 35, 2
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
   %div = fdiv fast <4 x double> %a1, %splat.splat
   %sub = fsub fast <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/fma-combine.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -enable-no-signed-zeros-fp-math \
 ; RUN:     -enable-unsafe-fp-math  < %s | FileCheck -check-prefix=CHECK-FAST %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -enable-no-signed-zeros-fp-math \
 ; RUN:     -enable-unsafe-fp-math -mattr=-vsx < %s | FileCheck -check-prefix=CHECK-FAST-NOVSX %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define double @fma_combine1(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine1:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
-; CHECK-FAST-NEXT:    xsmsubadp 1, 0, 2
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine1:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    fmsub 1, 0, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 3, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %fneg1 = fneg double %c
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define double @fma_combine2(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine2:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
-; CHECK-FAST-NEXT:    xsmsubadp 1, 2, 0
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 2, 3
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine2:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    fmsub 1, 2, 0, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 2, 3, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 2, 0
 ; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %fneg1 = fneg double %c
   %mul = fmul double %b, %fneg1
   %add = fsub double %mul, %a
   ret double %add
 }
 
 @v = common local_unnamed_addr global double 0.000000e+00, align 8
 @z = common local_unnamed_addr global double 0.000000e+00, align 8
 define double @fma_combine_two_uses(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_two_uses:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
+; CHECK-FAST-NEXT:    xsnegdp 0, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NEXT:    addis 4, 2, z@toc@ha
-; CHECK-FAST-NEXT:    xsnegdp 3, 1
-; CHECK-FAST-NEXT:    xsmsubadp 1, 0, 2
-; CHECK-FAST-NEXT:    stfd 0, z@toc@l(4)
-; CHECK-FAST-NEXT:    stfd 3, v@toc@l(3)
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
+; CHECK-FAST-NEXT:    xsnegdp 2, 3
+; CHECK-FAST-NEXT:    stfd 0, v@toc@l(3)
+; CHECK-FAST-NEXT:    stfd 2, z@toc@l(4)
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_two_uses:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 3, 3
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 0, 3, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    addis 4, 2, z@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmsub 0, 3, 2, 1
-; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
-; CHECK-FAST-NOVSX-NEXT:    stfd 3, z@toc@l(4)
+; CHECK-FAST-NOVSX-NEXT:    fneg 3, 3
 ; CHECK-FAST-NOVSX-NEXT:    fmr 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    stfd 2, v@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    stfd 3, z@toc@l(4)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_two_uses:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 3, 3
 ; CHECK-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-NEXT:    addis 4, 2, z@toc@ha
 ; CHECK-NEXT:    xsmuldp 0, 3, 2
entry:
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define double @fma_combine_one_use(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_one_use:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    xsnegdp 0, 3
+; CHECK-FAST-NEXT:    xsnegdp 0, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NEXT:    xsnegdp 3, 1
-; CHECK-FAST-NEXT:    xsmsubadp 1, 0, 2
-; CHECK-FAST-NEXT:    stfd 3, v@toc@l(3)
+; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
+; CHECK-FAST-NEXT:    stfd 0, v@toc@l(3)
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_one_use:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmsub 0, 0, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 0, 3, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    fmr 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    stfd 2, v@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_one_use:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    addis 3, 2, v@toc@ha

llvm/test/CodeGen/PowerPC/qpx-recipest.ll

 
 define <4 x double> @foo2_fmf(<4 x double> %a, <4 x double> %b) nounwind {
 ; CHECK-LABEL: foo2_fmf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; CHECK-NEXT:    qvfre 3, 2
 ; CHECK-NEXT:    addi 3, 3, .LCPI8_0@toc@l
 ; CHECK-NEXT:    qvlfdx 0, 0, 3
-; CHECK-NEXT:    qvfnmsub 0, 2, 3, 0
-; CHECK-NEXT:    qvfmadd 0, 3, 0, 3
+; CHECK-NEXT:    qvfmadd 0, 2, 3, 0
+; CHECK-NEXT:    qvfnmsub 0, 3, 0, 3
 ; CHECK-NEXT:    qvfmul 3, 1, 0
 ; CHECK-NEXT:    qvfnmsub 1, 2, 3, 1
 ; CHECK-NEXT:    qvfmadd 1, 0, 1, 3
 ; CHECK-NEXT:    blr
 entry:
   %r = fdiv fast <4 x double> %a, %b
   ret <4 x double> %r
 }

llvm/test/CodeGen/PowerPC/recipest.ll

; CHECK: blr
   %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
   %r = fdiv <4 x float> %a, %x
   ret <4 x float> %r
 }
 
 define double @foo2_fmf(double %a, double %b) nounwind {
 ; CHECK: @foo2_fmf
 ; CHECK-DAG: fre
-; CHECK-DAG: fnmsub
-; CHECK: fmadd
+; CHECK-DAG: fmadd
+; CHECK: fnmsub
 ; CHECK-NEXT: fmul
 ; CHECK-NEXT: fnmsub
 ; CHECK-NEXT: fmadd
 ; CHECK-NEXT: blr
   %r = fdiv fast double %a, %b
   ret double %r
 }
 

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
 
 define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
 ; CHECK-LABEL: repeated_fp_divisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    xxspltw 0, 0, 0
 ; CHECK-NEXT:    xvresp 1, 0
-; CHECK-NEXT:    xvnmsubasp 35, 0, 1
+; CHECK-NEXT:    xvmaddasp 35, 0, 1
 ; CHECK-NEXT:    xvmulsp 0, 34, 36
-; CHECK-NEXT:    xvmaddasp 1, 1, 35
+; CHECK-NEXT:    xvnmsubasp 1, 1, 35
 ; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul fast <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
   %mul = fdiv fast <4 x float> %t1, %splat
   ret <4 x float> %mul
 }