[ELF] Add IpltSection

[MaskRay]

Summary

PltSection is used by both PLT and IPLT. The PLT section may have a
header while the IPLT section does not. Split off IpltSection from
PltSection to be clearer.

Unlike other targets, PPC64 cannot use the same code sequence for PLT
and IPLT. This helps make a future PPC64 patch (D71509) more isolated.

On EM_386 and EM_X86_64, when PLT is empty while IPLT is not, currently
we are inconsistent whether the PLT header is attached to in.plt or
in.iplt . Consistently attach the HEADER to in.plt can make the -z
retpolineplt logic simpler. It also makes jmp point to an
aesthetically better place for non-retpolineplt cases.

[ruiu]

LGTM

lld/ELF/Arch/AArch64.cpp

66–67

For consistency, I'd write one line per an assignment.

lld/ELF/SyntheticSections.cpp

2516

Can you use a range-based for loop?

lld/ELF/Target.h

48

I'd add a comment saying that all but PPC64 use the same format for .plt and .iplt entries.

[MaskRay]

pltEntrySize = ipltEntrySize = 16;

=>

pltEntrySize = 16;
ipltEntrySize = 16;

[MaskRay]

Add a comment to writeIplt
Use range-based loop

[grimar]

lld/ELF/SyntheticSections.cpp

2489–2490

The comment seems to be broken, should it be
Some architectures adds additional symbols?

2511

You do not need curly bracers around a single line.

2538

Should it be target->ipltEntrySize? How about adding a helper to
remove the duplication we have in PltSection::addSymbols() and here?

[peter.smith]

Looks good to me. One minor nit about a stale comment. I'll be out of office for the next few weeks, I'll check to make sure there isn't anything critical but otherwise might be a bit slow to respond.

lld/ELF/SyntheticSections.h

664–665

This comment looks like it will no longer be true.

[MaskRay]

lld/ELF/SyntheticSections.cpp

2511

https://reviews.llvm.org/D71520 will add another line here. So the curly brace is added beforehand to minimize diff:)

2538

Thanks for catching this!

ipltEntrySize = pltEntrySize on all targets which we support Iplt before https://reviews.llvm.org/D71509

Looks like I forgot to attach a test there and caught the issue.

Regarding the duplication with PltSection::addSymbols. The former has an addition call to addPltHeaderSymbols. The functions are simply anyway, and may not be simple to deduplicate.

[MaskRay]

Address comments

[MaskRay]

On EM_386 and EM_X86_64, consistently attach PLT header to in.plt to make jmp look better.
There is no correctness issue because push; jmp are not called anyway.

[MaskRay]

Rebase. De-template IpltSection::addEntry. PltSection::addEntry has been de-templated in a separate commit.

[MaskRay]

d.value = sym.pltIndex * target->pltEntrySize;

>

d.value = sym.pltIndex * target->ipltEntrySize;

It only affects EM_PPC64 (D71509).

[grimar]

LGTM

[jrtc27]

lld/ELF/SyntheticSections.h

685

PltSection cannot can only contain entries -> PltSection can only contain entries

[MaskRay]

lld/ELF/SyntheticSections.h

685

Thanks. Fixed.

lld/ELF/Arch/AArch64.cpp

AArch64::AArch64() {
   copyRel = R_AARCH64_COPY;
   relativeRel = R_AARCH64_RELATIVE;
   iRelativeRel = R_AARCH64_IRELATIVE;
   gotRel = R_AARCH64_GLOB_DAT;
   noneRel = R_AARCH64_NONE;
   pltRel = R_AARCH64_JUMP_SLOT;
   symbolicRel = R_AARCH64_ABS64;
   tlsDescRel = R_AARCH64_TLSDESC;
   tlsGotRel = R_AARCH64_TLS_TPREL64;
-  pltEntrySize = 16;
   pltHeaderSize = 32;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
   defaultMaxPageSize = 65536;
 
   // Align to the 2 MiB page size (known as a superpage or huge page).
   // FreeBSD automatically promotes 2 MiB-aligned allocations.
   defaultImageBase = 0x200000;
 
   needsThunks = true;
 }
AArch64BtiPac::AArch64BtiPac() {
   // indirect jump to the PLT entry. This can happen when the address
   // of the PLT entry for a function is canonicalised due to the address of
   // the function in an executable being taken by a shared library.
   // FIXME: There is a potential optimization to omit the BTI if we detect
   // that the address of the PLT entry isn't taken.
   btiEntry = btiHeader && !config->shared;
   pacEntry = (config->andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_PAC);
 
-  if (btiEntry || pacEntry)
+  if (btiEntry || pacEntry) {
     pltEntrySize = 24;
+    ipltEntrySize = 24;
+  }
 }
 
 void AArch64BtiPac::writePltHeader(uint8_t *buf) const {
   const uint8_t btiData[] = { 0x5f, 0x24, 0x03, 0xd5 }; // bti c
   const uint8_t pltData[] = {
       0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
       0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
       0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]

lld/ELF/Arch/ARM.cpp

ARM::ARM() {
   gotRel = R_ARM_GLOB_DAT;
   noneRel = R_ARM_NONE;
   pltRel = R_ARM_JUMP_SLOT;
   symbolicRel = R_ARM_ABS32;
   tlsGotRel = R_ARM_TLS_TPOFF32;
   tlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
   tlsOffsetRel = R_ARM_TLS_DTPOFF32;
   gotBaseSymInGotPlt = false;
-  pltEntrySize = 16;
   pltHeaderSize = 32;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
   trapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
   needsThunks = true;
 }
 
 uint32_t ARM::calcEFlags() const {
   // The ABIFloatType is used by loaders to detect the floating point calling
   // convention.
   uint32_t abiFloatType = 0;

lld/ELF/Arch/PPC.cpp

PPC::PPC() {
   relativeRel = R_PPC_RELATIVE;
   iRelativeRel = R_PPC_IRELATIVE;
   symbolicRel = R_PPC_ADDR32;
   gotBaseSymInGotPlt = false;
   gotHeaderEntriesNum = 3;
   gotPltHeaderEntriesNum = 0;
   pltHeaderSize = 64; // size of PLTresolve in .glink
   pltEntrySize = 4;
+  ipltEntrySize = 4;
 
   needsThunks = true;
 
   tlsModuleIndexRel = R_PPC_DTPMOD32;
   tlsOffsetRel = R_PPC_DTPREL32;
   tlsGotRel = R_PPC_TPREL32;
 
   defaultMaxPageSize = 65536;

lld/ELF/Arch/PPC64.cpp

 
 PPC64::PPC64() {
   gotRel = R_PPC64_GLOB_DAT;
   noneRel = R_PPC64_NONE;
   pltRel = R_PPC64_JMP_SLOT;
   relativeRel = R_PPC64_RELATIVE;
   iRelativeRel = R_PPC64_IRELATIVE;
   symbolicRel = R_PPC64_ADDR64;
+  pltHeaderSize = 60;
   pltEntrySize = 4;
+  ipltEntrySize = 4;
   gotBaseSymInGotPlt = false;
   gotHeaderEntriesNum = 1;
   gotPltHeaderEntriesNum = 2;
-  pltHeaderSize = 60;
   needsThunks = true;
 
   tlsModuleIndexRel = R_PPC64_DTPMOD64;
   tlsOffsetRel = R_PPC64_DTPREL64;
 
   tlsGotRel = R_PPC64_TPREL64;
 
   needsMoreStackNonSplit = false;

lld/ELF/Arch/RISCV.cpp

RISCV::RISCV() {
 
   // .got[0] = _DYNAMIC
   gotBaseSymInGotPlt = false;
   gotHeaderEntriesNum = 1;
 
   // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
   gotPltHeaderEntriesNum = 2;
 
-  pltEntrySize = 16;
   pltHeaderSize = 32;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
 }
 
 static uint32_t getEFlags(InputFile *f) {
   if (config->is64)
     return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader()->e_flags;
   return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags;
 }
 

lld/ELF/Arch/X86.cpp

X86::X86() {
   noneRel = R_386_NONE;
   pltRel = R_386_JUMP_SLOT;
   iRelativeRel = R_386_IRELATIVE;
   relativeRel = R_386_RELATIVE;
   symbolicRel = R_386_32;
   tlsGotRel = R_386_TLS_TPOFF;
   tlsModuleIndexRel = R_386_TLS_DTPMOD32;
   tlsOffsetRel = R_386_TLS_DTPOFF32;
-  pltEntrySize = 16;
   pltHeaderSize = 16;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
   trapInstr = {0xcc, 0xcc, 0xcc, 0xcc}; // 0xcc = INT3
 
   // Align to the non-PAE large page size (known as a superpage or huge page).
   // FreeBSD automatically promotes large, superpage-aligned allocations.
   defaultImageBase = 0x400000;
 }
 
 int X86::getTlsGdRelaxSkip(RelType type) const {
const uint8_t inst[] = {
         0x68, 0,    0, 0, 0,    // pushl $reloc_offset
         0xe9, 0,    0, 0, 0,    // jmp .PLT0@PC
     };
     memcpy(buf, inst, sizeof(inst));
     write32le(buf + 2, gotPltEntryAddr);
   }
 
   write32le(buf + 7, relOff);
-  write32le(buf + 12, -pltHeaderSize - pltEntrySize * index - 16);
+  write32le(buf + 12, in.plt->getVA() - pltEntryAddr - 16);
 }
 
 int64_t X86::getImplicitAddend(const uint8_t *buf, RelType type) const {
   switch (type) {
   case R_386_8:
   case R_386_PC8:
     return SignExtend64<8>(*buf);
   case R_386_16:
public:
   void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
                 int32_t index) const override;
 };
 } // namespace
 
 RetpolinePic::RetpolinePic() {
   pltHeaderSize = 48;
   pltEntrySize = 32;
+  ipltEntrySize = 32;
 }
 
 void RetpolinePic::writeGotPlt(uint8_t *buf, const Symbol &s) const {
   write32le(buf, s.getPltVA() + 17);
 }
 
 void RetpolinePic::writePltHeader(uint8_t *buf) const {
   const uint8_t insn[] = {
const uint8_t insn[] = {
       0xe9, 0,    0,    0,    0,       // jmp plt+0x12
       0x68, 0,    0,    0,    0,       // pushl $reloc_offset
       0xe9, 0,    0,    0,    0,       // jmp plt+0
       0xcc, 0xcc, 0xcc, 0xcc, 0xcc,    // int3; padding
   };
   memcpy(buf, insn, sizeof(insn));
 
   uint32_t ebx = in.gotPlt->getVA();
-  unsigned off = pltHeaderSize + pltEntrySize * index;
+  unsigned off = pltEntryAddr - in.plt->getVA();
   write32le(buf + 3, gotPltEntryAddr - ebx);
   write32le(buf + 8, -off - 12 + 32);
   write32le(buf + 13, -off - 17 + 18);
   write32le(buf + 18, relOff);
   write32le(buf + 23, -off - 27);
 }
 
 RetpolineNoPic::RetpolineNoPic() {
   pltHeaderSize = 48;
   pltEntrySize = 32;
+  ipltEntrySize = 32;
 }
 
 void RetpolineNoPic::writeGotPlt(uint8_t *buf, const Symbol &s) const {
   write32le(buf, s.getPltVA() + 16);
 }
 
 void RetpolineNoPic::writePltHeader(uint8_t *buf) const {
   const uint8_t insn[] = {
const uint8_t insn[] = {
       0xe9, 0,    0,    0,    0,    // b:  jmp plt+0x11
       0x68, 0,    0,    0,    0,    // 10: pushl $reloc_offset
       0xe9, 0,    0,    0,    0,    // 15: jmp plt+0
       0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 1a: int3; padding
       0xcc,                         // 1f: int3; padding
   };
   memcpy(buf, insn, sizeof(insn));
 
-  unsigned off = pltHeaderSize + pltEntrySize * index;
+  unsigned off = pltEntryAddr - in.plt->getVA();
   write32le(buf + 2, gotPltEntryAddr);
   write32le(buf + 7, -off - 11 + 32);
   write32le(buf + 12, -off - 16 + 17);
   write32le(buf + 17, relOff);
   write32le(buf + 22, -off - 26);
 }
 
 TargetInfo *getX86TargetInfo() {

lld/ELF/Arch/X86_64.cpp

X86_64::X86_64() {
   pltRel = R_X86_64_JUMP_SLOT;
   relativeRel = R_X86_64_RELATIVE;
   iRelativeRel = R_X86_64_IRELATIVE;
   symbolicRel = R_X86_64_64;
   tlsDescRel = R_X86_64_TLSDESC;
   tlsGotRel = R_X86_64_TPOFF64;
   tlsModuleIndexRel = R_X86_64_DTPMOD64;
   tlsOffsetRel = R_X86_64_DTPOFF64;
-  pltEntrySize = 16;
   pltHeaderSize = 16;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
   trapInstr = {0xcc, 0xcc, 0xcc, 0xcc}; // 0xcc = INT3
 
   // Align to the large page size (known as a superpage or huge page).
   // FreeBSD automatically promotes large, superpage-aligned allocations.
   defaultImageBase = 0x200000;
 }
 
 int X86_64::getTlsGdRelaxSkip(RelType type) const { return 2; }
const uint8_t inst[] = {
       0xff, 0x25, 0, 0, 0, 0, // jmpq *got(%rip)
       0x68, 0, 0, 0, 0,       // pushq <relocation index>
       0xe9, 0, 0, 0, 0,       // jmpq plt[0]
   };
   memcpy(buf, inst, sizeof(inst));
 
   write32le(buf + 2, gotPltEntryAddr - pltEntryAddr - 6);
   write32le(buf + 7, index);
-  write32le(buf + 12, -pltHeaderSize - pltEntrySize * index - 16);
+  write32le(buf + 12, in.plt->getVA() - pltEntryAddr - 16);
 }
 
 RelType X86_64::getDynRel(RelType type) const {
   if (type == R_X86_64_64 || type == R_X86_64_PC64 || type == R_X86_64_SIZE32 ||
       type == R_X86_64_SIZE64)
     return type;
   return R_X86_64_NONE;
 }
public:
   void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
                 int32_t index) const override;
 };
 } // namespace
 
 Retpoline::Retpoline() {
   pltHeaderSize = 48;
   pltEntrySize = 32;
+  ipltEntrySize = 32;
 }
 
 void Retpoline::writeGotPlt(uint8_t *buf, const Symbol &s) const {
   write64le(buf, s.getPltVA() + 17);
 }
 
 void Retpoline::writePltHeader(uint8_t *buf) const {
   const uint8_t insn[] = {
const uint8_t insn[] = {
       0xe8, 0,    0,    0,    0,    // 7:  callq plt+0x20
       0xe9, 0,    0,    0,    0,    // c:  jmp plt+0x12
       0x68, 0,    0,    0,    0,    // 11: pushq <relocation index>
       0xe9, 0,    0,    0,    0,    // 16: jmp plt+0
       0xcc, 0xcc, 0xcc, 0xcc, 0xcc, // 1b: int3; padding
   };
   memcpy(buf, insn, sizeof(insn));
 
-  uint64_t off = pltHeaderSize + pltEntrySize * index;
+  uint64_t off = pltEntryAddr - in.plt->getVA();
 
   write32le(buf + 3, gotPltEntryAddr - pltEntryAddr - 7);
   write32le(buf + 8, -off - 12 + 32);
   write32le(buf + 13, -off - 17 + 18);
   write32le(buf + 18, index);
   write32le(buf + 23, -off - 27);
 }
 
 RetpolineZNow::RetpolineZNow() {
   pltHeaderSize = 32;
   pltEntrySize = 16;
+  ipltEntrySize = 16;
 }
 
 void RetpolineZNow::writePltHeader(uint8_t *buf) const {
   const uint8_t insn[] = {
       0xe8, 0x0b, 0x00, 0x00, 0x00, // 0:    call next
       0xf3, 0x90,                   // 5:  loop: pause
       0x0f, 0xae, 0xe8,             // 7:    lfence
       0xeb, 0xf9,                   // a:    jmp loop
void RetpolineZNow::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
   const uint8_t insn[] = {
       0x4c, 0x8b, 0x1d, 0,    0, 0, 0, // mov foo@GOTPLT(%rip), %r11
       0xe9, 0,    0,    0,    0,       // jmp plt+0
       0xcc, 0xcc, 0xcc, 0xcc,          // int3; padding
   };
   memcpy(buf, insn, sizeof(insn));
 
   write32le(buf + 3, gotPltEntryAddr - pltEntryAddr - 7);
-  write32le(buf + 8, -pltHeaderSize - pltEntrySize * index - 12);
+  write32le(buf + 8, in.plt->getVA() - pltEntryAddr - 12);
 }
 
 static TargetInfo *getTargetInfo() {
   if (config->zRetpolineplt) {
     if (config->zNow) {
       static RetpolineZNow t;
       return &t;
     }

lld/ELF/Relocations.cpp

if (part.relrDyn && isec->alignment >= 2 && offsetInSec % 2 == 0) {
     isec->relocations.push_back({expr, type, offsetInSec, addend, sym});
     part.relrDyn->relocs.push_back({isec, offsetInSec});
     return;
   }
   part.relaDyn->addReloc(target->relativeRel, isec, offsetInSec, sym, addend,
                          expr, type);
 }
 
-template <class GotPltSection>
+template <class PltSection, class GotPltSection>
 static void addPltEntry(PltSection *plt, GotPltSection *gotPlt,
                         RelocationBaseSection *rel, RelType type, Symbol &sym) {
   plt->addEntry(sym);
   gotPlt->addEntry(sym);
   rel->addReloc(
       {type, gotPlt, sym.getGotPltOffset(), !sym.isPreemptible, &sym, 0});
 }
 
if (needsGot(expr)) {
       //
       // This field is also used to keep track of whether we ever needed a GOT
       // entry. If we did and we make the PLT canonical later, we'll need to
       // create a GOT entry pointing to the PLT entry for Sym.
       sym.gotInIgot = true;
     } else if (!needsPlt(expr)) {
       // Make the ifunc's PLT entry canonical by changing the value of its
       // symbol to redirect all references to point to it.
-      unsigned entryOffset = sym.pltIndex * target->pltEntrySize;
-      if (config->zRetpolineplt)
-        entryOffset += target->pltHeaderSize;
-
       auto &d = cast<Defined>(sym);
       d.section = in.iplt;
-      d.value = entryOffset;
+      d.value = sym.pltIndex * target->ipltEntrySize;
       d.size = 0;
       // It's important to set the symbol type here so that dynamic loaders
       // don't try to call the PLT as if it were an ifunc resolver.
       d.type = STT_FUNC;
 
       if (sym.gotInIgot) {
         // We previously encountered a GOT generating reference that we
         // redirected to the Igot. Now that the PLT entry is canonical we must

lld/ELF/Symbols.cpp

 
 uint64_t Symbol::getGotPltOffset() const {
   if (isInIplt)
     return pltIndex * config->wordsize;
   return (pltIndex + target->gotPltHeaderEntriesNum) * config->wordsize;
 }
 
 uint64_t Symbol::getPltVA() const {
-  PltSection *plt = isInIplt ? in.iplt : in.plt;
-  uint64_t outVA =
-      plt->getVA() + plt->headerSize + pltIndex * target->pltEntrySize;
+  uint64_t outVA = isInIplt
+                       ? in.iplt->getVA() + pltIndex * target->ipltEntrySize
+                       : in.plt->getVA() + in.plt->headerSize +
+                             pltIndex * target->pltEntrySize;
+
   // While linking microMIPS code PLT code are always microMIPS
   // code. Set the less-significant bit to track that fact.
   // See detailed comment in the `getSymVA` function.
   if (config->emachine == EM_MIPS && isMicroMips())
     outVA |= 1;
   return outVA;
 }
 

lld/ELF/SyntheticSections.h

public:
   HashTableSection();
   void finalizeContents() override;
   void writeTo(uint8_t *buf) override;
   size_t getSize() const override { return size; }
 
 private:
   size_t size = 0;
 };
 
-// The PltSection is used for both the Plt and Iplt. The former usually has a
-// header as its first entry that is used at run-time to resolve lazy binding.
-// The latter is used for GNU Ifunc symbols, that will be subject to a
-// Target->IRelativeRel.
+// Used for PLT entries. It usually has a PLT header for lazy binding. Each PLT
+// entry is associated with a JUMP_SLOT relocation, which may be resolved lazily
+// at runtime.
 class PltSection : public SyntheticSection {
 public:
-  PltSection(bool isIplt);
+  PltSection();
   void writeTo(uint8_t *buf) override;
   size_t getSize() const override;
-  bool isNeeded() const override { return !entries.empty(); }
+  bool isNeeded() const override;
   void addSymbols();
   void addEntry(Symbol &sym);
 
   size_t headerSize;
 
 private:
   std::vector<const Symbol *> entries;
-  bool isIplt;
+};
+
+// Used for non-preemptible ifuncs. It does not have a header. Each entry is
+// associated with an IRELATIVE relocation, which will be resolved eagerly at
+// runtime. PltSection cannot can only contain entries associated with JUMP_SLOT
+// relocations, so IPLT entries are in a separate section.
+class IpltSection final : public SyntheticSection {
+  std::vector<const Symbol *> entries;
+
+public:
+  IpltSection();
+  void writeTo(uint8_t *buf) override;
+  size_t getSize() const override;
+  bool isNeeded() const override { return !entries.empty(); }
+  void addSymbols();
+  void addEntry(Symbol &sym);
 };
 
 class GdbIndexSection final : public SyntheticSection {
 public:
   struct AddressEntry {
     InputSection *section;
     uint64_t lowAddress;
     uint64_t highAddress;
struct InStruct {
   GotPltSection *gotPlt;
   IgotPltSection *igotPlt;
   PPC64LongBranchTargetSection *ppc64LongBranchTarget;
   MipsGotSection *mipsGot;
   MipsRldMapSection *mipsRldMap;
   SyntheticSection *partEnd;
   SyntheticSection *partIndex;
   PltSection *plt;
-  PltSection *iplt;
+  IpltSection *iplt;
   PPC32Got2Section *ppc32Got2;
   RelocationBaseSection *relaPlt;
   RelocationBaseSection *relaIplt;
   StringTableSection *shStrTab;
   StringTableSection *strTab;
   SymbolTableBaseSection *symTab;
   SymtabShndxSection *symTabShndx;
 };
 
 extern InStruct in;
 
 } // namespace elf
 } // namespace lld
 
 #endif

lld/ELF/SyntheticSections.cpp

for (const SymbolTableEntry &s : symTab->getSymbols()) {
     uint32_t hash = hashSysV(name) % numSymbols;
     chains[i] = buckets[hash];
     write32(buckets + hash, i);
   }
 }
 
 // On PowerPC64 the lazy symbol resolvers go into the `global linkage table`
 // in the .glink section, rather then the typical .plt section.
-PltSection::PltSection(bool isIplt)
-    : SyntheticSection(
-          SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16,
-          (config->emachine == EM_PPC || config->emachine == EM_PPC64)
-              ? ".glink"
-              : ".plt"),
-      headerSize(!isIplt || config->zRetpolineplt ? target->pltHeaderSize : 0),
-      isIplt(isIplt) {
+PltSection::PltSection()
+    : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16, ".plt"),
+      headerSize(target->pltHeaderSize) {
+  if (config->emachine == EM_PPC || config->emachine == EM_PPC64) {
+    name = ".glink";
+  }
+
   // The PLT needs to be writable on SPARC as the dynamic linker will
   // modify the instructions in the PLT entries.
   if (config->emachine == EM_SPARCV9)
     this->flags |= SHF_WRITE;
 }
 
 void PltSection::writeTo(uint8_t *buf) {
   if (config->emachine == EM_PPC) {
     writePPC32GlinkSection(buf, entries.size());
     return;
   }
 
-  // At beginning of PLT or retpoline IPLT, we have code to call the dynamic
+  // At beginning of PLT, we have code to call the dynamic
   // linker to resolve dynsyms at runtime. Write such code.
-  if (headerSize)
-    target->writePltHeader(buf);
   size_t off = headerSize;
 
   for (size_t i = 0, e = entries.size(); i != e; ++i) {
     const Symbol *b = entries[i];
     uint64_t got = b->getGotPltVA();
     uint64_t plt = this->getVA() + off;
     target->writePlt(buf + off, got, plt, b->pltIndex);
     off += target->pltEntrySize;
   }
 }
 
 void PltSection::addEntry(Symbol &sym) {
   sym.pltIndex = entries.size();
   entries.push_back(&sym);
 }
 
 size_t PltSection::getSize() const {
   return headerSize + entries.size() * target->pltEntrySize;
 }
 
-// Some architectures such as additional symbols in the PLT section. For
-// example ARM uses mapping symbols to aid disassembly
+bool PltSection::isNeeded() const {
+  // For -z retpolineplt, .iplt needs the .plt header.
+  return !entries.empty() || (config->zRetpolineplt && in.iplt->isNeeded());
+}
+
+// Used by ARM to add mapping symbols in the PLT section, which aid
+// disassembly.
 void PltSection::addSymbols() {
-  // The PLT may have symbols defined for the Header, the IPLT has no header
-  if (!isIplt)
-    target->addPltHeaderSymbols(*this);
 
   size_t off = headerSize;
   for (size_t i = 0; i < entries.size(); ++i) {
     target->addPltSymbols(*this, off);
     off += target->pltEntrySize;
   }
 }
 
+IpltSection::IpltSection()
+    : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16, ".plt") {
+  if (config->emachine == EM_PPC || config->emachine == EM_PPC64) {
+    name = ".glink";
+  }
+}
+
+void IpltSection::writeTo(uint8_t *buf) {
+  uint32_t off = 0;
+  for (const Symbol *sym : entries) {
+    target->writeIplt(buf + off, sym->getGotPltVA(), getVA() + off,
+                      sym->pltIndex);
+    off += target->ipltEntrySize;
+  }
+}
+
+size_t IpltSection::getSize() const {
+  return entries.size() * target->ipltEntrySize;
+}
+
+void IpltSection::addEntry(Symbol &sym) {
+  sym.pltIndex = entries.size();
+  entries.push_back(&sym);
+}
+
+// ARM uses mapping symbols to aid disassembly.
+void IpltSection::addSymbols() {
+  size_t off = 0;
+  for (size_t i = 0, e = entries.size(); i != e; ++i) {
+    target->addPltSymbols(*this, off);
+    off += target->pltEntrySize;
+  }
+}
+
 // The string hash function for .gdb_index.
 static uint32_t computeGdbHash(StringRef s) {
   uint32_t h = 0;
   for (uint8_t c : s)
     h = h * 67 + toLower(c) - 113;
   return h;
 }
 

lld/ELF/Target.h

public:
 
   // If lazy binding is supported, the first entry of the PLT has code
   // to call the dynamic linker to resolve PLT entries the first time
   // they are called. This function writes that code.
   virtual void writePltHeader(uint8_t *buf) const {}
 
   virtual void writePlt(uint8_t *buf, uint64_t gotEntryAddr,
                         uint64_t pltEntryAddr, int32_t index) const {}
+  virtual void writeIplt(uint8_t *buf, uint64_t gotEntryAddr,
+                         uint64_t pltEntryAddr, int32_t index) const {
+    // All but PPC64 use the same format for .plt and .iplt entries.
+    writePlt(buf, gotEntryAddr, pltEntryAddr, index);
+  }
   virtual void addPltHeaderSymbols(InputSection &isec) const {}
   virtual void addPltSymbols(InputSection &isec, uint64_t off) const {}
 
   // Returns true if a relocation only uses the low bits of a value such that
   // all those bits are in the same page. For example, if the relocation
   // only uses the low 12 bits in a system with 4k pages. If this is true, the
   // bits will always have the same value at runtime and we don't have to emit
   // a dynamic relocation.
public:
   RelType iRelativeRel;
   RelType symbolicRel;
   RelType tlsDescRel;
   RelType tlsGotRel;
   RelType tlsModuleIndexRel;
   RelType tlsOffsetRel;
   unsigned pltEntrySize;
   unsigned pltHeaderSize;
+  unsigned ipltEntrySize;
 
   // At least on x86_64 positions 1 and 2 are used by the first plt entry
   // to support lazy loading.
   unsigned gotPltHeaderEntriesNum = 3;
 
   // On PPC ELF V2 abi, the first entry in the .got is the .TOC.
   unsigned gotHeaderEntriesNum = 0;
 

lld/ELF/Writer.cpp

template <class ELFT> void createSyntheticSections() {
   // that would cause a section type mismatch. However, because the Android
   // dynamic loader reads .rel.plt after .rel.dyn, we can get the desired
   // behaviour by placing the iplt section in .rel.plt.
   in.relaIplt = make<RelocationSection<ELFT>>(
       config->androidPackDynRelocs ? in.relaPlt->name : relaDynName,
       /*sort=*/false);
   add(in.relaIplt);
 
-  in.plt = make<PltSection>(false);
+  in.plt = make<PltSection>();
   add(in.plt);
-  in.iplt = make<PltSection>(true);
+  in.iplt = make<IpltSection>();
   add(in.iplt);
 
   if (config->andFeatures)
     add(make<GnuPropertySection>());
 
   // .note.GNU-stack is always added when we are creating a re-linkable
   // object file. Other linkers are using the presence of this marker
   // section to control the executable-ness of the stack area, but that

lld/test/ELF/gnu-ifunc-i386.s

 // DISASM-NEXT:                 movl $4194516, %edx
 // DISASM-NEXT:                 movl $4194532, %edx
 // DISASM-EMPTY:
 // DISASM-NEXT: Disassembly of section .plt:
 // DISASM-EMPTY:
 // DISASM-NEXT: foo:
 // DISASM-NEXT:   401100:       jmpl *4202784
 // DISASM-NEXT:                 pushl $0
-// DISASM-NEXT:                 jmp -32 <_start+0xa>
+// DISASM-NEXT:                 jmp -16 <foo>
 // DISASM:      bar:
 // DISASM-NEXT:   401110:       jmpl *4202788
 // DISASM-NEXT:                 pushl $8
-// DISASM-NEXT:                 jmp -48 <_start+0xa>
+// DISASM-NEXT:                 jmp -32 <foo>
 
 .text
 .type foo STT_GNU_IFUNC
 .globl foo
 foo:
 .type foo_resolver STT_FUNC
 .globl foo_resolver
 foo_resolver:

lld/test/ELF/gnu-ifunc-plt-i386.s

 // DISASM-NEXT:                  jmp     -32 <.plt>
 // DISASM-EMPTY:
 // DISASM-NEXT:   zed2@plt:
 // DISASM-NEXT:    4011f0:       jmpl    *4207272
 // DISASM-NEXT:                  pushl   $8
 // DISASM-NEXT:                  jmp     -48 <.plt>
 // DISASM-NEXT:                  jmpl    *4207276
 // DISASM-NEXT:                  pushl   $0
-// DISASM-NEXT:                  jmp     -32 <zed2@plt>
+// DISASM-NEXT:                  jmp     -64 <.plt>
 // DISASM-NEXT:                  jmpl    *4207280
 // DISASM-NEXT:                  pushl   $8
-// DISASM-NEXT:                  jmp     -48 <zed2@plt>
+// DISASM-NEXT:                  jmp     -80 <.plt>
 
 .text
 .type foo STT_GNU_IFUNC
 .globl foo
 foo:
  ret
 
 .type bar STT_GNU_IFUNC

lld/test/ELF/gnu-ifunc-plt.s

 // DISASM-NEXT:   20130b:       jmp     -32 <.plt>
 // DISASM-EMPTY:
 // DISASM-NEXT:   zed2@plt:
 // DISASM-NEXT:   201310:       jmpq    *8506(%rip)
 // DISASM-NEXT:   201316:       pushq   $1
 // DISASM-NEXT:   20131b:       jmp     -48 <.plt>
 // DISASM-NEXT:   201320:       jmpq    *8498(%rip)
 // DISASM-NEXT:   201326:       pushq   $0
-// DISASM-NEXT:   20132b:       jmp     -32 <zed2@plt>
+// DISASM-NEXT:   20132b:       jmp     -64 <.plt>
 // DISASM-NEXT:   201330:       jmpq    *8490(%rip)
 // DISASM-NEXT:   201336:       pushq   $1
-// DISASM-NEXT:   20133b:       jmp     -48 <zed2@plt>
+// DISASM-NEXT:   20133b:       jmp     -80 <.plt>
 
 .text
 .type foo STT_GNU_IFUNC
 .globl foo
 foo:
  ret
 
 .type bar STT_GNU_IFUNC

lld/test/ELF/gnu-ifunc-shared.s

 // DISASM-NEXT:     133b:       jmp     -32 <.plt>
 // DISASM-EMPTY:
 // DISASM-NEXT:   f2@plt:
 // DISASM-NEXT:     1340:       jmpq    *8474(%rip)
 // DISASM-NEXT:     1346:       pushq   $1
 // DISASM-NEXT:     134b:       jmp     -48 <.plt>
 // DISASM-NEXT:     1350:       jmpq    *8466(%rip)
 // DISASM-NEXT:     1356:       pushq   $0
-// DISASM-NEXT:     135b:       jmp     -32 <f2@plt>
+// DISASM-NEXT:     135b:       jmp     -64 <.plt>
 
 // CHECK: Relocations [
 // CHECK-NEXT:   Section (5) .rela.dyn {
 // CHECK-NEXT:     0x3468 R_X86_64_IRELATIVE - 0x1308
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section (6) .rela.plt {
 // CHECK-NEXT:     0x3458 R_X86_64_JUMP_SLOT fct2 0x0
 // CHECK-NEXT:     0x3460 R_X86_64_JUMP_SLOT f2 0x0

lld/test/ELF/gnu-ifunc.s

 // DISASM-NEXT:  201199: {{.*}} movl $2097544, %edx
 // DISASM-NEXT:  20119e: {{.*}} movl $2097545, %edx
 // DISASM-EMPTY:
 // DISASM-NEXT: Disassembly of section .plt:
 // DISASM-EMPTY:
 // DISASM-NEXT: .plt:
 // DISASM-NEXT:  2011b0: {{.*}} jmpq *4122(%rip)
 // DISASM-NEXT:  2011b6: {{.*}} pushq $0
-// DISASM-NEXT:  2011bb: {{.*}} jmp -32 <_start+0x16>
+// DISASM-NEXT:  2011bb: {{.*}} jmp -16 <.plt>
 // DISASM-NEXT:  2011c0: {{.*}} jmpq *4114(%rip)
 // DISASM-NEXT:  2011c6: {{.*}} pushq $1
-// DISASM-NEXT:  2011cb: {{.*}} jmp -48 <_start+0x16>
+// DISASM-NEXT:  2011cb: {{.*}} jmp -32 <.plt>
 
 .text
 .type foo STT_GNU_IFUNC
 .globl foo
 foo:
  ret
 
 .type bar STT_GNU_IFUNC