[PowerPC][NFC] Rename record instructions to use _rec suffix instead of o

[jsji]

Summary

We use o suffix to indicate record form instuctions,
(as it is similar to dot '.' in mne?)

This was fine before, as we did not support XO-form.
However, with https://reviews.llvm.org/D66902,
we now have XO-form support.

It becomes confusing now to still use 'o' for record form,
and it is weird to have something like 'Oo' .

This patch rename all 'o' instructions to use '_rec' instead.
Also rename isDot to isRecordForm.

[steven.zhang]

LGTM as it is straightforward. However, please hold on for some time in case someone else has other concern.

[jsji]

Rebased to resolve conflict.

[nemanjai]

I am going to mark this as requiring changes until we can get more consensus on the direction. This is a very pervasive change that is completely subjective and as such should require agreement from more than two people that work on the target.

Personally, I am on the fence with a slight lean towards keeping the o convention we had before. While I understand that things like ADDOo may appear a bit ambiguous, I would say that ANDIr and RLDICRr is downright weird. To me, the fact that the mnemonic is all uppercase and the o that is a stand-in for the dot is pretty clear, but that may just be the fact that I am so familiar with the existing naming. Furthermore, the flag we set in the multiclasses is called isDOT and there is no clear relationship between this "dot" and the letter r. All that said, I will not block this if the majority is in agreement (or indifferent). But let's get some more eyes on this.

Perhaps @hfinkel, @jhibbits, @echristo or @joerg might have some input on this patch.

[jhibbits]

I second @nemanjai, the lowercase 'o' suffix stands out to me as a clear indicator of it being punctuation, not a letter in the instruction. I would much rather see ANDIo than ANDIr, the 'r' just doesn't look right when reading over it. My vote is to reject. It looks like a lot of churn without much benefit.

[jsji]

Furthermore, the flag we set in the multiclasses is called isDOT and there is no clear relationship between this "dot" and the letter r. All that said, I will not block this if the majority is in agreement (or indifferent). But let's get some more eyes on this.

Thanks for the review. Yes, welcome others' input and comments.
To me isDOT is saying the mne will have dot '.' at the end , that is exactly what the ISA says about mne of record form. And we can also rename isDOT to isRecord if we do need it to be explicit.

[jsji]

In D70758#1765982, @jhibbits wrote:

I second @nemanjai, the lowercase 'o' suffix stands out to me as a clear indicator of it being punctuation, not a letter in the instruction. I would much rather see ANDIo than ANDIr, the 'r' just doesn't look right when reading over it. My vote is to reject. It looks like a lot of churn without much benefit.

I understand that it might not be a big problem if you are familiar with the code base, but it is confusing to new comers.

For example, if you are discussing about some optimization related to ADD-o,
then you don't know exactly what you are talking about.

You will need to clarify more :

are you talking about big O or small o?

are you talking about assembly addo or opcode ADDO?

I need to change some o-form instructions..... wait, are you talking about record form or XO-form?

This is an effort to avoid confusion for newcomers, especially when dealing with assembly as well.

If r is not as straightforward as it should be, how about _r? eg: ANDI_r instead of ANDIo. Or any other suggestions?

[jhibbits]

When discussing optimizations related to "ADD-o", if it's "ADDO" I'd call it "ADD-O", but if it's "ADDo" I'd call it "ADD-dot", since all record forms are referred to as 'dot's, even in all the documentation I've seen. For instance, immediately above this text box is the "rlwinm_rldicl_to_andi.mir" test, with the change of "ANDIo8..." to "ANDIr8".... I read that instinctively as "ANDI-dot-8", whereas "ANDIr8" looks like "ANDI-R-8" which doesn't have a corresponding instruction in the ISA. Additionally, the asm string in PPCInstrInfo.td is "andi. ...", which would make someone question what the 'r' is for, when it doesn't even exist in the instruction. Seeing a 'ANDIo' alongside "andi." someone will easily see the 'o' stands for the '.'.

I understand where you're coming from, but with the (supposed) goal being to mimic the mnemonics as closely as possible, I still believe keeping 'o' is the right course.

[nemanjai]

Yeah, I actually added my initial comment precisely because I thought the existing form is more familiar to those that do not have deep experience with the ISA. What I mean is that the r is fairly intuitive to those of us that are deeply familiar with the ISA - it means "record-form". But to those less familiar with the ISA, the phrase "record-form" may be completely foreign and the choice of r would then be quite confusing. Whereas looking at the mnemonics in the ISA:

add
add.
addo
addo.

and the corresponding mnemonics in our td files:

ADD
ADDo
ADDO
ADDOo

it does not require a lot of familiarity to connect the uppercase letters to the letters in the mnemonic and the lowercase letter to the dot.

(note that I do realize that these have 4/8 on them and chose those to illustrate that the more confusing part to a newcomer is the 32/64 bit versions)

[jsji]

In D70758#1766055, @jhibbits wrote:

When discussing optimizations related to "ADD-o", if it's "ADDO" I'd call it "ADD-O", but if it's "ADDo" I'd call it "ADD-dot",

Thanks. Yeah, agree that is a good trick, iff we already know we should call small 'o' as 'dot', instead of O, then it will be better.

But I believe that is not obvious to new members..
At least I did not recall any of our new members being able to read it as 'ADD-dot'.

[hfinkel]

Hrmm... the current naming convention predates me, but it wasn't difficult to figure out. If you're familiar with the ISA and the fact that the record forms have mnemonics ending in a '.'. Honestly, replacing 'o' with 'r' doesn't seem all that much better to me, as I still need to know that the 'r' stands for record form and understand what that means. It's not like searching the ISA manual for '.', or 'o', or 'r', is going to buy one much of anything. I am sympathetic to none of these being immediately obvious, and I'd be happy with some fix to that situation.

To make things more obvious, we could replace isDOT with isRecordForm, the 'o' suffix with _record (moving the numeric suffix, where present, to before the underscore). What do you think of that?

[jsji]

To make things more obvious, we could replace isDOT with isRecordForm, the 'o' suffix with _record (moving the numeric suffix, where present, to before the underscore). What do you think of that?

Thanks! Regarding numeric suffixes, ANDI(S) are the only two that were not consistent, i planned to rename them independent of record suffix renaming, in
https://reviews.llvm.org/D70928.

I will update the patch to base on D70928, then do renaming of isDot and 'o' to '_record'.

[jsji]

Rename record instructions to use _record suffix instead of o
Rename isDot to isRecordForm

[jsji]

Rename RLWINM(I)_recordbm to RLWINM(I)bm_record

[nemanjai]

I was originally going to suggest a more verbose suffix much as Hal suggested, since any single letter is kind of meaningless. But to be honest, I hate the added verbosity and feel that instruction mnemonics are just an inherently tricky thing that requires experience with the ISA document.

So since the status quo is at the top of my list of naming convention preferences in this case, I will abstain from further comments and will accept whatever the majority decides.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1392–1395

Ugh.

[jhibbits]

I still hold pretty strongly that this change is a more negative impact than positive. As shown in the tests, it's very easy to read the generated statements as "FOO-dot", and search for what 'foo.' actually is. The only difficult part is the '*8' vs '*4', since you can't search for that, and need to remember to drop the number, which isn't difficult after the first time.

Searching the POWER ISA 3.0B reference, I see IBM using "period(.)", while the "EREF_RM" (NXP/Freescale Book-E reference) uses "dot suffix", with "record-form" only being used when describing the actual encoding.

[jsji]

In D70758#1766818, @nemanjai wrote:

So since the status quo is at the top of my list of naming convention preferences in this case, I will abstain from further comments and will accept whatever the majority decides.

Thanks for the kindness to support efforts for helping newcomers. @nemanjai

In D70758#1767084, @jhibbits wrote:

I still hold pretty strongly that this change is a more negative impact than positive.

Can you be more specific about the negative impact of new proposal (_record suffix)?

What I can think of is:

1. longer name
2. breaking existing user's habit
3. breaking downstream code.

#3 shouldn't be a problem if we agree that it is a correct direction to make the code more readable and less confusion, to make it easier for newcomers to contribute.
#2 might be annoying to existing developers, especially experts like you and @nemanjai. However, I believe experts like you will have mercy on newcomers.
#1 I think it depends on how you look at it. -- To me, it is more verbose, and also call more attention to such opcodes: paying attention that this is a record form instruction, it is different from normal form!

As shown in the tests, it's very easy to read the generated statements as "FOO-dot", and search for what 'foo.' actually is.

Again, it is easy for experts like you, but non obvious for newcomers without background.

Searching the POWER ISA 3.0B reference, I see IBM using "period(.)", while the "EREF_RM" (NXP/Freescale Book-E reference) uses "dot suffix", with "record-form" only being used when describing the actual encoding.

Thanks for double check both Power ISA and EREF_RM. Yeah, so, record-form is the ONLY common terminology here.

If you still feel strongly against the new suffixes (_record) that Hal proposed, do you have any other suggestions?

Stepping back, or do you think it is NOT confusing at all? or you think it is somehow a little confusing but no good way to fix it?

Thanks. @jhibbits

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1392–1395

Agree that this ISD name is somehow ugly. We can definitely rename them if needed.
However, looks like to me that they are for a 'AND glue' bug only, should eventually go away.

[jhibbits]

I personally think the status quo is easy to read. The definitions look like the instructions themselves, and the added verbosity seems very unnecessary. I don't know about others, but I consider people working in the PPCInstr*.td files to be either knowing exactly what they're looking for (grepping), or have a sufficient handle on the ISA that the existing notation is clear. At most I could see changing the 'o' suffix to '_o', which might help newcomers familiar with '_' notation to indicate a diminutive or subscript, but '_record' is very verbose, and as @nemanjai points out, can make some text very ugly.

[jsji]

In D70758#1767545, @jhibbits wrote:

I personally think the status quo is easy to read. The definitions look like the instructions themselves, and the added verbosity seems very unnecessary. I don't know about others, but I consider people working in the PPCInstr*.td files to be either knowing exactly what they're looking for (grepping), or have a sufficient handle on the ISA that the existing notation is clear. At most I could see changing the 'o' suffix to '_o', which might help newcomers familiar with '_' notation to indicate a diminutive or subscript, but '_record' is very verbose, and as @nemanjai points out, can make some text very ugly.

'status quo' was OK if we don't have XO-form support.

The motivation of this patch is to avoid confusion between 'o' and 'O' suffixes, and make it easier to connect 'o' to record form in ISA,
apparently, changing 'o' to '_o' won't help with that.

I see the benefit of verbose (_record) here: lower the barrier of 2-3 levels for newcomers.

1. You don't necessarily know 'o' at the end of opcode should be read as 'dot', not as o character itself.
2. You don't necessarily know that 'o' will be corresponding to period(.) at the end of assembly mnemonics.
3. You don't necessarily know that mnemonics with period(.) or dot suffixes is called record form in ISA.
4. You don't necessarily know that record form will modify condition registers

It will take a newcomer at least above 4 steps to figure out what is the difference between SUBICo and SUBIC,
and what is worse, one may easily be blocked by misunderstandings in any of these steps.

But with SUBIC_record, one can easily figure out it in one step: searching SUBIC and record in ISA.

Yes, _record is a bit longer and verbose, and may be somehow *ugly* to someone,
but I see the benefits outweigh tidy/compact code.

What do you think?

[lkail]

As a newbie of PowerPC backend, I think what @jsji proposed will ease my mind burden when faced with o ended instructions. I have read ISA-3.0 and know

A period (.) as the last character of an instruction
mnemonic means that the instruction *records* sta-
tus information in certain fields of the Condition
Register as a side effect of execution.

I can directly react to the effect of record-form instruction if it ends with _record. If _record is too long, how about _rec, just like X86's _alt ended instructions?

[jhibbits]

I might object less to a _rec suffix. However, you would still need to understand what "record form" means, which requires understanding of the ISA. Why not simply add a comment block to the top of PPCInstrInfo.td, describing things like this? I have a feeling other newbies would have similar questions/concerns/complaints, and they can't all be addressed by renaming everything.

I would propose something along the lines of the following as a block comment in PPCInstrInfo.td:

The following conventions are used for PowerISA definitions:

• - 'o' suffix: Record-form of an instruction, updates CR
• - '8' suffix: 64-bit version of an instruction

These can be chained, such as in the case of 'ANDI8o'

[jsji]

In D70758#1771145, @jhibbits wrote:

I might object less to a _rec suffix. However, you would still need to understand what "record form" means, which requires understanding of the ISA. Why not simply add a comment block to the top of PPCInstrInfo.td, describing things like this? I have a feeling other newbies would have similar questions/concerns/complaints, and they can't all be addressed by renaming everything.

Although I still prefer _record as what Hal proposed. Verbose and Simplicity. _rec also acceptable to me.

I would propose something along the lines of the following as a block comment in PPCInstrInfo.td:

Sure, we can always add similar comments besides renaming.

The downside of only putting some block comment in certain file is:
most of the time you will still miss it if you don't happen to look into the specific section of that file.

I don't expect everyone be able to find and read this specific block comment in PPCInstrInfo.td,
when he/she start to look at some code, and confused about SUBICo and SUBIC.
He/she may be able to look back into definition of SUBIC, but if the comment is not nearby,
he might not have idea to where to find that block of comments.
And we can't expect everyone to be able to read all important files, or know which file to look at.

[jsji]

Hi all, thanks for the review and discussion.
I'd like to make a final decision about commit or abandon, I don't see any point of leaving this longer.

Currently,
@jsji (me) is still prefer _record, can accept _rec.
@jhibbits is still against _record (prefer no change or at most _rec).
@lkail agreed with _record as a relatively new comer, can accept _rec.
@nemanjai is still kindly silent.

@steven.zhang @hfinkel Any further comments or suggestions? Thanks.

[hfinkel]

In D70758#1775807, @jsji wrote:

Hi all, thanks for the review and discussion.
I'd like to make a final decision about commit or abandon, I don't see any point of leaving this longer.

Currently,
@jsji (me) is still prefer _record, can accept _rec.
@jhibbits is still against _record (prefer no change or at most _rec).
@lkail agreed with _record as a relatively new comer, can accept _rec.
@nemanjai is still kindly silent.

@steven.zhang @hfinkel Any further comments or suggestions? Thanks.

So the common subset is _rec, right?

[steven.zhang]

When my first time see the suffix "o" in the opcode, it is really hard for me to know that it is record form...(o stands for .) As mentioned before, there is no good way to use short character(such as 'o' or 'r') to indicate too much information. But we could have some information in the instruction definition if people really want to know what it is. Personally, I don't like the _record, even the _rec, as it will make the opcode longer(i.e. ANDI_record_1_GT_BIT8). I will vote for abandon if we want to change it to _rec or _record. But you can skip my opinion as I didn't have strong bias on this :)

[jsji]

In D70758#1776123, @hfinkel wrote:

So the common subset is _rec, right?

Yes, you are right! I will update the patch to use _rec.

In D70758#1776504, @steven.zhang wrote:

When my first time see the suffix "o" in the opcode, it is really hard for me to know that it is record form...(o stands for .)

Thanks for double confirming the problem.

I will vote for abandon if we want to change it to _rec or _record.

I think we shouldn't abandon just due to longer name.
As I mentioned above, yes, renaming may be somehow *ugly* to someone,
but I see the benefits outweigh tidy/compact code. (especially for newcomers).

[jsji]

Rename to _rec instead.

[merge_guards_bot]

Build result: pass - 60660 tests passed, 0 failed and 726 were skipped.

Log files: console-log.txt, CMakeCache.txt

[jsji]

Ping...

[jsji]

Ping....

[jsji]

Ping ...

[hfinkel]

In D70758#1798961, @jsji wrote:

Ping ...

LGTM

[lkail]

LGTM. Given some verbosity can really help us to understand code quickly.

[jsji]

Thanks, Hal & Kai.
@jhibbits @nemanjai , are you OK with this now?

[nemanjai]

I would say that this is as close to a [perhaps begrudging] consensus as we'll get. Lets get this bike shed built. Please go ahead with the commit. LGTM.

[jsji]

Rebase

[merge_guards_bot]

Unit tests: pass. 61160 tests passed, 0 failed and 728 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[jsji]

clang-tidy failure fixed in https://reviews.llvm.org/rGfcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2.

Rebase and run git-clang-format HEAD^ as sugggested by merge_guards_bot.

[merge_guards_bot]

Unit tests: pass. 61160 tests passed, 0 failed and 728 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[jsji]

clang-tidy: fail. Please fix clang-tidy findings.

...llvm/lib/Target/PowerPC/PPCISelLowering.cpp:7399:28: warning: invalid case style for function 'LowerTRUNCATEVector' [readability-identifier-naming]
SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,

^~~~~~~~~~~~~~~~~~~
 lowerTruncateVector

I have fixed one the the clang-tidy failure in https://github.com/llvm/llvm-project/commit/fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2,
but as @nemanjai pointed out 'It is questionable how/whether this renaming applies to well established conventions that do not conform…'

In this case it might be worse, as we have some non-conform naming in target independent code as well.

eg:

$ grep ":Lower.*(" llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
SDValue TargetLowering::LowerAsmOutputForConstraint(
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,

My understanding is we want to avoid large-scale renaming just due to naming convention, but we should gradually transform to keep the source code clang-tidy conform, and pre-merge testing green?
In some cases, this means we will gradually getting some new code that conform to clang-tidy, but break well established conventions .

Is that OK? @hfinkel
If not, what direction we should pursue? Thanks.

[jsji]

@jhibbits: are you OK with this now? Most of the other reviewers are OK with this now. Thanks.

[jhibbits]

Not happy, but won't hold it up.

I'd rather see just the "isDOT" changed to "isRecord" and leave the rest as-is, but I'll defer to everyone else.

[jsji]

In D70758#1805850, @jhibbits wrote:

Not happy, but won't hold it up.

I'd rather see just the "isDOT" changed to "isRecord" and leave the rest as-is, but I'll defer to everyone else.

OK.. Sorry to make you unhappy..
Thank you for the kindness to sacrifice and support efforts for helping newcomers.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

case PPC::SUBIC: {
     MCInst TmpInst;
     TmpInst.setOpcode(PPC::ADDIC);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
     Inst = TmpInst;
     break;
   }
-  case PPC::SUBICo: {
+  case PPC::SUBIC_rec: {
     MCInst TmpInst;
-    TmpInst.setOpcode(PPC::ADDICo);
+    TmpInst.setOpcode(PPC::ADDIC_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
     Inst = TmpInst;
     break;
   }
   case PPC::EXTLWI:
-  case PPC::EXTLWIo: {
+  case PPC::EXTLWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(N - 1));
     Inst = TmpInst;
     break;
   }
   case PPC::EXTRWI:
-  case PPC::EXTRWIo: {
+  case PPC::EXTRWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B + N));
     TmpInst.addOperand(MCOperand::createImm(32 - N));
     TmpInst.addOperand(MCOperand::createImm(31));
     Inst = TmpInst;
     break;
   }
   case PPC::INSLWI:
-  case PPC::INSLWIo: {
+  case PPC::INSLWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - B));
     TmpInst.addOperand(MCOperand::createImm(B));
     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
     Inst = TmpInst;
     break;
   }
   case PPC::INSRWI:
-  case PPC::INSRWIo: {
+  case PPC::INSRWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
     TmpInst.addOperand(MCOperand::createImm(B));
     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
     Inst = TmpInst;
     break;
   }
   case PPC::ROTRWI:
-  case PPC::ROTRWIo: {
+  case PPC::ROTRWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - N));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(31));
     Inst = TmpInst;
     break;
   }
   case PPC::SLWI:
-  case PPC::SLWIo: {
+  case PPC::SLWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(31 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::SRWI:
-  case PPC::SRWIo: {
+  case PPC::SRWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - N));
     TmpInst.addOperand(MCOperand::createImm(N));
     TmpInst.addOperand(MCOperand::createImm(31));
     Inst = TmpInst;
     break;
   }
   case PPC::CLRRWI:
-  case PPC::CLRRWIo: {
+  case PPC::CLRRWI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(31 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::CLRLSLWI:
-  case PPC::CLRLSLWIo: {
+  case PPC::CLRLSLWI_rec: {
     MCInst TmpInst;
     int64_t B = Inst.getOperand(2).getImm();
     int64_t N = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
     TmpInst.addOperand(MCOperand::createImm(B - N));
     TmpInst.addOperand(MCOperand::createImm(31 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::EXTLDI:
-  case PPC::EXTLDIo: {
+  case PPC::EXTLDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B));
     TmpInst.addOperand(MCOperand::createImm(N - 1));
     Inst = TmpInst;
     break;
   }
   case PPC::EXTRDI:
-  case PPC::EXTRDIo: {
+  case PPC::EXTRDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B + N));
     TmpInst.addOperand(MCOperand::createImm(64 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::INSRDI:
-  case PPC::INSRDIo: {
+  case PPC::INSRDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
     TmpInst.addOperand(MCOperand::createImm(B));
     Inst = TmpInst;
     break;
   }
   case PPC::ROTRDI:
-  case PPC::ROTRDIo: {
+  case PPC::ROTRDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(64 - N));
     TmpInst.addOperand(MCOperand::createImm(0));
     Inst = TmpInst;
     break;
   }
   case PPC::SLDI:
-  case PPC::SLDIo: {
+  case PPC::SLDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
     TmpInst.addOperand(MCOperand::createImm(63 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::SUBPCIS: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(1).getImm();
     TmpInst.setOpcode(PPC::ADDPCIS);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(MCOperand::createImm(-N));
     Inst = TmpInst;
     break;
   }
   case PPC::SRDI:
-  case PPC::SRDIo: {
+  case PPC::SRDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(64 - N));
     TmpInst.addOperand(MCOperand::createImm(N));
     Inst = TmpInst;
     break;
   }
   case PPC::CLRRDI:
-  case PPC::CLRRDIo: {
+  case PPC::CLRRDI_rec: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(0));
     TmpInst.addOperand(MCOperand::createImm(63 - N));
     Inst = TmpInst;
     break;
   }
   case PPC::CLRLSLDI:
-  case PPC::CLRLSLDIo: {
+  case PPC::CLRLSLDI_rec: {
     MCInst TmpInst;
     int64_t B = Inst.getOperand(2).getImm();
     int64_t N = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
+    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
     TmpInst.addOperand(MCOperand::createImm(B - N));
     Inst = TmpInst;
     break;
   }
   case PPC::RLWINMbm:
-  case PPC::RLWINMobm: {
+  case PPC::RLWINMbm_rec: {
     unsigned MB, ME;
     int64_t BM = Inst.getOperand(3).getImm();
     if (!isRunOfOnes(BM, MB, ME))
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(MCOperand::createImm(MB));
     TmpInst.addOperand(MCOperand::createImm(ME));
     Inst = TmpInst;
     break;
   }
   case PPC::RLWIMIbm:
-  case PPC::RLWIMIobm: {
+  case PPC::RLWIMIbm_rec: {
     unsigned MB, ME;
     int64_t BM = Inst.getOperand(3).getImm();
     if (!isRunOfOnes(BM, MB, ME))
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(MCOperand::createImm(MB));
     TmpInst.addOperand(MCOperand::createImm(ME));
     Inst = TmpInst;
     break;
   }
   case PPC::RLWNMbm:
-  case PPC::RLWNMobm: {
+  case PPC::RLWNMbm_rec: {
     unsigned MB, ME;
     int64_t BM = Inst.getOperand(3).getImm();
     if (!isRunOfOnes(BM, MB, ME))
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
+    TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(MCOperand::createImm(MB));
     TmpInst.addOperand(MCOperand::createImm(ME));
     Inst = TmpInst;
     break;
   }
case PPC::CP_COPY_FIRST: {
     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
 
     Inst = TmpInst;
     break;
   }
   case PPC::CP_PASTEx :
   case PPC::CP_PASTE_LAST: {
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
-                      PPC::CP_PASTE : PPC::CP_PASTEo);
+    TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE
+                                               : PPC::CP_PASTE_rec);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
 
     Inst = TmpInst;
     break;
   }
   }

llvm/lib/Target/PowerPC/P9InstrResources.td

 )>;
 
 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C],
       (instrs
     (instregex "XSMAX(C|J)?DP$"),
     (instregex "XSMIN(C|J)?DP$"),
     (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
-    (instregex "CNT(L|T)Z(D|W)(8)?(o)?$"),
+    (instregex "CNT(L|T)Z(D|W)(8)?(_rec)?$"),
     (instregex "POPCNT(D|W)$"),
     (instregex "CMPB(8)?$"),
     (instregex "SETB(8)?$"),
     XSTDIVDP,
     XSTSQRTDP,
     XSXSIGDP,
     XSCVSPDPN,
     BPERMD
 )>;
 
 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
       (instrs
     (instregex "S(L|R)D$"),
     (instregex "SRAD(I)?$"),
     (instregex "EXTSWSLI_32_64$"),
     (instregex "MFV(S)?RD$"),
     (instregex "MTV(S)?RD$"),
     (instregex "MTV(S)?RW(A|Z)$"),
     (instregex "CMP(WI|LWI|W|LW)(8)?$"),
     (instregex "CMP(L)?D(I)?$"),
     (instregex "SUBF(I)?C(8)?(O)?$"),
-    (instregex "ANDI(S)?(8)?(o)?$"),
+    (instregex "ANDI(S)?(8)?(_rec)?$"),
     (instregex "ADDC(8)?(O)?$"),
-    (instregex "ADDIC(8)?(o)?$"),
-    (instregex "ADD(8|4)(O)?(o)?$"),
-    (instregex "ADD(E|ME|ZE)(8)?(O)?(o)?$"),
-    (instregex "SUBF(E|ME|ZE)?(8)?(O)?(o)?$"),
-    (instregex "NEG(8)?(O)?(o)?$"),
+    (instregex "ADDIC(8)?(_rec)?$"),
+    (instregex "ADD(8|4)(O)?(_rec)?$"),
+    (instregex "ADD(E|ME|ZE)(8)?(O)?(_rec)?$"),
+    (instregex "SUBF(E|ME|ZE)?(8)?(O)?(_rec)?$"),
+    (instregex "NEG(8)?(O)?(_rec)?$"),
     (instregex "POPCNTB$"),
     (instregex "ADD(I|IS)?(8)?$"),
     (instregex "LI(S)?(8)?$"),
-    (instregex "(X)?OR(I|IS)?(8)?(o)?$"),
-    (instregex "NAND(8)?(o)?$"),
-    (instregex "AND(C)?(8)?(o)?$"),
-    (instregex "NOR(8)?(o)?$"),
-    (instregex "OR(C)?(8)?(o)?$"),
-    (instregex "EQV(8)?(o)?$"),
-    (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
+    (instregex "(X)?OR(I|IS)?(8)?(_rec)?$"),
+    (instregex "NAND(8)?(_rec)?$"),
+    (instregex "AND(C)?(8)?(_rec)?$"),
+    (instregex "NOR(8)?(_rec)?$"),
+    (instregex "OR(C)?(8)?(_rec)?$"),
+    (instregex "EQV(8)?(_rec)?$"),
+    (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"),
     (instregex "ADD(4|8)(TLS)?(_)?$"),
     (instregex "NEG(8)?(O)?$"),
     (instregex "ADDI(S)?toc(HA|L)(8)?$"),
     COPY,
     MCRF,
     MCRXRX,
     XSNABSDP,
     XSXEXPDP,
def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
     (instregex "M(T|F)VSCR$"),
     (instregex "VCMPNEZ(B|H|W)$"),
     (instregex "VCMPEQU(B|H|W|D)$"),
     (instregex "VCMPNE(B|H|W)$"),
     (instregex "VABSDU(B|H|W)$"),
     (instregex "VADDU(B|H|W)S$"),
     (instregex "VAVG(S|U)(B|H|W)$"),
-    (instregex "VCMP(EQ|GE|GT)FP(o)?$"),
-    (instregex "VCMPBFP(o)?$"),
+    (instregex "VCMP(EQ|GE|GT)FP(_rec)?$"),
+    (instregex "VCMPBFP(_rec)?$"),
     (instregex "VC(L|T)Z(B|H|W|D)$"),
     (instregex "VADDS(B|H|W)S$"),
     (instregex "V(MIN|MAX)FP$"),
     (instregex "V(MIN|MAX)(S|U)(B|H|W|D)$"),
     VBPERMD,
     VADDCUW,
     VPOPCNTW,
     VPOPCNTD,
     VPRTYBD,
     VPRTYBW,
     VSHASIGMAD,
     VSHASIGMAW,
     VSUBSBS,
     VSUBSHS,
     VSUBSWS,
     VSUBUBS,
     VSUBUHS,
     VSUBUWS,
     VSUBCUW,
     VCMPGTSB,
-    VCMPGTSBo,
+    VCMPGTSB_rec,
     VCMPGTSD,
-    VCMPGTSDo,
+    VCMPGTSD_rec,
     VCMPGTSH,
-    VCMPGTSHo,
+    VCMPGTSH_rec,
     VCMPGTSW,
-    VCMPGTSWo,
+    VCMPGTSW_rec,
     VCMPGTUB,
-    VCMPGTUBo,
+    VCMPGTUB_rec,
     VCMPGTUD,
-    VCMPGTUDo,
+    VCMPGTUD_rec,
     VCMPGTUH,
-    VCMPGTUHo,
+    VCMPGTUH_rec,
     VCMPGTUW,
-    VCMPGTUWo,
-    VCMPNEBo,
-    VCMPNEHo,
-    VCMPNEWo,
-    VCMPNEZBo,
-    VCMPNEZHo,
-    VCMPNEZWo,
-    VCMPEQUBo,
-    VCMPEQUDo,
-    VCMPEQUHo,
-    VCMPEQUWo,
+    VCMPGTUW_rec,
+    VCMPNEB_rec,
+    VCMPNEH_rec,
+    VCMPNEW_rec,
+    VCMPNEZB_rec,
+    VCMPNEZH_rec,
+    VCMPNEZW_rec,
+    VCMPEQUB_rec,
+    VCMPEQUD_rec,
+    VCMPEQUH_rec,
+    VCMPEQUW_rec,
     XVCMPEQDP,
-    XVCMPEQDPo,
+    XVCMPEQDP_rec,
     XVCMPEQSP,
-    XVCMPEQSPo,
+    XVCMPEQSP_rec,
     XVCMPGEDP,
-    XVCMPGEDPo,
+    XVCMPGEDP_rec,
     XVCMPGESP,
-    XVCMPGESPo,
+    XVCMPGESP_rec,
     XVCMPGTDP,
-    XVCMPGTDPo,
+    XVCMPGTDP_rec,
     XVCMPGTSP,
-    XVCMPGTSPo,
+    XVCMPGTSP_rec,
     XVMAXDP,
     XVMAXSP,
     XVMINDP,
     XVMINSP,
     XVTDIVDP,
     XVTDIVSP,
     XVTSQRTDP,
     XVTSQRTSP,

 )>;
 
 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
 // These operations can be done in parallel. The DP is restricted so we need a
 // full 4 dispatches.
 def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "FSEL(D|S)o$")
+    (instregex "FSEL(D|S)_rec$")
 )>;
 
 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
 def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "MUL(H|L)(D|W)(U)?(O)?o$")
+    (instregex "MUL(H|L)(D|W)(U)?(O)?_rec$")
 )>;
 
 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
 // These operations must be done sequentially.The DP is restricted so we need a
 // full 4 dispatches.
 def : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "FRI(N|P|Z|M)(D|S)o$"),
-    (instregex "FRE(S)?o$"),
-    (instregex "FADD(S)?o$"),
-    (instregex "FSUB(S)?o$"),
-    (instregex "F(N)?MSUB(S)?o$"),
-    (instregex "F(N)?MADD(S)?o$"),
-    (instregex "FCFID(U)?(S)?o$"),
-    (instregex "FCTID(U)?(Z)?o$"),
-    (instregex "FCTIW(U)?(Z)?o$"),
-    (instregex "FMUL(S)?o$"),
-    (instregex "FRSQRTE(S)?o$"),
-    FRSPo
+    (instregex "FRI(N|P|Z|M)(D|S)_rec$"),
+    (instregex "FRE(S)?_rec$"),
+    (instregex "FADD(S)?_rec$"),
+    (instregex "FSUB(S)?_rec$"),
+    (instregex "F(N)?MSUB(S)?_rec$"),
+    (instregex "F(N)?MADD(S)?_rec$"),
+    (instregex "FCFID(U)?(S)?_rec$"),
+    (instregex "FCTID(U)?(Z)?_rec$"),
+    (instregex "FCTIW(U)?(Z)?_rec$"),
+    (instregex "FMUL(S)?_rec$"),
+    (instregex "FRSQRTE(S)?_rec$"),
+    FRSP_rec
 )>;
 
 // 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
 def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C],
       (instrs
     XSADDDP,
     XSADDSP,
     XSCVDPHP,
def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C],
     VSUBECUQ,
     VSUBEUQM,
     VSUBUQM,
     XSCMPEXPQP,
     XSCMPOQP,
     XSCMPUQP,
     XSTSTDCQP,
     XSXSIGQP,
-    BCDCFNo,
-    BCDCFZo,
-    BCDCPSGNo,
-    BCDCTNo,
-    BCDCTZo,
-    BCDSETSGNo,
-    BCDSo,
-    BCDTRUNCo,
-    BCDUSo,
-    BCDUTRUNCo
+    BCDCFN_rec,
+    BCDCFZ_rec,
+    BCDCPSGN_rec,
+    BCDCTN_rec,
+    BCDCTZ_rec,
+    BCDSETSGN_rec,
+    BCDS_rec,
+    BCDTRUNC_rec,
+    BCDUS_rec,
+    BCDUTRUNC_rec
 )>;
 
 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
 // dispatch.
 def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDSRo,
+    BCDSR_rec,
     XSADDQP,
     XSADDQPO,
     XSCVDPQP,
     XSCVQPDP,
     XSCVQPDPO,
     XSCVQPSDZ,
     XSCVQPSWZ,
     XSCVQPUDZ,
     XSCVQPUWZ,
     XSCVSDQP,
     XSCVUDQP,
     XSRQPI,
     XSRQPIX,
     XSRQPXP,
     XSSUBQP,
     XSSUBQPO
 )>;
 
 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
 // dispatch.
 def : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDCTSQo
+    BCDCTSQ_rec
 )>;
 
 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
 // dispatch.
 def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
     XSMADDQP,
     XSMADDQPO,
     XSMSUBQP,
     XSMSUBQPO,
     XSMULQP,
     XSMULQPO,
     XSNMADDQP,
     XSNMADDQPO,
     XSNMSUBQP,
     XSNMSUBQPO
 )>;
 
 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
 // dispatch.
 def : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDCFSQo
+    BCDCFSQ_rec
 )>;
 
 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
 // superslice. That includes both exec pipelines (EXECO, EXECE) and one
 // dispatch.
 def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
     XSDIVQP,

 
 // Cracked Load instruction.
 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
               DISP_1C, DISP_1C],
       (instrs
     (instregex "LHA(X)?(8)?$"),
-    (instregex "CP_PASTE(8)?o$"),
+    (instregex "CP_PASTE(8)?_rec$"),
     (instregex "LWA(X)?(_32)?$"),
     TCHECK
 )>;
 
 // Cracked Restricted Load instruction.
 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
 // operations cannot be done at the same time and so their latencies are added.
 // Full 6 dispatches are required as this is both cracked and restricted.

 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
 // and one full superslice for the DIV operation since there is only one DIV per
 // superslice. Latency of DIV plus ALU is 26.
 def : InstRW<[P9_IntDivAndALUOp_18C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    (instregex "DIVW(U)?(O)?o$")
+    (instregex "DIVW(U)?(O)?_rec$")
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
 // and one full superslice for the DIV operation since there is only one DIV per
 // superslice. Latency of DIV plus ALU is 26.
 def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    DIVDo,
-    DIVDOo,
-    DIVDUo,
-    DIVDUOo,
-    DIVWEo,
-    DIVWEOo,
-    DIVWEUo,
-    DIVWEUOo
+    DIVD_rec,
+    DIVDO_rec,
+    DIVDU_rec,
+    DIVDUO_rec,
+    DIVWE_rec,
+    DIVWEO_rec,
+    DIVWEU_rec,
+    DIVWEUO_rec
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
 // and one full superslice for the DIV operation since there is only one DIV per
 // superslice. Latency of DIV plus ALU is 42.
 def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    DIVDEo,
-    DIVDEOo,
-    DIVDEUo,
-    DIVDEUOo
+    DIVDE_rec,
+    DIVDEO_rec,
+    DIVDEU_rec,
+    DIVDEUO_rec
 )>;
 
 // CR access instructions in _BrMCR, IIC_BrMCRX.
 
 // Cracked, restricted, ALU operations.
 // Here the two ALU ops can actually be done in parallel and therefore the
 // latencies are not added together. Otherwise this is like having two
 // instructions running together on two pipelines and 6 dispatches. ALU ops are
 // 2 cycles each.
 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
     MTCRF,
     MTCRF8
 )>;
 
 // Cracked ALU operations.
 // Here the two ALU ops can actually be done in parallel and therefore the
 // latencies are not added together. Otherwise this is like having two
 // instructions running together on two pipelines and 2 dispatches. ALU ops are
 // 2 cycles each.
 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C],
       (instrs
-    (instregex "ADDC(8)?(O)?o$"),
-    (instregex "SUBFC(8)?(O)?o$")
+    (instregex "ADDC(8)?(O)?_rec$"),
+    (instregex "SUBFC(8)?(O)?_rec$")
 )>;
 
 // Cracked ALU operations.
 // Two ALU ops can be done in parallel.
 // One is three cycle ALU the ohter is a two cycle ALU.
 // One of the ALU ops is restricted the other is not so we have a total of
 // 5 dispatches.
 def : InstRW<[P9_ALU_2C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "F(N)?ABS(D|S)o$"),
-    (instregex "FCPSGN(D|S)o$"),
-    (instregex "FNEG(D|S)o$"),
-    FMRo
+    (instregex "F(N)?ABS(D|S)_rec$"),
+    (instregex "FCPSGN(D|S)_rec$"),
+    (instregex "FNEG(D|S)_rec$"),
+    FMR_rec
 )>;
 
 // Cracked ALU operations.
 // Here the two ALU ops can actually be done in parallel and therefore the
 // latencies are not added together. Otherwise this is like having two
 // instructions running together on two pipelines and 2 dispatches.
 // ALU ops are 3 cycles each.
 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C],
       (instrs
     MCRFS
 )>;
 
 // Cracked Restricted ALU operations.
 // Here the two ALU ops can actually be done in parallel and therefore the
 // latencies are not added together. Otherwise this is like having two
 // instructions running together on two pipelines and 6 dispatches.
 // ALU ops are 3 cycles each.
 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
-    (instregex "MTFSF(b|o)?$"),
-    (instregex "MTFSFI(o)?$")
+    (instregex "MTFSF(b|_rec)?$"),
+    (instregex "MTFSFI(_rec)?$")
 )>;
 
 // Cracked instruction made of two ALU ops.
 // The two ops cannot be done in parallel.
 // One of the ALU ops is restricted and takes 3 dispatches.
 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "RLD(I)?C(R|L)o$"),
-    (instregex "RLW(IMI|INM|NM)(8)?o$"),
-    (instregex "SLW(8)?o$"),
-    (instregex "SRAW(I)?o$"),
-    (instregex "SRW(8)?o$"),
-    RLDICL_32o,
-    RLDIMIo
+    (instregex "RLD(I)?C(R|L)_rec$"),
+    (instregex "RLW(IMI|INM|NM)(8)?_rec$"),
+    (instregex "SLW(8)?_rec$"),
+    (instregex "SRAW(I)?_rec$"),
+    (instregex "SRW(8)?_rec$"),
+    RLDICL_32_rec,
+    RLDIMI_rec
 )>;
 
 // Cracked instruction made of two ALU ops.
 // The two ops cannot be done in parallel.
 // Both of the ALU ops are restricted and take 3 dispatches.
 def : InstRW<[P9_ALU2OpAndALU2Op_6C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
-    (instregex "MFFS(L|CE|o)?$")
+    (instregex "MFFS(L|CE|_rec)?$")
 )>;
 
 // Cracked ALU instruction composed of three consecutive 2 cycle loads for a
 // total of 6 cycles. All of the ALU operations are also restricted so each
 // takes 3 dispatches for a total of 9.
 def : InstRW<[P9_ALUOpAndALUOpAndALUOp_6C, IP_EXEC_1C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
     (instregex "MFCR(8)?$")
 )>;
 
 // Cracked instruction made of two ALU ops.
 // The two ops cannot be done in parallel.
 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
-    (instregex "EXTSWSLI_32_64o$"),
-    (instregex "SRAD(I)?o$"),
-    EXTSWSLIo,
-    SLDo,
-    SRDo,
-    RLDICo
+    (instregex "EXTSWSLI_32_64_rec$"),
+    (instregex "SRAD(I)?_rec$"),
+    EXTSWSLI_rec,
+    SLD_rec,
+    SRD_rec,
+    RLDIC_rec
 )>;
 
 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_3SLOTS_1C],
       (instrs
     FDIV
 )>;
 
 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
 def : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FDIVo
+    FDIV_rec
 )>;
 
 // 36 Cycle DP Instruction.
 // Instruction can be done on a single slice.
 def : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_1C],
       (instrs
     XSSQRTDP
 )>;
def : InstRW<[P9_DPE_27C_10, P9_DPO_27C_10, IP_EXECE_1C, IP_EXECO_1C,
       (instrs
     XVSQRTSP
 )>;
 
 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
 def : InstRW<[P9_DPOpAndALU2Op_39C_10, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FSQRTo
+    FSQRT_rec
 )>;
 
 // 26 Cycle DP Instruction.
 def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_1C],
       (instrs
     XSSQRTSP
 )>;
 
 // 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
 def : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
       (instrs
     FSQRTS
 )>;
 
 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
 def : InstRW<[P9_DPOpAndALU2Op_29C_5, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FSQRTSo
+    FSQRTS_rec
 )>;
 
 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C],
       (instrs
     XSDIVDP
 )>;
 
 // 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
 def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_3SLOTS_1C],
       (instrs
     FDIVS
 )>;
 
 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
 def : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FDIVSo
+    FDIVS_rec
 )>;
 
 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
 def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C],
       (instrs
     XSDIVSP
 )>;
 
def : InstRW<[],
   (instregex "TLB(IA|IVAX|SX|SX2|SX2D|LD|LI|RE|RE2|WE|WE2)$"),
   (instregex "WRTEE(I)?$"),
   ATTN,
   CLRBHRB,
   MFBHRBE,
   MBAR,
   MSYNC,
   SLBSYNC,
-  SLBFEEo,
+  SLBFEE_rec,
   NAP,
   STOP,
   TRAP,
   RFCI,
   RFDI,
   RFMCI,
   SC,
   DCBA,
   DCBI,
   DCCCI,
   ICCCI
 )> { let Unsupported = 1; }

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

for (ValueRotInfo &VRI : ValueRotsVec) {
         VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
                                               Ops), 0);
       } else {
         VRot = TruncateToInt32(VRI.V, dl);
       }
 
       SDValue ANDIVal, ANDISVal;
       if (ANDIMask != 0)
-        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
-                            VRot, getI32Imm(ANDIMask, dl)), 0);
+        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI_rec, dl, MVT::i32,
+                                                 VRot, getI32Imm(ANDIMask, dl)),
+                          0);
       if (ANDISMask != 0)
-        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
-                             VRot, getI32Imm(ANDISMask, dl)), 0);
+        ANDISVal =
+            SDValue(CurDAG->getMachineNode(PPC::ANDIS_rec, dl, MVT::i32, VRot,
+                                           getI32Imm(ANDISMask, dl)),
+                    0);
 
       SDValue TotalVal;
       if (!ANDIVal)
         TotalVal = ANDISVal;
       else if (!ANDISVal)
         TotalVal = ANDIVal;
       else
         TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
if (LateMask) {
              "No set bits in zeros mask?");
 
       if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
                                (unsigned) (ANDISMask != 0) +
                                (unsigned) (ANDIMask != 0 && ANDISMask != 0);
 
       SDValue ANDIVal, ANDISVal;
       if (ANDIMask != 0)
-        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
-                            Res, getI32Imm(ANDIMask, dl)), 0);
+        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI_rec, dl, MVT::i32,
+                                                 Res, getI32Imm(ANDIMask, dl)),
+                          0);
       if (ANDISMask != 0)
-        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
-                             Res, getI32Imm(ANDISMask, dl)), 0);
+        ANDISVal =
+            SDValue(CurDAG->getMachineNode(PPC::ANDIS_rec, dl, MVT::i32, Res,
+                                           getI32Imm(ANDISMask, dl)),
+                    0);
 
       if (!ANDIVal)
         Res = ANDISVal;
       else if (!ANDISVal)
         Res = ANDIVal;
       else
         Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
                         ANDIVal, ANDISVal), 0);
for (ValueRotInfo &VRI : ValueRotsVec) {
 
       SDValue TotalVal;
       if (Use32BitInsts) {
         assert((ANDIMask != 0 || ANDISMask != 0) &&
                "No set bits in mask when using 32-bit ands for 64-bit value");
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8_rec, dl, MVT::i64,
                                                    ExtendToInt64(VRot, dl),
                                                    getI32Imm(ANDIMask, dl)),
                             0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
-                                                    ExtendToInt64(VRot, dl),
-                                                    getI32Imm(ANDISMask, dl)),
-                             0);
+          ANDISVal =
+              SDValue(CurDAG->getMachineNode(PPC::ANDIS8_rec, dl, MVT::i64,
 
         if (!ANDIVal)
           TotalVal = ANDISVal;
         else if (!ANDISVal)
           TotalVal = ANDIVal;
         else
           TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
                                ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
if (LateMask) {
                "No set bits in mask when using 32-bit ands for 64-bit value");
 
         if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
                                  (unsigned) (ANDISMask != 0) +
                                  (unsigned) (ANDIMask != 0 && ANDISMask != 0);
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
-                              ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8_rec, dl, MVT::i64,
+                                                   ExtendToInt64(Res, dl),
+                                                   getI32Imm(ANDIMask, dl)),
+                            0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
-                               ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
+          ANDISVal =
+              SDValue(CurDAG->getMachineNode(PPC::ANDIS8_rec, dl, MVT::i64,
+                                             ExtendToInt64(Res, dl),
+                                             getI32Imm(ANDISMask, dl)),
+                      0);
 
         if (!ANDIVal)
           Res = ANDISVal;
         else if (!ANDISVal)
           Res = ANDIVal;
         else
           Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
                           ExtendToInt64(ANDIVal, dl), ANDISVal), 0);
if (NewOpc != -1 && IsBitwiseNegate) {
     WideOp =
       SDValue(CurDAG->getMachineNode(NewOpc, dl,
                                      OpToConvToRecForm.getValueType(),
                                      MVT::Glue, Ops), 0);
   } else {
     assert((NewOpc != -1 || !IsBitwiseNegate) &&
            "No record form available for AND8/OR8/XOR8?");
     WideOp =
-      SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8o : NewOpc, dl,
-                                     MVT::i64, MVT::Glue, LHS, RHS), 0);
+        SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8_rec : NewOpc,
+                                       dl, MVT::i64, MVT::Glue, LHS, RHS),
+                0);
   }
 
   // Select this node to a single bit from CR0 set by the record-form node
   // just created. For bitwise negation, use the EQ bit which is the equivalent
   // of negating the result (i.e. it is a bit set when the result of the
   // operation is zero).
   SDValue SRIdxVal =
     CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
       CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
       return;
     }
 
     // Other cases are autogenerated.
     break;
   }
   // FIXME: Remove this once the ANDI glue bug is fixed:
-  case PPCISD::ANDIo_1_EQ_BIT:
-  case PPCISD::ANDIo_1_GT_BIT: {
+  case PPCISD::ANDI_rec_1_EQ_BIT:
+  case PPCISD::ANDI_rec_1_GT_BIT: {
     if (!ANDIGlueBug)
       break;
 
     EVT InVT = N->getOperand(0).getValueType();
     assert((InVT == MVT::i64 || InVT == MVT::i32) &&
-           "Invalid input type for ANDIo_1_EQ_BIT");
+           "Invalid input type for ANDI_rec_1_EQ_BIT");
 
-    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8o : PPC::ANDIo;
+    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec;
     SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
                                         N->getOperand(0),
                                         CurDAG->getTargetConstant(1, dl, InVT)),
                  0);
     SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
-    SDValue SRIdxVal =
-      CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
-                                PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
+    SDValue SRIdxVal = CurDAG->getTargetConstant(
+        N->getOpcode() == PPCISD::ANDI_rec_1_EQ_BIT ? PPC::sub_eq : PPC::sub_gt,
+        dl, MVT::i32);
 
     CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
                          SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
     return;
   }
   case ISD::SELECT_CC: {
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
     EVT PtrVT =
if (Op1OK)
       ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
 
     return true;
   }
 
   // For ANDI and ANDIS, the higher-order bits are zero if either that is true
   // of the first operand, or if the second operand is positive (so that it is
   // not sign extended).
-  if (Op32.getMachineOpcode() == PPC::ANDIo ||
-      Op32.getMachineOpcode() == PPC::ANDISo) {
+  if (Op32.getMachineOpcode() == PPC::ANDI_rec ||
+      Op32.getMachineOpcode() == PPC::ANDIS_rec) {
     SmallPtrSet<SDNode *, 16> ToPromote1;
     bool Op0OK =
       PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
     bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
     if (!Op0OK && !Op1OK)
       return false;
 
     ToPromote.insert(Op32.getNode());
for (SDNode *PN : ToPromote) {
       case PPC::CNTLZW:    NewOpcode = PPC::CNTLZW8; break;
       case PPC::CNTTZW:    NewOpcode = PPC::CNTTZW8; break;
       case PPC::RLWIMI:    NewOpcode = PPC::RLWIMI8; break;
       case PPC::OR:        NewOpcode = PPC::OR8; break;
       case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
       case PPC::ORI:       NewOpcode = PPC::ORI8; break;
       case PPC::ORIS:      NewOpcode = PPC::ORIS8; break;
       case PPC::AND:       NewOpcode = PPC::AND8; break;
-      case PPC::ANDIo:     NewOpcode = PPC::ANDI8o; break;
-      case PPC::ANDISo:    NewOpcode = PPC::ANDIS8o; break;
+      case PPC::ANDI_rec:
+        NewOpcode = PPC::ANDI8_rec;
+        break;
+      case PPC::ANDIS_rec:
+        NewOpcode = PPC::ANDIS8_rec;
+        break;
       }
 
       // Note: During the replacement process, the nodes will be in an
       // inconsistent state (some instructions will have operands with values
       // of the wrong type). Once done, however, everything should be right
       // again.
 
       SmallVector<SDValue, 4> Ops;

llvm/lib/Target/PowerPC/PPCISelLowering.h

namespace PPCISD {
     // When adding a NEW PPCISD node please add it to the correct position in
     // the enum. The order of elements in this enum matters!
     // Values that are added after this entry:
     //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
     // are considered memory opcodes and are treated differently than entries
     // that come before it. For example, ADD or MUL should be placed before
     // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
     // after it.
-    enum NodeType : unsigned {
-      // Start the numbering where the builtin ops and target ops leave off.
-      FIRST_NUMBER = ISD::BUILTIN_OP_END,
 
-      /// FSEL - Traditional three-operand fsel node.
-      ///
-      FSEL,
 
-      /// XSMAXCDP, XSMINCDP - C-type min/max instructions.
-      XSMAXCDP, XSMINCDP,
+    XSMAXCDP,
+    XSMINCDP,
 
-      /// FCFID - The FCFID instruction, taking an f64 operand and producing
-      /// and f64 value containing the FP representation of the integer that
-      /// was temporarily in the f64 operand.
-      FCFID,
 
-      /// Newer FCFID[US] integer-to-floating-point conversion instructions for
-      /// unsigned integers and single-precision outputs.
-      FCFIDU, FCFIDS, FCFIDUS,
+    FCFIDU,
+    FCFIDS,
+    FCFIDUS,
 
-      /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
-      /// operand, producing an f64 value containing the integer representation
-      /// of that FP value.
-      FCTIDZ, FCTIWZ,
+    FCTIDZ,
+    FCTIWZ,
 
-      /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
-      /// unsigned integers with round toward zero.
-      FCTIDUZ, FCTIWUZ,
+    FCTIDUZ,
+    FCTIWUZ,
 
-      /// Floating-point-to-interger conversion instructions
-      FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
+    FP_TO_UINT_IN_VSR,
+    FP_TO_SINT_IN_VSR,
 
-      /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
-      /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
-      VEXTS,
 
-      /// SExtVElems, takes an input vector of a smaller type and sign
-      /// extends to an output vector of a larger type.
-      SExtVElems,
 
-      /// Reciprocal estimate instructions (unary FP ops).
-      FRE, FRSQRTE,
+    FRE,
+    FRSQRTE,
 
-      // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
-      // three v4f32 operands and producing a v4f32 result.
-      VMADDFP, VNMSUBFP,
+    VMADDFP,
+    VNMSUBFP,
 
-      /// VPERM - The PPC VPERM Instruction.
-      ///
-      VPERM,
 
-      /// XXSPLT - The PPC VSX splat instructions
-      ///
-      XXSPLT,
 
-      /// VECINSERT - The PPC vector insert instruction
-      ///
-      VECINSERT,
 
-      /// VECSHL - The PPC vector shift left instruction
-      ///
-      VECSHL,
 
-      /// XXPERMDI - The PPC XXPERMDI instruction
-      ///
-      XXPERMDI,
 
-      /// The CMPB instruction (takes two operands of i32 or i64).
-      CMPB,
 
-      /// Hi/Lo - These represent the high and low 16-bit parts of a global
-      /// address respectively.  These nodes have two operands, the first of
-      /// which must be a TargetGlobalAddress, and the second of which must be a
-      /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
-      /// though these are usually folded into other nodes.
-      Hi, Lo,
+    Hi,
+    Lo,
 
-      /// The following two target-specific nodes are used for calls through
-      /// function pointers in the 64-bit SVR4 ABI.
 
-      /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
-      /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
-      /// compute an allocation on the stack.
-      DYNALLOC,
 
-      /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
-      /// compute an offset from native SP to the address  of the most recent
-      /// dynamic alloca.
-      DYNAREAOFFSET,
 
-      /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
-      /// at function entry, used for PIC code.
-      GlobalBaseReg,
 
-      /// These nodes represent PPC shifts.
-      ///
-      /// For scalar types, only the last `n + 1` bits of the shift amounts
-      /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
-      /// for exact behaviors.
-      ///
-      /// For vector types, only the last n bits are used. See vsld.
-      SRL, SRA, SHL,
+    SRL,
+    SRA,
+    SHL,
 
-      /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
-      /// word and shift left immediate.
-      EXTSWSLI,
 
-      /// The combination of sra[wd]i and addze used to implemented signed
-      /// integer division by a power of 2. The first operand is the dividend,
-      /// and the second is the constant shift amount (representing the
-      /// divisor).
-      SRA_ADDZE,
 
-      /// CALL - A direct function call.
-      /// CALL_NOP is a call with the special NOP which follows 64-bit
-      /// SVR4 calls and 32-bit/64-bit AIX calls.
-      CALL, CALL_NOP,
+    CALL,
+    CALL_NOP,
 
-      /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
-      /// MTCTR instruction.
-      MTCTR,
 
-      /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
-      /// BCTRL instruction.
-      BCTRL,
 
-      /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
-      /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
-      /// and 64-bit AIX.
-      BCTRL_LOAD_TOC,
 
-      /// Return with a flag operand, matched by 'blr'
-      RET_FLAG,
 
-      /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
-      /// This copies the bits corresponding to the specified CRREG into the
-      /// resultant GPR.  Bits corresponding to other CR regs are undefined.
-      MFOCRF,
 
-      /// Direct move from a VSX register to a GPR
-      MFVSR,
 
-      /// Direct move from a GPR to a VSX register (algebraic)
-      MTVSRA,
 
-      /// Direct move from a GPR to a VSX register (zero)
-      MTVSRZ,
 
-      /// Direct move of 2 consecutive GPR to a VSX register.
-      BUILD_FP128,
 
-      /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
-      /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
-      /// unsupported for this target.
-      /// Merge 2 GPRs to a single SPE register.
-      BUILD_SPE64,
 
-      /// Extract SPE register component, second argument is high or low.
-      EXTRACT_SPE,
 
-      /// Extract a subvector from signed integer vector and convert to FP.
-      /// It is primarily used to convert a (widened) illegal integer vector
-      /// type to a legal floating point vector type.
-      /// For example v2i32 -> widened to v4i32 -> v2f64
-      SINT_VEC_TO_FP,
 
-      /// Extract a subvector from unsigned integer vector and convert to FP.
-      /// As with SINT_VEC_TO_FP, used for converting illegal types.
-      UINT_VEC_TO_FP,
 
-      // FIXME: Remove these once the ANDI glue bug is fixed:
-      /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
-      /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
-      /// implement truncation of i32 or i64 to i1.
-      ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
+    /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
+    ANDI_rec_1_EQ_BIT,
+    ANDI_rec_1_GT_BIT,
 
-      // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
-      // target (returns (Lo, Hi)). It takes a chain operand.
-      READ_TIME_BASE,
 
-      // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
-      EH_SJLJ_SETJMP,
 
-      // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
-      EH_SJLJ_LONGJMP,
 
-      /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
-      /// instructions.  For lack of better number, we use the opcode number
-      /// encoding for the OPC field to identify the compare.  For example, 838
-      /// is VCMPGTSH.
-      VCMP,
 
-      /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
-      /// altivec VCMP*o instructions.  For lack of better number, we use the
-      /// opcode number encoding for the OPC field to identify the compare.  For
-      /// example, 838 is VCMPGTSH.
-      VCMPo,
 
-      /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
-      /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
-      /// condition register to branch on, OPC is the branch opcode to use (e.g.
-      /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
-      /// an optional input flag argument.
-      COND_BRANCH,
 
-      /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
-      /// loops.
-      BDNZ, BDZ,
+    BDNZ,
+    BDZ,
 
-      /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
-      /// towards zero.  Used only as part of the long double-to-int
-      /// conversion sequence.
-      FADDRTZ,
 
-      /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
-      MFFS,
 
-      /// TC_RETURN - A tail call return.
-      ///   operand #0 chain
-      ///   operand #1 callee (register or absolute)
-      ///   operand #2 stack adjustment
-      ///   operand #3 optional in flag
-      TC_RETURN,
 
-      /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
-      CR6SET,
-      CR6UNSET,
 
-      /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
-      /// for non-position independent code on PPC32.
-      PPC32_GOT,
 
-      /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
-      /// local dynamic TLS and position indendepent code on PPC32.
-      PPC32_PICGOT,
 
-      /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
-      /// TLS model, produces an ADDIS8 instruction that adds the GOT
-      /// base to sym\@got\@tprel\@ha.
-      ADDIS_GOT_TPREL_HA,
 
-      /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
-      /// TLS model, produces a LD instruction with base register G8RReg
-      /// and offset sym\@got\@tprel\@l.  This completes the addition that
-      /// finds the offset of "sym" relative to the thread pointer.
-      LD_GOT_TPREL_L,
 
-      /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
-      /// model, produces an ADD instruction that adds the contents of
-      /// G8RReg to the thread pointer.  Symbol contains a relocation
-      /// sym\@tls which is to be replaced by the thread pointer and
-      /// identifies to the linker that the instruction is part of a
-      /// TLS sequence.
-      ADD_TLS,
 
-      /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
-      /// model, produces an ADDIS8 instruction that adds the GOT base
-      /// register to sym\@got\@tlsgd\@ha.
-      ADDIS_TLSGD_HA,
 
-      /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
-      /// model, produces an ADDI8 instruction that adds G8RReg to
-      /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
-      /// ADDIS_TLSGD_L_ADDR until after register assignment.
-      ADDI_TLSGD_L,
 
-      /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
-      /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
-      /// ADDIS_TLSGD_L_ADDR until after register assignment.
-      GET_TLS_ADDR,
 
-      /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
-      /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
-      /// register assignment.
-      ADDI_TLSGD_L_ADDR,
 
-      /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
-      /// model, produces an ADDIS8 instruction that adds the GOT base
-      /// register to sym\@got\@tlsld\@ha.
-      ADDIS_TLSLD_HA,
 
-      /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
-      /// model, produces an ADDI8 instruction that adds G8RReg to
-      /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
-      /// ADDIS_TLSLD_L_ADDR until after register assignment.
-      ADDI_TLSLD_L,
 
-      /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
-      /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
-      /// ADDIS_TLSLD_L_ADDR until after register assignment.
-      GET_TLSLD_ADDR,
 
-      /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
-      /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
-      /// following register assignment.
-      ADDI_TLSLD_L_ADDR,
 
-      /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
-      /// model, produces an ADDIS8 instruction that adds X3 to
-      /// sym\@dtprel\@ha.
-      ADDIS_DTPREL_HA,
 
-      /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
-      /// model, produces an ADDI8 instruction that adds G8RReg to
-      /// sym\@got\@dtprel\@l.
-      ADDI_DTPREL_L,
 
-      /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
-      /// during instruction selection to optimize a BUILD_VECTOR into
-      /// operations on splats.  This is necessary to avoid losing these
-      /// optimizations due to constant folding.
-      VADD_SPLAT,
 
-      /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
-      /// operand identifies the operating system entry point.
-      SC,
 
-      /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
-      CLRBHRB,
 
-      /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
-      /// history rolling buffer entry.
-      MFBHRBE,
 
-      /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
-      RFEBB,
 
-      /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
-      /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
-      /// or stxvd2x instruction.  The chain is necessary because the
-      /// sequence replaces a load and needs to provide the same number
-      /// of outputs.
-      XXSWAPD,
 
-      /// An SDNode for swaps that are not associated with any loads/stores
-      /// and thereby have no chain.
-      SWAP_NO_CHAIN,
-      
-      /// An SDNode for Power9 vector absolute value difference.
-      /// operand #0 vector
-      /// operand #1 vector
-      /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
-      /// the most significant bit for signed i32
-      ///
-      /// Power9 VABSD* instructions are designed to support unsigned integer
-      /// vectors (byte/halfword/word), if we want to make use of them for signed
-      /// integer vectors, we have to flip their sign bits first. To flip sign bit
-      /// for byte/halfword integer vector would become inefficient, but for word
-      /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
-      /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 
-      ///               => VABSDUW((XVNEGSP a), (XVNEGSP b))
-      VABSD,
+    /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
 
-      /// QVFPERM = This corresponds to the QPX qvfperm instruction.
-      QVFPERM,
 
-      /// QVGPCI = This corresponds to the QPX qvgpci instruction.
-      QVGPCI,
 
-      /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
-      QVALIGNI,
 
-      /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
-      QVESPLATI,
 
-      /// QBFLT = Access the underlying QPX floating-point boolean
-      /// representation.
-      QBFLT,
 
-      /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
-      /// lower (IDX=1) half of v4f32 to v2f64.
-      FP_EXTEND_HALF,
 
-      /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
-      /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
-      /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
-      /// i32.
-      STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 
-      /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
-      /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
-      /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
-      /// or i32.
-      LBRX,
 
-      /// STFIWX - The STFIWX instruction.  The first operand is an input token
-      /// chain, then an f64 value to store, then an address to store it to.
-      STFIWX,
 
-      /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
-      /// load which sign-extends from a 32-bit integer value into the
-      /// destination 64-bit register.
-      LFIWAX,
 
-      /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
-      /// load which zero-extends from a 32-bit integer value into the
-      /// destination 64-bit register.
-      LFIWZX,
 
-      /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
-      /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
-      /// This can be used for converting loaded integers to floating point.
-      LXSIZX,
 
-      /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
-      /// chain, then an f64 value to store, then an address to store it to,
-      /// followed by a byte-width for the store.
-      STXSIX,
 
-      /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
-      /// Maps directly to an lxvd2x instruction that will be followed by
-      /// an xxswapd.
-      LXVD2X,
 
-      /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
-      /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
-      /// the vector type to load vector in big-endian element order.
-      LOAD_VEC_BE,
 
-      /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
-      /// v2f32 value into the lower half of a VSR register.
-      LD_VSX_LH,
 
-      /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
-      /// instructions such as LXVDSX, LXVWSX.
-      LD_SPLAT,
 
-      /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
-      /// Maps directly to an stxvd2x instruction that will be preceded by
-      /// an xxswapd.
-      STXVD2X,
 
-      /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
-      /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
-      /// the vector type to store vector in big-endian element order.
-      STORE_VEC_BE,
 
-      /// Store scalar integers from VSR.
-      ST_VSR_SCAL_INT,
 
-      /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
-      /// The 4xf32 load used for v4i1 constants.
-      QVLFSb,
 
-      /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
-      /// except they ensure that the compare input is zero-extended for
-      /// sub-word versions because the atomic loads zero-extend.
-      ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
+    ATOMIC_CMP_SWAP_8,
+    ATOMIC_CMP_SWAP_16,
 
-      /// GPRC = TOC_ENTRY GA, TOC
-      /// Loads the entry for GA from the TOC, where the TOC base is given by
-      /// the last operand.
-      TOC_ENTRY
-    };
 
   } // end namespace PPCISD
 
   /// Define some predicates that are used for node matching.
   namespace PPC {
 
     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
     /// VPKUHUM instruction.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::EH_SJLJ_SETJMP:  return "PPCISD::EH_SJLJ_SETJMP";
   case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
   case PPCISD::MFOCRF:          return "PPCISD::MFOCRF";
   case PPCISD::MFVSR:           return "PPCISD::MFVSR";
   case PPCISD::MTVSRA:          return "PPCISD::MTVSRA";
   case PPCISD::MTVSRZ:          return "PPCISD::MTVSRZ";
   case PPCISD::SINT_VEC_TO_FP:  return "PPCISD::SINT_VEC_TO_FP";
   case PPCISD::UINT_VEC_TO_FP:  return "PPCISD::UINT_VEC_TO_FP";
-  case PPCISD::ANDIo_1_EQ_BIT:  return "PPCISD::ANDIo_1_EQ_BIT";
-  case PPCISD::ANDIo_1_GT_BIT:  return "PPCISD::ANDIo_1_GT_BIT";
+  case PPCISD::ANDI_rec_1_EQ_BIT:
+    return "PPCISD::ANDI_rec_1_EQ_BIT";
+  case PPCISD::ANDI_rec_1_GT_BIT:
+    return "PPCISD::ANDI_rec_1_GT_BIT";
   case PPCISD::VCMP:            return "PPCISD::VCMP";
   case PPCISD::VCMPo:           return "PPCISD::VCMPo";
   case PPCISD::LBRX:            return "PPCISD::LBRX";
   case PPCISD::STBRX:           return "PPCISD::STBRX";
   case PPCISD::LFIWAX:          return "PPCISD::LFIWAX";
   case PPCISD::LFIWZX:          return "PPCISD::LFIWZX";
   case PPCISD::LXSIZX:          return "PPCISD::LXSIZX";
   case PPCISD::STXSIX:          return "PPCISD::STXSIX";

 }
 
 // FIXME: Remove this once the ANDI glue bug is fixed:
 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
   assert(Op.getValueType() == MVT::i1 &&
          "Custom lowering only for i1 results");
 
   SDLoc DL(Op);
-  return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
-                     Op.getOperand(0));
+  return DAG.getNode(PPCISD::ANDI_rec_1_GT_BIT, DL, MVT::i1, Op.getOperand(0));
 }
 
 SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
                                                SelectionDAG &DAG) const {
 
   // Implements a vector truncate that fits in a vector register as a shuffle.
   // We want to legalize vector truncates down to where the source fits in
   // a vector register (and target is therefore smaller than vector register
   // size).  At that point legalization will try to custom lower the sub-legal
   // result and get here - where we can contain the truncate as a single target
   // operation.
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
 
     // Perform addition.
     BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
 
     // Restore FPSCR value.
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
-  } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
-             MI.getOpcode() == PPC::ANDIo_1_GT_BIT ||
-             MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
-             MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
-    unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
-                       MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
-                          ? PPC::ANDI8o
-                          : PPC::ANDIo;
-    bool IsEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
-                 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
+  } else if (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
+             MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT ||
+             MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
+             MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8) {
+    unsigned Opcode = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
+                       MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8)
+                          ? PPC::ANDI8_rec
+                          : PPC::ANDI_rec;
+    bool IsEQ = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
+                 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     Register Dest = RegInfo.createVirtualRegister(
-        Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
+        Opcode == PPC::ANDI_rec ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
 
     DebugLoc Dl = MI.getDebugLoc();
     BuildMI(*BB, MI, Dl, TII->get(Opcode), Dest)
         .addReg(MI.getOperand(1).getReg())
         .addImm(1);
     BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
             MI.getOperand(0).getReg())
         .addReg(IsEQ ? PPC::CR0EQ : PPC::CR0GT);

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 // Instructions to support atomic operations
 let mayLoad = 1, hasSideEffects = 0 in {
 def LDARX : XForm_1_memOp<31,  84, (outs g8rc:$rD), (ins memrr:$ptr),
                           "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
 
 // Instruction to support lock versions of atomics
 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
 def LDARXL : XForm_1<31,  84, (outs g8rc:$rD), (ins memrr:$ptr),
-                     "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
+                     "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm;
 
 let hasExtraDefRegAllocReq = 1 in
 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
                          "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64,
            Requires<[IsISA3_0]>;
 }
 
 let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
 def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
-                          "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
+                          "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm;
 
 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
                           "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
             Requires<[IsISA3_0]>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      "xor", "$rA, $rS, $rB", IIC_IntSimple,
                      [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
 } // let isCommutable = 1
 
 // Logical ops with immediate.
 let Defs = [CR0] in {
-def ANDI8o  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+def ANDI8_rec  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "andi. $dst, $src1, $src2", IIC_IntGeneral,
                       [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
-                      isDOT;
-def ANDIS8o : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+                      isRecordForm;
+def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                      "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
-                     isDOT;
+                     isRecordForm;
 }
 def ORI8    : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "ori $dst, $src1, $src2", IIC_IntSimple,
                       [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
 def ORIS8   : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "oris $dst, $src1, $src2", IIC_IntSimple,
                     [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
 def XORI8   : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),

 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
                    InstrItinClass itin, list<dag> pattern>
   : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
                  !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_L1_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8  : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
-def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
+def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
 }
 
 // SLB Invalidate Entry Global
 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
                       "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
               IIC_VecFPCompare,
               [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
   let Defs = [CR6];
   let RC = 1;
 }
 
 // f32 element comparisons.0
 def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
-def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
+def VCMPBFP_rec  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
 def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
-def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
+def VCMPEQFP_rec : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
 def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
-def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
+def VCMPGEFP_rec : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
 def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
-def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
+def VCMPGTFP_rec : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
 
 // i8 element comparisons.
 def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
-def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
+def VCMPEQUB_rec : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
 def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
-def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
+def VCMPGTSB_rec : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
 def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
-def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
+def VCMPGTUB_rec : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
 def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
-def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
+def VCMPEQUH_rec : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
 def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
-def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
+def VCMPGTSH_rec : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
 def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
-def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
+def VCMPGTUH_rec : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
 
 // i32 element comparisons.
 def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
-def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
+def VCMPEQUW_rec : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
 def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
-def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
+def VCMPGTSW_rec : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
 def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
-def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
+def VCMPGTUW_rec : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
 
 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
     isReMaterializable = 1 in {
 
 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
                       "vxor $vD, $vD, $vD", IIC_VecFP,
                       [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),

 
 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                       "vorc $vD, $vA, $vB", IIC_VecGeneral,
                       [(set v4i32:$vD, (or v4i32:$vA,
                                            (vnot_ppc v4i32:$vB)))]>;
 
 // i64 element comparisons.
 def VCMPEQUD  : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
-def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
+def VCMPEQUD_rec : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
 def VCMPGTSD  : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
-def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
+def VCMPGTSD_rec : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
 def VCMPGTUD  : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
-def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
+def VCMPGTUD_rec : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
 
 // The cryptography instructions that do not require Category:Vector.Crypto
 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
                          int_ppc_altivec_crypto_vpmsumb, v16i8>;
 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
                          int_ppc_altivec_crypto_vpmsumh, v8i16>;
 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
                          int_ppc_altivec_crypto_vpmsumw, v4i32>;

 } // HasP8Crypto
 
 // The following altivec instructions were introduced in Power ISA 3.0
 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
 let Predicates = [HasP9Altivec] in {
 
 // i8 element comparisons.
 def VCMPNEB   : VCMP   <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
-def VCMPNEBo  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
+def VCMPNEB_rec  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
 def VCMPNEZB  : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
-def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
+def VCMPNEZB_rec : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
 def VCMPNEH   : VCMP < 71, "vcmpneh $vD, $vA, $vB"  , v8i16>;
-def VCMPNEHo  : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
+def VCMPNEH_rec  : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
 def VCMPNEZH  : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
-def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
+def VCMPNEZH_rec : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
 
 // i32 element comparisons.
 def VCMPNEW   : VCMP <135, "vcmpnew $vD, $vA, $vB"  , v4i32>;
-def VCMPNEWo  : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
+def VCMPNEW_rec  : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
 def VCMPNEZW  : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
-def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
+def VCMPNEZW_rec : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
 
 // VX-Form: [PO VRT / UIM VRB XO].
 // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
 // "/ UIM" (1 + 4 bit)
 class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
   : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
              !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
 
class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
                            list<dag> pattern>
   : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
                            !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
   let Defs = [CR6];
   let PS = 0;
 }
 
 // Decimal Convert From/to National/Zoned/Signed-QWord
-def BCDCFNo  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
-def BCDCFZo  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
-def BCDCTNo  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
-def BCDCTZo  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
-def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
-def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
+def BCDCFN_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
+def BCDCFZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
+def BCDCTN_rec  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
+def BCDCTZ_rec  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
+def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
+def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
 
 // Decimal Copy-Sign/Set-Sign
 let Defs = [CR6] in
-def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
+def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
 
-def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
+def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
 
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
 class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo,
                    (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
                    !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
   let Defs = [CR6];
 }
 
 // [PO VRT VRA VRB 1 / XO]
 class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
   let Defs = [CR6];
   let PS = 0;
 }
 
 // Decimal Shift/Unsigned-Shift/Shift-and-Round
-def BCDSo :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
-def BCDUSo : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
-def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
+def BCDS_rec :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
+def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
+def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
 
 // Decimal (Unsigned) Truncate
-def BCDTRUNCo :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
-def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
+def BCDTRUNC_rec :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
+def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
 
 // Absolute Difference
 def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                        "vabsdub $vD, $vA, $vB", IIC_VecGeneral,
                        [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>;
 def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                        "vabsduh $vD, $vA, $vB", IIC_VecGeneral,
                        [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>;
 def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                        "vabsduw $vD, $vA, $vB", IIC_VecGeneral,
                        [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>;
 
 } // end HasP9Altivec

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
   let Inst{16-31} = C;
 }
 
 
 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
 
-  // Even though ADDICo does not really have an RC bit, provide
-  // the declaration of one here so that isDOT has something to set.
+  // Even though ADDIC_rec does not really have an RC bit, provide
+  // the declaration of one here so that isRecordForm has something to set.
   bit RC = 0;
 }
 
 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                  InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5>  A;
   bits<16> B;
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                       InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RST;
   bits<5> A;
   bits<5> B;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RST;
   let Inst{11-15} = A;
   let Inst{16-20} = B;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 

 class XForm_base_r3xo_swapped
         <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
         InstrItinClass itin> 
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> A;
   bits<5> RST;
   bits<5> B;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RST;
   let Inst{11-15} = A;
   let Inst{16-20} = B;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 

 
 // This is used for MFFS, MTFSB0, MTFSB1.  42 is arbitrary; this series of
 // numbers presumably relates to some document, but I haven't found it.
 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RST;
   let Inst{11-20} = 0;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let Pattern = pattern;
   bits<5> FM;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = FM;
   let Inst{11-20} = 0;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
 class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
   let Inst{31}    = RC;
 }
 
 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bit L;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{7-9}   = 0;
   let Inst{10}    = L;
   let Inst{11-20} = 0;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<6> XA;
   bits<6> XB;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = XT{4-0};
   let Inst{11-15} = XA{4-0};
   let Inst{16-20} = XB{4-0};
   let Inst{21}    = RC;
   let Inst{22-28} = xo;
   let Inst{29}    = XA{5};
   let Inst{30}    = XB{5};

 // This is probably 1.7.9, but I don't have the reference that uses this
 // numbering scheme...
 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag>pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<8> FM;
   bits<5> rT;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
   let Pattern = pattern;
 
   let Inst{6} = 0;
   let Inst{7-14}  = FM;
   let Inst{15} = 0;
   let Inst{16-20} = rT;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                 InstrItinClass itin, list<dag>pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bit L;
   bits<8> FLM;
   bit W;
   bits<5> FRB;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
   let Pattern = pattern;
 
   let Inst{6}     = L;
   let Inst{7-14}  = FLM;
   let Inst{15}    = W;
   let Inst{16-20} = FRB;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
 // 1.7.10 XS-Form - SRADI.
 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> A;
   bits<5> RS;
   bits<6> SH;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
   let Pattern = pattern;
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = A;
   let Inst{16-20} = SH{4,3,2,1,0};
   let Inst{21-29} = xo;
   let Inst{30}    = SH{5};
   let Inst{31}    = RC;
 }
 
 // 1.7.11 XO-Form
 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RT;
   bits<5> RA;
   bits<5> RB;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RT;
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21}    = oe;
   let Inst{22-30} = xo;
   let Inst{31}    = RC;  
 }
class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRT;
   bits<5> FRA;
   bits<5> FRC;
   bits<5> FRB;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = FRT;
   let Inst{11-15} = FRA;
   let Inst{16-20} = FRB;
   let Inst{21-25} = FRC;
   let Inst{26-30} = xo;
   let Inst{31}    = RC;
 }
class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
   bits<5> RA;
   bits<5> RS;
   bits<5> RB;
   bits<5> MB;
   bits<5> ME;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-25} = MB;
   let Inst{26-30} = ME;
   let Inst{31}    = RC;
 }
class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
     : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RA;
   bits<5> RS;
   bits<6> SH;
   bits<6> MBE;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = RA;
   let Inst{16-20} = SH{4,3,2,1,0};
   let Inst{21-26} = MBE{4,3,2,1,0,5};
   let Inst{27-29} = xo;
   let Inst{30}    = SH{5};
   let Inst{31}    = RC;
 }
 
 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
                 InstrItinClass itin, list<dag> pattern>
     : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RA;
   bits<5> RS;
   bits<5> RB;
   bits<6> MBE;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RS;
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-26} = MBE{4,3,2,1,0,5};
   let Inst{27-30} = xo;
   let Inst{31}    = RC;
 }
class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRT;
   bits<5> FRA;
   bits<5> FRB;
   bits<2> idx;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = FRT;
   let Inst{11-15} = FRA;
   let Inst{16-20} = FRB;
   let Inst{21-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;
 }
 
 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let FRB = 0;
 }
 
 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRT;
   bits<12> idx;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = FRT;
   let Inst{11-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;
 }
 
 class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> VRT;
   bit R;
   bits<5> VRB;
   bits<2> idx;
 
   let Pattern = pattern;
 
-  bit RC = 0;    // set by isDOT
+  bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = VRT;
   let Inst{11-14} = 0;
   let Inst{15} = R;
   let Inst{16-20} = VRB;
   let Inst{21-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;

llvm/lib/Target/PowerPC/PPCInstrHTM.td

 def TBEGIN : XForm_htm0 <31, 654,
                          (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
 
 def TEND : XForm_htm1 <31, 686,
                        (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
 
 def TABORT : XForm_base_r3xo <31, 910,
                               (outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
-                              []>, isDOT {
+                              []>, isRecordForm {
   let RST = 0;
   let B = 0;
 }
 
 def TABORTWC : XForm_base_r3xo <31, 782,
                                 (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
                                 "tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>,
-                                isDOT;
+                                isRecordForm;
 
 def TABORTWCI : XForm_base_r3xo <31, 846,
                                  (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
                                  "tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>,
-                                 isDOT;
+                                 isRecordForm;
 
 def TABORTDC : XForm_base_r3xo <31, 814,
                                 (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B),
                                 "tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>,
-                                isDOT;
+                                isRecordForm;
 
 def TABORTDCI : XForm_base_r3xo <31, 878,
                                  (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
                                  "tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>,
-                                 isDOT;
+                                 isRecordForm;
 
 def TSR : XForm_htm2 <31, 750,
                       (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
-                      isDOT;
+                      isRecordForm;
 
 def TRECLAIM : XForm_base_r3xo <31, 942,
                                 (outs), (ins gprc:$A), "treclaim. $A",
                                 IIC_SprMTSPR, []>,
-                                isDOT {
+                                isRecordForm {
   let RST = 0;
   let B = 0;
 }
 
 def TRECHKPT : XForm_base_r3xo <31, 1006,
                                 (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,
-                                isDOT {
+                                isRecordForm {
   let RST = 0;
   let A = 0;
   let B = 0;
 }
 
 }
 
 def TCHECK : XForm_htm3 <31, 718,

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 }
 
 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                                    unsigned OpIdx1,
                                                    unsigned OpIdx2) const {
   MachineFunction &MF = *MI.getParent()->getParent();
 
   // Normal instructions can be commuted the obvious way.
-  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
+  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec)
     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
   // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
   // changing the relative order of the mask operands might change what happens
   // to the high-bits of the mask (and, thus, the result).
 
   // Cannot commute if it has a non-zero rotate count.
   if (MI.getOperand(3).getImm() != 0)
     return nullptr;
 
   // If we have a zero rotate count, we have:
   //   M = mask(MB,ME)
   //   Op0 = (Op1 & ~M) | (Op2 & M)
   // Change this to:
   //   M = mask((ME+1)&31, (MB-1)&31)
   //   Op0 = (Op2 & ~M) | (Op1 & M)
 
   // Swap op1/op2
   assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
-         "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
+         "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
   Register Reg0 = MI.getOperand(0).getReg();
   Register Reg1 = MI.getOperand(1).getReg();
   Register Reg2 = MI.getOperand(2).getReg();
   unsigned SubReg1 = MI.getOperand(1).getSubReg();
   unsigned SubReg2 = MI.getOperand(2).getSubReg();
   bool Reg1IsKill = MI.getOperand(1).isKill();
   bool Reg2IsKill = MI.getOperand(2).isKill();
   bool ChangeReg0 = false;
bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
   if (!MI && !Sub)
     return false;
 
   // The single candidate is called MI.
   if (!MI) MI = Sub;
 
   int NewOpC = -1;
   int MIOpC = MI->getOpcode();
-  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDI8o ||
-      MIOpC == PPC::ANDISo || MIOpC == PPC::ANDIS8o)
+  if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
+      MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
     NewOpC = MIOpC;
   else {
     NewOpC = PPC::getRecordFormOpcode(MIOpC);
     if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
       NewOpC = MIOpC;
   }
 
   // FIXME: On the non-embedded POWER architectures, only some of the record
if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
       bool MBInLoHWord = MB >= 16;
       bool MEInLoHWord = ME >= 16;
       uint64_t Mask = ~0LLU;
 
       if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
         Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
         // The mask value needs to shift right 16 if we're emitting andis.
         Mask >>= MBInLoHWord ? 0 : 16;
-        NewOpC = MIOpC == PPC::RLWINM ?
-          (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
-          (MBInLoHWord ? PPC::ANDI8o :PPC::ANDIS8o);
+        NewOpC = MIOpC == PPC::RLWINM
+                     ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
+                     : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
       } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
                  (ME - MB + 1 == SH) && (MB >= 16)) {
         // If we are rotating by the exact number of bits as are in the mask
         // and the mask is in the least significant bits of the register,
         // that's just an andis. (as long as the GPR result has no uses).
         Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
         Mask >>= 16;
-        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDIS8o;
+        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
       }
       // If we've set the mask, we can transform.
       if (Mask != ~0LLU) {
         MI->RemoveOperand(4);
         MI->RemoveOperand(3);
         MI->getOperand(2).setImm(Mask);
         NumRcRotatesConvertedToRcAnd++;
       }
     } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
       int64_t MB = MI->getOperand(3).getImm();
       if (MB >= 48) {
         uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
-        NewOpC = PPC::ANDI8o;
+        NewOpC = PPC::ANDI8_rec;
         MI->RemoveOperand(3);
         MI->getOperand(2).setImm(Mask);
         NumRcRotatesConvertedToRcAnd++;
       }
     }
 
     const MCInstrDesc &NewDesc = get(NewOpC);
     MI->setDesc(NewDesc);
void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
                                       const LoadImmediateInfo &LII) const {
   // Remove existing operands.
   int OperandToKeep = LII.SetCR ? 1 : 0;
   for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
     MI.RemoveOperand(i);
 
   // Replace the instruction.
   if (LII.SetCR) {
-    MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8o : PPC::ANDIo));
+    MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
     // Set the immediate.
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
     return;
   }
   else
     MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
 
if (MRI->isSSA()) {
     }
   } else {
     // Looking back through the definition for each operand could be expensive,
     // so exit early if this isn't an instruction that either has an immediate
     // form or is already an immediate form that we can handle.
     ImmInstrInfo III;
     unsigned Opc = MI.getOpcode();
     bool ConvertibleImmForm =
-      Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
-      Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
-      Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
-      Opc == PPC::ORI || Opc == PPC::ORI8 ||
-      Opc == PPC::XORI || Opc == PPC::XORI8 ||
-      Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
+        Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
+        Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
+        Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
+        Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
         Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
-      Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
-      Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
+        Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
+        Opc == PPC::RLWINM8_rec;
     bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
                        ? isVFRegister(MI.getOperand(0).getReg())
                        : false;
     if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
       return nullptr;
 
     // Don't convert or %X, %Y, %Y since that's just a register move.
     if ((Opc == PPC::OR || Opc == PPC::OR8) &&
if (isInt<16>(Addend + SExtImm)) {
       ReplaceWithLI = true;
       Is64BitLI = Opc == PPC::ADDI8;
       NewImm = Addend + SExtImm;
       break;
     }
     return false;
   }
   case PPC::RLDICL:
-  case PPC::RLDICLo:
+  case PPC::RLDICL_rec:
   case PPC::RLDICL_32:
   case PPC::RLDICL_32_64: {
     // Use APInt's rotate function.
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
-    APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
-                64 : 32, SExtImm, true);
+    APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
+                SExtImm, true);
     InVal = InVal.rotl(SH);
     uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use
-    // ANDIo which won't sign extend, so that's safe.
+    // ANDI_rec which won't sign extend, so that's safe.
     if (isUInt<15>(InVal.getSExtValue()) ||
-        (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
+        (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) {
       ReplaceWithLI = true;
       Is64BitLI = Opc != PPC::RLDICL_32;
       NewImm = InVal.getSExtValue();
-      SetCR = Opc == PPC::RLDICLo;
+      SetCR = Opc == PPC::RLDICL_rec;
       break;
     }
     return false;
   }
   case PPC::RLWINM:
   case PPC::RLWINM8:
-  case PPC::RLWINMo:
-  case PPC::RLWINM8o: {
+  case PPC::RLWINM_rec:
+  case PPC::RLWINM8_rec: {
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
     int64_t ME = MI.getOperand(4).getImm();
     APInt InVal(32, SExtImm, true);
     InVal = InVal.rotl(SH);
     // Set the bits (        MB + 32        ) to (        ME + 32        ).
     uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use
-    // ANDIo which won't sign extend, so that's safe.
+    // ANDI_rec which won't sign extend, so that's safe.
     bool ValueFits = isUInt<15>(InVal.getSExtValue());
-    ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
+    ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
                   isUInt<16>(InVal.getSExtValue()));
     if (ValueFits) {
       ReplaceWithLI = true;
-      Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
+      Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec;
       NewImm = InVal.getSExtValue();
-      SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
+      SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec;
       break;
     }
     return false;
   }
   case PPC::ORI:
   case PPC::ORI8:
   case PPC::XORI:
   case PPC::XORI8: {
if (ReplaceWithLI) {
     LLVM_DEBUG(MI.dump());
     LLVM_DEBUG(dbgs() << "Fed by:\n");
     LLVM_DEBUG(DefMI->dump());
     LoadImmediateInfo LII;
     LII.Imm = NewImm;
     LII.Is64Bit = Is64BitLI;
     LII.SetCR = SetCR;
     // If we're setting the CR, the original load-immediate must be kept (as an
-    // operand to ANDIo/ANDI8o).
+    // operand to ANDI_rec/ANDI8_rec).
     if (KilledDef && SetCR)
       *KilledDef = nullptr;
     replaceInstrWithLI(MI, LII);
 
     // Fixup killed/dead flag after transformation.
     // Pattern:
     // ForwardingOperandReg = LI imm1
     // y = op2 imm2, ForwardingOperandReg(killed)
bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
   case PPC::ADDC8:
     III.SignedImm = true;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = true;
     III.IsSummingOperands = true;
     III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
     break;
-  case PPC::ADDCo:
+  case PPC::ADDC_rec:
     III.SignedImm = true;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = true;
     III.IsSummingOperands = true;
-    III.ImmOpcode = PPC::ADDICo;
+    III.ImmOpcode = PPC::ADDIC_rec;
     break;
   case PPC::SUBFC:
   case PPC::SUBFC8:
     III.SignedImm = true;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = false;
     III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
   case PPC::CMPLW:
   case PPC::CMPLD:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = false;
     III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
     break;
-  case PPC::ANDo:
-  case PPC::AND8o:
+  case PPC::AND_rec:
+  case PPC::AND8_rec:
   case PPC::OR:
   case PPC::OR8:
   case PPC::XOR:
   case PPC::XOR8:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = true;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
-    case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
-    case PPC::AND8o: III.ImmOpcode = PPC::ANDI8o; break;
+    case PPC::AND_rec:
+      III.ImmOpcode = PPC::ANDI_rec;
+      break;
+    case PPC::AND8_rec:
+      III.ImmOpcode = PPC::ANDI8_rec;
+      break;
     case PPC::OR: III.ImmOpcode = PPC::ORI; break;
     case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
     case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
     case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
     }
     break;
   case PPC::RLWNM:
   case PPC::RLWNM8:
-  case PPC::RLWNMo:
-  case PPC::RLWNM8o:
+  case PPC::RLWNM_rec:
+  case PPC::RLWNM8_rec:
   case PPC::SLW:
   case PPC::SLW8:
-  case PPC::SLWo:
-  case PPC::SLW8o:
+  case PPC::SLW_rec:
+  case PPC::SLW8_rec:
   case PPC::SRW:
   case PPC::SRW8:
-  case PPC::SRWo:
-  case PPC::SRW8o:
+  case PPC::SRW_rec:
+  case PPC::SRW8_rec:
   case PPC::SRAW:
-  case PPC::SRAWo:
+  case PPC::SRAW_rec:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = false;
     // This isn't actually true, but the instructions ignore any of the
     // upper bits, so any immediate loaded with an LI is acceptable.
     // This does not apply to shift right algebraic because a value
     // out of range will produce a -1/0.
     III.ImmWidth = 16;
-    if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
-        Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
+    if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
+        Opc == PPC::RLWNM8_rec)
       III.TruncateImmTo = 5;
     else
       III.TruncateImmTo = 6;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
     case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::RLWNM_rec:
+      III.ImmOpcode = PPC::RLWINM_rec;
+      break;
+    case PPC::RLWNM8_rec:
+      III.ImmOpcode = PPC::RLWINM8_rec;
+      break;
     case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::SLW_rec:
+      III.ImmOpcode = PPC::RLWINM_rec;
+      break;
+    case PPC::SLW8_rec:
+      III.ImmOpcode = PPC::RLWINM8_rec;
+      break;
     case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::SRW_rec:
+      III.ImmOpcode = PPC::RLWINM_rec;
+      break;
+    case PPC::SRW8_rec:
+      III.ImmOpcode = PPC::RLWINM8_rec;
+      break;
     case PPC::SRAW:
       III.ImmWidth = 5;
       III.TruncateImmTo = 0;
       III.ImmOpcode = PPC::SRAWI;
       break;
-    case PPC::SRAWo:
+    case PPC::SRAW_rec:
       III.ImmWidth = 5;
       III.TruncateImmTo = 0;
-      III.ImmOpcode = PPC::SRAWIo;
+      III.ImmOpcode = PPC::SRAWI_rec;
       break;
     }
     break;
   case PPC::RLDCL:
-  case PPC::RLDCLo:
+  case PPC::RLDCL_rec:
   case PPC::RLDCR:
-  case PPC::RLDCRo:
+  case PPC::RLDCR_rec:
   case PPC::SLD:
-  case PPC::SLDo:
+  case PPC::SLD_rec:
   case PPC::SRD:
-  case PPC::SRDo:
+  case PPC::SRD_rec:
   case PPC::SRAD:
-  case PPC::SRADo:
+  case PPC::SRAD_rec:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = false;
     // This isn't actually true, but the instructions ignore any of the
     // upper bits, so any immediate loaded with an LI is acceptable.
     // This does not apply to shift right algebraic because a value
     // out of range will produce a -1/0.
     III.ImmWidth = 16;
-    if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
-        Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
+    if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
+        Opc == PPC::RLDCR_rec)
       III.TruncateImmTo = 6;
     else
       III.TruncateImmTo = 7;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
     case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
-    case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
+    case PPC::RLDCL_rec:
+      III.ImmOpcode = PPC::RLDICL_rec;
+      break;
     case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
-    case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
+    case PPC::RLDCR_rec:
+      III.ImmOpcode = PPC::RLDICR_rec;
+      break;
     case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
-    case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
+    case PPC::SLD_rec:
+      III.ImmOpcode = PPC::RLDICR_rec;
+      break;
     case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
-    case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
+    case PPC::SRD_rec:
+      III.ImmOpcode = PPC::RLDICL_rec;
+      break;
     case PPC::SRAD:
       III.ImmWidth = 6;
       III.TruncateImmTo = 0;
       III.ImmOpcode = PPC::SRADI;
        break;
-    case PPC::SRADo:
+    case PPC::SRAD_rec:
       III.ImmWidth = 6;
       III.TruncateImmTo = 0;
-      III.ImmOpcode = PPC::SRADIo;
+      III.ImmOpcode = PPC::SRADI_rec;
       break;
     }
     break;
   // Loads and stores:
   case PPC::LBZX:
   case PPC::LBZX8:
   case PPC::LHZX:
   case PPC::LHZX8:
bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
   }
 
   // Get killed info in case fixup needed after transformation.
   unsigned ForwardKilledOperandReg = ~0U;
   if (PostRA && MI.getOperand(ConstantOpNo).isKill())
     ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
 
   unsigned Opc = MI.getOpcode();
-  bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLWo ||
-                        Opc == PPC::SRW || Opc == PPC::SRWo ||
-                        Opc == PPC::SLW8 || Opc == PPC::SLW8o ||
-                        Opc == PPC::SRW8 || Opc == PPC::SRW8o;
-  bool SpecialShift64 =
-    Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
-  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
-    Opc == PPC::SLDo || Opc == PPC::SRDo;
-  bool RightShift =
-    Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
+  bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec ||
+                        Opc == PPC::SRW || Opc == PPC::SRW_rec ||
+                        Opc == PPC::SLW8 || Opc == PPC::SLW8_rec ||
+                        Opc == PPC::SRW8 || Opc == PPC::SRW8_rec;
+  bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec ||
+                        Opc == PPC::SRD || Opc == PPC::SRD_rec;
+  bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec ||
+               Opc == PPC::SLD_rec || Opc == PPC::SRD_rec;
+  bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD ||
+                    Opc == PPC::SRD_rec;
 
   MI.setDesc(get(III.ImmOpcode));
   if (ConstantOpNo == III.OpNoForForwarding) {
     // Converting shifts to immediate form is a bit tricky since they may do
     // one of three things:
     // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
     // 2. If the shift amount is zero, the result is unchanged (save for maybe
     //    setting CR0)
int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
   return PPC::getRecordFormOpcode(Opcode);
 }
 
 // This function returns true if the machine instruction
 // always outputs a value by sign-extending a 32 bit value,
 // i.e. 0 to 31-th bits are same as 32-th bit.
 static bool isSignExtendingOp(const MachineInstr &MI) {
   int Opcode = MI.getOpcode();
-  if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
-      Opcode == PPC::LIS    || Opcode == PPC::LIS8    ||
-      Opcode == PPC::SRAW   || Opcode == PPC::SRAWo   ||
-      Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIo  ||
-      Opcode == PPC::LWA    || Opcode == PPC::LWAX    ||
-      Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
-      Opcode == PPC::LHA    || Opcode == PPC::LHAX    ||
-      Opcode == PPC::LHA8   || Opcode == PPC::LHAX8   ||
-      Opcode == PPC::LBZ    || Opcode == PPC::LBZX    ||
-      Opcode == PPC::LBZ8   || Opcode == PPC::LBZX8   ||
-      Opcode == PPC::LBZU   || Opcode == PPC::LBZUX   ||
-      Opcode == PPC::LBZU8  || Opcode == PPC::LBZUX8  ||
-      Opcode == PPC::LHZ    || Opcode == PPC::LHZX    ||
-      Opcode == PPC::LHZ8   || Opcode == PPC::LHZX8   ||
-      Opcode == PPC::LHZU   || Opcode == PPC::LHZUX   ||
-      Opcode == PPC::LHZU8  || Opcode == PPC::LHZUX8  ||
-      Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
-      Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
-      Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
-      Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
-      Opcode == PPC::SETB   || Opcode == PPC::SETB8   ||
+  if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
+      Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
+      Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
+      Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
+      Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
+      Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
+      Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
+      Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+      Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
+      Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
+      Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
+      Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
+      Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
+      Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
+      Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
       Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
       Opcode == PPC::EXTSB8_32_64)
     return true;
 
   if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
     return true;
 
-  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMo) &&
+  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
+       Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
       MI.getOperand(3).getImm() > 0 &&
       MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
     return true;
 
   return false;
 }
 
 // This function returns true if the machine instruction
 // always outputs zeros in higher 32 bits.
 static bool isZeroExtendingOp(const MachineInstr &MI) {
   int Opcode = MI.getOpcode();
   // The 16-bit immediate is sign-extended in li/lis.
   // If the most significant bit is zero, all higher bits are zero.
   if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
       Opcode == PPC::LIS || Opcode == PPC::LIS8) {
     int64_t Imm = MI.getOperand(1).getImm();
     if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
       return true;
   }
 
   // We have some variations of rotate-and-mask instructions
   // that clear higher 32-bits.
-  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
-       Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo  ||
+  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
+       Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
        Opcode == PPC::RLDICL_32_64) &&
       MI.getOperand(3).getImm() >= 32)
     return true;
 
-  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
       MI.getOperand(3).getImm() >= 32 &&
       MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
     return true;
 
-  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
+       Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
       MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
     return true;
 
   // There are other instructions that clear higher 32-bits.
-  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
-      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
+      Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
       Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
-      Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
-      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo ||
-      Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
-      Opcode == PPC::SLW     || Opcode == PPC::SLWo    ||
-      Opcode == PPC::SRW     || Opcode == PPC::SRWo    ||
-      Opcode == PPC::SLW8    || Opcode == PPC::SRW8    ||
-      Opcode == PPC::SLWI    || Opcode == PPC::SLWIo   ||
-      Opcode == PPC::SRWI    || Opcode == PPC::SRWIo   ||
-      Opcode == PPC::LWZ     || Opcode == PPC::LWZX    ||
-      Opcode == PPC::LWZU    || Opcode == PPC::LWZUX   ||
-      Opcode == PPC::LWBRX   || Opcode == PPC::LHBRX   ||
-      Opcode == PPC::LHZ     || Opcode == PPC::LHZX    ||
-      Opcode == PPC::LHZU    || Opcode == PPC::LHZUX   ||
-      Opcode == PPC::LBZ     || Opcode == PPC::LBZX    ||
-      Opcode == PPC::LBZU    || Opcode == PPC::LBZUX   ||
-      Opcode == PPC::LWZ8    || Opcode == PPC::LWZX8   ||
-      Opcode == PPC::LWZU8   || Opcode == PPC::LWZUX8  ||
-      Opcode == PPC::LWBRX8  || Opcode == PPC::LHBRX8  ||
-      Opcode == PPC::LHZ8    || Opcode == PPC::LHZX8   ||
-      Opcode == PPC::LHZU8   || Opcode == PPC::LHZUX8  ||
-      Opcode == PPC::LBZ8    || Opcode == PPC::LBZX8   ||
-      Opcode == PPC::LBZU8   || Opcode == PPC::LBZUX8  ||
-      Opcode == PPC::ANDIo   || Opcode == PPC::ANDISo  ||
-      Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIo ||
-      Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIo ||
+      Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
+      Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
+      Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
+      Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
+      Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
+      Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
+      Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
+      Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
+      Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
+      Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
+      Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
+      Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
+      Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
+      Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
+      Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
+      Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+      Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
+      Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
+      Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
       Opcode == PPC::MFVSRWZ)
     return true;
 
   return false;
 }
 
 // This function returns true if the input MachineInstr is a TOC save
 // instruction.
if (!Register::isVirtualRegister(SrcReg))
       return false;
     const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
     if (SrcMI != NULL)
       return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
 
     return false;
   }
 
-  case PPC::ANDIo:
-  case PPC::ANDISo:
+  case PPC::ANDI_rec:
+  case PPC::ANDIS_rec:
   case PPC::ORI:
   case PPC::ORIS:
   case PPC::XORI:
   case PPC::XORIS:
-  case PPC::ANDI8o:
-  case PPC::ANDIS8o:
+  case PPC::ANDI8_rec:
+  case PPC::ANDIS8_rec:
   case PPC::ORI8:
   case PPC::ORIS8:
   case PPC::XORI8:
   case PPC::XORIS8: {
     // logical operation with 16-bit immediate does not change the upper bits.
     // So, we track the operand register as we do for register copy.
     Register SrcReg = MI.getOperand(1).getReg();
     if (!Register::isVirtualRegister(SrcReg))

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 def add_without_simm16 : BinOpWithoutSImm16Operand<add>;
 def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Flag Definitions.
 
 class isPPC64 { bit PPC64 = 1; }
-class isDOT   { bit RC = 1; }
+class isRecordForm   { bit RC = 1; }
 
 class RegConstraint<string C> {
   string Constraints = C;
 }
 class NoEncode<string E> {
   string DisableEncoding = E;
 }
 

 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XForm_6<opcode, xo, OOL, IOL,
+    def _rec    : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                      string asmbase, string asmstr, InstrItinClass itin,
                      list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XForm_6<opcode, xo, OOL, IOL,
+    def _rec    : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XForm_10<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XForm_10<opcode, xo, OOL, IOL,
+    def _rec    : XForm_10<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XForm_11<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XForm_11<opcode, xo, OOL, IOL,
+    def _rec    : XForm_11<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def _rec    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 // Multiclass for instructions which have a record overflow form as well
 // as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.)
 multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XOForm_1<opcode, xo, 0, OOL, IOL,
                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                         pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, 0, OOL, IOL,
+    def _rec    : XOForm_1<opcode, xo, 0, OOL, IOL,
                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
   let BaseName = !strconcat(asmbase, "O") in {
     let Defs = [XER] in
     def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo    : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def O_rec    : XOForm_1<opcode, xo, 1, OOL, IOL,
                          !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
-                         []>, isDOT, RecFormRel;
+                         []>, isRecordForm, RecFormRel;
   }
 }
 
 // Multiclass for instructions for which the non record form is not cracked
 // and the record form is cracked (i.e. divw, mullw, etc.)
 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def _rec    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
+                       []>, isRecordForm, RecFormRel, PPC970_DGroup_First,
                        PPC970_DGroup_Cracked;
   }
   let BaseName = !strconcat(asmbase, "O") in {
     let Defs = [XER] in
     def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def O_rec   : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def _rec    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
   let BaseName = !strconcat(asmbase, "O") in {
     let Defs = [CARRY, XER] in
     def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [CARRY, XER, CR0] in
-    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def O_rec   : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
+    def _rec    : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
   let BaseName = !strconcat(asmbase, "O") in {
     let Defs = [XER] in
     def O    : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
+    def O_rec   : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
+    def _rec    : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
   let BaseName = !strconcat(asmbase, "O") in {
     let Defs = [CARRY, XER] in
     def O    : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [CARRY, XER, CR0] in
-    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
+    def O_rec   : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : MForm_2<opcode, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MForm_2<opcode, OOL, IOL,
+    def _rec    : MForm_2<opcode, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : MDForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MDForm_1<opcode, xo, OOL, IOL,
+    def _rec    : MDForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
                      string asmbase, string asmstr, InstrItinClass itin,
                      list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : MDSForm_1<opcode, xo, OOL, IOL,
                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                         pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MDSForm_1<opcode, xo, OOL, IOL,
+    def _rec    : MDSForm_1<opcode, xo, OOL, IOL,
                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                        []>, isDOT, RecFormRel;
+                        []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XSForm_1<opcode, xo, OOL, IOL,
+    def _rec    : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XSForm_1<opcode, xo, OOL, IOL,
+    def _rec    : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XForm_26<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : XForm_26<opcode, xo, OOL, IOL,
+    def _rec    : XForm_26<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XForm_28<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : XForm_28<opcode, xo, OOL, IOL,
+    def _rec    : XForm_28<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : AForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_1<opcode, xo, OOL, IOL,
+    def _rec    : AForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : AForm_2<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_2<opcode, xo, OOL, IOL,
+    def _rec    : AForm_2<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : AForm_3<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_3<opcode, xo, OOL, IOL,
+    def _rec    : AForm_3<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
-                       []>, isDOT, RecFormRel;
+                       []>, isRecordForm, RecFormRel;
   }
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Definitions.
 
 // Pseudo instructions:
 
def LHARX : XForm_1_memOp<31,  116, (outs gprc:$rD), (ins memrr:$src),
                     Requires<[HasPartwordAtomics]>;
 
 def LWARX : XForm_1_memOp<31,  20, (outs gprc:$rD), (ins memrr:$src),
                     "lwarx $rD, $src", IIC_LdStLWARX, []>;
 
 // Instructions to support lock versions of atomics
 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
 def LBARXL : XForm_1_memOp<31,  52, (outs gprc:$rD), (ins memrr:$src),
-                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
+                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm,
                      Requires<[HasPartwordAtomics]>;
 
 def LHARXL : XForm_1_memOp<31,  116, (outs gprc:$rD), (ins memrr:$src),
-                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
+                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm,
                      Requires<[HasPartwordAtomics]>;
 
 def LWARXL : XForm_1_memOp<31,  20, (outs gprc:$rD), (ins memrr:$src),
-                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
+                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm;
 
 // The atomic instructions use the destination register as well as the next one
 // or two registers in order (modulo 31).
 let hasExtraSrcRegAllocReq = 1 in
 def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
                          "lwat $rD, $rA, $FC", IIC_LdStLoad>,
            Requires<[IsISA3_0]>;
 }
 
 let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
 def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
                     "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
-                    isDOT, Requires<[HasPartwordAtomics]>;
+                    isRecordForm, Requires<[HasPartwordAtomics]>;
 
 def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
                     "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
-                    isDOT, Requires<[HasPartwordAtomics]>;
+                    isRecordForm, Requires<[HasPartwordAtomics]>;
 
 def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
-                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
+                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm;
 }
 
 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
 def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
                           "stwat $rS, $rA, $FC", IIC_LdStStore>,
             Requires<[IsISA3_0]>;
 
 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
                      [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
 let BaseName = "addic" in {
 let Defs = [CARRY] in
 def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
                      "addic $rD, $rA, $imm", IIC_IntGeneral,
                      [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
                      RecFormRel, PPC970_DGroup_Cracked;
 let Defs = [CARRY, CR0] in
-def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
+def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
                      "addic. $rD, $rA, $imm", IIC_IntGeneral,
-                     []>, isDOT, RecFormRel;
+                     []>, isRecordForm, RecFormRel;
 }
 def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
                      "addis $rD, $rA, $imm", IIC_IntSimple,
                      [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
 let isCodeGenOnly = 1 in
 def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
                      "la $rD, $sym($rA)", IIC_IntGeneral,
                      [(set i32:$rD, (add i32:$rA,
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
   def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
                        "lis $rD, $imm", IIC_IntSimple,
                        [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
 }
 }
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
-def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
+def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andi. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
-                    isDOT;
-def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
+                    isRecordForm;
+def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
-                    isDOT;
+                    isRecordForm;
 }
 def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "ori $dst, $src1, $src2", IIC_IntSimple,
                     [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
 def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "oris $dst, $src1, $src2", IIC_IntSimple,
                     [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
 def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),

 }
 let Uses = [RM] in {
   def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
                          "mffs $rT", IIC_IntMFFS,
                          [(set f64:$rT, (PPCmffs))]>,
                PPC970_DGroup_Single, PPC970_Unit_FPU;
 
   let Defs = [CR1] in
-  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
-                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
+  def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins),
+                      "mffs. $rT", IIC_IntMFFS, []>, isRecordForm;
 
   def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
                                   "mffsce $rT", IIC_IntMFFS, []>,
                PPC970_DGroup_Single, PPC970_Unit_FPU;
 
   def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
                                          (ins f8rc:$FRB), "mffscdrn $rT, $FRB",
                                          IIC_IntMFFS, []>,
defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
                        RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
 }
 let BaseName = "rlwinm" in {
 def RLWINM : MForm_2<21,
                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
                      "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
                      []>, RecFormRel;
 let Defs = [CR0] in
-def RLWINMo : MForm_2<21,
+def RLWINM_rec : MForm_2<21,
                       (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
                       "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
-                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
+                      []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked;
 }
 defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
                        (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
                        "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
                        []>;
 }
 } // hasSideEffects = 0
 
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
           (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
           (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
           (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
           (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
 
-def ANDIo_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
-                             "#ANDIo_1_EQ_BIT",
+def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
+                             "#ANDI_rec_1_EQ_BIT",
                              [(set i1:$dst, (trunc (not i32:$in)))]>;
-def ANDIo_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
-                             "#ANDIo_1_GT_BIT",
+def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
+                             "#ANDI_rec_1_GT_BIT",
                              [(set i1:$dst, (trunc i32:$in))]>;
 
-def ANDIo_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
-                              "#ANDIo_1_EQ_BIT8",
+def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
+                              "#ANDI_rec_1_EQ_BIT8",
                               [(set i1:$dst, (trunc (not i64:$in)))]>;
-def ANDIo_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
-                              "#ANDIo_1_GT_BIT8",
+def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
+                              "#ANDI_rec_1_GT_BIT8",
                               [(set i1:$dst, (trunc i64:$in))]>;
 
 def : Pat<(i1 (not (trunc i32:$in))),
-           (ANDIo_1_EQ_BIT $in)>;
+           (ANDI_rec_1_EQ_BIT $in)>;
 def : Pat<(i1 (not (trunc i64:$in))),
-           (ANDIo_1_EQ_BIT8 $in)>;
+           (ANDI_rec_1_EQ_BIT8 $in)>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instructions used for assembler/disassembler only
 //
 
 // FIXME: For B=0 or B > 8, the registers following RT are used.
 // WARNING: Do not add patterns for this instruction without fixing this.
 def LSWI  : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT),
def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
                     "mtmsrd $RS, $L", IIC_SprMTMSRD>;
 
 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
                      "mcrfs $BF, $BFA", IIC_BrMCR>;
 
 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                       "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
 
-def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
-                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
+def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
 
 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
-def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
+def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
 
 let Predicates = [HasFPU] in {
 def MTFSF : XFLForm_1<63, 711, (outs),
                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
                       "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
-def MTFSFo : XFLForm_1<63, 711, (outs),
+def MTFSF_rec : XFLForm_1<63, 711, (outs),
                        (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
-                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
+                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
 
 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
-def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
+def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 }
 
 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
                         "slbie $RB", IIC_SprSLBIE, []>;
 
 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
                     "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
 
 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
                        "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
 
 def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
                        "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
 
 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
 
 let Defs = [CR0] in
-def SLBFEEo : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
-                         "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isDOT;
+def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
+                         "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm;
 
 def TLBIA : XForm_0<31, 370, (outs), (ins),
                         "tlbia", IIC_SprTLBIA, []>;
 
 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
                         "tlbsync", IIC_SprTLBSYNC, []>;
 
 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
                "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
 
 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
                              "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
                              Requires<[IsPPC4xx]>;
 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
                               (ins gprc:$RST, gprc:$A, gprc:$B),
                               "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
-                              Requires<[IsPPC4xx]>, isDOT;
+                              Requires<[IsPPC4xx]>, isRecordForm;
 
 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
 
 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
                   Requires<[IsBookE]>;
 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
                    Requires<[IsBookE]>;
 

 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
 
 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
 
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
-def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
-def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
 
 foreach BATR = 0-3 in {
     def : InstAlias<"mtdbatu "#BATR#", $Rx",
                     (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
                     Requires<[IsPPC6xx]>;
     def : InstAlias<"mfdbatu $Rx, "#BATR,

 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
 
 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
-def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
+def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm",
                           (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 
 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
-def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
-def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 
 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
 
 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
 
 foreach SPRG = 0-3 in {
def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
                 Requires<[IsPPC4xx]>;
 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
                 Requires<[IsPPC4xx]>;
 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
                 Requires<[IsPPC4xx]>;
 
 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
+def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
+def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
+def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
+def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
+def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
+def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n",
                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
+def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n",
                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
+def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
-def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
+def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
-def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
-def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
+def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
-def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 
 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
-def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>;
 // The POWER variant
 def : MnemonicAlias<"cntlz",  "cntlzw">;
 def : MnemonicAlias<"cntlz.", "cntlzw.">;
 
 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
+def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
+def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
+def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
+def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
+def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n",
                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
+def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n",
                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
+def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
-def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
+def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
                              (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
-def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
-def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
+def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi $rA, $rS, $n",
                 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
-def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
+def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;
 
 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
                             (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
-def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
+def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
                             (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
-def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
+def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
                             (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
-def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
+def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
 
 // These generic branch instruction forms are used for the assembler parser only.
 // Defs and Uses are conservative, since we don't know the BO value.
 let PPC970_Unit = 7, isBranch = 1 in {
   let Defs = [CTR], Uses = [CTR, RM] in {
     def gBC : BForm_3<16, 0, 0, (outs),
                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),

 // PASTE for naming consistency.
 let mayLoad = 1 in
 def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
 
 let mayStore = 1 in
 def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
 
 let mayStore = 1, Defs = [CR0] in
-def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
+def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm;
 
 def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
 def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
 def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
                                   (ins gprc:$rA, gprc:$rB)>;
 def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
                                   (ins gprc:$rA, gprc:$rB)>;
 def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,
                     string asmstr, InstrItinClass itin, Intrinsic Int,
                     ValueType OutTy, ValueType InTy> {
   let BaseName = asmbase in {
     def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>;
     let Defs = [CR6] in
-    def o    : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+    def _rec    : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        [(set InTy:$XT,
                                 (InTy (PPCvcmp_o InTy:$XA, InTy:$XB, xo)))]>,
-                       isDOT;
+                       isRecordForm;
   }
 }
 
 // Instruction form with a single input register for instructions such as
 // XXPERMDI. The reason for defining this is that specifying multiple chained
 // operands (such as loads) to an instruction will perform both chained
 // operations rather than coalescing them into a single register - even though
 // the source memory location is the same. This simply forces the instruction
def VectorExtractions {
 
   /*  BE variable byte
       The algorithm here is the same as the LE variable byte except:
       - The shift in the VMX register is by 0/8 for opposite element numbers so
         we simply AND the element number with 0x8
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-7
   */
-  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8o $Idx, 8)));
+  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8)));
   dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
   dag BE_MV_VBYTE = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),
                                        sub_32);
   dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT),
                                          sub_32);
 
   /*  BE variable halfword
       The algorithm here is the same as the LE variable halfword except:
       - The shift in the VMX register is by 0/8 for opposite element numbers so
         we simply AND the element number with 0x4 and multiply by 2
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-3
   */
   dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDI8o $Idx, 4), 1, 62)));
+                                       (RLDICR (ANDI8_rec $Idx, 4), 1, 62)));
   dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
   dag BE_MV_VHALF = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),
                                        sub_32);
   dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT),
                                          sub_32);
 
   /*  BE variable word
       The algorithm is the same as the LE variable word except:
       - The shift in the VMX register happens for opposite element numbers
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-1
   */
   dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDI8o $Idx, 2), 2, 61)));
+                                       (RLDICR (ANDI8_rec $Idx, 2), 2, 61)));
   dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
   dag BE_MV_VWORD = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58),
                                        sub_32);
   dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT),
                                          sub_32);
 
   /*  BE variable doubleword
       Same as the LE doubleword except we shift in the VMX register for opposite
       element indices.
   */
   dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                        (RLDICR (ANDI8o $Idx, 1), 3, 60)));
+                                        (RLDICR (ANDI8_rec $Idx, 1), 3, 60)));
   dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
   dag BE_VARIABLE_DWORD =
         (MFVSRD (EXTRACT_SUBREG
                   (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)),
                   sub_64));
 
   /*  BE variable float
       - Shift the vector to line up the desired element to BE Word 0
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                       list<dag> pattern>
     : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
                     !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
 
   // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
   class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                          list<dag> pattern>
-    : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isDOT;
+    : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm;
 
   // [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
   // So we use different operand class for VRB
   class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                            RegisterOperand vbtype, list<dag> pattern>
     : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
                     !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
 
   // [PO VRT XO VRB XO /]
   class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                       list<dag> pattern>
     : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB),
                     !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
 
   // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
   class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                          list<dag> pattern>
-    : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isDOT;
+    : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm;
 
   // [PO T XO B XO BX /]
   class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
                         list<dag> pattern>
     : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
                       !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
 
   // [PO T XO B XO BX TX]
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
                       list<dag> pattern>
     : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
               !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>;
 
   // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
   class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
                          list<dag> pattern>
-    : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isDOT;
+    : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm;
 
   // [PO VRT VRA VRB XO /]
   class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
                           list<dag> pattern>
     : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB),
               !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>,
               RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">;
 
   // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
   class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
                           list<dag> pattern>
-    : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isDOT;
+    : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm;
 
   //===--------------------------------------------------------------------===//
   // Quad-Precision Scalar Move Instructions:
 
   // Copy Sign
   def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
                                 [(set f128:$vT,
                                       (fcopysign f128:$vB, f128:$vA))]>;

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
   return MRI->getVRegDef(Reg);
 }
 
 // This function returns number of known zero bits in output of MI
 // starting from the most significant bit.
 static unsigned
 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
   unsigned Opcode = MI->getOpcode();
-  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
-      Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo)
+  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
+      Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
     return MI->getOperand(3).getImm();
 
-  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
-       MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
     return MI->getOperand(3).getImm();
 
-  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
+       Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
-       MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return 32 + MI->getOperand(3).getImm();
 
-  if (Opcode == PPC::ANDIo) {
+  if (Opcode == PPC::ANDI_rec) {
     uint16_t Imm = MI->getOperand(2).getImm();
     return 48 + countLeadingZeros(Imm);
   }
 
-  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
-      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
+      Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
       Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
     // The result ranges from 0 to 32.
     return 58;
 
-  if (Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
-      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo)
+  if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
+      Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec)
     // The result ranges from 0 to 64.
     return 57;
 
   if (Opcode == PPC::LHZ   || Opcode == PPC::LHZX  ||
       Opcode == PPC::LHZ8  || Opcode == PPC::LHZX8 ||
       Opcode == PPC::LHZU  || Opcode == PPC::LHZUX ||
       Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
     return 48;
for (MachineInstr &MI : MBB) {
         break;
       }
       case PPC::RLDICR: {
         Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
       case PPC::RLWINM:
-      case PPC::RLWINMo:
+      case PPC::RLWINM_rec:
       case PPC::RLWINM8:
-      case PPC::RLWINM8o: {
+      case PPC::RLWINM8_rec: {
         unsigned FoldingReg = MI.getOperand(1).getReg();
         if (!Register::isVirtualRegister(FoldingReg))
           break;
 
         MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
         if (SrcMI->getOpcode() != PPC::RLWINM &&
-            SrcMI->getOpcode() != PPC::RLWINMo &&
+            SrcMI->getOpcode() != PPC::RLWINM_rec &&
             SrcMI->getOpcode() != PPC::RLWINM8 &&
-            SrcMI->getOpcode() != PPC::RLWINM8o)
+            SrcMI->getOpcode() != PPC::RLWINM8_rec)
           break;
         assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
                 MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
                 SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
                "Invalid PPC::RLWINM Instruction!");
         uint64_t SHSrc = SrcMI->getOperand(2).getImm();
         uint64_t SHMI = MI.getOperand(2).getImm();
         uint64_t MBSrc = SrcMI->getOperand(3).getImm();
for (MachineInstr &MI : MBB) {
 
         APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
         APInt FinalMask = RotatedSrcMask & MaskMI;
         uint32_t NewMB, NewME;
 
         // If final mask is 0, MI result should be 0 too.
         if (FinalMask.isNullValue()) {
           bool Is64Bit = (MI.getOpcode() == PPC::RLWINM8 ||
-                          MI.getOpcode() == PPC::RLWINM8o);
+                          MI.getOpcode() == PPC::RLWINM8_rec);
 
           LLVM_DEBUG(dbgs() << "Replace Instr: ");
           LLVM_DEBUG(MI.dump());
 
           if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
             // Replace MI with "LI 0"
             MI.RemoveOperand(4);
             MI.RemoveOperand(3);
             MI.RemoveOperand(2);
             MI.getOperand(1).ChangeToImmediate(0);
             MI.setDesc(TII->get(Is64Bit ? PPC::LI8 : PPC::LI));
           } else {
-            // Replace MI with "ANDIo reg, 0"
+            // Replace MI with "ANDI_rec reg, 0"
             MI.RemoveOperand(4);
             MI.RemoveOperand(3);
             MI.getOperand(2).setImm(0);
-            MI.setDesc(TII->get(Is64Bit ? PPC::ANDI8o : PPC::ANDIo));
+            MI.setDesc(TII->get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
           }
           Simplified = true;
           NumRotatesCollapsed++;
 
           LLVM_DEBUG(dbgs() << "With: ");
           LLVM_DEBUG(MI.dump());
         } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB,
                                NewME) && NewMB <= NewME)|| SrcMaskFull) {
           // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger
           // than NewME. Otherwise we get a 64 bit value after folding, but MI
           // return a 32 bit value.
 
-          // If FoldingReg has only one use and it it not RLWINMo and
-          // RLWINM8o, safe to delete its def SrcMI. Otherwise keep it.
+          // If FoldingReg has only one use and it it not RLWINM_rec and
+          // RLWINM8_rec, safe to delete its def SrcMI. Otherwise keep it.
           if (MRI->hasOneNonDBGUse(FoldingReg) &&
               (SrcMI->getOpcode() == PPC::RLWINM ||
                SrcMI->getOpcode() == PPC::RLWINM8)) {
             ToErase = SrcMI;
             LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
             LLVM_DEBUG(SrcMI->dump());
           }
 

llvm/test/CodeGen/PowerPC/block-placement.mir

bb.2.while.body.i.preheader:
   
     renamable $x6 = ADDI8 renamable $x5, 2
     renamable $x7 = ADDI8 renamable $x4, 2
   
   bb.3.while.body.i:
     successors: %bb.4(0x04000000), %bb.10(0x7c000000)
     liveins: $r8, $x3, $x4, $x5, $x6, $x7
   
-    dead renamable $r8 = ANDIo killed renamable $r8, 65535, implicit-def $cr0
+    dead renamable $r8 = ANDI_rec killed renamable $r8, 65535, implicit-def $cr0
     BCC 68, killed renamable $cr0, %bb.10
   
   bb.4:
     renamable $x3 = LI8 1
     BLR8 implicit $lr8, implicit $rm, implicit killed $x3
   
   bb.5.if.then.i:
     successors: %bb.7(0x30000000), %bb.6(0x50000000)

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

--- |
   define i64 @testRLWNM8(i64 %a) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, 4
     %and = and i64 %shl, 4080
     ret i64 %and
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWNMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWNM_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLWNM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLWNM8_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %a.tr = trunc i64 %a to i32
     %0 = shl i32 %a.tr, 4
     %conv = and i32 %0, 4080
     %tobool = icmp eq i32 %conv, 0
     %conv1 = zext i32 %conv to i64
     %cond = select i1 %tobool, i64 %b, i64 %conv1
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     ret i32 %shl
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSLW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     %tobool = icmp eq i32 %shl, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define zeroext i32 @testSRW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     ret i32 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSRW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define signext i32 @testSRAW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     ret i32 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+  define signext i32 @testSRAW_rec(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
     %cond = select i1 %tobool, i32 %b, i32 %shr
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDCL(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     ret i64 %or
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     %tobool = icmp eq i64 %or, 0
     %cond = select i1 %tobool, i64 %and, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDCR(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     ret i64 %or
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCR_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     %tobool = icmp eq i64 %or, 0
     %cond = select i1 %tobool, i64 %and, i64 %a
     ret i64 %cond
   }
   
   define i64 @testSLD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     ret i64 %shl
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSLD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     %tobool = icmp eq i64 %shl, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testSRD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     ret i64 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testSRAD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     ret i64 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRAD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
     %cond = select i1 %tobool, i64 %b, i64 %shr
     ret i64 %cond
   }
   
   attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
bb.0.entry:
     %2 = RLWNM8 %1, %0, 20, 27
     ; CHECK: RLWINM8 %1, 10, 20, 27
     ; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
     $x3 = COPY %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLWNMo
-# CHECK-ALL: name: testRLWNMo
+name:            testRLWNM_rec
+# CHECK-ALL: name: testRLWNM_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWNMo %2, %3, 24, 31, implicit-def $cr0
-    ; CHECK: RLWINMo %2, 10, 24, 31, implicit-def $cr0
+    %4 = RLWNM_rec %2, %3, 24, 31, implicit-def $cr0
+    ; CHECK: RLWINM_rec %2, 10, 24, 31, implicit-def $cr0
     ; CHECK-LATE: li 3, -22
     ; CHECK-LATE: rlwinm. 5, 4, 10, 24, 31
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLWNM8o
-# CHECK-ALL: name: testRLWNM8o
+name:            testRLWNM8_rec
+# CHECK-ALL: name: testRLWNM8_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
-    %3 = RLWNM8o %1, %2, 20, 27, implicit-def $cr0
-    ; CHECK: RLWINM8o %1, 14, 20, 27, implicit-def $cr0
+    %3 = RLWNM8_rec %1, %2, 20, 27, implicit-def $cr0
+    ; CHECK: RLWINM8_rec %1, 14, 20, 27, implicit-def $cr0
     ; CHECK-LATE: rlwinm. 3, 4, 14, 20, 27
     %7 = COPY killed $cr0
     %6 = RLDICL killed %3, 0, 32
     %8 = ISEL8 %1, %6, %7.sub_eq
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
bb.0.entry:
     %8 = SLW killed %2, killed %5
     ; CHECK: RLWINM killed %2, 18, 0, 13
     ; CHECK-LATE: slwi 3, 4, 18
     $x3 = EXTSW_32_64 %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSLWo
-# CHECK-ALL: name: testSLWo
+name:            testSLW_rec
+# CHECK-ALL: name: testSLW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 35
     %3 = COPY %0.sub_32
-    %4 = SLWo %3, %2, implicit-def $cr0
-    ; CHECK: ANDIo %3, 0, implicit-def $cr0
+    %4 = SLW_rec %3, %2, implicit-def $cr0
+    ; CHECK: ANDI_rec %3, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
     %8 = SRW killed %5, killed %2
     ; CHECK: LI 0
     ; CHECK-LATE: li 3, 0
     $x3 = EXTSW_32_64 %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRWo
-# CHECK-ALL: name: testSRWo
+name:            testSRW_rec
+# CHECK-ALL: name: testSRW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI -7
     %3 = COPY %0.sub_32
-    %4 = SRWo %3, %2, implicit-def $cr0
-    ; CHECK: ANDIo %3, 0, implicit-def $cr0
+    %4 = SRW_rec %3, %2, implicit-def $cr0
+    ; CHECK: ANDI_rec %3, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
     ; CHECK: SRAW killed %3, killed %2, implicit-def dead $carry
     ; CHECK-LATE: sraw 3, 3, 4
     %5 = EXTSW_32_64 killed %4
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRAWo
-# CHECK-ALL: name: testSRAWo
+name:            testSRAW_rec
+# CHECK-ALL: name: testSRAW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 80
     %3 = COPY %0.sub_32
-    %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    %4 = SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sraw. 3, 3, 4
     %5 = COPY killed $cr0
     %6 = ISEL %2, %4, %5.sub_eq
     %7 = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
bb.0.entry:
     %4 = RLDCL %0, killed %3, 0
     ; CHECK: RLDICL %0, 12, 0
     ; CHECK-LATE: rotldi 3, 3, 12
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDCLo
-# CHECK-ALL: name: testRLDCLo
+name:            testRLDCL_rec
+# CHECK-ALL: name: testRLDCL_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI -37
-    %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 27, 0, implicit-def $cr0
+    %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 27, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %4 = RLDCR %0, killed %3, 0
     ; CHECK: RLDICR %0, 44, 0
     ; CHECK-LATE: rldicr 3, 3, 44, 0
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDCRo
-# CHECK-ALL: name: testRLDCRo
+name:            testRLDCR_rec
+# CHECK-ALL: name: testRLDCR_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI -18
-    %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 46, 0, implicit-def $cr0
+    %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICR_rec %0, 46, 0, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 46, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %3 = SLD %0, killed %2
     ; CHECK: LI8 0
     ; CHECK-LATE: li 3, 0
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSLDo
-# CHECK-ALL: name: testSLDo
+name:            testSLD_rec
+# CHECK-ALL: name: testSLD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 88
-    %3 = SLDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDI8o %0, 0, implicit-def $cr0
+    %3 = SLD_rec %0, killed %2, implicit-def $cr0
+    ; CHECK: ANDI8_rec %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %3 = SRD %0, killed %2
     ; CHECK: RLDICL %0, 48, 16
     ; CHECK-LATE: rldicl 3, 3, 48, 16
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRDo
-# CHECK-ALL: name: testSRDo
+name:            testSRD_rec
+# CHECK-ALL: name: testSRD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 64
-    %3 = SRDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDI8o %0, 0, implicit-def $cr0
+    %3 = SRD_rec %0, killed %2, implicit-def $cr0
+    ; CHECK: ANDI8_rec %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %3 = SRAD %0, killed %2, implicit-def dead $carry
     ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
     ; CHECK-LATE: srad 3, 3, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRADo
-# CHECK-ALL: name: testSRADo
+name:            testSRAD_rec
+# CHECK-ALL: name: testSRAD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 68
-    %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srad. 3, 3, 5
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

--- |
   ; Function Attrs: norecurse nounwind readnone
   define i128 @testADDC8(i128 %a, i128 %b) local_unnamed_addr #0 {
   entry:
     %add = add nsw i128 %b, %a
     ret i128 %add
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testADDCo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testADDC_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %add = add nsw i64 %b, %a
     %cmp = icmp eq i64 %add, 0
     %neg = sext i1 %cmp to i64
     %retval.0 = xor i64 %add, %neg
     ret i64 %retval.0
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define signext i32 @testADDI(i32 signext %a) local_unnamed_addr #0 {
   entry:
     %add = add nsw i32 %a, 44
     ret i32 %add
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define signext i32 @testADDI8(i32 signext %a) local_unnamed_addr #0 {
   entry:
     %add = add nsw i32 %a, 44
     ret i32 %add
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testANDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define signext i32 @testAND_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, %a
     %tobool = icmp eq i64 %and, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     %conv = trunc i64 %cond to i32
     ret i32 %conv
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testAND8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testAND8_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, %a
     %tobool = icmp eq i64 %and, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
entry:
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     ret i64 %or
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     %tobool = icmp eq i64 %or, 0
     %cond = select i1 %tobool, i64 %and, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDCR(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     ret i64 %or
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCR_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
     %sub = sub nsw i64 64, %and
     %shr = lshr i64 %a, %sub
     %or = or i64 %shr, %shl
     %tobool = icmp eq i64 %or, 0
     %cond = select i1 %tobool, i64 %and, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLDICL(i64 %a) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
     ret i64 %and
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
     %tobool = icmp eq i64 %and, 0
     %cond = select i1 %tobool, i64 %b, i64 %and
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICL_rec2(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
     %tobool = icmp eq i64 %and, 0
     %cond = select i1 %tobool, i64 %b, i64 %and
     ret i64 %cond
   }
 
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICL_rec3(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
     %tobool = icmp eq i64 %and, 0
     %cond = select i1 %tobool, i64 %b, i64 %and
     ret i64 %cond
   }
   
--- |
   define i64 @testRLWINM8(i64 %a) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, 4
     %and = and i64 %shl, 4080
     ret i64 %and
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWINMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWINM_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWINM_rec2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
 
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLWINM8_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %a.tr = trunc i64 %a to i32
     %0 = shl i32 %a.tr, 4
     %conv = and i32 %0, 4080
     %tobool = icmp eq i32 %conv, 0
     %conv1 = zext i32 %conv to i64
     %cond = select i1 %tobool, i64 %b, i64 %conv1
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testSLD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     ret i64 %shl
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSLD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     %tobool = icmp eq i64 %shl, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testSRD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     ret i64 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
     %cond = select i1 %tobool, i64 %b, i64 %a
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     ret i32 %shl
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSLW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     %tobool = icmp eq i32 %shl, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define zeroext i32 @testSRW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     ret i32 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSRW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
     %cond = select i1 %tobool, i32 %b, i32 %a
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define signext i32 @testSRAW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     ret i32 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+  define signext i32 @testSRAW_rec(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
     %cond = select i1 %tobool, i32 %b, i32 %shr
     ret i32 %cond
   }
   
   ; Function Attrs: norecurse nounwind readnone
   define i64 @testSRAD(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     ret i64 %shr
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRAD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
     %cond = select i1 %tobool, i64 %b, i64 %shr
     ret i64 %cond
   }
   
   ; Function Attrs: norecurse nounwind
bb.0.entry:
     ; CHECK-LATE: addic 3, 5, 777
     %5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
     $x3 = COPY %4
     $x4 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
 
 ...
 ---
-name:            testADDCo
-# CHECK-ALL: name: testADDCo
+name:            testADDC_rec
+# CHECK-ALL: name: testADDC_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = LI 433
     %0 = COPY $x3
     %2 = COPY %0.sub_32
-    %3 = ADDCo %1, %2, implicit-def $cr0, implicit-def $carry
-    ; CHECK: ADDICo %2, 433, implicit-def $cr0, implicit-def $carry
+    %3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $carry
+    ; CHECK: ADDIC_rec %2, 433, implicit-def $cr0, implicit-def $carry
     ; CHECK-LATE: addic. 3, 3, 433
     %4 = COPY killed $cr0
     %5 = COPY %4.sub_eq
     %6 = LI8 0
     %7 = LI8 -1
     %8 = ISEL8 %7, %6, %5
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
     ; CHECK: LI8 377
     ; CHECK-LATE: li 3, 377
     %3 = EXTSW killed %2
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testANDo
-# CHECK-ALL: name: testANDo
+name:            testAND_rec
+# CHECK-ALL: name: testAND_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = LI 78
     %0 = COPY $x3
     %2 = COPY %0.sub_32
-    %3 = ANDo %1, %2, implicit-def $cr0
-    ; CHECK: ANDIo %2, 78, implicit-def $cr0
+    %3 = AND_rec %1, %2, implicit-def $cr0
+    ; CHECK: ANDI_rec %2, 78, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 78
     %4 = COPY killed $cr0
     %5 = ISEL %2, %1, %4.sub_eq
     %6 = EXTSW_32_64 killed %5
     $x3 = COPY %6
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testAND8o
-# CHECK-ALL: name: testAND8o
+name:            testAND8_rec
+# CHECK-ALL: name: testAND8_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = LI8 321
     %0 = COPY $x3
-    %2 = AND8o %1, %0, implicit-def $cr0
-    ; CHECK: ANDI8o %0, 321, implicit-def $cr0
+    %2 = AND8_rec %1, %0, implicit-def $cr0
+    ; CHECK: ANDI8_rec %0, 321, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 321
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %0, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %4 = RLDCL %0, killed %3, 0
     ; CHECK: RLDICL %0, 14, 0
     ; CHECK-LATE: rotldi 3, 3, 14
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDCLo
-# CHECK-ALL: name: testRLDCLo
+name:            testRLDCL_rec
+# CHECK-ALL: name: testRLDCL_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI 37
-    %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 37, 0, implicit-def $cr0
+    %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 37, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %4 = RLDCR %0, killed %3, 0
     ; CHECK: RLDICR %0, 0, 0
     ; CHECK-LATE: rldicr 3, 3, 0, 0
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDCRo
-# CHECK-ALL: name: testRLDCRo
+name:            testRLDCR_rec
+# CHECK-ALL: name: testRLDCR_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI 18
-    %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 18, 0, implicit-def $cr0
+    %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICR_rec %0, 18, 0, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 18, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %1 = RLDICL %0, 53, 49
     ; CHECK: LI8 32767
     ; CHECK-LATE: li 3, 32767
     $x3 = COPY %1
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDICLo
-# CHECK-ALL: name: testRLDICLo
+name:            testRLDICL_rec
+# CHECK-ALL: name: testRLDICL_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 -1
-    %2 = RLDICLo %0, 53, 48, implicit-def $cr0
-    ; CHECK: ANDI8o %0, 65535
+    %2 = RLDICL_rec %0, 53, 48, implicit-def $cr0
+    ; CHECK: ANDI8_rec %0, 65535
     ; CHECK-LATE: li 3, -1
     ; CHECK-LATE: andi. 3, 3, 65535
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDICLo2
-# CHECK-ALL: name: testRLDICLo2
+name:            testRLDICL_rec2
+# CHECK-ALL: name: testRLDICL_rec2
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 200
-    %2 = RLDICLo %0, 61, 3, implicit-def $cr0
+    %2 = RLDICL_rec %0, 61, 3, implicit-def $cr0
     ; CHECK: LI8 25
-    ; CHECK: ANDI8o %0, 25
+    ; CHECK: ANDI8_rec %0, 25
     ; CHECK-LATE-NOT: andi.
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLDICLo3
-# CHECK-ALL: name: testRLDICLo3
+name:            testRLDICL_rec3
+# CHECK-ALL: name: testRLDICL_rec3
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 2
-    %2 = RLDICLo %0, 32, 32, implicit-def $cr0
-    ; CHECK: ANDI8o %0, 0
+    %2 = RLDICL_rec %0, 32, 32, implicit-def $cr0
+    ; CHECK: ANDI8_rec %0, 0
     ; CHECK-LATE: li 3, 2
     ; CHECK-LATE: andi. 3, 3, 0
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
bb.0.entry:
     %1 = RLWINM8 %0, 4, 20, 27
     ; CHECK: LI8 3744
     ; CHECK-LATE: li 3, 3744
     $x3 = COPY %1
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLWINMo
-# CHECK-ALL: name: testRLWINMo
+name:            testRLWINM_rec
+# CHECK-ALL: name: testRLWINM_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWINMo %3, 0, 24, 31, implicit-def $cr0
+    %4 = RLWINM_rec %3, 0, 24, 31, implicit-def $cr0
     ; CHECK: LI -22
-    ; CHECK: ANDIo %3, 65514
+    ; CHECK: ANDI_rec %3, 65514
     ; CHECK-LATE: li 3, -22
     ; CHECK-LATE: andi. 5, 3, 234
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLWINMo2
-# CHECK-ALL: name: testRLWINMo2
+name:            testRLWINM_rec2
+# CHECK-ALL: name: testRLWINM_rec2
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
+    %4 = RLWINM_rec %3, 5, 24, 31, implicit-def $cr0
     ; CHECK: LI -22
-    ; CHECK-NOT: ANDI8o %3, 65514
+    ; CHECK-NOT: ANDI8_rec %3, 65514
     ; CHECK-LATE-NOT: andi.
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testRLWINM8o
-# CHECK-ALL: name: testRLWINM8o
+name:            testRLWINM8_rec
+# CHECK-ALL: name: testRLWINM8_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
-    %3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0
-    ; CHECK: ANDI8o %2, 3808
+    %3 = RLWINM8_rec %2, 4, 20, 27, implicit-def $cr0
+    ; CHECK: ANDI8_rec %2, 3808
     ; CHECK-LATE: li 3, -18
     ; CHECK-LATE: andi. 3, 3, 3808
     %7 = COPY killed $cr0
     %6 = RLDICL killed %3, 0, 32
     %8 = ISEL8 %1, %6, %7.sub_eq
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %3 = SLD %0, killed %2
     ; CHECK: RLDICR %0, 13, 50
     ; CHECK-LATE: sldi 3, 3, 13
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSLDo
-# CHECK-ALL: name: testSLDo
+name:            testSLD_rec
+# CHECK-ALL: name: testSLD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 17
-    %3 = SLDo %0, killed %2, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 17, 46, implicit-def $cr0
+    %3 = SLD_rec %0, killed %2, implicit-def $cr0
+    ; CHECK: RLDICR_rec %0, 17, 46, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 17, 46
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %3 = SRD %0, killed %2
     ; CHECK: RLDICL %0, 60, 4
     ; CHECK-LATE: rldicl 3, 3, 60, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRDo
-# CHECK-ALL: name: testSRDo
+name:            testSRD_rec
+# CHECK-ALL: name: testSRD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 17
-    %3 = SRDo %0, killed %2, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 47, 17, implicit-def $cr0
+    %3 = SRD_rec %0, killed %2, implicit-def $cr0
+    ; CHECK: RLDICL_rec %0, 47, 17, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 47, 17
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %8 = SLW killed %2, killed %5
     ; CHECK: RLWINM killed %2, 21, 0, 10
     ; CHECK-LATE: slwi 3, 4, 21
     $x3 = EXTSW_32_64 %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSLWo
-# CHECK-ALL: name: testSLWo
+name:            testSLW_rec
+# CHECK-ALL: name: testSLW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 11
     %3 = COPY %0.sub_32
-    %4 = SLWo %3, %2, implicit-def $cr0
-    ; CHECK: RLWINMo %3, 11, 0, 20, implicit-def $cr0
+    %4 = SLW_rec %3, %2, implicit-def $cr0
+    ; CHECK: RLWINM_rec %3, 11, 0, 20, implicit-def $cr0
     ; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
     %8 = SRW killed %5, killed %2
     ; CHECK: RLWINM killed %5, 24, 8, 31
     ; CHECK-LATE: srwi 3, 3, 8
     $x3 = EXTSW_32_64 %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRWo
-# CHECK-ALL: name: testSRWo
+name:            testSRW_rec
+# CHECK-ALL: name: testSRW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 7
     %3 = COPY %0.sub_32
-    %4 = SRWo %3, %2, implicit-def $cr0
-    ; CHECK: RLWINMo %3, 25, 7, 31
+    %4 = SRW_rec %3, %2, implicit-def $cr0
+    ; CHECK: RLWINM_rec %3, 25, 7, 31
     ; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
     ; CHECK: SRAWI killed %3, 15, implicit-def dead $carry
     ; CHECK-LATE: srawi 3, 3, 15
     %5 = EXTSW_32_64 killed %4
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRAWo
-# CHECK-ALL: name: testSRAWo
+name:            testSRAW_rec
+# CHECK-ALL: name: testSRAW_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 8
     %3 = COPY %0.sub_32
-    %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAWIo killed %3, 8, implicit-def dead $carry, implicit-def $cr0
+    %4 = SRAW_rec killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAWI_rec killed %3, 8, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srawi. 3, 3, 8
     %5 = COPY killed $cr0
     %6 = ISEL %2, %4, %5.sub_eq
     %7 = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
bb.0.entry:
     %3 = SRAD %0, killed %2, implicit-def dead $carry
     ; CHECK: SRADI %0, 44, implicit-def dead $carry
     ; CHECK-LATE: sradi 3, 3, 44
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
-name:            testSRADo
-# CHECK-ALL: name: testSRADo
+name:            testSRAD_rec
+# CHECK-ALL: name: testSRAD_rec
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: g8rc, preferred-register: '' }

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 61
-    %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRADIo %0, 61, implicit-def dead $carry, implicit-def $cr0
+    %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRADI_rec %0, 61, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sradi. 3, 3, 61
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

bb.0.entry:
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
     ; CHECK: %2:gprc = RLWINM %1, 27, 5, 10
     %3:gprc = RLWINM %2:gprc, 8, 5, 10
     ; CHECK: %3:gprc = LI 0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
-name: testFoldRLWINMoToZero
-#CHECK : name : testFoldRLWINMoToZero
+name: testFoldRLWINM_recToZero
+#CHECK : name : testFoldRLWINM_recToZero
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
     ; CHECK: %2:gprc = RLWINM %1, 27, 5, 10
-    %3:gprc = RLWINMo %2:gprc, 8, 5, 10, implicit-def $cr0
-    ; CHECK: %3:gprc = ANDIo %2, 0, implicit-def $cr0
+    %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
+    ; CHECK: %3:gprc = ANDI_rec %2, 0, implicit-def $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMInvalidMask
 #CHECK : name : testFoldRLWINMInvalidMask
 tracksRegLiveness: true
 body: |
   bb.0.entry:

llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir

 # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -run-pass=if-converter %s -o - | FileCheck %s
 ---
 name:           foo
 body:           |
   bb.0:
   liveins: $x0, $x3
   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 
-  dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+  dead renamable $x3 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
   $cr2lt = CROR $cr0gt, $cr0gt
   BCn killed renamable $cr2lt, %bb.2
   B %bb.1
 
   bb.1:
     renamable $x3 = LIS8 4096
     MTLR8 $x0, implicit-def $lr8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
   bb.2:
     renamable $x3 = LIS8 4096
     MTLR8 $x0, implicit-def $lr8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 ...
 
 # Diamond testcase with equivalent branches terminating in returns.
 
 # CHECK: body:             |          
 # CHECK:  bb.0:
-# CHECK:    dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+# CHECK:    dead renamable $x3 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
 # CHECK:    $cr2lt = CROR $cr0gt, $cr0gt
 # CHECK:    renamable $x3 = LIS8 4096
 # CHECK:    MTLR8 $x0, implicit-def $lr8
 # CHECK:    BLR8 implicit $lr8, implicit $rm, implicit $x3
 

llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 
 ; CHECK-LABEL: fn1
 define signext i32 @fn1(i32 %baz) {
   %1 = mul nsw i32 %baz, 208
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
 ; CHECK: RLWINM8 killed {{[^,]+}}, 0, 16, 27
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDI8o {{[^,]+}}, 65520, implicit-def $cr0
+; CHECK: ANDI8_rec {{[^,]+}}, 65520, implicit-def $cr0
 ; CHECK: COPY killed $cr0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
   br i1 %5, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; CHECK-LABEL: fn2
 define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
+; CHECK: OR8_rec {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed $cr
 ; CHECK: BCC 12, killed [[CREG]]
   %1 = or i64 %b, %a
   %2 = icmp sgt i64 %1, -1
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
+; CHECK: ANDI_rec killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
 ; CHECK: BCC 76, killed [[CREG]]
   %1 = and i32 %a, 10
   %2 = icmp ne i32 %1, 0
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; This test case confirms that a record-form instruction is
 ; generated even if the branch has a static branch hint.
 
 ; CHECK-LABEL: fn4
 define i64 @fn4(i64 %a, i64 %b) {
-; CHECK: ADD8o
+; CHECK: ADD8_rec
 ; CHECK-NOT: CMP
 ; CHECK: BCC 71
 
 entry:
   %add = add nsw i64 %b, %a
   %cmp = icmp eq i64 %add, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @exit(i32 signext 0) #3
   unreachable
 
 if.end:
   ret i64 %add
 }
 
 declare void @exit(i32 signext)
 
 ; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended.
-; In this case, we want to use ORo instead of OR + CMPLWI.
+; In this case, we want to use OR_rec instead of OR + CMPLWI.
 
 ; CHECK-LABEL: fn5
 define zeroext i32 @fn5(i32* %p1, i32* %p2) {
-; CHECK: ORo
+; CHECK: OR_rec
 ; CHECK-NOT: CMP
 ; CHECK: BCC
   %v1 = load i32, i32* %p1
   %v2 = load i32, i32* %p2
   %1 = or i32 %v1, %v2
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; This test confirms record-form instructions are emitted for comparison
 ; against a non-zero value.
 
 ; CHECK-LABEL: fn6
 define i8* @fn6(i8* readonly %p) {
 ; CHECK: LBZU
-; CHECK: EXTSBo
+; CHECK: EXTSB_rec
 ; CHECK-NOT: CMP
 ; CHECK: BCC
 ; CHECK: LBZU
-; CHECK: EXTSBo
+; CHECK: EXTSB_rec
 ; CHECK-NOT: CMP
 ; CHECK: BCC
 
 entry:
   %incdec.ptr = getelementptr inbounds i8, i8* %p, i64 -1
   %0 = load i8, i8* %incdec.ptr
   %cmp = icmp sgt i8 %0, -1
   br i1 %cmp, label %out, label %if.end

llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir

bb.1.loop:
     %17 = ADDI8 %16, -1
     %18 = ADDI8 %15, -1
     %19 = ANDC8 killed %17, %16
     %20 = ANDC8 killed %18, %15
     %22 = CNTLZD killed %19
     %24 = CNTLZD killed %20
     %25 = CMPLDI %15, 0
     BCC 76, %25, %bb.2.loop
-    ; CHECK: SUBFC8o %3, %1, implicit-def $carry, implicit-def $cr0
+    ; CHECK: SUBFC8_rec %3, %1, implicit-def $carry, implicit-def $cr0
     ; CHECK: COPY killed $cr0
     ; CHECK: BCC
 
   bb.4:
     successors: %bb.3.loop
 
     %27 = SUBF8 %24, %23
     B %bb.3.loop

llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
 # RUN: -simplify-mir %s -o - | FileCheck %s
 ---
 name:            poc
 alignment:       16
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: poc
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1, %bb.2
   ; CHECK:   liveins: $x3, $x4, $x5, $x6
   ; CHECK:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
   ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x5
   ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
   ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
-  ; CHECK:   [[ANDI8o_:%[0-9]+]]:g8rc = ANDI8o [[COPY1]], 1, implicit-def $cr0
+  ; CHECK:   [[ANDI8_rec_:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
   ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
   ; CHECK:   BCn killed [[COPY4]], %bb.2
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
   ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
-  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8o_]], 2, 61
+  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
   ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
   ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2:
   ; CHECK:   [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
   ; CHECK:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
   ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
   ; CHECK:   $x3 = COPY [[INSERT_SUBREG]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $x3, $x4, $x5, $x6
 
     %4:g8rc = COPY $x6
     %3:g8rc = COPY $x5
     %2:g8rc = COPY $x4
     %1:g8rc_and_g8rc_nox0 = COPY $x3
-    %11:g8rc = ANDI8o %3, 1, implicit-def $cr0
+    %11:g8rc = ANDI8_rec %3, 1, implicit-def $cr0
     %6:crbitrc = COPY $cr0gt
     BCn killed %6, %bb.2
     B %bb.1
 
   bb.1:
     liveins: $x3
 
     %0:g8rc = EXTSW $x3

llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc = COPY $x4
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc = LI -11
-    %4:gprc_and_gprc_nor0 = RLWINMo %3, 2, 20, 31, implicit-def $cr0
+    %4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI 4055
-    ; CHECK: ANDIo %3, 4055
+    ; CHECK: ANDI_rec %3, 4055
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
     %6:gprc = ISEL %4, %2, %5.sub_eq
     %7:g8rc = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc = COPY $x4
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc_and_gprc_nor0 = LI 1
-    %4:gprc = RLWINMo %3, 21, 20, 31, implicit-def $cr0
+    %4:gprc = RLWINM_rec %3, 21, 20, 31, implicit-def $cr0
     ; CHECK: LI 1
-    ; CHECK: ANDIo %3, 0
+    ; CHECK: ANDI_rec %3, 0
     ; CHECK-LATE: li [[IMM:[0-9]+]], 1
     ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
     %5:crrc = COPY killed $cr0
     %6:gprc = ISEL %3, %2, %5.sub_eq
     %7:g8rc = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc = COPY $x4
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc_and_gprc_nor0 = LI -11
-    %4:gprc = RLWINMo %3, 2, 20, 31, implicit-def $cr0
+    %4:gprc = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI -11
-    ; CHECK: ANDIo %3, 65525
+    ; CHECK: ANDI_rec %3, 65525
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
     %6:gprc = ISEL %3, %2, %5.sub_eq
     %7:g8rc = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc = LI8 -11
-    %2:g8rc_and_g8rc_nox0  = RLDICLo %0, 2, 49, implicit-def $cr0
+    %2:g8rc_and_g8rc_nox0  = RLDICL_rec %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 32727
-    ; CHECK: ANDI8o %0, 32727
+    ; CHECK: ANDI8_rec %0, 32727
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %2, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 1
-    %2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0
+    %2:g8rc = RLDICL_rec %0, 32, 33, implicit-def $cr0
     ; CHECK: LI8 1
-    ; CHECK: ANDI8o %0, 0
+    ; CHECK: ANDI8_rec %0, 0
     ; CHECK-LATE: li [[IMM:[0-9]+]], 1
     ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %0, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 stack:           
 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 -11
-    %2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0
+    %2:g8rc = RLDICL_rec %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 -11
-    ; CHECK: ANDI8o %0, 65525
+    ; CHECK: ANDI8_rec %0, 65525
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %0, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...