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jhibbits (Justin Hibbits)
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User Since
Sep 8 2014, 1:26 PM (314 w, 5 d)

Recent Activity

Jul 31 2020

jhibbits committed rG7e9153e940e2: PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE (authored by jhibbits).
PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE
Jul 31 2020, 9:04 PM
jhibbits closed D77773: PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE.
Jul 31 2020, 9:04 PM · Restricted Project
jhibbits committed rG914dbf4808d4: PowerPC: Fix SPE extloadf32 handling. (authored by jhibbits).
PowerPC: Fix SPE extloadf32 handling.
Jul 31 2020, 8:54 PM
jhibbits closed D78670: PowerPC: Fix SPE extloadf32 handling..
Jul 31 2020, 8:54 PM · Restricted Project

Jul 21 2020

jhibbits added a comment to D78669: PowerPC: Add emergency stack spill slots for SPE.

As mentioned before, I can only seem to reproduce this running natively on powerpcspe; running the test on powerpc64, even without this patch, succeeds. This is extremely bizarre, but this fix gets the native build to produce the exact same text as running the test on powerpc64.

Jul 21 2020, 8:50 AM · Restricted Project
jhibbits updated the diff for D78669: PowerPC: Add emergency stack spill slots for SPE.

Simplify the test a little.

Jul 21 2020, 8:10 AM · Restricted Project

Jul 10 2020

jhibbits added a comment to D78669: PowerPC: Add emergency stack spill slots for SPE.

Funny thing, I'm able to reproduce it *only* while running natively on a powerpcspe based device, not on any other device I've tested. I'll try to reduce the testcase even further, since it really is unwieldy.

Jul 10 2020, 6:03 PM · Restricted Project
jhibbits added a comment to D78670: PowerPC: Fix SPE extloadf32 handling..

Ping again? Since it's a trivial change, and isolated at that, I'm not opposed to post-commit review instead.

Jul 10 2020, 6:00 PM · Restricted Project
jhibbits accepted D82747: [PowerPC] Support constrained int/fp conversion in SPE targets.

Looks fine to me.

Jul 10 2020, 5:58 PM · Restricted Project

Jun 26 2020

jhibbits added inline comments to D81537: [PowerPC] Support constrained fp operation for scalar fptosi/fptoui.
Jun 26 2020, 2:41 PM · Restricted Project

Jun 25 2020

jhibbits added inline comments to D81537: [PowerPC] Support constrained fp operation for scalar fptosi/fptoui.
Jun 25 2020, 12:28 PM · Restricted Project

Jun 24 2020

jhibbits added inline comments to D81537: [PowerPC] Support constrained fp operation for scalar fptosi/fptoui.
Jun 24 2020, 6:59 AM · Restricted Project

Jun 6 2020

jhibbits added inline comments to D78669: PowerPC: Add emergency stack spill slots for SPE.
Jun 6 2020, 8:48 PM · Restricted Project

May 29 2020

jhibbits added inline comments to D78669: PowerPC: Add emergency stack spill slots for SPE.
May 29 2020, 8:39 AM · Restricted Project

May 26 2020

jhibbits added a comment to D78670: PowerPC: Fix SPE extloadf32 handling..

Ping?

May 26 2020, 7:34 AM · Restricted Project
jhibbits added a comment to D78669: PowerPC: Add emergency stack spill slots for SPE.

Ping?

May 26 2020, 7:34 AM · Restricted Project

May 12 2020

jhibbits committed rG0138cc012506: PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE (authored by jhibbits).
PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE
May 12 2020, 3:38 PM
jhibbits closed D78668: PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE.
May 12 2020, 3:38 PM · Restricted Project

Apr 30 2020

jhibbits updated the diff for D78668: PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE.

Address feedback from @shchenz. Much better!

Apr 30 2020, 6:07 PM · Restricted Project
jhibbits added inline comments to D78668: PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE.
Apr 30 2020, 10:08 AM · Restricted Project

Apr 22 2020

jhibbits created D78670: PowerPC: Fix SPE extloadf32 handling..
Apr 22 2020, 2:09 PM · Restricted Project
jhibbits created D78668: PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE.
Apr 22 2020, 2:09 PM · Restricted Project
jhibbits created D78669: PowerPC: Add emergency stack spill slots for SPE.
Apr 22 2020, 2:09 PM · Restricted Project

Apr 21 2020

jhibbits committed rG4ca2cad947d0: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF (authored by jhibbits).
[PowerPC] Add clang -msvr4-struct-return for 32-bit ELF
Apr 21 2020, 6:25 PM
jhibbits closed D73290: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF.
Apr 21 2020, 6:25 PM · Restricted Project

Apr 8 2020

jhibbits created D77773: PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE.
Apr 8 2020, 9:02 PM · Restricted Project

Apr 7 2020

jhibbits added a reviewer for D73290: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF: nemanjai.

@ZarkoCA I think someone else should also review this, so added @nemanjai as a potential reviewer. He might have more insight to the code in question. I'd like to see this go in soon, though, so that it gets into 11, and we can use it in FreeBSD.

Apr 7 2020, 7:34 AM · Restricted Project
jhibbits updated the summary of D77558: PowerPC: Don't hoist float multiply + add to fused operation on SPE.
Apr 7 2020, 7:34 AM · Restricted Project
jhibbits added a comment to D77558: PowerPC: Don't hoist float multiply + add to fused operation on SPE.

This happens too late for the CTR usability test to veto using the CTR in a loop, and results in an assert "Invalid PPC CTR loop!".

This means after not hoisting fmul makes a case have "Invalid PPC CTR loop!" assertion? This is a little surprised for me. Hoist or not hoist fmul should not impact CTR register.
Looking forward to your case.

Apr 7 2020, 7:34 AM · Restricted Project

Apr 6 2020

jhibbits created D77558: PowerPC: Don't hoist float multiply + add to fused operation on SPE.
Apr 6 2020, 8:38 AM · Restricted Project

Apr 3 2020

jhibbits added a comment to D77433: PowerPCSPE: Stop libunwind from complaining about SPE registers.

Im surprised that no tests need changing here. Could you please add a clang/llvm test to validate that the generated information matches what libunwind will start looking for?

Apr 3 2020, 9:38 PM · Restricted Project, Restricted Project
jhibbits accepted D73290: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF.

Code looks fine, and others have tested it. Good to see a reversion of the ABI to expected for GCC compatibility on the BSDs.

Apr 3 2020, 9:38 PM · Restricted Project
jhibbits created D77433: PowerPCSPE: Stop libunwind from complaining about SPE registers.
Apr 3 2020, 3:11 PM · Restricted Project, Restricted Project

Mar 26 2020

jhibbits committed rG459e8e94886f: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 (authored by jhibbits).
[PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32
Mar 26 2020, 9:13 AM
jhibbits closed D76662: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32.
Mar 26 2020, 9:13 AM · Restricted Project

Mar 25 2020

jhibbits added a comment to D76773: [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled, fix PR45297.

Can you fix the title of this? "Fix PR45297" is not very descriptive unless someone also reviews the PR.

Mar 25 2020, 8:04 AM · Restricted Project

Mar 24 2020

jhibbits updated the diff for D76662: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32.

Update tests. Updated other tests in the same file that looked suspect as well.

Mar 24 2020, 12:53 PM · Restricted Project

Mar 23 2020

jhibbits created D76662: [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32.
Mar 23 2020, 6:32 PM · Restricted Project
jhibbits committed rGf0990e104b08: [PowerPC]: e500 target can't use lwsync, use msync instead (authored by jhibbits).
[PowerPC]: e500 target can't use lwsync, use msync instead
Mar 23 2020, 3:17 PM
jhibbits closed D76614: [PowerPC]: e500 target can't use lwsync, use msync instead.
Mar 23 2020, 3:17 PM · Restricted Project
jhibbits created D76614: [PowerPC]: e500 target can't use lwsync, use msync instead.
Mar 23 2020, 8:08 AM · Restricted Project

Feb 4 2020

jhibbits committed rGb8dc54cf39b4: PowerPC: Remove redundancy in ternary for predicate selection (authored by jhibbits).
PowerPC: Remove redundancy in ternary for predicate selection
Feb 4 2020, 8:40 AM

Jan 22 2020

jhibbits accepted D73170: Handle subregs and superregs in callee-saved register mask.

Thanks for doing this! It's been on my TODO list for a little while already for SPE, but I never got around to it.

Jan 22 2020, 7:12 AM · Restricted Project

Jan 14 2020

jhibbits added inline comments to D72673: [PowerPC] Fix powerpcspe subtarget enablement in llvm backend.
Jan 14 2020, 7:43 AM · Restricted Project

Jan 13 2020

jhibbits created D72673: [PowerPC] Fix powerpcspe subtarget enablement in llvm backend.
Jan 13 2020, 6:14 PM · Restricted Project

Jan 10 2020

jhibbits accepted D72433: [Driver][PowerPC] Move powerpcspe logic from cc1 to Driver.

Fine with me. I just wanted -target powerpcspe-... to work with D72014.

Jan 10 2020, 11:46 AM · Restricted Project

Jan 8 2020

jhibbits updated subscribers of D72014: [PowerPC]: Add powerpcspe target triple subarch component.
Jan 8 2020, 8:09 AM · Restricted Project, Restricted Project

Jan 7 2020

jhibbits accepted D72363: [PowerPC] Default ppc64 linux-gnu/freebsd to -fno-PIC.
Jan 7 2020, 2:54 PM · Restricted Project

Jan 6 2020

jhibbits resigned from D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

Not happy, but won't hold it up.

Jan 6 2020, 7:11 AM · Restricted Project

Jan 5 2020

jhibbits added a comment to D72014: [PowerPC]: Add powerpcspe target triple subarch component.

Any more feedback on this?

Jan 5 2020, 11:39 AM · Restricted Project, Restricted Project

Jan 2 2020

jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

@Jim Yeah, I know. I normally do fix the commit message, but forgot before pushing this one. I'll have to check, but I thought arc had a way to update the commit message when generating the review.

Jan 2 2020, 7:30 PM · Restricted Project
jhibbits closed D69483: [PowerPC]: Fix predicate handling with SPE.

Committed as 2c4620ad57b

Jan 2 2020, 5:38 PM · Restricted Project
jhibbits updated the diff for D69483: [PowerPC]: Fix predicate handling with SPE.

Address comments. As part of this I ran 'update_llc_test_checks.py' on the
whole spe.ll file. I'm not sure if that's necessary for this, but I included
the output anyway. If it's better as a separate change I can do that.

Jan 2 2020, 1:21 PM · Restricted Project

Dec 31 2019

jhibbits updated the diff for D72014: [PowerPC]: Add powerpcspe target triple subarch component.

Add triple unit test. I chose freebsd as the OS since that's my environment.

Dec 31 2019, 8:46 AM · Restricted Project, Restricted Project

Dec 30 2019

jhibbits added inline comments to D69483: [PowerPC]: Fix predicate handling with SPE.
Dec 30 2019, 8:32 PM · Restricted Project
jhibbits updated the diff for D72014: [PowerPC]: Add powerpcspe target triple subarch component.

Reuse the SPE feature test preprocessor test check instead of duplicating it.
powerpcspe-* is exactly equivalent to the -mspe command line argument.

Dec 30 2019, 7:36 PM · Restricted Project, Restricted Project
jhibbits added inline comments to D72014: [PowerPC]: Add powerpcspe target triple subarch component.
Dec 30 2019, 7:27 PM · Restricted Project, Restricted Project
jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

Looks like to me that Vector Compare in SPE also has different CR bit semantics .
So this patch will only handle floating point part for SPE? If so, maybe we should make it explicit in title.

Dec 30 2019, 1:48 PM · Restricted Project
jhibbits updated the diff for D72014: [PowerPC]: Add powerpcspe target triple subarch component.

Fix a test typo made at the last minute.

Dec 30 2019, 1:20 PM · Restricted Project, Restricted Project
jhibbits created D72014: [PowerPC]: Add powerpcspe target triple subarch component.
Dec 30 2019, 1:14 PM · Restricted Project, Restricted Project
jhibbits accepted D72008: [PowerPC][docs] Update Embedded PowerPC docs in Compiler Writers Info page.
Dec 30 2019, 11:21 AM · Restricted Project
jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

Ping on this? I've been using this patch for quite some time now, and really want to get it in before 10.

Dec 30 2019, 7:16 AM · Restricted Project

Dec 27 2019

jhibbits added a comment to D71287: [PowerPC] Use fcti[dw] instructions in additional cases.

The conflict I see is the other patch uses VSX for the operations, but this uses instructions that have been around as far back as the PPC970.

Dec 27 2019, 9:58 AM · Restricted Project

Dec 19 2019

jhibbits added a comment to D69484: [PowerPC] Relax the restrictions on loading doubles with SPE.

@kthomsen do you have any tests we can massage for this?

Dec 19 2019, 7:44 AM · Restricted Project

Dec 18 2019

jhibbits updated the diff for D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.

Updated diff after clang-format. I actually had run git-clang-format on it
before submitting, but forgot to amend it to the change before submitting
for review.

Dec 18 2019, 8:28 AM · Restricted Project
jhibbits updated the diff for D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.

Update diff. It would help if I actually compiled when rebasing...

Dec 18 2019, 8:04 AM · Restricted Project

Dec 17 2019

jhibbits updated the diff for D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.

Rebase

Dec 17 2019, 12:17 PM · Restricted Project

Dec 16 2019

jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

Thanks @Jim, yes the code was copied from a comment in another review and I didn't run clang-format on it. Thanks for pointing out 'git-clang-format', I didn't know about that before.

Dec 16 2019, 7:38 AM · Restricted Project
jhibbits updated the diff for D69483: [PowerPC]: Fix predicate handling with SPE.

Apply style fixes.

Dec 16 2019, 7:38 AM · Restricted Project

Dec 13 2019

jhibbits updated the diff for D69483: [PowerPC]: Fix predicate handling with SPE.

Add tests, taken from the C test in comments in D54583.

Dec 13 2019, 8:24 AM · Restricted Project

Dec 10 2019

jhibbits added a comment to D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.

@MaskRay , @jhibbits Thank you for providing the correct ABI doc, and for the answers. I'll start going through it.

  • It is an error to not use a PLTREL relocation for a call that needs to be indirected through the PLT. The linker will complain to recompile with -fPIC.

Means you can't link static execs against shared objects anymore. Is this the intent? Or am I missing something obvious?

Dec 10 2019, 1:15 PM · Restricted Project
jhibbits added a comment to D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.

@Bdragon28 we might need to use -mlongcall for modules, if we aren't already. This should(?) force the compiler to generate the appropriate long-distance code sequences. I'm not sure, though, if clang supports this yet.

Dec 10 2019, 10:37 AM · Restricted Project

Dec 5 2019

jhibbits added a comment to D69486: PowerPC: Fix SPE f64 VAARG handling..

Hi Stefan, thanks for the review. You're right this and the other two reviews (D69483, D69484) need tests. @kthomsen created these, I'm trying to marshall them in. He has some tests, but not in a state that's committable yet, and is working on that/looking for help to create reduced cases.

Dec 5 2019, 1:03 PM · Restricted Project
jhibbits added a reviewer for D69486: PowerPC: Fix SPE f64 VAARG handling.: Restricted Project.
Dec 5 2019, 9:55 AM · Restricted Project
jhibbits added a reviewer for D69484: [PowerPC] Relax the restrictions on loading doubles with SPE: Restricted Project.
Dec 5 2019, 9:55 AM · Restricted Project
jhibbits added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I might object less to a _rec suffix. However, you would still need to understand what "record form" means, which requires understanding of the ISA. Why not simply add a comment block to the top of PPCInstrInfo.td, describing things like this? I have a feeling other newbies would have similar questions/concerns/complaints, and they can't all be addressed by renaming everything.

Dec 5 2019, 9:55 AM · Restricted Project

Dec 3 2019

jhibbits added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I personally think the status quo is easy to read. The definitions look like the instructions themselves, and the added verbosity seems very unnecessary. I don't know about others, but I consider people working in the PPCInstr*.td files to be either knowing exactly what they're looking for (grepping), or have a sufficient handle on the ISA that the existing notation is clear. At most I could see changing the 'o' suffix to '_o', which might help newcomers familiar with '_' notation to indicate a diminutive or subscript, but '_record' is very verbose, and as @nemanjai points out, can make some text very ugly.

Dec 3 2019, 11:29 AM · Restricted Project
jhibbits accepted D70928: [PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o.
Dec 3 2019, 7:46 AM · Restricted Project
jhibbits added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I still hold pretty strongly that this change is a more negative impact than positive. As shown in the tests, it's very easy to read the generated statements as "FOO-dot", and search for what 'foo.' actually is. The only difficult part is the '*8' vs '*4', since you can't search for that, and need to remember to drop the number, which isn't difficult after the first time.

Dec 3 2019, 7:27 AM · Restricted Project

Dec 2 2019

jhibbits added a comment to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

When discussing optimizations related to "ADD-o", if it's "ADDO" I'd call it "ADD-O", but if it's "ADDo" I'd call it "ADD-dot", since all record forms are referred to as 'dot's, even in all the documentation I've seen. For instance, immediately above this text box is the "rlwinm_rldicl_to_andi.mir" test, with the change of "ANDIo8..." to "ANDIr8".... I read that instinctively as "ANDI-dot-8", whereas "ANDIr8" looks like "ANDI-R-8" which doesn't have a corresponding instruction in the ISA. Additionally, the asm string in PPCInstrInfo.td is "andi. ...", which would make someone question what the 'r' is for, when it doesn't even exist in the instruction. Seeing a 'ANDIo' alongside "andi." someone will easily see the 'o' stands for the '.'.

Dec 2 2019, 2:44 PM · Restricted Project
jhibbits requested changes to D70758: [PowerPC][NFC] Rename record instructions to use _rec suffix instead of o.

I second @nemanjai, the lowercase 'o' suffix stands out to me as a clear indicator of it being punctuation, not a letter in the instruction. I would much rather see ANDIo than ANDIr, the 'r' just doesn't look right when reading over it. My vote is to reject. It looks like a lot of churn without much benefit.

Dec 2 2019, 1:57 PM · Restricted Project

Nov 28 2019

jhibbits added a comment to D38554: Fixed ppc32 function relocations in non-pic mode.

Without this or D70570, secure-PLT does not work. the @plt relocation annotations cause GNU ld to force BSS-PLT instead.

Nov 28 2019, 7:28 AM

Nov 24 2019

jhibbits updated the diff for D69483: [PowerPC]: Fix predicate handling with SPE.

Update diff with @kthomsen's comment. With this, and D69484, D69486, and
D70570, clang can now build a fully working powerpcspe FreeBSD world.

Nov 24 2019, 12:44 PM · Restricted Project

Nov 21 2019

jhibbits created D70570: [PowerPC] Only use PLT annotations if using PIC relocation model.
Nov 21 2019, 2:39 PM · Restricted Project

Nov 16 2019

jhibbits accepted D70352: [PowerPC] Rename DarwinDirective to CPUDirective (NFC).
Nov 16 2019, 9:58 AM · Restricted Project

Nov 11 2019

jhibbits added a comment to D67787: Add 8548 CPU definition and attributes.

@vit9696 mind reviewing again with the added tests?

Nov 11 2019, 2:19 PM · Restricted Project
jhibbits requested review of D67787: Add 8548 CPU definition and attributes.
Nov 11 2019, 2:19 PM · Restricted Project

Nov 9 2019

jhibbits updated the diff for D67787: Add 8548 CPU definition and attributes.

Add clang-translation tests for e500 and 8548 CPU definitions.

Nov 9 2019, 11:53 AM · Restricted Project

Oct 29 2019

jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

@kthomsen you can use 'clang -emit-llvm' to emit LLVM IR from your C test cases. There are reducer passes that you can run on that as well, to reduce the test case to the smallest needed, but I can't recall what they are.

Oct 29 2019, 12:19 PM · Restricted Project

Oct 28 2019

jhibbits added a comment to D69483: [PowerPC]: Fix predicate handling with SPE.

Thanks, @kthomsen. Can you provide a LLVM IR test case for this? And test cases for the other two reviews I added you on, since you wrote the patches initially?

Oct 28 2019, 7:07 AM · Restricted Project

Oct 27 2019

jhibbits created D69486: PowerPC: Fix SPE f64 VAARG handling..
Oct 27 2019, 12:53 PM · Restricted Project
jhibbits created D69484: [PowerPC] Relax the restrictions on loading doubles with SPE.
Oct 27 2019, 12:48 PM · Restricted Project
jhibbits created D69483: [PowerPC]: Fix predicate handling with SPE.
Oct 27 2019, 12:48 PM · Restricted Project
jhibbits updated the diff for D67787: Add 8548 CPU definition and attributes.

Don't double-check 8548 CPU for setting LLVM CPU type.

Oct 27 2019, 12:39 PM · Restricted Project
jhibbits added inline comments to D67787: Add 8548 CPU definition and attributes.
Oct 27 2019, 12:39 PM · Restricted Project

Oct 25 2019

jhibbits updated the diff for D67787: Add 8548 CPU definition and attributes.

Make 8548 actually denote e500 LLVM target, add SPE checks to 8548 preprocessor test.

Oct 25 2019, 8:48 PM · Restricted Project

Oct 24 2019

jhibbits added a comment to D67787: Add 8548 CPU definition and attributes.

A side note regarding SPE support. I am currently upgrading to LLVM 9.0 and I discovered that this patch was not committed anyhow at all:
https://reviews.llvm.org/D54583#1444288

Oct 24 2019, 12:18 PM · Restricted Project

Oct 23 2019

jhibbits added a comment to D67787: Add 8548 CPU definition and attributes.

@vit9696 The only thing GCC defines for mcpu=8548 is NO_LWSYNC, the SPE-specific #defines are from -mspe. That said, since I explicitly do enable SPE for e500 CPU, I guess it makes sense to add it to the test.

Oct 23 2019, 2:05 PM · Restricted Project

Sep 19 2019

jhibbits added a comment to D67787: Add 8548 CPU definition and attributes.

I made 8548 an alias in clang to e500, because e500 is recognized in llvm as a CPU, so gets us the feature list and, more importantly, the instruction scheduler.

Sep 19 2019, 8:23 PM · Restricted Project
jhibbits created D67787: Add 8548 CPU definition and attributes.
Sep 19 2019, 8:23 PM · Restricted Project