[MI] New flag mayAccessMemory

[uweigand]

Summary

Machine instructions today can be marked as "mayLoad" or "mayStore" to indicate memory accesses. If there is a MachineMemOperand attached to the an instruction so marked, its properties will further restrict the type of memory access performed, but it there is no such operand, the instruction will be assumed to load from or store to any part of memory.

The new flag mayAccessMemory introduced here has somewhat different semantics. If there is a MachineMemOperand attached to the instruction, the instruction will be assumed to access the memory described by the operand (as if there were a mayLoad/mayStore). But if there is no such operand, then the instruction will instead be assumed to have no memory-related side effect.

This allows defining instructions that *optionally* access memory. The plan is use this to implement strict floating-point handling in the back end (as part of https://reviews.llvm.org/D45576). A target may mark floating-point instructions as "mayAccessMemory". The common code DAG expansion will add a MachineMemOperand (refering a floating-point status PseudoSourceValue marker) to the instruction if strict FP operation is desired, but will add no such operand for regular (non-strict) FP operations. This means that the usual memory access logic will create the required dependencies for strict operations, but no such dependencies for regular operations -- allowing a target to handle both cases without duplicating all FP insn definitions.

Patch split off from D45576 to simplify review, but this patch on its own isn't really useful and will only be committed together with D45576 (assuming both are approved).

include/llvm/CodeGen/MachineInstr.h

 #include "llvm/ADT/DenseMapInfo.h"
 #include "llvm/ADT/PointerSumType.h"
 #include "llvm/ADT/ilist.h"
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/ArrayRecycler.h"
 #include "llvm/Support/TrailingObjects.h"
 #include <algorithm>
public:
 
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis
   //===--------------------------------------------------------------------===//
 
   /// Return true if this instruction could possibly read memory.
   /// Instructions with this flag set are not necessarily simple load
   /// instructions, they may load a value and modify it, for example.
+  /// Also returns true if an instruction is marked mayAccessMemory
+  /// *and* carries a memory operand representing a load.
   bool mayLoad(QueryType Type = AnyInBundle) const {
     if (isInlineAsm()) {
       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
       if (ExtraInfo & InlineAsm::Extra_MayLoad)
         return true;
     }
+    if (hasProperty(MCID::MayAccessMemory, Type)) {
+      for (const auto *MMO : memoperands())
+        if (MMO->isLoad())
+          return true;
+    }
     return hasProperty(MCID::MayLoad, Type);
   }
 
   /// Return true if this instruction could possibly modify memory.
   /// Instructions with this flag set are not necessarily simple store
   /// instructions, they may store a modified value based on their operands, or
   /// may not actually modify anything, for example.
+  /// Also returns true if an instruction is marked mayAccessMemory
+  /// *and* carries a memory operand representing a store.
   bool mayStore(QueryType Type = AnyInBundle) const {
     if (isInlineAsm()) {
       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
       if (ExtraInfo & InlineAsm::Extra_MayStore)
         return true;
     }
+    if (hasProperty(MCID::MayAccessMemory, Type)) {
+      for (const auto *MMO : memoperands())
+        if (MMO->isStore())
+          return true;
+    }
     return hasProperty(MCID::MayStore, Type);
   }
 
   /// Return true if this instruction could possibly read or modify memory.
   bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
     return mayLoad(Type) || mayStore(Type);
   }
 

include/llvm/MC/MCInstrDesc.h

enum Flag {
   MoveImm,
   MoveReg,
   Bitcast,
   Select,
   DelaySlot,
   FoldableAsLoad,
   MayLoad,
   MayStore,
+  MayAccessMemory,
   Predicable,
   NotDuplicable,
   UnmodeledSideEffects,
   Commutable,
   ConvertibleTo3Addr,
   UsesCustomInserter,
   HasPostISelHook,
   Rematerializable,
public:
   bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
 
   /// Return true if this instruction could possibly modify memory.
   /// Instructions with this flag set are not necessarily simple store
   /// instructions, they may store a modified value based on their operands, or
   /// may not actually modify anything, for example.
   bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
 
+  /// Return true if this instruction may optionally access memory.
+  /// Such instructions are only considered to actually access memory
+  /// if they carry MachineMemOperand entries.
+  bool mayAccessMemory() const {
+    return Flags & (1ULL << MCID::MayAccessMemory);
+  }
+
   /// Return true if this instruction has side
   /// effects that are not modeled by other flags.  This does not return true
   /// for instructions whose effects are captured by:
   ///
   ///  1. Their operand list and implicit definition/use list.  Register use/def
   ///     info is explicit for instructions.
   ///  2. Memory accesses.  Use mayLoad/mayStore.
   ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.

include/llvm/Target/Target.td

class Instruction {
   bit isSelect     = 0;     // Is this instruction a select instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isAdd        = 0;     // Is this instruction an add instruction?
   bit isTrap       = 0;     // Is this instruction a trap instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = ?;     // Is it possible for this inst to read memory?
   bit mayStore     = ?;     // Is it possible for this inst to write memory?
+  bit mayAccessMemory = 0;  // Can this inst have optional memory operands?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit isReMaterializable = 0; // Is this instruction re-materializable?
   bit isPredicable = 0;     // Is this instruction predicable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomInserter = 0; // Pseudo instr needing special help.
   bit hasPostISelHook = 0;  // To be *adjusted* after isel by target hook.

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

case OPC_MorphNodeTo0: case OPC_MorphNodeTo1: case OPC_MorphNodeTo2: {
       //
       // FIXME: This is vastly incorrect for patterns with multiple outputs
       // instructions that access memory and for ComplexPatterns that match
       // loads.
       if (EmitNodeInfo & OPFL_MemRefs) {
         // Only attach load or store memory operands if the generated
         // instruction may load or store.
         const MCInstrDesc &MCID = TII->get(TargetOpc);
-        bool mayLoad = MCID.mayLoad();
-        bool mayStore = MCID.mayStore();
+        bool mayLoad = MCID.mayAccessMemory() || MCID.mayLoad();
+        bool mayStore = MCID.mayAccessMemory() || MCID.mayStore();
 
         // We expect to have relatively few of these so just filter them into a
         // temporary buffer so that we can easily add them to the instruction.
         SmallVector<MachineMemOperand *, 4> FilteredMemRefs;
         for (MachineMemOperand *MMO : MatchedMemRefs) {
           if (MMO->isLoad()) {
             if (mayLoad)
               FilteredMemRefs.push_back(MMO);

utils/TableGen/CodeGenInstruction.h

public:
     bool isCall : 1;
     bool isAdd : 1;
     bool isTrap : 1;
     bool canFoldAsLoad : 1;
     bool mayLoad : 1;
     bool mayLoad_Unset : 1;
     bool mayStore : 1;
     bool mayStore_Unset : 1;
+    bool mayAccessMemory : 1;
     bool isPredicable : 1;
     bool isConvertibleToThreeAddress : 1;
     bool isCommutable : 1;
     bool isTerminator : 1;
     bool isReMaterializable : 1;
     bool hasDelaySlot : 1;
     bool usesCustomInserter : 1;
     bool hasPostISelHook : 1;

utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
   FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
   mayLoad_Unset = Unset;
   mayStore     = R->getValueAsBitOrUnset("mayStore", Unset);
   mayStore_Unset = Unset;
+  mayAccessMemory = R->getValueAsBit("mayAccessMemory");
   hasSideEffects = R->getValueAsBitOrUnset("hasSideEffects", Unset);
   hasSideEffects_Unset = Unset;
 
   isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
   hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq");
   hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq");
   isCodeGenOnly = R->getValueAsBit("isCodeGenOnly");
   isPseudo = R->getValueAsBit("isPseudo");

utils/TableGen/DAGISelMatcherGen.cpp

 }
 
 static bool
 mayInstNodeLoadOrStore(const TreePatternNode *N,
                        const CodeGenDAGPatterns &CGP) {
   Record *Op = N->getOperator();
   const CodeGenTarget &CGT = CGP.getTargetInfo();
   CodeGenInstruction &II = CGT.getInstruction(Op);
-  return II.mayLoad || II.mayStore;
+  return II.mayLoad || II.mayStore || II.mayAccessMemory;
 }
 
 static unsigned
 numNodesThatMayLoadOrStore(const TreePatternNode *N,
                            const CodeGenDAGPatterns &CGP) {
   if (N->isLeaf())
     return 0;
 

utils/TableGen/InstrInfoEmitter.cpp

void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
+  if (Inst.mayAccessMemory)    OS << "|(1ULL<<MCID::MayAccessMemory)";
   if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
   if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
   if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
   if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";
   if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
   if (Inst.isNotDuplicable)    OS << "|(1ULL<<MCID::NotDuplicable)";
   if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
   if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";