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uweiganduweigand
committedJun 5, 2019
Allow target to handle STRICT floating-point nodes
The ISD::STRICT_ nodes used to implement the constrained floating-point intrinsics are currently never passed to the target back-end, which makes it impossible to handle them correctly (e.g. mark instructions are depending on a floating-point status and control register, or mark instructions as possibly trapping). This patch allows the target to use setOperationAction to switch the action on ISD::STRICT_ nodes to Legal. If this is done, the SelectionDAG common code will stop converting the STRICT nodes to regular floating-point nodes, but instead pass the STRICT nodes to the target using normal SelectionDAG matching rules. To avoid having the back-end duplicate all the floating-point instruction patterns to handle both strict and non-strict variants, we make the MI codegen explicitly aware of the floating-point exceptions by introducing two new concepts: - A new MCID flag "mayRaiseFPException" that the target should set on any instruction that possibly can raise FP exception according to the architecture definition. - A new MI flag FPExcept that CodeGen/SelectionDAG will set on any MI instruction resulting from expansion of any constrained FP intrinsic. Any MI instruction that is *both* marked as mayRaiseFPException *and* FPExcept then needs to be considered as raising exceptions by MI-level codegen (e.g. scheduling). Setting those two new flags is straightforward. The mayRaiseFPException flag is simply set via TableGen by marking all relevant instruction patterns in the .td files. The FPExcept flag is set in SDNodeFlags when creating the STRICT_ nodes in the SelectionDAG, and gets inherited in the MachineSDNode nodes created from it during instruction selection. The flag is then transfered to an MIFlag when creating the MI from the MachineSDNode. This is handled just like fast-math flags like no-nans are handled today. This patch includes both common code changes required to implement the new features, and the SystemZ implementation. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D55506 llvm-svn: 362663
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‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,10 @@ class MachineInstr
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// no unsigned wrap.
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NoSWrap = 1 << 12, // Instruction supports binary operator
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// no signed wrap.
105-
IsExact = 1 << 13 // Instruction supports division is
105+
IsExact = 1 << 13, // Instruction supports division is
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// known to be exact.
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FPExcept = 1 << 14, // Instruction may raise floating-point
108+
// exceptions.
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};
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private:
@@ -830,6 +832,17 @@ class MachineInstr
830832
return mayLoad(Type) || mayStore(Type);
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}
832834

835+
/// Return true if this instruction could possibly raise a floating-point
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/// exception. This is the case if the instruction is a floating-point
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/// instruction that can in principle raise an exception, as indicated
838+
/// by the MCID::MayRaiseFPException property, *and* at the same time,
839+
/// the instruction is used in a context where we expect floating-point
840+
/// exceptions might be enabled, as indicated by the FPExcept MI flag.
841+
bool mayRaiseFPException() const {
842+
return hasProperty(MCID::MayRaiseFPException) &&
843+
getFlag(MachineInstr::MIFlag::FPExcept);
844+
}
845+
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//===--------------------------------------------------------------------===//
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// Flags that indicate whether an instruction can be modified by a method.
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//===--------------------------------------------------------------------===//

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -368,14 +368,21 @@ struct SDNodeFlags {
368368
bool ApproximateFuncs : 1;
369369
bool AllowReassociation : 1;
370370

371+
// We assume instructions do not raise floating-point exceptions by default,
372+
// and only those marked explicitly may do so. We could choose to represent
373+
// this via a positive "FPExcept" flags like on the MI level, but having a
374+
// negative "NoFPExcept" flag here (that defaults to true) makes the flag
375+
// intersection logic more straightforward.
376+
bool NoFPExcept : 1;
377+
371378
public:
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/// Default constructor turns off all optimization flags.
373380
SDNodeFlags()
374381
: AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
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Exact(false), NoNaNs(false), NoInfs(false),
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NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
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AllowContract(false), ApproximateFuncs(false),
378-
AllowReassociation(false) {}
385+
AllowReassociation(false), NoFPExcept(true) {}
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380387
/// Propagate the fast-math-flags from an IR FPMathOperator.
381388
void copyFMF(const FPMathOperator &FPMO) {
@@ -438,6 +445,10 @@ struct SDNodeFlags {
438445
setDefined();
439446
AllowReassociation = b;
440447
}
448+
void setFPExcept(bool b) {
449+
setDefined();
450+
NoFPExcept = !b;
451+
}
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// These are accessors for each flag.
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bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
@@ -451,9 +462,10 @@ struct SDNodeFlags {
451462
bool hasAllowContract() const { return AllowContract; }
452463
bool hasApproximateFuncs() const { return ApproximateFuncs; }
453464
bool hasAllowReassociation() const { return AllowReassociation; }
465+
bool hasFPExcept() const { return !NoFPExcept; }
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455467
bool isFast() const {
456-
return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs &&
468+
return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
457469
AllowContract && ApproximateFuncs && AllowReassociation;
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}
459471

@@ -473,6 +485,7 @@ struct SDNodeFlags {
473485
AllowContract &= Flags.AllowContract;
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ApproximateFuncs &= Flags.ApproximateFuncs;
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AllowReassociation &= Flags.AllowReassociation;
488+
NoFPExcept &= Flags.NoFPExcept;
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}
477490
};
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