[MIPS] Handle cross-mode (regular <-> microMIPS) jumps

[atanasyan]

Summary

1. MIPS ABI allows to mix regular and microMIPS code and perform cross-mode jumps. Linker needs to detect such cases and replace jump/branch instructions by their cross-mode equivalents.

2. Other tools like dunamic linkers need to recognize cases when dynamic table entries, e_entry field of an ELF header etc point to microMIPS symbol. Linker should provide such information.

The first task is implemented in the MIPS<ELFT>::relocateOne() method. New routine fixupCrossModeJump detects ISA mode change, checks and replaces an instruction.

The main problem is how to recognize that relocation target is microMIPS symbol. For absolute and section symbols compiler or assembler set the less-significant bit of the symbol's value or sum of the symbol's value and addend. And this bit signals to linker about microMIPS code. For global symbols compiler cannot do the same trick because other tools like, for example, disassembler wants to know an actual position of the symbol. So compiler sets STO_MIPS_MICROMIPS flag in the st_other field.

In MIPS<ELFT>::relocateOne() method we have a symbol's value only and cannot access any symbol's attributes. To pass type of the symbol (regular/microMIPS) to that routine as well as other places where we write a symbol value as-is (.dynamic section, Elf_Ehdr::e_entry field etc) we set when necessary a less-significant bit in the getSymVA function.

[ruiu]

ELF/Arch/Mips.cpp

474

Can you write default at end?

497

This needs a comment so that not only a person who understand the details of MIPS ABI can edit this function.

[ruiu]

ELF/Symbols.cpp

107 ↗

(On Diff #123236)

I do understand why you need this by reading comment, but doing this in this function doesn't feel right. This function returns an address of a symbol, and the tag whether the target is microMIPS or not is not logically part of its address. Can't you do this when you apply relocations?

[atanasyan]

ELF/Arch/Mips.cpp

474

Can you write default at end?

Will do.

497

This needs a comment so that not only a person who understand the details of MIPS ABI can edit this function.

OK

ELF/Symbols.cpp

107 ↗

(On Diff #123236)

Can't you do this when you apply relocations?

I had such patch. In that case we need:

• Add the less-significant bit in the InputSectionBase::relocateAlloc() or getRelocTargetVA before calling the relocateOne. We can't do that in the MIPS::relocateOne because we do not have any information about target there.
• Add the less-significant bit in the Writer::getEntryAddr. The Elf_Ehdr::e_entry field holds just a value so we have to signal a loader that the entry symbol is microMIPS.
• Add the less-significant bit in the DynamicSection::writeTo. By the same reason as above.

This way looks more correct, but introduces more changes in the code. Do you think it's acceptable?

[atanasyan]

In this variant of the patch I do not modify the getSymVA function. Instead of that the less-significant bit is configured right before using in the following methods:

• InputSection::relocateNonAlloc
• InputSectionBase::relocateAlloc
• DynamicSection<ELFT>::addSym
• Writer<ELFT>::getEntryAddr

It's more correct solution but it adds more if (MIPS) statements in the code.

[atanasyan]

• Updated the patch against the trunk.

[ruiu]

ELF/Arch/Mips.cpp

497

I'd return a new Val instead of mutating a given value through a pointer.

ELF/InputSection.cpp

694–697

Is this really unavaoidable to add this MIPS-specific code to this generic function?

723

Ditto -- adding more code to this function makes this function hard to understand.

ELF/SyntheticSections.cpp

1025

Ditto

[atanasyan]

ELF/Arch/Mips.cpp

497

OK

ELF/InputSection.cpp

694–697

There are alternatives:

• Setup the bit in the getSymVA or in the Symbol::getVA like I did in the first version of the patch.
• Pass more information about the symbol to the relocateOne routine and setup the bit there.
• Create and use R_MICROMIPS_xxx relocations expressions. In that case we need to add 5-7 new expressions.

I could try to create a patch with the third solution if you think it might make a sense.

ELF/SyntheticSections.cpp

1025

When dynamic linker reads "symbol" tags it needs to know a type of the symbol to use, for example, a correct instruction for jumping. It gets a symbol's value only so we have to setup the less-significant bit to pass the symbol's type to it. The first alternative solution is to setup the bit in every place where we call DynamicSection<ELFT>::addSym. The second alternative is to setup the bit in the getSymVA or in the Symbol::getVA.

[atanasyan]

One more variant of the patch. The if Mips code were removed from InputSectionBase::relocate and InputSection::relocateNonAlloc methods. Now the less-significant bit is configured in the getRelocTargetVA routine. I could not remove Mips-ness from DynamicSection<ELFT>::addSym and Writer<ELFT>::getEntryAddr because if an e_entry field or a dynamic table entry contains microMIPS symbol value this value should have the less-significant bit to notify loader / dynamic-linker about the symbol's type.

[atanasyan]

Ping?

[atanasyan]

Ping?

[ruiu]

Sorry for the belated response. A few minor comments.

ELF/InputSection.cpp

469

Please add comment so that people who don't know about MIPS can change this code and this file.

687

nit: add {}

ELF/SyntheticSections.cpp

1024–1032

I'd move this if out of this lambda like this.

if (Config->EMachine == EM_MIPS && ...)
  Entries.push_back({Tag, [=] { return Sym->getVA() | 1; }});
else
  Entries.push_back({Tag, [=] { return Sym->getVA(); }});

1027–1029

I don't think people who don't know MIPS can understand this comment. Why does the reader (who is the reader?) has to know if it is MicroMIPS?

[atanasyan]

• Addressing review comments

[ruiu]

ELF/InputSection.cpp

469–474

Oh, thank you for writing this. I think I finally understand what it does correctly. So, you are using the least significant bit just to signal to the later pass that this is a MicroMIPS code, right? I was thinking that jump instructions jumping to MicroMIPS code must be marked with LSB 1, but it looks like you cleared the last bit, so the bit you set in this function is not used there. You set the least significant bit just to encode some information that is consumed in the later pass.

That makes me wonder if that's the best way of doing that. Apparently, the side effect of embedding some information to the address isn't negligible -- you needed to update a lot of places to set/unset the least significant bit. That doesn't seem like a good way to encode that kind of out-of-bound information. Address should be just an address.

What if you pass Symbol to relocateOne? Does this solve the issue? I'm not suggesting you do right now, but I'm wondering that's what you wanted to do.

[atanasyan]

• Pass a pointer to relocatable symbol to the relocateOne method
• Move handling of the less-significant bit from relocateNonAlloc and relocateAlloc to MIPS::relocateOne

[atanasyan]

Ping?

[atanasyan]

Ping?

[atanasyan]

Ping?

[atanasyan]

Ping? This patch got the last comment more than a month ago.

[atanasyan]

Ping?

[atanasyan]

Rebased against the trunk.

[atanasyan]

Ping?

This patch have not got any comments since Feb 16. Does it mean that the patch cab be committed without any additional approval?

[atanasyan]

Ping? I'm going to commit this patch in a couple of weeks if I do not receive any objections. We can always perform a post-commit review.

[atanasyan]

Rebased against the trunk.

[atanasyan]

Ping?

[atanasyan]

Ping?

[atanasyan]

Ping?

@ruiu could I use a post-commit review option in that case?

[emaste]

Perhaps someone else can review?

[MaskRay]

ELF/Arch/AArch64.cpp

46–47

I like this change.

With const Symbol *S, we can improve error reporting of relocation overflow of checkUInt(...)

[ruiu]

ELF/Arch/AArch64.cpp

46–47

Adding const Symbol * to relocateOne might be fine, but I don't like to add a default argument to the parameter. How many locations do we call relocateOne? Can we just always pass a symbol to the function?

[atanasyan]

• Rebase against the trunk
• Remove default nullptr value from the relocateOne method

[atanasyan]

• Really remove default nullptr argument value from the relocateOne method

[ruiu]

Adding a new parameter to relocateOne doesn't look beautiful, but that makes me think whether you are editing the right place of the code. relocateOne is supposed to apply a single relocation based on a value passed to the function. No complex logic should be in the function. Passing one more parameter so that you can do more complex computation in the function may not be a good idea.

[atanasyan]

In D40147#1308904, @ruiu wrote:

Adding a new parameter to relocateOne doesn't look beautiful, but that makes me think whether you are editing the right place of the code. relocateOne is supposed to apply a single relocation based on a value passed to the function. No complex logic should be in the function. Passing one more parameter so that you can do more complex computation in the function may not be a good idea.

That's interesting - you suggested to pass a Symbol to relocateOne on Feb 16.
https://reviews.llvm.org/D40147#inline-379274

I will try to implement an alternative solution. Maybe by updating one of initial patches.

[ruiu]

In D40147#1309748, @atanasyan wrote:

In D40147#1308904, @ruiu wrote:

Adding a new parameter to relocateOne doesn't look beautiful, but that makes me think whether you are editing the right place of the code. relocateOne is supposed to apply a single relocation based on a value passed to the function. No complex logic should be in the function. Passing one more parameter so that you can do more complex computation in the function may not be a good idea.

That's interesting - you suggested to pass a Symbol to relocateOne on Feb 16.
https://reviews.llvm.org/D40147#inline-379274

I will try to implement an alternative solution. Maybe by updating one of initial patches.

Yeah, sorry, but until code is actually written, I don't know whether it is going to look good or not, so I can suggest, but my suggestion is not a promise or anything.

[atanasyan]

• Remove new argument from relocateOne methods
• Introduce new helper function setMicroMipsBit and call it before the relocateOne

[atanasyan]

Gentle ping...

[atanasyan]

Gentle ping...

Any chance to get review this year or at least before 8.0 release?

[atanasyan]

Gentle ping...

[atanasyan]

Gentle ping...

[grimar]

I am pretty sure we can land this because having a patch on a review for about a year is always a terrible thing. My comments are inline.

ELF/InputSection.cpp

693

I wonder if this piece of code can be in MIPS::relocateOne ?

750

Same?

ELF/SyntheticSections.cpp

1025

The comment does not answer why we do that..

ELF/Writer.cpp

2062

Should it be in a getVA()?

test/ELF/mips-micro-bad-cross-calls.s

9

Please move the REQUIRES on the first line.

[atanasyan]

In D40147#1352518, @grimar wrote:

I am pretty sure we can land this because having a patch on a review for about a year is always a terrible thing. My comments are inline.

Thanks for review.

We cannot move call of setMicroMipsBit to the MIPS::relocateOne because the relocateOne does not have a reference to the "target" symbol. One possible solution is to extend the getVA() and getPltVA() routines and add a less-significant bit there when necessary. That eliminates almost all manipulations with the bit in other places and makes calls of the setMicroMipsBit routine unnecessary. It's interesting that this approach was implemented in the first version of this patch https://reviews.llvm.org/D40147?id=123236.

I will try to restore that version of the patch.

[atanasyan]

• Move the most part of manipulations with the less-significant bit to the getSymVA and Symbol::getPltVA() methods.

[grimar]

I am not a specialist in MIPS, but the code itself in this diff looks much better to me.

lld/ELF/Arch/Mips.cpp

471 ↗

(On Diff #185709)

I would rewrite this in a shorter way:

return Type == R_MIPS_26 || Type == R_MIPS_PC26_S2 ... ;

483 ↗

(On Diff #185709)

The same.

523 ↗

(On Diff #185709)

Is it ok to ignore these, or should it trigger an error instead maybe?

[grimar]

LGTM, but please wait for Rui's opinion too.

lld/ELF/Arch/Mips.cpp

523 ↗

(On Diff #185709)

Oh, please ignore this comment. So the error below will be triggered.

[atanasyan]

• Use if instead of switch

[atanasyan]

In D40147#1390202, @grimar wrote:

LGTM, but please wait for Rui's opinion too.

Thanks for review.

[atanasyan]

@ruiu : Do you have any comments?

[grimar]

LGTM. This patch is more or less isolated, so I think you can land it if there will be no objections/comments in a reasonable amount of time, let's say until EOW.

ELF/Arch/AArch64.cpp

public:
   void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
   bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
   bool usesOnlyLowPageBits(RelType Type) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
   RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
 };
 } // namespace
 

 
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
 
 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
   or32le(L, (Imm & 0xFFF) << 10);
 }
 
-void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                          const Symbol *S) const {
   switch (Type) {
   case R_AARCH64_ABS16:
   case R_AARCH64_PREL16:
     checkIntUInt<16>(Loc, Val, Type);
     write16le(Loc, Val);
     break;
   case R_AARCH64_ABS32:
   case R_AARCH64_PREL32:

ELF/Arch/AMDGPU.cpp

 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class AMDGPU final : public TargetInfo {
 public:
   AMDGPU();
   uint32_t calcEFlags() const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
 };
 } // namespace
 
 AMDGPU::AMDGPU() {
   RelativeRel = R_AMDGPU_RELATIVE64;
   GotRel = R_AMDGPU_ABS64;
for (InputFile *F : makeArrayRef(ObjectFiles).slice(1)) {
     if (Ret == getEFlags(F))
       continue;
     error("incompatible e_flags: " + toString(F));
     return 0;
   }
   return Ret;
 }
 
-void AMDGPU::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void AMDGPU::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                         const Symbol *S) const {
   switch (Type) {
   case R_AMDGPU_ABS32:
   case R_AMDGPU_GOTPCREL:
   case R_AMDGPU_GOTPCREL32_LO:
   case R_AMDGPU_REL32:
   case R_AMDGPU_REL32_LO:
     write32le(Loc, Val);
     break;

ELF/Arch/ARM.cpp

public:
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void addPltSymbols(InputSection &IS, uint64_t Off) const override;
   void addPltHeaderSymbols(InputSection &ISD) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
   bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 };
 } // namespace
 
 ARM::ARM() {
   CopyRel = R_ARM_COPY;
   RelativeRel = R_ARM_RELATIVE;
   IRelativeRel = R_ARM_IRELATIVE;
   GotRel = R_ARM_GLOB_DAT;
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
   else
     // Bit 0 == 1 denotes Thumb state, it is not part of the range
     Dst &= ~0x1;
 
   uint64_t Distance = (Src > Dst) ? Src - Dst : Dst - Src;
   return Distance <= Range;
 }
 
-void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                      const Symbol *S) const {
   switch (Type) {
   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
   case R_ARM_GLOB_DAT:
   case R_ARM_GOTOFF32:
   case R_ARM_GOT_BREL:
   case R_ARM_GOT_PREL:
   case R_ARM_REL32:

ELF/Arch/AVR.cpp

 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class AVR final : public TargetInfo {
 public:
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 };
 } // namespace
 
 RelExpr AVR::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   return R_ABS;
 }
 
-void AVR::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void AVR::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                      const Symbol *S) const {
   switch (Type) {
   case R_AVR_CALL: {
     uint16_t Hi = Val >> 17;
     uint16_t Lo = Val >> 1;
     write16le(Loc, read16le(Loc) | ((Hi >> 1) << 4) | (Hi & 1));
     write16le(Loc + 2, Lo);
     break;
   }

ELF/Arch/Mips.cpp

public:
   bool isPicRel(RelType Type) const override;
   RelType getDynRel(RelType Type) const override;
   void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
   bool usesOnlyLowPageBits(RelType Type) const override;
 };
 } // namespace
 
 template <class ELFT> MIPS<ELFT>::MIPS() {
   GotPltHeaderEntriesNum = 2;
   DefaultMaxPageSize = 65536;
   GotEntrySize = sizeof(typename ELFT::uint);
calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
   if (Type2 == R_MICROMIPS_SUB &&
       (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16))
     return std::make_pair(Type3, -Val);
   error(getErrorLocation(Loc) + "unsupported relocations combination " +
         Twine(Type));
   return std::make_pair(Type & 0xff, Val);
 }
 
+static bool isBranchReloc(RelType Type) {
+  switch (Type) {
+  case R_MIPS_26:
+  case R_MIPS_PC26_S2:
+  case R_MIPS_PC21_S2:
+  case R_MIPS_PC16:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static bool isMicroBranchReloc(RelType Type) {
+  switch (Type) {
+  case R_MICROMIPS_26_S1:
+  case R_MICROMIPS_PC26_S1:
+  case R_MICROMIPS_PC16_S1:
+  case R_MICROMIPS_PC10_S1:
+  case R_MICROMIPS_PC7_S1:
+    return true;
+  default:
+    return false;
+  }
+}
+
 template <class ELFT>
-void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+static uint64_t fixupCrossModeJump(uint8_t *Loc, RelType Type, uint64_t Val,
+                                   bool IsMicroTgt) {
+  // Here we need to detect jump/branch from regular MIPS code
+  // to a microMIPS target and vice versa. In that cases jump
+  // instructions need to be replaced by their "cross-mode"
+  // equivalents.
+  const endianness E = ELFT::TargetEndianness;
+  bool IsCrossJump = (IsMicroTgt && isBranchReloc(Type)) ||
+                     (!IsMicroTgt && isMicroBranchReloc(Type));
+  if (!IsCrossJump)
+    return Val;
+
+  switch (Type) {
+  case R_MIPS_26: {
+    uint32_t Inst = read32<E>(Loc) >> 26;
+    if (Inst == 0x3 || Inst == 0x1d) { // JAL or JALX
+      writeValue<E>(Loc, 0x1d << 26, 32, 0);
+      return Val;
+    }
+    break;
+  }
+  case R_MICROMIPS_26_S1: {
+    uint32_t Inst = readShuffle<E>(Loc) >> 26;
+    if (Inst == 0x3d || Inst == 0x3c) { // JAL32 or JALX32
+      Val >>= 1;
+      writeShuffleValue<E>(Loc, 0x3c << 26, 32, 0);
+      return Val;
+    }
+    break;
+  }
+  case R_MIPS_PC26_S2:
+  case R_MIPS_PC21_S2:
+  case R_MIPS_PC16:
+  case R_MICROMIPS_PC16_S1:
+  case R_MICROMIPS_PC10_S1:
+  case R_MICROMIPS_PC7_S1:
+    // FIXME (simon): Support valid branch relocations.
+    break;
+  default:
+    llvm_unreachable("unexpected jump/branch relocation");
+  }
+
+  error(getErrorLocation(Loc) +
+        "unsupported jump/branch instruction between ISA modes referenced by " +
+        toString(Type) + " relocation");
+  return Val;
+}
+
+template <class ELFT>
+void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                             const Symbol *S) const {
   const endianness E = ELFT::TargetEndianness;
 
   if (ELFT::Is64Bits || Config->MipsN32Abi)
     std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
 
+  if (S) {
+    // MIPS processors use different instructions to jump / branch between
+    // between the same (regulat-to-regular or microMIPS-to_microMIPS) or
+    // mixed (regular-to-microMIPS or microMIPS-to_regular) code. When we
+    // write a symbols's value we need to keep information about type of
+    // the symbol: regular or microMIPS to allow a reader of this value
+    // (dynamic linker, loader, debugger etc) will be able to adjust a jump
+    // / branch instruction properly. To do so we set the less-significant
+    // bit for microMIPS symbols.
+
+    // We consider a symbol as a microMIPS one if it has the STO_MIPS_MICROMIPS
+    // flag or if its value is an address of the corresponding PLT entry.
+    // The best solution is to create a regular PLT entry for a regular symbol
+    // and a mciroMIPS PLT entry for a microMIPS symbol. But in that case if
+    // the same routine is called by both regular and microMIPS code, we should
+    // create two PLT entries. That solution minimizes cross-mode jumps. Now
+    // LLD implements more simple solution. If the file uses microMIPS code,
+    // all PLT entries are microMIPS. Otherwise all entries are regular. That
+    // works fine for/ case when all code is either regular or microMIPS, but
+    // increase number/ of cross-mode jumps for mixed code.
+    bool IsMicroTgt =
+        (S->StOther & STO_MIPS_MICROMIPS) || (S->isInPlt() && isMicroMips());
+    if (IsMicroTgt) {
+      switch (getRelExpr(Type, *S, Loc)) {
+      case R_ABS:
+      case R_MIPS_GOTREL:
+      case R_PC:
+        Val |= 1;
+        break;
+      default:
+        break;
+      }
+    }
+
+    // Detect cross-mode jump/branch and fix instruction.
+    Val = fixupCrossModeJump<ELFT>(Loc, Type, Val, IsMicroTgt);
+  }
+
   // Thread pointer and DRP offsets from the start of TLS data area.
   // https://www.linux-mips.org/wiki/NPTL
   if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
       Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
       Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
       Type == R_MICROMIPS_TLS_DTPREL_LO16) {
     Val -= 0x8000;
   } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||

ELF/Arch/PPC.cpp

 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class PPC final : public TargetInfo {
 public:
   PPC() { GotBaseSymOff = 0x8000; }
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
 };
 } // namespace
 
 RelExpr PPC::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   switch (Type) {
   case R_PPC_REL24:
   case R_PPC_REL32:
     return R_PC;
   case R_PPC_PLTREL24:
     return R_PLT_PC;
   default:
     return R_ABS;
   }
 }
 
-void PPC::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void PPC::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                      const Symbol *S) const {
   switch (Type) {
   case R_PPC_ADDR16_HA:
     write16be(Loc, (Val + 0x8000) >> 16);
     break;
   case R_PPC_ADDR16_HI:
     write16be(Loc, Val >> 16);
     break;
   case R_PPC_ADDR16_LO:

ELF/Arch/PPC64.cpp

 namespace {
 class PPC64 final : public TargetInfo {
 public:
   PPC64();
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 };
 } // namespace
 
 // Relocation masks following the #lo(value), #hi(value), #ha(value),
 // #higher(value), #highera(value), #highest(value), and #highesta(value)
 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
 // document.
 static uint16_t applyPPCLo(uint64_t V) { return V; }
case R_PPC64_TOC16_LO:
     return {R_PPC64_ADDR16_LO, V};
   case R_PPC64_TOC16_LO_DS:
     return {R_PPC64_ADDR16_LO_DS, V};
   default:
     return {Type, Val};
   }
 }
 
-void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                        const Symbol *S) const {
   // For a TOC-relative relocation, proceed in terms of the corresponding
   // ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
   case R_PPC64_ADDR14: {
     checkAlignment<4>(Loc, Val, Type);
     // Preserve the AA/LK bits in the branch instruction

ELF/Arch/SPARCV9.cpp

 namespace {
 class SPARCV9 final : public TargetInfo {
 public:
   SPARCV9();
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 };
 } // namespace
 
 SPARCV9::SPARCV9() {
   CopyRel = R_SPARC_COPY;
   GotRel = R_SPARC_GLOB_DAT;
   PltRel = R_SPARC_JMP_SLOT;
   RelativeRel = R_SPARC_RELATIVE;
case R_SPARC_WPLT30:
     return R_PLT_PC;
   case R_SPARC_NONE:
     return R_NONE;
   default:
     return R_INVALID;
   }
 }
 
-void SPARCV9::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void SPARCV9::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                          const Symbol *S) const {
   switch (Type) {
   case R_SPARC_32:
   case R_SPARC_UA32:
     // V-word32
     checkUInt<32>(Loc, Val, Type);
     write32be(Loc, Val);
     break;
   case R_SPARC_DISP32:

ELF/Arch/X86.cpp

public:
   int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
   void writeGotPltHeader(uint8_t *Buf) const override;
   RelType getDynRel(RelType Type) const override;
   void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
   void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 
   RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
 };
int64_t X86::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
   case R_386_TLS_LDO_32:
   case R_386_TLS_LE:
     return SignExtend64<32>(read32le(Buf));
   default:
     return 0;
   }
 }
 
-void X86::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void X86::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                      const Symbol *S) const {
   switch (Type) {
   case R_386_8:
     // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are
     // being used for some 16-bit programs such as boot loaders, so
     // we want to support them.
     checkUInt<8>(Loc, Val, Type);
     *Loc = Val;
     break;

ELF/Arch/X86_64.cpp

public:
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   bool isPicRel(RelType Type) const override;
   void writeGotPltHeader(uint8_t *Buf) const override;
   void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
-  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                   const Symbol *S = nullptr) const override;
 
   RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxGot(uint8_t *Loc, uint64_t Val) const override;
   void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
const uint8_t Inst[] = {
       0x66, 0x66,                                           // .word 0x6666
       0x66,                                                 // .byte 0x66
       0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0,%rax
   };
   memcpy(Loc - 3, Inst, sizeof(Inst));
 }
 
 template <class ELFT>
-void X86_64<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+void X86_64<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                               const Symbol *S) const {
   switch (Type) {
   case R_X86_64_8:
     checkUInt<8>(Loc, Val, Type);
     *Loc = Val;
     break;
   case R_X86_64_16:
     checkUInt<16>(Loc, Val, Type);
     write16le(Loc, Val);

ELF/InputSection.cpp

 // of the RW segment.
 static uint64_t getARMStaticBase(const Symbol &Sym) {
   OutputSection *OS = Sym.getOutputSection();
   if (!OS || !OS->PtLoad || !OS->PtLoad->FirstSec)
     fatal("SBREL relocation to " + Sym.getName() + " without static base");
   return OS->PtLoad->FirstSec->Addr;
 }
 
 static uint64_t getRelocTargetVA(RelType Type, int64_t A, uint64_t P,
                                  const Symbol &Sym, RelExpr Expr) {
   switch (Expr) {
   case R_INVALID:
     return 0;
   case R_ABS:
   case R_RELAX_GOT_PC_NOPIC:
     return Sym.getVA(A);
   case R_ADDEND:
     return A;
   case R_ARM_SBREL:
     return Sym.getVA(A) - getARMStaticBase(Sym);
   case R_GOT:
   case R_RELAX_TLS_GD_TO_IE_ABS:
if (Expr != R_ABS) {
       // address 0. For bug-compatibilty, we accept them with warnings. We
       // know Steel Bank Common Lisp as of 2018 have this bug.
       warn(Msg);
       Target->relocateOne(BufLoc, Type,
                           SignExtend64<Bits>(Sym.getVA(Addend - Offset)));
       continue;
     }
 
     if (Sym.isTls() && !Out::TlsPhdr)
       Target->relocateOne(BufLoc, Type, 0);
     else
-      Target->relocateOne(BufLoc, Type, SignExtend64<Bits>(Sym.getVA(Addend)));
+      Target->relocateOne(BufLoc, Type, SignExtend64<Bits>(Sym.getVA(Addend)),
+                          &Sym);
   }
 }
 
 template <class ELFT>
 void InputSectionBase::relocate(uint8_t *Buf, uint8_t *BufEnd) {
   if (Flags & SHF_ALLOC) {
     relocateAlloc(Buf, BufEnd);
     return;
   }
 
   auto *Sec = cast<InputSection>(this);
   if (Sec->AreRelocsRela)
     Sec->relocateNonAlloc<ELFT>(Buf, Sec->template relas<ELFT>());
   else
for (const Relocation &Rel : Relocations) {
     uint8_t *BufLoc = Buf + Offset;
     RelType Type = Rel.Type;
 
     uint64_t AddrLoc = getOutputSection()->Addr + Offset;
     RelExpr Expr = Rel.Expr;
     uint64_t TargetVA = SignExtend64(
         getRelocTargetVA(Type, Rel.Addend, AddrLoc, *Rel.Sym, Expr), Bits);
 
     switch (Expr) {
     case R_RELAX_GOT_PC:
     case R_RELAX_GOT_PC_NOPIC:
       Target->relaxGot(BufLoc, TargetVA);
       break;
     case R_RELAX_TLS_IE_TO_LE:
       Target->relaxTlsIeToLe(BufLoc, Type, TargetVA);
       break;
     case R_RELAX_TLS_LD_TO_LE:
case R_RELAX_TLS_GD_TO_IE_END:
       Target->relaxTlsGdToIe(BufLoc, Type, TargetVA);
       break;
     case R_PPC_PLT_OPD:
       // Patch a nop (0x60000000) to a ld.
       if (BufLoc + 8 <= BufEnd && read32be(BufLoc + 4) == 0x60000000)
         write32be(BufLoc + 4, 0xe8410028); // ld %r2, 40(%r1)
       LLVM_FALLTHROUGH;
     default:
-      Target->relocateOne(BufLoc, Type, TargetVA);
+      Target->relocateOne(BufLoc, Type, TargetVA, Rel.Sym);
       break;
     }
   }
 }
 
 template <class ELFT> void InputSection::writeTo(uint8_t *Buf) {
   if (Type == SHT_NOBITS)
     return;

ELF/SyntheticSections.cpp

 
 template <class ELFT>
 void DynamicSection<ELFT>::addSize(int32_t Tag, OutputSection *Sec) {
   Entries.push_back({Tag, [=] { return Sec->Size; }});
 }
 
 template <class ELFT>
 void DynamicSection<ELFT>::addSym(int32_t Tag, Symbol *Sym) {
+  if (Config->EMachine == EM_MIPS && (Sym->StOther & STO_MIPS_MICROMIPS))
+    // Set the less-significant bit for a microMIPS symbol.
+    // When loader / dynamic linker reads this tag, it will
+    // know that the symbol is microMIPS and adjust a jump
+    // instruction appropriately to handle possible cross-mode
+    // (regular-to-microMIPS) jump.
+    Entries.push_back({Tag, [=] { return Sym->getVA() | 1; }});
+  else
     Entries.push_back({Tag, [=] { return Sym->getVA(); }});
 }
 
 // Add remaining entries to complete .dynamic contents.
 template <class ELFT> void DynamicSection<ELFT>::finalizeContents() {
   if (this->Size)
     return; // Already finalized.
 
   // Set DT_FLAGS and DT_FLAGS_1.

ELF/Target.h

virtual bool needsThunk(RelExpr Expr, RelType RelocType,
                           const InputFile *File, uint64_t BranchAddr,
                           const Symbol &S) const;
   // Return true if we can reach Dst from Src with Relocation RelocType
   virtual bool inBranchRange(RelType Type, uint64_t Src,
                              uint64_t Dst) const;
   virtual RelExpr getRelExpr(RelType Type, const Symbol &S,
                              const uint8_t *Loc) const = 0;
 
-  virtual void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const = 0;
+  virtual void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val,
+                           const Symbol *S = nullptr) const = 0;
 
   virtual ~TargetInfo();
 
   unsigned TlsGdRelaxSkip = 1;
   unsigned PageSize = 4096;
   unsigned DefaultMaxPageSize = 4096;
 
   uint64_t getImageBase();

ELF/Writer.cpp

 // 1. the '-e' entry command-line option;
 // 2. the ENTRY(symbol) command in a linker control script;
 // 3. the value of the symbol _start, if present;
 // 4. the number represented by the entry symbol, if it is a number;
 // 5. the address of the first byte of the .text section, if present;
 // 6. the address 0.
 template <class ELFT> uint64_t Writer<ELFT>::getEntryAddr() {
   // Case 1, 2 or 3
-  if (Symbol *B = Symtab->find(Config->Entry))
+  if (Symbol *B = Symtab->find(Config->Entry)) {
+    // Set the less-significant bit for a microMIPS symbol.
+    // When loader reads this entry, it will know that the symbol
+    // is microMIPS and adjust a jump instruction appropriately
+    // to handle possible cross-mode (regular-to-microMIPS) jump.
+    if (Config->EMachine == EM_MIPS && (B->StOther & STO_MIPS_MICROMIPS))
+      return B->getVA() | 1;
     return B->getVA();
+  }
 
   // Case 4
   uint64_t Addr;
   if (to_integer(Config->Entry, Addr))
     return Addr;
 
   // Case 5
   if (OutputSection *Sec = findSection(".text")) {

test/ELF/mips-micro-bad-cross-calls.s

+# Check error message for invalid cross-mode branch instructions.
+
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         %S/Inputs/mips-dynamic.s -o %t2.o
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t1.o
+# RUN: not ld.lld -o %t.exe %t1.o %t2.o 2>&1 | FileCheck %s
+
+# REQUIRES: mips
+
+# CHECK: (.text+0x0): unsupported jump/branch instruction between ISA modes referenced by R_MICROMIPS_PC10_S1 relocation
+
+  .text
+  .set micromips
+  .global __start
+__start:
+  b16 foo0

test/ELF/mips-micro-cross-calls.s

+# Check various cases of microMIPS - regular code cross-calls.
+
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         -mattr=micromips %s -o %t-eb.o
+# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
+# RUN:         -position-independent -mattr=micromips \
+# RUN:         %S/Inputs/mips-micro.s -o %t-eb-pic.o
+# RUN: ld.lld -o %t-eb.exe %t-eb.o %t-eb-pic.o
+# RUN: llvm-objdump -d -mattr=-micromips %t-eb.exe \
+# RUN:   | FileCheck --check-prefix=REG %s
+# RUN: llvm-objdump -d -mattr=+micromips %t-eb.exe \
+# RUN:   | FileCheck --check-prefix=MICRO %s
+
+# REQUIRES: mips
+
+# REG:        __start:
+# REG-NEXT:      20000:       74 00 80 04     jalx 131088 <micro>
+# REG-NEXT:      20004:       00 00 00 00     nop
+# REG-NEXT:      20008:       74 00 80 08     jalx 131104 <__microLA25Thunk_foo>
+
+# REG:        __LA25Thunk_bar:
+# REG-NEXT:      20030:       3c 19 00 02     lui     $25, 2
+# REG-NEXT:      20034:       08 00 80 11     j       131140 <bar>
+
+# MICRO:      micro:
+# MICRO-NEXT:    20010:       f0 00 80 00     jalx 65536
+# MICRO-NEXT:    20014:       00 00 00 00     nop
+# MICRO-NEXT:    20018:       f0 00 80 0c     jalx 65560
+
+# MICRO:      __microLA25Thunk_foo:
+# MICRO-NEXT:    20020:       41 b9 00 02     lui     $25, 2
+# MICRO-NEXT:    20024:       d4 01 00 20     j       131136
+
+  .text
+  .set nomicromips
+  .global __start
+__start:
+  jal micro
+  jal foo
+
+  .set micromips
+  .global micro
+micro:
+  jal __start
+  jal bar

test/ELF/mips-micro-plt.s

 # Check less-significant bit setup for microMIPS PLT.
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %S/Inputs/mips-dynamic.s -o %t-dso.o
 # RUN: ld.lld %t-dso.o -shared -o %t.so
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t-exe.o
 # RUN: ld.lld %t-exe.o %t.so -o %t.exe
 # RUN: llvm-readobj -t -dt -mips-plt-got %t.exe | FileCheck %s
+# RUN: llvm-objdump -d -mattr=micromips %t.exe | FileCheck --check-prefix=ASM %s
 
 # REQUIRES: mips
 
 # CHECK:      Symbols [
 # CHECK:        Symbol {
 # CHECK:          Name: foo
-# CHECK-NEXT:     Value: 0x20008
+# CHECK-NEXT:     Value: 0x20010
 # CHECK-NEXT:     Size:
 # CHECK-NEXT:     Binding: Local
 # CHECK-NEXT:     Type: None
 # CHECK-NEXT:     Other [
 # CHECK-NEXT:       STO_MIPS_MICROMIPS
 # CHECK-NEXT:       STV_HIDDEN
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Section: .text
 # CHECK-NEXT:   }
 # CHECK:        Symbol {
 # CHECK:          Name: __start
 # CHECK-NEXT:     Value: 0x20000
 # CHECK-NEXT:     Size:
 # CHECK-NEXT:     Binding: Global
 # CHECK-NEXT:     Type: None
 # CHECK-NEXT:     Other [
 # CHECK-NEXT:       STO_MIPS_MICROMIPS
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Section: .text
 # CHECK-NEXT:   }
 # CHECK:        Symbol {
 # CHECK:          Name: foo0
-# CHECK-NEXT:     Value: 0x0
+# CHECK-NEXT:     Value: 0x20040
 # CHECK-NEXT:     Size:
 # CHECK-NEXT:     Binding: Global
 # CHECK-NEXT:     Type: Function
-# CHECK-NEXT:     Other: 0
+# CHECK-NEXT:     Other [
+# CHECK-NEXT:       STO_MIPS_MICROMIPS
+# CHECK-NEXT:       STO_MIPS_PLT
+# CHECK-NEXT:     ]
 # CHECK-NEXT:     Section: Undefined
 # CHECK-NEXT:   }
 # CHECK-NEXT: ]
 # CHECK:      DynamicSymbols [
 # CHECK:        Symbol {
 # CHECK:          Name: foo0
-# CHECK-NEXT:     Value: 0x0
+# CHECK-NEXT:     Value: 0x20041
 # CHECK-NEXT:     Size:
 # CHECK-NEXT:     Binding: Global
 # CHECK-NEXT:     Type: Function
-# CHECK-NEXT:     Other: 0
+# CHECK-NEXT:     Other [
+# CHECK-NEXT:       STO_MIPS_MICROMIPS
+# CHECK-NEXT:       STO_MIPS_PLT
+# CHECK-NEXT:     ]
 # CHECK-NEXT:     Section: Undefined
 # CHECK-NEXT:   }
 # CHECK-NEXT: ]
 
 # CHECK:      Primary GOT {
 # CHECK:        Local entries [
 # CHECK-NEXT:     Entry {
 # CHECK-NEXT:       Address:
 # CHECK-NEXT:       Access:
-# CHECK-NEXT:       Initial: 0x20009
+# CHECK-NEXT:       Initial: 0x20011
 # CHECK-NEXT:     }
 # CHECK:        ]
 # CHECK:      }
 
 # CHECK:      PLT GOT {
 # CHECK:        Entries [
 # CHECK-NEXT:     Entry {
 # CHECK-NEXT:       Address:
-# CHECK-NEXT:       Initial: 0x20011
-# CHECK-NEXT:       Value: 0x0
+# CHECK-NEXT:       Initial: 0x20021
+# CHECK-NEXT:       Value: 0x20041
 # CHECK-NEXT:       Type: Function
 # CHECK-NEXT:       Section: Undefined
 # CHECK-NEXT:       Name: foo0@
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ]
 # CHECK-NEXT: }
 
+# ASM:      __start:
+# ASM-NEXT:    20000:       fd 1c 80 18     lw      $8, -32744($gp)
+# ASM-NEXT:    20004:       11 08 00 11     addi    $8, $8, 17
+# ASM-NEXT:    20008:       41 a8 00 02     lui     $8, 2
+# ASM-NEXT:    2000c:       11 08 00 41     addi    $8, $8, 65
+#
+# ASM:      foo:
+# ASM-NEXT:    20010:       f4 01 00 20     jal     131136
+
   .text
   .set micromips
   .global foo
   .hidden foo
   .global __start
 __start:
   lw    $t0,%got(foo)($gp)
   addi  $t0,$t0,%lo(foo)
+  lui   $t0,%hi(foo0)
+  addi  $t0,$t0,%lo(foo0)
 foo:
   jal   foo0

test/ELF/mips-micro-relocs.s

 # Check handling of microMIPS relocations.
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %S/Inputs/mips-micro.s -o %t1eb.o
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2eb.o
 # RUN: ld.lld -o %teb.exe %t1eb.o %t2eb.o
-# RUN: llvm-objdump -d -t -mattr=micromips %teb.exe \
+# RUN: llvm-objdump -d -t -s -mattr=micromips %teb.exe \
 # RUN:   | FileCheck --check-prefixes=EB,SYM %s
 
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips %S/Inputs/mips-micro.s -o %t1el.o
 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-linux \
 # RUN:         -mattr=micromips %s -o %t2el.o
 # RUN: ld.lld -o %tel.exe %t1el.o %t2el.o
-# RUN: llvm-objdump -d -t -mattr=micromips %tel.exe \
+# RUN: llvm-objdump -d -t -s -mattr=micromips %tel.exe \
 # RUN:   | FileCheck --check-prefixes=EL,SYM %s
 
 # REQUIRES: mips
 
 # EB:      __start:
 # EB-NEXT:      20010:       41 a3 00 01     lui     $3, 1
-# EB-NEXT:      20014:       30 63 7f df     addiu   $3, $3, 32735
+# EB-NEXT:      20014:       30 63 7f ef     addiu   $3, $3, 32751
 # EB-NEXT:      20018:       fc 7c 80 18     lw      $3, -32744($gp)
 # EB-NEXT:      2001c:       fc 63 80 18     lw      $3, -32744($3)
 # EB-NEXT:      20020:       8f 70           beqz16  $6, -32
 # EB-NEXT:      20022:       00 7e 00 00     sll     $3, $fp, 0
 # EB-NEXT:      20026:       cf ec           b16     -40
 # EB-NEXT:      20028:       00 00 00 00     nop
 # EB-NEXT:      2002c:       94 00 ff e8     b       -44
 
+# EB:      Contents of section .data:
+# EB-NEXT:  30000 fffe8011
+
+# EB:      Contents of section .debug_info
+# EB-NEXT:  0000 00020011
+
 # EL:      __start:
 # EL-NEXT:      20010:       a3 41 01 00     lui     $3, 1
-# EL-NEXT:      20014:       63 30 df 7f     addiu   $3, $3, 32735
+# EL-NEXT:      20014:       63 30 ef 7f     addiu   $3, $3, 32751
 # EL-NEXT:      20018:       7c fc 18 80     lw      $3, -32744($gp)
 # EL-NEXT:      2001c:       63 fc 18 80     lw      $3, -32744($3)
 # EL-NEXT:      20020:       70 8f           beqz16  $6, -32
 # EL-NEXT:      20022:       7e 00 00 00     sll     $3, $fp, 0
 # EL-NEXT:      20026:       ec cf           b16     -40
 # EL-NEXT:      20028:       00 00 00 00     nop
 # EL-NEXT:      2002c:       00 94 e8 ff     b       -44
 
-# SYM: 00037ff0         .got            00000000 .hidden _gp
+# EL:      Contents of section .data:
+# EL-NEXT:  30000 1180feff
+
+# EL:      Contents of section .debug_info
+# EL-NEXT:  0000 11000200
+
+# SYM: 00038000         .got            00000000 .hidden _gp
 # SYM: 00020000 g F     .text           00000000 foo
 # SYM: 00020010         .text           00000000 __start
 
   .text
   .set micromips
   .global __start
 __start:
   lui     $3, %hi(_gp_disp)       # R_MICROMIPS_HI16
   addiu   $3, $3, %lo(_gp_disp)   # R_MICROMIPS_LO16
 
   lw      $3, %call16(foo)($gp)   # R_MICROMIPS_CALL16
   lw      $3, %got(foo)($3)       # R_MICROMIPS_GOT16
 
   beqz16  $6, foo                 # R_MICROMIPS_PC7_S1
   b16     foo                     # R_MICROMIPS_PC10_S1
   b       foo                     # R_MICROMIPS_PC16_S1
+
+  .data
+  .gpword __start                 # R_MIPS_GPREL32
+
+  .section .debug_info
+  .word __start                   # R_MIPS_32