[MCParser] Refactory ParseDirective to add parameter OperandVector &Operands

[xiangzhai]

Summary

Hi LLVM developers,

Currently ParseDirective is able to parse .byte foo, but not able to parse .byte lo8(foo), so I override ParseDirective to parse such Identifier Token, and getKindByName for lo8 Modifier, then create MCExpr for this ModifierKind, but I can not able to CreateImm nor insert into Operands.

As suggested in D38029 , May I Refactory ParseDirective to add parameter OperandVector &Operands? please reivew my patch, and give me some suggestion, thanks a lot!

Regards,
Leslie Zhai

[rnk]

I don't see why we need to pass the operands to ParseDirective. It seems like the expression parser should recognize lo8() and build an MCExpr that feeds to the .byte directive.

[xiangzhai]

Dear Deid,

I am not available until October 10th https://mail.kde.org/pipermail/k3b/2017-September/001783.html Happy Chinese National Day!

Regards,
Leslie Zhai

include/llvm/MC/MCParser/MCTargetAsmParser.h

public:
   /// The parser is positioned following the directive name.  The target
   /// specific directive parser should parse the entire directive doing or
   /// recording any target specific work, or return true and do nothing if the
   /// directive is not target specific. If the directive is specific for
   /// the target, the entire line is parsed up to and including the
   /// end-of-statement token and false is returned.
   ///
   /// \param DirectiveID - the identifier token of the directive.
-  virtual bool ParseDirective(AsmToken DirectiveID) = 0;
+  //  \param Operands [out] -  The list of parsed operands, this returns
+  //         ownership of them to the caller.
+  virtual bool ParseDirective(AsmToken DirectiveID,
+                              OperandVector &Operands) = 0;
 
   /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
   /// instruction as an actual MCInst and emit it to the specified MCStreamer.
   /// This returns false on success and returns true on failure to match.
   ///
   /// On failure, the target parser is responsible for emitting a diagnostic
   /// explaining the match failure.
   virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,

lib/MC/MCParser/AsmParser.cpp

if (IDVal[0] == '.' && IDVal != ".") {
     // 3. The generic directive parser implemented by this class. These are
     //    all the directives that behave in a target and platform independent
     //    manner, or at least have a default behavior that's shared between
     //    all targets and platforms.
 
     getTargetParser().flushPendingInstructions(getStreamer());
 
     SMLoc StartTokLoc = getTok().getLoc();
-    bool TPDirectiveReturn = getTargetParser().ParseDirective(ID);
+    bool TPDirectiveReturn =
+        getTargetParser().ParseDirective(ID, Info.ParsedOperands);
 
     if (hasPendingError())
       return true;
     // Currently the return value should be true if we are
     // uninterested but as this is at odds with the standard parsing
     // convention (return true = error) we have instances of a parsed
     // directive that fails returning true as an error. Catch these
     // cases as best as possible errors here.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
   }
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   static bool classifySymbolRef(const MCExpr *Expr,
                                 AArch64MCExpr::VariantKind &ELFRefKind,
                                 MCSymbolRefExpr::VariantKind &DarwinRefKind,
                                 int64_t &Addend);
 };
case Match_MRS: {
     return showMatchError(ErrorLoc, MatchResult, Operands);
   }
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 /// ParseDirective parses the arm specific directives
-bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
+bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID,
+                                      OperandVector &Operands) {
   const MCObjectFileInfo::Environment Format =
     getContext().getObjectFileInfo()->getObjectFileType();
   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
 
   StringRef IDVal = DirectiveID.getIdentifier();
   SMLoc Loc = DirectiveID.getLoc();
   if (IDVal == ".arch")

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
   StringRef parseMnemonicSuffix(StringRef Name);
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   //bool ProcessInstruction(MCInst &Inst);
 
   OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int);
 
bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
 
   getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
                                            ELF::STT_AMDGPU_HSA_KERNEL);
   Lex();
   KernelScope.initialize(getContext());
   return false;
 }
 
-bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID,
+                                     OperandVector &Operands) {
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".hsa_code_object_version")
     return ParseDirectiveHSACodeObjectVersion();
 
   if (IDVal == ".hsa_code_object_isa")
     return ParseDirectiveHSACodeObjectISA();
 

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
 
     NextSymbolIsThumb = false;
   }
 
   // Implementation of the MCTargetAsmParser interface:
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
case Match_AlignedMemoryRequires64or128or256:
     }
   }
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 /// parseDirective parses the arm specific directives
-bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool ARMAsmParser::ParseDirective(AsmToken DirectiveID,
+                                  OperandVector &Operands) {
   const MCObjectFileInfo::Environment Format =
     getContext().getObjectFileInfo()->getObjectFileType();
   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
 
   StringRef IDVal = DirectiveID.getIdentifier();
   if (IDVal == ".word")
     parseLiteralValues(4, DirectiveID.getLoc());

lib/Target/BPF/AsmParser/BPFAsmParser.cpp

bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   // "=" is used as assignment operator for assembly statment, so can't be used
   // for symbol assignment.
   bool equalIsAsmAssignment() override { return false; }
   // "*" is used for dereferencing memory that it will be the start of
   // statement.
   bool starIsStartOfStatement() override { return true; }
 
if (getLexer().isNot(AsmToken::EndOfStatement)) {
     return Error(Loc, "unexpected token");
   }
 
   // Consume the EndOfStatement.
   getParser().Lex();
   return false;
 }
 
-bool BPFAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
+bool BPFAsmParser::ParseDirective(AsmToken DirectiveID,
+                                  OperandVector &Operands) {
+ return true;
+}
 
 extern "C" void LLVMInitializeBPFAsmParser() {
   RegisterMCAsmParser<BPFAsmParser> X(getTheBPFTarget());
   RegisterMCAsmParser<BPFAsmParser> Y(getTheBPFleTarget());
   RegisterMCAsmParser<BPFAsmParser> Z(getTheBPFbeTarget());
 }

lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

public:
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override {
     llvm_unreachable("Unimplemented");
   }
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
                         OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 };
 
 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
 /// instruction.
 struct HexagonOperand : public MCParsedAsmOperand {
   enum KindTy { Token, Immediate, Register } Kind;
 
   SMLoc StartLoc, EndLoc;
HexagonMCInstrInfo::extendIfNeeded(
       getParser().getContext(), MCII, MCB, *SubInst);
   MCB.addOperand(MCOperand::createInst(SubInst));
   if (!InBrackets)
     return finishBundle(IDLoc, Out);
   return false;
 }
 
 /// ParseDirective parses the Hexagon specific directives
-bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID,
+                                      OperandVector &Operands) {
   StringRef IDVal = DirectiveID.getIdentifier();
   if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
     return ParseDirectiveValue(4, DirectiveID.getLoc());
   if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
       IDVal.lower() == ".half")
     return ParseDirectiveValue(2, DirectiveID.getLoc());
   if (IDVal.lower() == ".falign")
     return ParseDirectiveFalign(256, DirectiveID.getLoc());

lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp

class LanaiAsmParser : public MCTargetAsmParser {
   unsigned parseAluOperator(bool PreOp, bool PostOp);
 
   // Split the mnemonic stripping conditional code and quantifiers
   StringRef splitMnemonic(StringRef Name, SMLoc NameLoc,
                           OperandVector *Operands);
 
   bool parsePrePost(StringRef Type, int *OffsetValue);
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
   bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   bool MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op,
     Op->Mem.OffsetReg = 0;
     Op->Mem.Offset = Imm;
     return Op;
   }
 };
 
 } // end anonymous namespace
 
-bool LanaiAsmParser::ParseDirective(AsmToken /*DirectiveId*/) { return true; }
+bool LanaiAsmParser::ParseDirective(AsmToken /*DirectiveId*/,
+                                    OperandVector &Operands) {
+  return true;
+}
 
 bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
                                              OperandVector &Operands,
                                              MCStreamer &Out,
                                              uint64_t &ErrorInfo,
                                              bool MatchingInlineAsm) {
   MCInst Inst;
   SMLoc ErrorLoc;

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
 
   bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   OperandMatchResultTy parseMemOperand(OperandVector &Operands);
   OperandMatchResultTy
   matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
                                     StringRef Identifier, SMLoc S);
   OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
                                                      SMLoc S);
   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
if (Lexer.is(AsmToken::Integer)) {
     }
 
     return true;
   }
 
   return false;
 }
 
-bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool MipsAsmParser::ParseDirective(AsmToken DirectiveID,
+                                   OperandVector &Operands) {
   // This returns false if this function recognizes the directive
   // regardless of whether it is successfully handles or reports an
   // error. Otherwise it returns true to give the generic parser a
   // chance at recognizing it.
 
   MCAsmParser &Parser = getParser();
   StringRef IDVal = DirectiveID.getString();
 

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
     IsDarwin = TheTriple.isMacOSX();
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   const MCExpr *applyModifierToExpr(const MCExpr *E,
                                     MCSymbolRefExpr::VariantKind,
                                     MCContext &Ctx) override;
 };
if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
     std::swap(Operands[1], Operands[3]);
     std::swap(Operands[2], Operands[1]);
   }
 
   return false;
 }
 
 /// ParseDirective parses the PPC specific directives
-bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool PPCAsmParser::ParseDirective(AsmToken DirectiveID,
+                                  OperandVector &Operands) {
   StringRef IDVal = DirectiveID.getIdentifier();
   if (isDarwin()) {
     if (IDVal == ".machine")
       ParseDarwinDirectiveMachine(DirectiveID.getLoc());
     else
       return true;
   } else if (IDVal == ".word")
     ParseDirectiveWord(2, DirectiveID);

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
 #include "RISCVGenAsmMatcher.inc"
 
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
   OperandMatchResultTy parseRegister(OperandVector &Operands);
   OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
if (getLexer().isNot(AsmToken::EndOfStatement)) {
     getParser().eatToEndOfStatement();
     return Error(Loc, "unexpected token");
   }
 
   getParser().Lex(); // Consume the EndOfStatement.
   return false;
 }
 
-bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
+bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID,
+                                    OperandVector &Operands) {
+  return true;
+}
 
 extern "C" void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
   RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
 }

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

#include "SparcGenAsmMatcher.inc"
   // public interface of the MCTargetAsmParser.
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   // Custom parse functions for Sparc specific operands.
   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
 
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
if (getLexer().isNot(AsmToken::EndOfStatement)) {
     SMLoc Loc = getLexer().getLoc();
     return Error(Loc, "unexpected token");
   }
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
 bool SparcAsmParser::
-ParseDirective(AsmToken DirectiveID)
+ParseDirective(AsmToken DirectiveID, OperandVector &Operands)
 {
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".byte")
     return parseDirectiveWord(1, DirectiveID.getLoc());
 
   if (IDVal == ".half")
     return parseDirectiveWord(2, DirectiveID.getLoc());

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
     // Alias the .word directive to .short.
     parser.addAliasForDirective(".word", ".short");
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
   }
 
   // Override MCTargetAsmParser.
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 
SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
   SMLoc EndLoc =
     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
                                                Index, Length, LengthReg,
                                                StartLoc, EndLoc));
   return MatchOperand_Success;
 }
 
-bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID,
+                                      OperandVector &Operands) {
   StringRef IDVal = DirectiveID.getIdentifier();
 
   if (IDVal == ".insn")
     return ParseDirectiveInsn(DirectiveID.getLoc());
 
   return true;
 }
 

lib/Target/X86/AsmParser/X86AsmParser.cpp

public:
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   void SetFrameRegister(unsigned RegNo) override;
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID) override;
+  bool ParseDirective(AsmToken DirectiveID, OperandVector &Operands) override;
 };
 } // end anonymous namespace
 
 /// @name Auto-generated Match Functions
 /// {
 
 static unsigned MatchRegisterName(StringRef Name);
 
bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
   return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
                MatchingInlineAsm);
 }
 
 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
   return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
 }
 
-bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
+bool X86AsmParser::ParseDirective(AsmToken DirectiveID,
+                                  OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   StringRef IDVal = DirectiveID.getIdentifier();
   if (IDVal == ".word")
     return ParseDirectiveWord(2, DirectiveID.getLoc());
   else if (IDVal.startswith(".code"))
     return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
   else if (IDVal.startswith(".att_syntax")) {
     getParser().setParsingInlineAsm(false);