[RFC] Implement variable-width register classes, step 1: API changes

[kparzysz]

Summary

Follow-up to the discussion in D23561: implementation of support for register classes with variable-sized registers.

Outline of the plan:

• Make register sizes, spill slot sizes and spill slot alignment be determined by feature bits from MCSubtargetInfo. At the moment, the AMD target uses the register size at that level, so this data must be available even without MachineFunction/TargetRegisterInfo/etc.

The register size and the spill slot size can actually be different (certain cases on Hexagon), and since there are cases where the intended meaning of the RC->getSize() is the register size (parts of the AMDGPU code) as well as cases where it is taken to be spill slot size (register allocation), the distinction between these two interpretations will be made explicit.

• The register size, spill slot size, and spill slot alignment will be acquired for a register class by functions from MCRegisterInfo, not from MCRegisterClass directly. These functions will also take MCSubtargetInfo as a parameter, to allow consultation with the feature bits.

• The actual format of the register class data as calculated by TableGen is not implemented in this step, and it will be done in the next step, together with the implementation of the .td syntax changes.

• This step is a NFC change to put new APIs in place. The rest of the changes should be isolated to the parts directly involved with processing the register class data, i.e. TableGen, MCRegisterInfo, and MCSubtargetInfo. It should not be committed by itself, it serves to demonstrate this part of the proposed solution.

[MatzeB]

• A register in the scheme here should still have a definite encoding, so it should be possible to not require this knowledge at all in the MC layer. Are there other ways to rewrite AMDGPU (like looking which register class a register belongs to determine the size?) I would consider the register size/spillslot properties a part of the TargetRegisterInfo here.
• I would not add proxy calls in MachineRegisterInfo. MRI is there to deal with things related to virtual registers not necessarily register classes IMO.
• You get instances of TargetRegisterInfo from the TargetSubtargetInfo anyway, so it should not be necessary to pass the SubtargetInfo around to the various calls. Instead you should be able to create specialized TargetRegisterInfo instances for the different sizes in TargetSubtargetInfo::getRegisterInfo().

[asb]

Hi Krzysztof. So as discussed in D23561 the motivating problem for this work is cases (as in Hexagon HVX) where instructions with identical encodings but different RegisterClasses currently need to be defined twice. An example of this is valignb. Having a register class with a non-constant register size and alignment would solve the issue for HVX, but there's also the hope it will be useful for other targets. For these HVX instructions there is no list<dag> pattern defined. If a pattern was specified, surely even with this new functionality you'd need to have repeated instruction definitions in order to define multiple patterns, because they would need different ValueTypes? Do you have something in mind that would address this as well?

[kparzysz]

In D24631#544247, @MatzeB wrote:

• A register in the scheme here should still have a definite encoding, so it should be possible to not require this knowledge at all in the MC layer. Are there other ways to rewrite AMDGPU (like looking which register class a register belongs to determine the size?) I would consider the register size/spillslot properties a part of the TargetRegisterInfo here.

I published a patch for that: D24675.

• I would not add proxy calls in MachineRegisterInfo. MRI is there to deal with things related to virtual registers not necessarily register classes IMO.

Sure, with the transition to having all this information defined at the TargetRegisterInfo level, there should not be any need for them. There isn't any need anyway even with this code, I just added it to make the changes a bit shorter.

• You get instances of TargetRegisterInfo from the TargetSubtargetInfo anyway, so it should not be necessary to pass the SubtargetInfo around to the various calls. Instead you should be able to create specialized TargetRegisterInfo instances for the different sizes in TargetSubtargetInfo::getRegisterInfo().

Good idea.

[kparzysz]

In D24631#544549, @asb wrote:

Having a register class with a non-constant register size and alignment would solve the issue for HVX, but there's also the hope it will be useful for other targets.

That's a requirement! :)

Most HVX instructions don't have patterns defining them, since they correspond to fairly complex operations. For C/C++ programmers, the current HVX programming model is to use intrinsics, and those we do map to HVX instructions. An alternative is to use Halide (which under the covers also generates intrinsics). At the moment, the compiler does not perform any auto-vectorization to use HVX.

This explains the absence of patterns for HVX, but many core Hexagon instructions lack patterns in instruction definitions as well. Instead, we use the "Pat" class. For the purpose of this effort, that may be the preferred approach, since pats are more amenable to various types of annotations. In particular, you can use a "Predicate" object to decide whether a pat should apply or not. The solution I have in mind for the .td format is based on the predicates to determine the hardware mode, and for patterns it would amount to a syntactic sugar for multiple pats, each predicated on its own predicate for each hardware mode. An instruction definition also has a list of predicates, but they only enable or disable the single defining pattern: any alternatives need to be provided via pats.

I hope this addresses this part as well:

For these HVX instructions there is no list<dag> pattern defined. If a pattern was specified, surely even with this new functionality you'd need to have repeated instruction definitions in order to define multiple patterns, because they would need different ValueTypes? Do you have something in mind that would address this as well?

[kparzysz]

I posted an RFC on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html

[kparzysz]

Already implemented.

include/llvm/CodeGen/MachineRegisterInfo.h

private:
   void operator=(const MachineRegisterInfo&) = delete;
 public:
   explicit MachineRegisterInfo(MachineFunction *MF);
 
   const TargetRegisterInfo *getTargetRegisterInfo() const {
     return MF->getSubtarget().getRegisterInfo();
   }
 
+  const TargetSubtargetInfo &getTargetSubtargetInfo() const {
+    return MF->getSubtarget();
+  }
+
   void resetDelegate(Delegate *delegate) {
     // Ensure another delegate does not take over unless the current
     // delegate first unattaches itself. If we ever need to multicast
     // notifications, we will need to change to using a list.
     assert(TheDelegate == delegate &&
            "Only the current delegate can perform reset!");
     TheDelegate = nullptr;
   }
#endif
   void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
                         const TargetRegisterInfo &TRI,
                         const TargetInstrInfo &TII);
 
   /// Returns a mask covering all bits that can appear in lane masks of
   /// subregisters of the virtual register @p Reg.
   LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
 
+  /// \brief Returns the size of a register from the register class \p RC.
+  unsigned getRegSize(const TargetRegisterClass *RC) const {
+    return getTargetRegisterInfo()->getRegSize(RC->getID(),
+                                               getTargetSubtargetInfo());
+  }
+
+  /// \brief Returns the minimum size of a spill slot for storing a register
+  /// from the register class \p RC.
+  unsigned getSpillSize(const TargetRegisterClass *RC) const {
+    return getTargetRegisterInfo()->getSpillSize(RC->getID(),
+                                                 getTargetSubtargetInfo());
+  }
+
+  /// \brief Returns the minimum alignment of a spill slot for storing a
+  /// register from the register class \p RC.
+  unsigned getSpillAlignment(const TargetRegisterClass *RC) const {
+    return getTargetRegisterInfo()->getSpillAlignment(RC->getID(),
+                                                      getTargetSubtargetInfo());
+  }
+
   /// defusechain_iterator - This class provides iterator support for machine
   /// operands in the function that use or define a specific register.  If
   /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
   /// returns defs.  If neither are true then you are silly and it always
   /// returns end().  If SkipDebug is true it skips uses marked Debug
   /// when incrementing.
   template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
            bool ByOperand, bool ByInstr, bool ByBundle>

include/llvm/CodeGen/StackMaps.h

 #include "llvm/MC/MCSymbol.h"
 #include <vector>
 
 namespace llvm {
 
 class AsmPrinter;
 class MCExpr;
 class MCStreamer;
+class TargetSubtargetInfo;
 
 /// \brief MI-level stackmap operands.
 ///
 /// MI stackmap operations take the form:
 /// <id>, <numBytes>, live args...
 class StackMapOpers {
 public:
   /// Enumerate the meta operands.
private:
 
   MachineInstr::const_mop_iterator
   parseOperand(MachineInstr::const_mop_iterator MOI,
                MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
                LiveOutVec &LiveOuts) const;
 
   /// \brief Create a live-out register record for the given register @p Reg.
   LiveOutReg createLiveOutReg(unsigned Reg,
-                              const TargetRegisterInfo *TRI) const;
+                              const TargetRegisterInfo *TRI,
+                              const TargetSubtargetInfo &STI) const;
 
   /// \brief Parse the register live-out mask and return a vector of live-out
   /// registers that need to be recorded in the stackmap.
   LiveOutVec parseRegisterLiveOutMask(const uint32_t *Mask) const;
 
   /// This should be called by the MC lowering code _immediately_ before
   /// lowering the MI to an MCInst. It records where the operands for the
   /// instruction are stored, and outputs a label to record the offset of

include/llvm/MC/MCRegisterInfo.h

 #include <cassert>
 
 namespace llvm {
 
 /// An unsigned integer type large enough to represent all physical registers,
 /// but not necessarily virtual registers.
 typedef uint16_t MCPhysReg;
 
+class MCSubtargetInfo;
+
 /// MCRegisterClass - Base class of TargetRegisterClass.
 class MCRegisterClass {
 public:
   typedef const MCPhysReg* iterator;
   typedef const MCPhysReg* const_iterator;
 
   const iterator RegsBegin;
   const uint8_t *const RegSet;
bool contains(unsigned Reg) const {
     return (RegSet[Byte] & (1 << InByte)) != 0;
   }
 
   /// contains - Return true if both registers are in this class.
   bool contains(unsigned Reg1, unsigned Reg2) const {
     return contains(Reg1) && contains(Reg2);
   }
 
-  /// getSize - Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return RegSize; }
-
-  /// getAlignment - Return the minimum required alignment for a register of
-  /// this class.
-  unsigned getAlignment() const { return Alignment; }
-
   /// getCopyCost - Return the cost of copying a value between two registers in
   /// this class. A negative number means the register class is very expensive
   /// to copy e.g. status flag register classes.
   int getCopyCost() const { return CopyCost; }
 
   /// isAllocatable - Return true if this register class may be used to create
   /// virtual registers.
   bool isAllocatable() const { return Allocatable; }
+
+private:
+  // XXX: Move these functions here to avoid accidental use.
+  unsigned getSize() const { return RegSize; }
+  unsigned getAlignment() const { return Alignment; }
+  friend class MCRegisterInfo;
 };
 
 /// MCRegisterDesc - This record contains information about a particular
 /// register.  The SubRegs field is a zero terminated array of registers that
 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
 /// of AX. The SuperRegs field is a zero terminated array of registers that are
 /// super-registers of the specific register, e.g. RAX, EAX, are
 /// super-registers of AX.
bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
     return RegA == RegB || isSuperRegister(RegA, RegB);
   }
 
   /// \brief Returns true if RegB is a super-register or sub-register of RegA
   /// or if RegB == RegA.
   bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
     return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
   }
+
+  /// \brief Returns the size of a register from the register class with
+  /// id \p RCID.
+  unsigned getRegSize(uint16_t RCID, const MCSubtargetInfo &STI) const {
+    // XXX No-op change.
+    return getRegClass(RCID).getSize();
+  }
+
+  /// \brief Returns the minimum size of a spill slot for storing a register
+  /// from the register class with id \p RCID.
+  unsigned getSpillSize(uint16_t RCID, const MCSubtargetInfo &STI) const {
+    // XXX No-op change.
+    return getRegClass(RCID).getSize();
+  }
+
+  /// \brief Returns the minimum alignment of a spill slot for storing a
+  /// register from the register class with id \p RCID.
+  unsigned getSpillAlignment(uint16_t RCID, const MCSubtargetInfo &STI) const {
+    // XXX No-op change.
+    return getRegClass(RCID).getAlignment();
+  }
 };
 
 //===----------------------------------------------------------------------===//
 //                          Register List Iterators
 //===----------------------------------------------------------------------===//
 
 // MCRegisterInfo provides lists of super-registers, sub-registers, and
 // aliasing registers. Use these iterator classes to traverse the lists.

include/llvm/Target/TargetLowering.h

protected:
 
   /// \brief Remove all operation actions.
   void clearOperationActions() {
   }
 
   /// Return the largest legal super-reg register class of the register class
   /// for the specified type and its associated "cost".
   virtual std::pair<const TargetRegisterClass *, uint8_t>
-  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
+  findRepresentativeClass(const TargetSubtargetInfo &STI, MVT VT) const;
 
   /// Once all of the register classes are added, this allows us to compute
   /// derived properties we expose.
-  void computeRegisterProperties(const TargetRegisterInfo *TRI);
+  void computeRegisterProperties(const TargetSubtargetInfo &STI);
 
   /// Indicate that the specified operation does not work with the specified
   /// type and indicate what to do about it.
   void setOperationAction(unsigned Op, MVT VT,
                           LegalizeAction Action) {
     assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
     OpActions[(unsigned)VT.SimpleTy][Op] = Action;
   }

include/llvm/Target/TargetRegisterInfo.h

 
 class BitVector;
 class MachineFunction;
 class RegScavenger;
 template<class T> class SmallVectorImpl;
 class VirtRegMap;
 class raw_ostream;
 class LiveRegMatrix;
+class TargetSubtargetInfo;
 
 /// A bitmask representing the covering of a register with sub-registers.
 ///
 /// This is typically used to track liveness at sub-register granularity.
 /// Lane masks for sub-register indices are similar to register units for
 /// physical registers. The individual bits in a lane mask can't be assigned
 /// any specific meaning. They can be used to check if two sub-register
 /// indices overlap.
bool contains(unsigned Reg) const {
     return MC->contains(Reg);
   }
 
   /// Return true if both registers are in this class.
   bool contains(unsigned Reg1, unsigned Reg2) const {
     return MC->contains(Reg1, Reg2);
   }
 
-  /// Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return MC->getSize(); }
-
-  /// Return the minimum required alignment for a register of this class.
-  unsigned getAlignment() const { return MC->getAlignment(); }
-
   /// Return the cost of copying a value between two registers in this class.
   /// A negative number means the register class is very expensive
   /// to copy e.g. status flag register classes.
   int getCopyCost() const { return MC->getCopyCost(); }
 
   /// Return true if this register class may be used to create virtual
   /// registers.
   bool isAllocatable() const { return MC->isAllocatable(); }
public:
   virtual const TargetRegisterClass *
   getMatchingSuperRegClass(const TargetRegisterClass *A,
                            const TargetRegisterClass *B, unsigned Idx) const;
 
   // For a copy-like instruction that defines a register of class DefRC with
   // subreg index DefSubReg, reading from another source with class SrcRC and
   // subregister SrcSubReg return true if this is a preferrable copy
   // instruction or an earlier use should be used.
-  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+  virtual bool shouldRewriteCopySrc(const TargetSubtargetInfo &STI,
+                                    const TargetRegisterClass *DefRC,
                                     unsigned DefSubReg,
                                     const TargetRegisterClass *SrcRC,
                                     unsigned SrcSubReg) const;
 
   /// Returns the largest legal sub-class of RC that
   /// supports the sub-register index Idx.
   /// If no such sub-class exists, return NULL.
   /// If all registers in RC already have an Idx sub-register, return RC.
public:
   /// that case, the returned register class will be a sub-class of the
   /// corresponding argument register class.
   ///
   /// The function returns NULL if no register class can be found.
   ///
   const TargetRegisterClass*
   getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
                          const TargetRegisterClass *RCB, unsigned SubB,
+                         const TargetSubtargetInfo &STI,
                          unsigned &PreA, unsigned &PreB) const;
 
   //===--------------------------------------------------------------------===//
   // Register Class Information
   //
 
   /// Register class iterators
   ///

lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp

if (MLoc.isIndirect())
       // FIXME: We have no reasonable way of handling errors in here. The
       // caller might be in the middle of a dwarf expression. We should
       // probably assert that Reg >= 0 once debug info generation is more
       // mature.
       return Expr.EmitOp(dwarf::DW_OP_nop,
                          "nop (could not find a dwarf register number)");
 
     // Attempt to find a valid super- or sub-register.
-    if (!Expr.AddMachineRegPiece(*MF->getSubtarget().getRegisterInfo(),
-                                 MLoc.getReg()))
+    if (!Expr.AddMachineRegPiece(MF->getSubtarget(), MLoc.getReg()))
       Expr.EmitOp(dwarf::DW_OP_nop,
                   "nop (could not find a dwarf register number)");
     return;
   }
 
   if (MLoc.isIndirect())
     Expr.AddRegIndirect(Reg, MLoc.getOffset());
   else

lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

DIE *DwarfCompileUnit::constructVariableDIEImpl(const DbgVariable &DV,
   auto Expr = DV.getExpression().begin();
   DIELoc *Loc = new (DIEValueAllocator) DIELoc;
   DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc);
   for (auto FI : DV.getFrameIndex()) {
     unsigned FrameReg = 0;
     const TargetFrameLowering *TFI = Asm->MF->getSubtarget().getFrameLowering();
     int Offset = TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
     assert(Expr != DV.getExpression().end() && "Wrong number of expressions");
-    DwarfExpr.AddMachineRegIndirect(*Asm->MF->getSubtarget().getRegisterInfo(),
-                                    FrameReg, Offset);
+    DwarfExpr.AddMachineRegIndirect(Asm->MF->getSubtarget(), FrameReg, Offset);
     DwarfExpr.AddExpression((*Expr)->expr_op_begin(), (*Expr)->expr_op_end());
     ++Expr;
   }
   addBlock(*VariableDie, dwarf::DW_AT_location, Loc);
 
   return VariableDie;
 }
 

 /// location.  Add the DWARF information to the die.
 void DwarfCompileUnit::addComplexAddress(const DbgVariable &DV, DIE &Die,
                                          dwarf::Attribute Attribute,
                                          const MachineLocation &Location) {
   DIELoc *Loc = new (DIEValueAllocator) DIELoc;
   DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc);
   const DIExpression *Expr = DV.getSingleExpression();
   bool ValidReg;
-  const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
+  const TargetSubtargetInfo &STI = Asm->MF->getSubtarget();
   if (Location.getOffset()) {
-    ValidReg = DwarfExpr.AddMachineRegIndirect(TRI, Location.getReg(),
+    ValidReg = DwarfExpr.AddMachineRegIndirect(STI, Location.getReg(),
                                                Location.getOffset());
     if (ValidReg)
       DwarfExpr.AddExpression(Expr->expr_op_begin(), Expr->expr_op_end());
   } else
-    ValidReg = DwarfExpr.AddMachineRegExpression(TRI, Expr, Location.getReg());
+    ValidReg = DwarfExpr.AddMachineRegExpression(STI, Expr, Location.getReg());
 
   // Now attach the location information to the DIE.
   if (ValidReg)
     addBlock(Die, Attribute, Loc);
 }
 
 /// Add a Dwarf loclistptr attribute data and value.
 void DwarfCompileUnit::addLocationList(DIE &Die, dwarf::Attribute Attribute,

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

static void emitDebugLocValue(const AsmPrinter &AP, const DIBasicType *BT,
   } else if (Value.isLocation()) {
     MachineLocation Loc = Value.getLoc();
     const DIExpression *Expr = Value.getExpression();
     if (!Expr || !Expr->getNumElements())
       // Regular entry.
       AP.EmitDwarfRegOp(Streamer, Loc);
     else {
       // Complex address entry.
-      const TargetRegisterInfo &TRI = *AP.MF->getSubtarget().getRegisterInfo();
+      const TargetSubtargetInfo &STI = AP.MF->getSubtarget();
       if (Loc.getOffset()) {
-        DwarfExpr.AddMachineRegIndirect(TRI, Loc.getReg(), Loc.getOffset());
+        DwarfExpr.AddMachineRegIndirect(STI, Loc.getReg(), Loc.getOffset());
         DwarfExpr.AddExpression(Expr->expr_op_begin(), Expr->expr_op_end(),
                                 PieceOffsetInBits);
       } else
-        DwarfExpr.AddMachineRegExpression(TRI, Expr, Loc.getReg(),
+        DwarfExpr.AddMachineRegExpression(STI, Expr, Loc.getReg(),
                                           PieceOffsetInBits);
     }
   } else if (Value.isConstantFP()) {
     APInt RawBytes = Value.getConstantFP()->getValueAPF().bitcastToAPInt();
     DwarfExpr.AddUnsignedConstant(RawBytes);
   }
 }
 

lib/CodeGen/AsmPrinter/DwarfExpression.h

 #include "llvm/IR/DebugInfo.h"
 #include "llvm/Support/DataTypes.h"
 
 namespace llvm {
 
 class AsmPrinter;
 class ByteStreamer;
 class TargetRegisterInfo;
+class TargetSubtargetInfo;
 class DwarfUnit;
 class DIELoc;
 
 /// Base class containing the logic for constructing DWARF expressions
 /// independently of whether they are emitted into a DIE or into a .debug_loc
 /// entry.
 class DwarfExpression {
 protected:
public:
   /// However, in the past there was no better way  to describe a constant
   /// value, so the producers and consumers started to rely on heuristics
   /// to disambiguate the value vs. location status of the expression.
   /// See PR21176 for more details.
   void AddStackValue();
 
   /// Emit an indirect dwarf register operation for the given machine register.
   /// \return false if no DWARF register exists for MachineReg.
-  bool AddMachineRegIndirect(const TargetRegisterInfo &TRI, unsigned MachineReg,
-                             int Offset = 0);
+  bool AddMachineRegIndirect(const TargetSubtargetInfo &STI,
+                             unsigned MachineReg, int Offset = 0);
 
   /// \brief Emit a partial DWARF register operation.
   /// \param MachineReg        the register
   /// \param PieceSizeInBits   size and
   /// \param PieceOffsetInBits offset of the piece in bits, if this is one
   ///                          piece of an aggregate value.
   ///
   /// If size and offset is zero an operation for the entire
   /// register is emitted: Some targets do not provide a DWARF
   /// register number for every register.  If this is the case, this
   /// function will attempt to emit a DWARF register by emitting a
   /// piece of a super-register or by piecing together multiple
   /// subregisters that alias the register.
   ///
   /// \return false if no DWARF register exists for MachineReg.
-  bool AddMachineRegPiece(const TargetRegisterInfo &TRI, unsigned MachineReg,
+  bool AddMachineRegPiece(const TargetSubtargetInfo &STI, unsigned MachineReg,
                           unsigned PieceSizeInBits = 0,
                           unsigned PieceOffsetInBits = 0);
 
   /// Emit a signed constant.
   void AddSignedConstant(int64_t Value);
   /// Emit an unsigned constant.
   void AddUnsignedConstant(uint64_t Value);
   /// Emit an unsigned constant.
   void AddUnsignedConstant(const APInt &Value);
 
   /// \brief Emit an entire expression on top of a machine register location.
   ///
   /// \param PieceOffsetInBits If this is one piece out of a fragmented
   /// location, this is the offset of the piece inside the entire variable.
   /// \return false if no DWARF register exists for MachineReg.
-  bool AddMachineRegExpression(const TargetRegisterInfo &TRI,
+  bool AddMachineRegExpression(const TargetSubtargetInfo &STI,
                                const DIExpression *Expr, unsigned MachineReg,
                                unsigned PieceOffsetInBits = 0);
   /// Emit a the operations remaining the DIExpressionIterator I.
   /// \param PieceOffsetInBits If this is one piece out of a fragmented
   /// location, this is the offset of the piece inside the entire variable.
   void AddExpression(DIExpression::expr_op_iterator I,
                      DIExpression::expr_op_iterator E,
                      unsigned PieceOffsetInBits = 0);

lib/CodeGen/AsmPrinter/DwarfExpression.cpp

 }
 
 void DwarfExpression::AddShr(unsigned ShiftBy) {
   EmitOp(dwarf::DW_OP_constu);
   EmitUnsigned(ShiftBy);
   EmitOp(dwarf::DW_OP_shr);
 }
 
-bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI,
+bool DwarfExpression::AddMachineRegIndirect(const TargetSubtargetInfo &STI,
                                             unsigned MachineReg, int Offset) {
+  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
   if (isFrameRegister(TRI, MachineReg)) {
     // If variable offset is based in frame register then use fbreg.
     EmitOp(dwarf::DW_OP_fbreg);
     EmitSigned(Offset);
     return true;
   }
 
   int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
   if (DwarfReg < 0)
     return false;
 
   AddRegIndirect(DwarfReg, Offset);
   return true;
 }
 
-bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI,
+bool DwarfExpression::AddMachineRegPiece(const TargetSubtargetInfo &STI,
                                          unsigned MachineReg,
                                          unsigned PieceSizeInBits,
                                          unsigned PieceOffsetInBits) {
+  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
   if (!TRI.isPhysicalRegister(MachineReg))
     return false;
 
   int Reg = TRI.getDwarfRegNum(MachineReg, false);
 
   // If this is a valid register number, emit it.
   if (Reg >= 0) {
     AddReg(Reg);
bool DwarfExpression::AddMachineRegPiece(const TargetSubtargetInfo &STI,
 
   // Otherwise, attempt to find a covering set of sub-register numbers.
   // For example, Q0 on ARM is a composition of D0+D1.
   //
   // Keep track of the current position so we can emit the more
   // efficient DW_OP_piece.
   unsigned CurPos = PieceOffsetInBits;
   // The size of the register in bits, assuming 8 bits per byte.
-  unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
+  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
+  unsigned RegSize = TRI.getRegSize(RC->getID(), STI) * 8;
   // Keep track of the bits in the register we already emitted, so we
   // can avoid emitting redundant aliasing subregs.
   SmallBitVector Coverage(RegSize, false);
   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
     unsigned Size = TRI.getSubRegIdxSize(Idx);
     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
     Reg = TRI.getDwarfRegNum(*SR, false);

 static unsigned getOffsetOrZero(unsigned OffsetInBits,
                                 unsigned PieceOffsetInBits) {
   if (OffsetInBits == PieceOffsetInBits)
     return 0;
   assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
   return OffsetInBits;
 }
 
-bool DwarfExpression::AddMachineRegExpression(const TargetRegisterInfo &TRI,
+bool DwarfExpression::AddMachineRegExpression(const TargetSubtargetInfo &STI,
                                               const DIExpression *Expr,
                                               unsigned MachineReg,
                                               unsigned PieceOffsetInBits) {
   auto I = Expr->expr_op_begin();
   auto E = Expr->expr_op_end();
   if (I == E)
-    return AddMachineRegPiece(TRI, MachineReg);
+    return AddMachineRegPiece(STI, MachineReg);
 
   // Pattern-match combinations for which more efficient representations exist
   // first.
   bool ValidReg = false;
   switch (I->getOp()) {
   case dwarf::DW_OP_bit_piece: {
     unsigned OffsetInBits = I->getArg(0);
     unsigned SizeInBits   = I->getArg(1);
     // Piece always comes at the end of the expression.
-    return AddMachineRegPiece(TRI, MachineReg, SizeInBits,
+    return AddMachineRegPiece(STI, MachineReg, SizeInBits,
                getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
   }
   case dwarf::DW_OP_plus:
   case dwarf::DW_OP_minus: {
     // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
     // [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
     auto N = I.getNext();
     if (N != E && N->getOp() == dwarf::DW_OP_deref) {
       unsigned Offset = I->getArg(0);
       ValidReg = AddMachineRegIndirect(
-          TRI, MachineReg, I->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
+          STI, MachineReg, I->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
       std::advance(I, 2);
       break;
     } else
-      ValidReg = AddMachineRegPiece(TRI, MachineReg);
+      ValidReg = AddMachineRegPiece(STI, MachineReg);
   }
   case dwarf::DW_OP_deref: {
       // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
-      ValidReg = AddMachineRegIndirect(TRI, MachineReg);
+      ValidReg = AddMachineRegIndirect(STI, MachineReg);
       ++I;
       break;
   }
   default:
     llvm_unreachable("unsupported operand");
   }
 
   if (!ValidReg)

lib/CodeGen/AsmPrinter/DwarfUnit.cpp

 
 void DwarfUnit::addSourceLine(DIE &Die, const DINamespace *NS) {
   addSourceLine(Die, NS->getLine(), NS->getFilename(), NS->getDirectory());
 }
 
 bool DwarfUnit::addRegisterOpPiece(DIELoc &TheDie, unsigned Reg,
                                    unsigned SizeInBits, unsigned OffsetInBits) {
   DIEDwarfExpression Expr(*Asm, *this, TheDie);
-  Expr.AddMachineRegPiece(*Asm->MF->getSubtarget().getRegisterInfo(), Reg,
-                          SizeInBits, OffsetInBits);
+  Expr.AddMachineRegPiece(Asm->MF->getSubtarget(), Reg, SizeInBits,
+                          OffsetInBits);
   return true;
 }
 
 bool DwarfUnit::addRegisterOffset(DIELoc &TheDie, unsigned Reg,
                                   int64_t Offset) {
   DIEDwarfExpression Expr(*Asm, *this, TheDie);
-  return Expr.AddMachineRegIndirect(*Asm->MF->getSubtarget().getRegisterInfo(),
-                                    Reg, Offset);
+  return Expr.AddMachineRegIndirect(Asm->MF->getSubtarget(), Reg, Offset);
 }
 
 /* Byref variables, in Blocks, are declared by the programmer as "SomeType
    VarName;", but the compiler creates a __Block_byref_x_VarName struct, and
    gives the variable VarName either the struct, or a pointer to the struct, as
    its type.  This is necessary for various behind-the-scenes things the
    compiler needs to do with by-reference variables in Blocks.
 

lib/CodeGen/DetectDeadLanes.cpp

static bool isCrossCopy(const MachineRegisterInfo &MRI,
   unsigned SrcReg = MO.getReg();
   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
   if (DstRC == SrcRC)
     return false;
 
   unsigned SrcSubIdx = MO.getSubReg();
 
   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
+  const TargetSubtargetInfo &STI = MRI.getTargetSubtargetInfo();
+
   unsigned DstSubIdx = 0;
   switch (MI.getOpcode()) {
   case TargetOpcode::INSERT_SUBREG:
     if (MI.getOperandNo(&MO) == 2)
       DstSubIdx = MI.getOperand(3).getImm();
     break;
   case TargetOpcode::REG_SEQUENCE: {
     unsigned OpNum = MI.getOperandNo(&MO);
     DstSubIdx = MI.getOperand(OpNum+1).getImm();
     break;
   }
   case TargetOpcode::EXTRACT_SUBREG: {
     unsigned SubReg = MI.getOperand(2).getImm();
     SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
   }
   }
 
   unsigned PreA, PreB; // Unused.
   if (SrcSubIdx && DstSubIdx)
-    return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
-                                       PreB);
+    return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, STI,
+                                       PreA, PreB);
   if (SrcSubIdx)
     return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
   if (DstSubIdx)
     return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
   return !TRI.getCommonSubClass(SrcRC, DstRC);
 }
 
 void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,

lib/CodeGen/MachineRegisterInfo.cpp

 }
 
 void MachineRegisterInfo::clearVirtRegTypes() {
 #ifndef NDEBUG
   // Verify that the size of the now-constrained vreg is unchanged.
   for (auto &VRegToType : getVRegToType()) {
     auto *RC = getRegClass(VRegToType.first);
     if (VRegToType.second.isSized() &&
-        VRegToType.second.getSizeInBits() > (RC->getSize() * 8))
+        VRegToType.second.getSizeInBits() > getRegSize(RC) * 8)
       llvm_unreachable(
           "Virtual register has explicit size different from its class size");
   }
 #endif
 
   getVRegToType().clear();
 }
 

lib/CodeGen/PeepholeOptimizer.cpp

bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
                                        RewriteMapTy &RewriteMap) {
   // Do not try to find a new source for a physical register.
   // So far we do not have any motivating example for doing that.
   // Thus, instead of maintaining untested code, we will revisit that if
   // that changes at some point.
   if (TargetRegisterInfo::isPhysicalRegister(Reg))
     return false;
   const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
+  const TargetSubtargetInfo &STI = MRI->getTargetSubtargetInfo();
 
   SmallVector<TargetInstrInfo::RegSubRegPair, 4> SrcToLook;
   TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
   SrcToLook.push_back(CurSrcPair);
 
   unsigned PHICount = 0;
   while (!SrcToLook.empty() && PHICount < RewritePHILimit) {
     TargetInstrInfo::RegSubRegPair Pair = SrcToLook.pop_back_val();
do {
       // Do not extend the live-ranges of physical registers as they add
       // constraints to the register allocator. Moreover, if we want to extend
       // the live-range of a physical register, unlike SSA virtual register,
       // we will have to check that they aren't redefine before the related use.
       if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
         return false;
 
       const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
-      ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
+      ShouldRewrite = TRI->shouldRewriteCopySrc(STI, DefRC, SubReg, SrcRC,
                                                 CurSrcPair.SubReg);
     } while (!ShouldRewrite);
 
     // Continue looking for new sources...
     if (Res.isValid())
       continue;
 
     // Do not continue searching for a new source if the there's at least

lib/CodeGen/PrologEpilogInserter.cpp

static void assignCalleeSavedSpillSlots(MachineFunction &F,
   const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
   MachineFrameInfo &MFI = F.getFrameInfo();
   if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
     // If target doesn't implement this, use generic code.
 
     if (CSI.empty())
       return; // Early exit if no callee saved registers are modified!
 
+    MachineRegisterInfo &MRI = F.getRegInfo();
     unsigned NumFixedSpillSlots;
     const TargetFrameLowering::SpillSlot *FixedSpillSlots =
         TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots);
 
     // Now that we know which registers need to be saved and restored, allocate
     // stack slots for them.
     for (auto &CS : CSI) {
       unsigned Reg = CS.getReg();
       const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
 
       int FrameIdx;
       if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
         CS.setFrameIdx(FrameIdx);
         continue;
       }
 
       // Check to see if this physreg must be spilled to a particular stack slot
       // on this target.
       const TargetFrameLowering::SpillSlot *FixedSlot = FixedSpillSlots;
       while (FixedSlot != FixedSpillSlots + NumFixedSpillSlots &&
              FixedSlot->Reg != Reg)
         ++FixedSlot;
 
+      unsigned Size = MRI.getSpillSize(RC);
+
       if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
         // Nope, just spill it anywhere convenient.
-        unsigned Align = RC->getAlignment();
+        unsigned Align = MRI.getSpillAlignment(RC);
         unsigned StackAlign = TFI->getStackAlignment();
-
         // We may not be able to satisfy the desired alignment specification of
         // the TargetRegisterClass if the stack alignment is smaller. Use the
         // min.
         Align = std::min(Align, StackAlign);
-        FrameIdx = MFI.CreateStackObject(RC->getSize(), Align, true);
+        FrameIdx = MFI.CreateStackObject(Size, Align, true);
         if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
         if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
       } else {
         // Spill it to the stack where we must.
-        FrameIdx =
-            MFI.CreateFixedSpillStackObject(RC->getSize(), FixedSlot->Offset);
+        FrameIdx = MFI.CreateFixedSpillStackObject(Size, FixedSlot->Offset);
       }
 
       CS.setFrameIdx(FrameIdx);
     }
   }
 
   MFI.setCalleeSavedInfo(CSI);
 }

lib/CodeGen/RegAllocFast.cpp

 /// to be held on the stack.
 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
   // Find the location Reg would belong...
   int SS = StackSlotForVirtReg[VirtReg];
   if (SS != -1)
     return SS;          // Already has space allocated?
 
   // Allocate a new stack object for this spill location...
-  int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
-                                                           RC->getAlignment());
+  unsigned Size = MRI->getSpillSize(RC);
+  unsigned Align = MRI->getSpillAlignment(RC);
+  int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
 
   // Assign the slot.
   StackSlotForVirtReg[VirtReg] = FrameIdx;
   return FrameIdx;
 }
 
 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
 /// its virtual register, and it is guaranteed to be a block-local register.

lib/CodeGen/RegisterCoalescer.cpp

bool CoalescerPair::setRegisters(const MachineInstr *MI) {
   if (TargetRegisterInfo::isPhysicalRegister(Src)) {
     if (TargetRegisterInfo::isPhysicalRegister(Dst))
       return false;
     std::swap(Src, Dst);
     std::swap(SrcSub, DstSub);
     Flipped = true;
   }
 
-  const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+  const MachineFunction &MF = *MI->getParent()->getParent();
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
 
   if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
     // Eliminate DstSub on a physreg.
     if (DstSub) {
       Dst = TRI.getSubReg(Dst, DstSub);
       if (!Dst) return false;
       DstSub = 0;
     }
if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
 
     // Both registers have subreg indices.
     if (SrcSub && DstSub) {
       // Copies between different sub-registers are never coalescable.
       if (Src == Dst && SrcSub != DstSub)
         return false;
 
-      NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
+      NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, STI,
                                          SrcIdx, DstIdx);
       if (!NewRC)
         return false;
     } else if (DstSub) {
       // SrcReg will be merged with a sub-register of DstReg.
       SrcIdx = DstSub;
       NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
     } else if (SrcSub) {

lib/CodeGen/RegisterScavenging.cpp

unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
   if (!isRegUsed(SReg)) {
     DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
     return SReg;
   }
 
   // Find an available scavenging slot with size and alignment matching
   // the requirements of the class RC.
   const MachineFrameInfo &MFI = MF.getFrameInfo();
-  unsigned NeedSize = RC->getSize();
-  unsigned NeedAlign = RC->getAlignment();
+  unsigned NeedSize = MRI->getSpillSize(RC);
+  unsigned NeedAlign = MRI->getSpillAlignment(RC);
 
   unsigned SI = Scavenged.size(), Diff = UINT_MAX;
   int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
   for (unsigned I = 0; I < Scavenged.size(); ++I) {
     if (Scavenged[I].Reg != 0)
       continue;
     // Verify that this slot is valid for this register.
     int FI = Scavenged[I].FrameIndex;

lib/CodeGen/StackMaps.cpp

static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
   assert(RegNum >= 0 && "Invalid Dwarf register number.");
   return (unsigned)RegNum;
 }
 
 MachineInstr::const_mop_iterator
 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
                         MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
                         LiveOutVec &LiveOuts) const {
-  const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
+  const TargetSubtargetInfo &STI = AP.MF->getSubtarget();
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
   if (MOI->isImm()) {
     switch (MOI->getImm()) {
     default:
       llvm_unreachable("Unrecognized operand type.");
     case StackMaps::DirectMemRefOp: {
       auto &DL = AP.MF->getDataLayout();
 
       unsigned Size = DL.getPointerSizeInBits();
if (MOI->isReg()) {
 
     unsigned Offset = 0;
     unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI);
     unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false);
     unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
     if (SubRegIdx)
       Offset = TRI->getSubRegIdxOffset(SubRegIdx);
 
-    Locs.emplace_back(Location::Register, RC->getSize(), DwarfRegNum, Offset);
+    unsigned Size = TRI->getSpillSize(RC->getID(), STI);
+    Locs.emplace_back(Location::Register, Size, DwarfRegNum, Offset);
     return ++MOI;
   }
 
   if (MOI->isRegLiveOut())
     LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
 
   return ++MOI;
 }
for (const auto &LO : LiveOuts) {
          << LO.Size << "]\n";
       Idx++;
     }
   }
 }
 
 /// Create a live-out register record for the given register Reg.
 StackMaps::LiveOutReg
-StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
+StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI,
+                            const TargetSubtargetInfo &STI) const {
   unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI);
-  unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
-  return LiveOutReg(Reg, DwarfRegNum, Size);
+  unsigned ID = TRI->getMinimalPhysRegClass(Reg)->getID();
+  return LiveOutReg(Reg, DwarfRegNum, TRI->getSpillSize(ID, STI));
 }
 
 /// Parse the register live-out mask and return a vector of live-out registers
 /// that need to be recorded in the stackmap.
 StackMaps::LiveOutVec
 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
   assert(Mask && "No register mask specified");
-  const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
+  const TargetSubtargetInfo &STI = AP.MF->getSubtarget();
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
   LiveOutVec LiveOuts;
 
   // Create a LiveOutReg for each bit that is set in the register mask.
   for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
     if ((Mask[Reg / 32] >> Reg % 32) & 1)
-      LiveOuts.push_back(createLiveOutReg(Reg, TRI));
+      LiveOuts.push_back(createLiveOutReg(Reg, TRI, STI));
 
   // We don't need to keep track of a register if its super-register is already
   // in the list. Merge entries that refer to the same dwarf register and use
   // the maximum size that needs to be spilled.
 
   std::sort(LiveOuts.begin(), LiveOuts.end(),
             [](const LiveOutReg &LHS, const LiveOutReg &RHS) {
               // Only sort by the dwarf register number.

lib/CodeGen/TargetInstrInfo.cpp

bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
   }
   return false;
 }
 
 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
                                         unsigned SubIdx, unsigned &Size,
                                         unsigned &Offset,
                                         const MachineFunction &MF) const {
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
+  unsigned RCSize = TRI->getSpillSize(RC->getID(), STI);
+
   if (!SubIdx) {
-    Size = RC->getSize();
+    Size = RCSize;
     Offset = 0;
     return true;
   }
-  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
   // Convert bit size to byte size to be consistent with
   // MCRegisterClass::getSize().
   if (BitSize % 8)
     return false;
 
   int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
   if (BitOffset < 0 || BitOffset % 8)
     return false;
 
   Size = BitSize /= 8;
   Offset = (unsigned)BitOffset / 8;
 
-  assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
+  assert(RCSize >= (Offset + Size) && "bad subregister range");
 
   if (!MF.getDataLayout().isLittleEndian()) {
-    Offset = RC->getSize() - (Offset + Size);
+    Offset = RCSize - (Offset + Size);
   }
   return true;
 }
 
 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned DestReg, unsigned SubIdx,
                                     const MachineInstr &Orig,

lib/CodeGen/TargetLoweringBase.cpp

 
 /// findRepresentativeClass - Return the largest legal super-reg register class
 /// of the register class for the specified type and its associated "cost".
 // This function is in TargetLowering because it uses RegClassForVT which would
 // need to be moved to TargetRegisterInfo and would necessitate moving
 // isTypeLegal over as well - a massive change that would just require
 // TargetLowering having a TargetRegisterInfo class member that it would use.
 std::pair<const TargetRegisterClass *, uint8_t>
-TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
+TargetLoweringBase::findRepresentativeClass(const TargetSubtargetInfo &STI,
                                             MVT VT) const {
   const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
   if (!RC)
     return std::make_pair(RC, 0);
 
   // Compute the set of all super-register classes.
-  BitVector SuperRegRC(TRI->getNumRegClasses());
-  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
+  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+  BitVector SuperRegRC(TRI.getNumRegClasses());
+  for (SuperRegClassIterator RCI(RC, &TRI); RCI.isValid(); ++RCI)
     SuperRegRC.setBitsInMask(RCI.getMask());
 
   // Find the first legal register class with the largest spill size.
   const TargetRegisterClass *BestRC = RC;
+  unsigned BestSize = TRI.getSpillSize(BestRC->getID(), STI);
+
   for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
-    const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
+    const TargetRegisterClass *SuperRC = TRI.getRegClass(i);
     // We want the largest possible spill size.
-    if (SuperRC->getSize() <= BestRC->getSize())
+    unsigned SuperSize = TRI.getSpillSize(SuperRC->getID(), STI);
+    if (SuperSize <= BestSize)
       continue;
     if (!isLegalRC(SuperRC))
       continue;
     BestRC = SuperRC;
+    BestSize = SuperSize;
   }
   return std::make_pair(BestRC, 1);
 }
 
 /// computeRegisterProperties - Once all of the register classes are added,
 /// this allows us to compute derived properties we expose.
 void TargetLoweringBase::computeRegisterProperties(
-    const TargetRegisterInfo *TRI) {
+    const TargetSubtargetInfo &STI) {
   static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
                 "Too many value types for ValueTypeActions to hold!");
 
   // Everything defaults to needing one register.
   for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
     NumRegistersForVT[i] = 1;
     RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
   }
void TargetLoweringBase::computeRegisterProperties(
   // Determine the 'representative' register class for each value type.
   // An representative register class is the largest (meaning one which is
   // not a sub-register class / subreg register class) legal register class for
   // a group of value types. For example, on i386, i8, i16, and i32
   // representative would be GR32; while on x86_64 it's GR64.
   for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
     const TargetRegisterClass* RRC;
     uint8_t Cost;
-    std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
+    std::tie(RRC, Cost) = findRepresentativeClass(STI, (MVT::SimpleValueType)i);
     RepRegClassForVT[i] = RRC;
     RepRegClassCostForVT[i] = Cost;
   }
 }
 
 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                            EVT VT) const {
   assert(!VT.isVector() && "No default SetCC type for vectors!");

lib/CodeGen/TargetRegisterInfo.cpp

if (RCI.getSubReg() == Idx)
       // by Idx. Find a class that is also a sub-class of A.
       return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
   return nullptr;
 }
 
 const TargetRegisterClass *TargetRegisterInfo::
 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
                        const TargetRegisterClass *RCB, unsigned SubB,
+                       const TargetSubtargetInfo &STI,
                        unsigned &PreA, unsigned &PreB) const {
   assert(RCA && SubA && RCB && SubB && "Invalid arguments");
 
   // Search all pairs of sub-register indices that project into RCA and RCB
   // respectively. This is quadratic, but usually the sets are very small. On
   // most targets like X86, there will only be a single sub-register index
   // (e.g., sub_16bit projecting into GR16).
   //
   // The worst case is a register class like DPR on ARM.
   // We have indices dsub_0..dsub_7 projecting into that class.
   //
   // It is very common that one register class is a sub-register of the other.
   // Arrange for RCA to be the larger register so the answer will be found in
   // the first iteration. This makes the search linear for the most common
   // case.
   const TargetRegisterClass *BestRC = nullptr;
   unsigned *BestPreA = &PreA;
   unsigned *BestPreB = &PreB;
-  if (RCA->getSize() < RCB->getSize()) {
+  if (getRegSize(RCA->getID(), STI) < getRegSize(RCB->getID(), STI)) {
     std::swap(RCA, RCB);
     std::swap(SubA, SubB);
     std::swap(BestPreA, BestPreB);
   }
 
   // Also terminate the search one we have found a register class as small as
   // RCA.
-  unsigned MinSize = RCA->getSize();
+  unsigned MinSize = getRegSize(RCA->getID(), STI);
 
   for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
     unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
     for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
       // Check if a common super-register class exists for this index pair.
       const TargetRegisterClass *RC =
         firstCommonClass(IA.getMask(), IB.getMask(), this);
-      if (!RC || RC->getSize() < MinSize)
+      if (!RC || getRegSize(RC->getID(), STI) < MinSize)
         continue;
 
       // The indexes must compose identically: PreA+SubA == PreB+SubB.
       unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
       if (FinalA != FinalB)
         continue;
 
       // Is RC a better candidate than BestRC?
-      if (BestRC && RC->getSize() >= BestRC->getSize())
+      if (BestRC &&
+          getRegSize(RC->getID(), STI) >= getRegSize(BestRC->getID(), STI))
         continue;
 
       // Yes, RC is the smallest super-register seen so far.
       BestRC = RC;
       *BestPreA = IA.getSubReg();
       *BestPreB = IB.getSubReg();
 
       // Bail early if we reached MinSize. We won't find a better candidate.
-      if (BestRC->getSize() == MinSize)
+      if (getRegSize(BestRC->getID(), STI) == MinSize)
         return BestRC;
     }
   }
   return BestRC;
 }
 
 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
 /// share the same register file.
-static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
+static bool shareSameRegisterFile(const TargetSubtargetInfo &STI,
                                   const TargetRegisterClass *DefRC,
                                   unsigned DefSubReg,
                                   const TargetRegisterClass *SrcRC,
                                   unsigned SrcSubReg) {
   // Same register class.
   if (DefRC == SrcRC)
     return true;
 
+  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+
   // Both operands are sub registers. Check if they share a register class.
   unsigned SrcIdx, DefIdx;
   if (SrcSubReg && DefSubReg) {
-    return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
+    return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, STI,
                                       SrcIdx, DefIdx) != nullptr;
   }
 
   // At most one of the register is a sub register, make it Src to avoid
   // duplicating the test.
   if (!SrcSubReg) {
     std::swap(DefSubReg, SrcSubReg);
     std::swap(DefRC, SrcRC);
   }
 
   // One of the register is a sub register, check if we can get a superclass.
   if (SrcSubReg)
     return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
 
   // Plain copy.
   return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
 }
 
-bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetSubtargetInfo &STI,
+                                              const TargetRegisterClass *DefRC,
                                               unsigned DefSubReg,
                                               const TargetRegisterClass *SrcRC,
                                               unsigned SrcSubReg) const {
   // If this source does not incur a cross register bank copy, use it.
-  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
+  assert(STI.getRegisterInfo() == this);
+  return shareSameRegisterFile(STI, DefRC, DefSubReg, SrcRC, SrcSubReg);
 }
 
 // Compute target-independent register allocator hints to help eliminate copies.
 void
 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
                                           ArrayRef<MCPhysReg> Order,
                                           SmallVectorImpl<MCPhysReg> &Hints,
                                           const MachineFunction &MF,

lib/CodeGen/VirtRegMap.cpp

 void VirtRegMap::grow() {
   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
   Virt2PhysMap.resize(NumRegs);
   Virt2StackSlotMap.resize(NumRegs);
   Virt2SplitMap.resize(NumRegs);
 }
 
 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
-  int SS = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
-                                                     RC->getAlignment());
+  const TargetSubtargetInfo &STI = MF->getSubtarget();
+  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+  unsigned Size = TRI.getSpillSize(RC->getID(), STI);
+  unsigned Align = TRI.getSpillAlignment(RC->getID(), STI);
+  int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
   ++NumSpillSlots;
   return SS;
 }
 
 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
   unsigned Hint = MRI->getSimpleHint(VirtReg);
   if (!Hint)
     return false;

lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   bool CanEliminateFrame = NumRegsSpilled == 0;
 
   // FIXME: Set BigStack if any stack slot references may be out of range.
   // For now, just conservatively guestimate based on unscaled indexing
   // range. We'll end up allocating an unnecessary spill slot a lot, but
   // realistically that's not a big deal at this stage of the game.
   // The CSR spill slots have not been allocated yet, so estimateStackSize
   // won't include them.
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned CFSize = MFI.estimateStackSize(MF) + 8 * NumRegsSpilled;
   DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
   bool BigStack = (CFSize >= 256);
   if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
     AFI->setHasStackFrame(true);
 
   // Estimate if we might need to scavenge a register at some point in order
if (UnspilledCSGPR != AArch64::NoRegister) {
       ExtraCSSpill = true;
       NumRegsSpilled = SavedRegs.count();
     }
 
     // If we didn't find an extra callee-saved register to spill, create
     // an emergency spill slot.
     if (!ExtraCSSpill) {
       const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
-      int FI = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), false);
+      int FI = MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                     MRI.getSpillAlignment(RC),
+                                     false);
       RS->addScavengingFrameIndex(FI);
       DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
                    << " as the emergency spill slot.\n");
     }
   }
 
   // Round up to register pair alignment to avoid additional SP adjustment
   // instructions.
   AFI->setCalleeSavedStackSize(alignTo(8 * NumRegsSpilled, 16));
 }
 
 bool AArch64FrameLowering::enableStackSlotScavenging(
     const MachineFunction &MF) const {
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   return AFI->hasCalleeSaveStackFreeSpace();
 }

lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
     addQRTypeForNEON(MVT::v16i8);
     addQRTypeForNEON(MVT::v8i16);
     addQRTypeForNEON(MVT::v4i32);
     addQRTypeForNEON(MVT::v2i64);
     addQRTypeForNEON(MVT::v8f16);
   }
 
   // Compute derived properties from the register classes
-  computeRegisterProperties(Subtarget->getRegisterInfo());
+  computeRegisterProperties(*Subtarget);
 
   // Provide all sorts of operation actions
   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
   setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
   setOperationAction(ISD::SETCC, MVT::i32, Custom);
   setOperationAction(ISD::SETCC, MVT::i64, Custom);
   setOperationAction(ISD::SETCC, MVT::f32, Custom);
   setOperationAction(ISD::SETCC, MVT::f64, Custom);

lib/Target/AArch64/AArch64InstrInfo.cpp

void AArch64InstrInfo::storeRegToStackSlot(
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
   unsigned Opc = 0;
   bool Offset = true;
-  switch (RC->getSize()) {
+  unsigned StoreSize = TRI->getSpillSize(RC->getID(), Subtarget);
+  switch (StoreSize) {
   case 1:
     if (AArch64::FPR8RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRBui;
     break;
   case 2:
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRHui;
     break;
void AArch64InstrInfo::loadRegFromStackSlot(
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
 
   unsigned Opc = 0;
   bool Offset = true;
-  switch (RC->getSize()) {
+  unsigned LoadSize = TRI->getSpillSize(RC->getID(), Subtarget);
+  switch (LoadSize) {
   case 1:
     if (AArch64::FPR8RegClass.hasSubClassEq(RC))
       Opc = AArch64::LDRBui;
     break;
   case 2:
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::LDRHui;
     break;

lib/Target/AMDGPU/AMDGPU.td

 }
 
 def AMDGPUAsmParser : AsmParser {
   // Some of the R600 registers have the same name, so this crashes.
   // For example T0_XYZW and T0_XY both have the asm name T0.
   let ShouldEmitMatchRegisterName = 0;
 }
 
+def AMDGPUAsmWriter : AsmWriter {
+  let PassSubtarget = 1;
+}
+
 def AMDGPUAsmVariants {
   string Default = "Default";
   int Default_ID = 0;
   string VOP3 = "VOP3";
   int VOP3_ID = 1;
   string SDWA = "SDWA";
   int SDWA_ID = 2;
   string DPP = "DPP";

 def AMDGPU : Target {
   // Pull in Instruction Info:
   let InstructionSet = AMDGPUInstrInfo;
   let AssemblyParsers = [AMDGPUAsmParser];
   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
                                 VOP3AsmParserVariant,
                                 SDWAAsmParserVariant,
                                 DPPAsmParserVariant];
+  let AssemblyWriters = [AMDGPUAsmWriter];
 }
 
 // Dummy Instruction itineraries for pseudo instructions
 def ALU_NULL : FuncUnit;
 def NullALU : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Predicate helper class

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

if (ExtraCode && ExtraCode[0]) {
     default:
       // See if this is a generic print operand
       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
     case 'r':
       break;
     }
   }
 
-  AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
-                   *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
+  const TargetSubtargetInfo &STI = MF->getSubtarget();
+  AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), STI, O,
+                                     *STI.getRegisterInfo());
   return false;
 }
 
 // Emit a key and an integer value for runtime metadata.
 static void emitRuntimeMDIntValue(MCStreamer &Streamer,
                                   RuntimeMD::Key K, uint64_t V,
                                   unsigned Size) {
   Streamer.EmitIntValue(K, 1);

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 
 void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val) const {
   const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
   auto OpNum = Inst.getNumOperands();
   // Check that this operand accepts literals
   assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
 
   APInt Literal(64, Val);
-  auto OpSize = AMDGPU::getRegOperandSize(AsmParser->getMRI(), InstDesc, OpNum); // expected operand size
+  // Expected operand size.
+  auto OpSize = AMDGPU::getRegOperandSize(AsmParser->getMRI(),
+                                          AsmParser->getSTI(), InstDesc, OpNum);
 
   if (Imm.IsFPImm) { // We got fp literal token
     if (OpSize == 8) { // Expected 64-bit operand
       // Check if literal is inlinable
       if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), AsmParser->isVI())) {
         Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
       } else if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
         // For fp operands we check if low 32 bits are zeros

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

 
 #include "llvm/MC/MCInstPrinter.h"
 
 namespace llvm {
 
 class AMDGPUInstPrinter : public MCInstPrinter {
 public:
   AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
-                     const MCRegisterInfo &MRI)
     : MCInstPrinter(MAI, MII, MRI) {}
 
   //Autogenerated by tblgen
-  void printInstruction(const MCInst *MI, raw_ostream &O);
+  void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
+                        raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
   void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
                  const MCSubtargetInfo &STI) override;
-  static void printRegOperand(unsigned RegNo, raw_ostream &O,
-                              const MCRegisterInfo &MRI);
+  static void printRegOperand(unsigned RegNo, const MCSubtargetInfo &STI,
+                              raw_ostream &O, const MCRegisterInfo &MRI);
 
 private:
-  void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O,
+  void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU8ImmOperand(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                            const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                            const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                             const MCSubtargetInfo &STI, raw_ostream &O);
+  void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+  void printNamedBit(const MCInst* MI, unsigned OpNo,
+                     const MCSubtargetInfo &STI, raw_ostream& O,
                      StringRef BitName);
-  void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOffset0(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOffset1(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSMRDOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printGDS(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printDMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printUNorm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printDA(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printR128(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printLWE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printRegOperand(unsigned RegNo, raw_ostream &O);
-  void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printImmediate32(uint32_t I, raw_ostream &O);
-  void printImmediate64(uint64_t I, raw_ostream &O);
-  void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printDPPCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printRowMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printBankMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printBoundCtrl(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSDWADstSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printSDWADstUnused(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
+  void printOffen(const MCInst *MI, unsigned OpNo,
+                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printIdxen(const MCInst *MI, unsigned OpNo,
+                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printAddr64(const MCInst *MI, unsigned OpNo,
+                   const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMBUFOffset(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOffset(const MCInst *MI, unsigned OpNo,
+                   const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOffset0(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOffset1(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSMRDOffset(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
+  void printGDS(const MCInst *MI, unsigned OpNo,
+                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printGLC(const MCInst *MI, unsigned OpNo,
+                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSLC(const MCInst *MI, unsigned OpNo,
+                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printTFE(const MCInst *MI, unsigned OpNo,
+                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printDMask(const MCInst *MI, unsigned OpNo,
+                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printUNorm(const MCInst *MI, unsigned OpNo,
+                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printDA(const MCInst *MI, unsigned OpNo,
+               const MCSubtargetInfo &STI, raw_ostream &O);
+  void printR128(const MCInst *MI, unsigned OpNo,
+                 const MCSubtargetInfo &STI, raw_ostream &O);
+  void printLWE(const MCInst *MI, unsigned OpNo,
+                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printVOPDst(const MCInst *MI, unsigned OpNo,
+                   const MCSubtargetInfo &STI, raw_ostream &O);
+  void printImmediate32(uint32_t I, const MCSubtargetInfo &STI, raw_ostream &O);
+  void printImmediate64(uint64_t I, const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOperand(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo,
+                                  const MCSubtargetInfo &STI, raw_ostream &O);
+  void printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI, raw_ostream &O);
+  void printDPPCtrl(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printRowMask(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printBankMask(const MCInst *MI, unsigned OpNo,
+                     const MCSubtargetInfo &STI, raw_ostream &O);
+  void printBoundCtrl(const MCInst *MI, unsigned OpNo,
+                      const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSDWASel(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSDWADstSel(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSDWADstUnused(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printInterpSlot(const MCInst *MI, unsigned OpNum,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMemOperand(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printIfSet(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O,
                          StringRef Asm, StringRef Default = "");
   static void printIfSet(const MCInst *MI, unsigned OpNo,
-                         raw_ostream &O, char Asm);
-  static void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printClampSI(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printOModSI(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+                         const MCSubtargetInfo &STI, raw_ostream &O, char Asm);
+  static void printAbs(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printClamp(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printClampSI(const MCInst *MI, unsigned OpNo,
+                           const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printOModSI(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+  void printLiteral(const MCInst *MI, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printLast(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printNeg(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printOMOD(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printRel(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
   static void printUpdateExecMask(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O);
-  static void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  static void printHwreg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+                                  const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printUpdatePred(const MCInst *MI, unsigned OpNo,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printWrite(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printSel(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printBankSwizzle(const MCInst *MI, unsigned OpNo,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printRSel(const MCInst *MI, unsigned OpNo,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printCT(const MCInst *MI, unsigned OpNo,
+                      const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printKCache(const MCInst *MI, unsigned OpNo,
+                          const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printSendMsg(const MCInst *MI, unsigned OpNo,
+                           const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printWaitFlag(const MCInst *MI, unsigned OpNo,
+                            const MCSubtargetInfo &STI, raw_ostream &O);
+  static void printHwreg(const MCInst *MI, unsigned OpNo,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
 };
 
 } // End namespace llvm
 
 #endif

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <string>
 
 using namespace llvm;
 
 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
-                                  StringRef Annot, const MCSubtargetInfo &STI) {
+                                  StringRef Annot,
+                                  const MCSubtargetInfo &STI) {
   OS.flush();
-  printInstruction(MI, OS);
+  printInstruction(MI, STI, OS);
 
   printAnnotation(OS, Annot);
 }
 
 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
-                                           raw_ostream &O) {
+                                          const MCSubtargetInfo &STI,
   O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
 }
 
 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
-                                           raw_ostream &O) {
+                                          const MCSubtargetInfo &STI,
   O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
 }
 
 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
+                                           const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
 }
 
 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
+                                           const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
   O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
 }
 
 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                                             const MCSubtargetInfo &STI,
                                              raw_ostream &O) {
   O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
 }
 
 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                                             const MCSubtargetInfo &STI,
                                              raw_ostream &O) {
   O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
 }
 
 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
+                                              const MCSubtargetInfo &STI,
                                               raw_ostream &O) {
   O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
 }
 
 void AMDGPUInstPrinter::printNamedBit(const MCInst* MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI,
                                       raw_ostream& O, StringRef BitName) {
   if (MI->getOperand(OpNo).getImm()) {
     O << ' ' << BitName;
   }
 }
 
 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "offen");
+  printNamedBit(MI, OpNo, STI, O, "offen");
 }
 
 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "idxen");
+  printNamedBit(MI, OpNo, STI, O, "idxen");
 }
 
 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "addr64");
+  printNamedBit(MI, OpNo, STI, O, "addr64");
 }
 
 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   if (MI->getOperand(OpNo).getImm()) {
     O << " offset:";
-    printU16ImmDecOperand(MI, OpNo, O);
+    printU16ImmDecOperand(MI, OpNo, STI, O);
   }
 }
 
 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
-                                      raw_ostream &O) {
+                                    const MCSubtargetInfo &STI,
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
     O << " offset:";
-    printU16ImmDecOperand(MI, OpNo, O);
+    printU16ImmDecOperand(MI, OpNo, STI, O);
   }
 }
 
 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
-                                        raw_ostream &O) {
+                                     const MCSubtargetInfo &STI,
   if (MI->getOperand(OpNo).getImm()) {
     O << " offset0:";
-    printU8ImmDecOperand(MI, OpNo, O);
+    printU8ImmDecOperand(MI, OpNo, STI, O);
   }
 }
 
 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
-                                        raw_ostream &O) {
+                                     const MCSubtargetInfo &STI,
   if (MI->getOperand(OpNo).getImm()) {
     O << " offset1:";
-    printU8ImmDecOperand(MI, OpNo, O);
+    printU8ImmDecOperand(MI, OpNo, STI, O);
   }
 }
 
 void AMDGPUInstPrinter::printSMRDOffset(const MCInst *MI, unsigned OpNo,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  printU32ImmOperand(MI, OpNo, O);
+  printU32ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
+                                               const MCSubtargetInfo &STI,
                                                raw_ostream &O) {
-  printU32ImmOperand(MI, OpNo, O);
+  printU32ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "gds");
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "gds");
 }
 
 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "glc");
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "glc");
 }
 
 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "slc");
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "slc");
 }
 
 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "tfe");
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "tfe");
 }
 
 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
-                                   raw_ostream &O) {
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   if (MI->getOperand(OpNo).getImm()) {
     O << " dmask:";
-    printU16ImmOperand(MI, OpNo, O);
+    printU16ImmOperand(MI, OpNo, STI, O);
   }
 }
 
 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "unorm");
+  printNamedBit(MI, OpNo, STI, O, "unorm");
 }
 
 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
-                                raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "da");
+                                const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "da");
 }
 
 void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "r128");
+                                  const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "r128");
 }
 
 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
-                                   raw_ostream &O) {
-  printNamedBit(MI, OpNo, O, "lwe");
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printNamedBit(MI, OpNo, STI, O, "lwe");
 }
 
-void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
+void AMDGPUInstPrinter::printRegOperand(unsigned reg,
+                                        const MCSubtargetInfo &STI,
+                                        raw_ostream &O,
                                         const MCRegisterInfo &MRI) {
   switch (reg) {
   case AMDGPU::VCC:
     O << "vcc";
     return;
   case AMDGPU::SCC:
     O << "scc";
     return;
if (NumRegs == 1) {
     O << RegIdx;
     return;
   }
 
   O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
 }
 
 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
   if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
     O << "_e64 ";
   else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
     O << "_dpp ";
   else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
     O << "_sdwa ";
   else
     O << "_e32 ";
 
-  printOperand(MI, OpNo, O);
+  printOperand(MI, OpNo, STI, O);
 }
 
-void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
+void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
   int32_t SImm = static_cast<int32_t>(Imm);
   if (SImm >= -16 && SImm <= 64) {
     O << SImm;
     return;
   }
 
   if (Imm == FloatToBits(0.0f))
     O << "0.0";
void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
   else if (Imm == FloatToBits(4.0f))
     O << "4.0";
   else if (Imm == FloatToBits(-4.0f))
     O << "-4.0";
   else
     O << formatHex(static_cast<uint64_t>(Imm));
 }
 
-void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
+void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
   int64_t SImm = static_cast<int64_t>(Imm);
   if (SImm >= -16 && SImm <= 64) {
     O << SImm;
     return;
   }
 
   if (Imm == DoubleToBits(0.0))
     O << "0.0";
else {
 
     // In rare situations, we will have a 32-bit literal in a 64-bit
     // operand. This is technically allowed for the encoding of s_mov_b64.
     O << formatHex(static_cast<uint64_t>(Imm));
   }
 }
 
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
-
   if (OpNo >= MI->getNumOperands()) {
     O << "/*Missing OP" << OpNo << "*/";
     return;
   }
 
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     switch (Op.getReg()) {
     // This is the default predicate state, so we don't need to print it.
     case AMDGPU::PRED_SEL_OFF:
       break;
 
     default:
-      printRegOperand(Op.getReg(), O, MRI);
+      printRegOperand(Op.getReg(), STI, O, MRI);
       break;
     }
   } else if (Op.isImm()) {
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     int RCID = Desc.OpInfo[OpNo].RegClass;
     if (RCID != -1) {
       const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
-      if (ImmRC.getSize() == 4)
-        printImmediate32(Op.getImm(), O);
-      else if (ImmRC.getSize() == 8)
-        printImmediate64(Op.getImm(), O);
+      if (MRI.getRegSize(ImmRC.getID(), STI) == 4)
+        printImmediate32(Op.getImm(), STI, O);
+      else if (MRI.getRegSize(ImmRC.getID(), STI) == 8)
+        printImmediate64(Op.getImm(), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
-      printImmediate32(Op.getImm(), O);
+      printImmediate32(Op.getImm(), STI, O);
     } else {
       // We hit this for the immediate instruction bits that don't yet have a
       // custom printer.
       // TODO: Eventually this should be unnecessary.
       O << formatDec(Op.getImm());
     }
   } else if (Op.isFPImm()) {
     // We special case 0.0 because otherwise it will be printed as an integer.
     if (Op.getFPImm() == 0.0)
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
       const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
-
-      if (ImmRC.getSize() == 4)
-        printImmediate32(FloatToBits(Op.getFPImm()), O);
-      else if (ImmRC.getSize() == 8)
-        printImmediate64(DoubleToBits(Op.getFPImm()), O);
+      if (MRI.getRegSize(ImmRC.getID(), STI) == 4)
+        printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
+      else if (MRI.getRegSize(ImmRC.getID(), STI) == 8)
+        printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     }
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O, &MAI);
   } else {
     O << "/*INV_OP*/";
   }
 }
 
 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
-                                                      unsigned OpNo,
-                                                      raw_ostream &O) {
+                                                   const MCSubtargetInfo &STI,
   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
   if (InputModifiers & SISrcMods::NEG)
     O << '-';
   if (InputModifiers & SISrcMods::ABS)
     O << '|';
-  printOperand(MI, OpNo + 1, O);
+  printOperand(MI, OpNo + 1, STI, O);
   if (InputModifiers & SISrcMods::ABS)
     O << '|';
 }
 
 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
-                                                     unsigned OpNo,
-                                                     raw_ostream &O) {
+                                                    const MCSubtargetInfo &STI,
   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
   if (InputModifiers & SISrcMods::SEXT)
     O << "sext(";
-  printOperand(MI, OpNo + 1, O);
+  printOperand(MI, OpNo + 1, STI, O);
   if (InputModifiers & SISrcMods::SEXT)
     O << ')';
 }
 
 
 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
+                                     const MCSubtargetInfo &STI,
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (Imm <= 0x0ff) {
     O << " quad_perm:[";
     O << formatDec(Imm & 0x3)         << ',';
     O << formatDec((Imm & 0xc)  >> 2) << ',';
     O << formatDec((Imm & 0x30) >> 4) << ',';
     O << formatDec((Imm & 0xc0) >> 6) << ']';
   } else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
     O << " row_shl:";
-    printU4ImmDecOperand(MI, OpNo, O);
+    printU4ImmDecOperand(MI, OpNo, STI, O);
   } else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
     O << " row_shr:";
-    printU4ImmDecOperand(MI, OpNo, O);
+    printU4ImmDecOperand(MI, OpNo, STI, O);
   } else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
     O << " row_ror:";
-    printU4ImmDecOperand(MI, OpNo, O);
+    printU4ImmDecOperand(MI, OpNo, STI, O);
   } else if (Imm == 0x130) {
     O << " wave_shl:1";
   } else if (Imm == 0x134) {
     O << " wave_rol:1";
   } else if (Imm == 0x138) {
     O << " wave_shr:1";
   } else if (Imm == 0x13c) {
     O << " wave_ror:1";
   } else if (Imm == 0x140) {
     O << " row_mirror";
   } else if (Imm == 0x141) {
     O << " row_half_mirror";
   } else if (Imm == 0x142) {
     O << " row_bcast:15";
   } else if (Imm == 0x143) {
     O << " row_bcast:31";
   } else {
     llvm_unreachable("Invalid dpp_ctrl value");
   }
 }
 
 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
-                                            raw_ostream &O) {
+                                     const MCSubtargetInfo &STI,
   O << " row_mask:";
-  printU4ImmOperand(MI, OpNo, O);
+  printU4ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
-                                             raw_ostream &O) {
+                                      const MCSubtargetInfo &STI,
   O << " bank_mask:";
-  printU4ImmOperand(MI, OpNo, O);
+  printU4ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
-                                              raw_ostream &O) {
+                                       const MCSubtargetInfo &STI,
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (Imm) {
     O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
   }
 }
 
 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   switch (Imm) {
   case 0: O << "BYTE_0"; break;
   case 1: O << "BYTE_1"; break;
   case 2: O << "BYTE_2"; break;
   case 3: O << "BYTE_3"; break;
   case 4: O << "WORD_0"; break;
   case 5: O << "WORD_1"; break;
   case 6: O << "DWORD"; break;
   default: llvm_unreachable("Invalid SDWA data select operand");
   }
 }
 
 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   O << "dst_sel:";
-  printSDWASel(MI, OpNo, O);
+  printSDWASel(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
+                                         const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   O << "src0_sel:";
-  printSDWASel(MI, OpNo, O);
+  printSDWASel(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
+                                         const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   O << "src1_sel:";
-  printSDWASel(MI, OpNo, O);
+  printSDWASel(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
+                                           const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
   O << "dst_unused:";
   unsigned Imm = MI->getOperand(OpNo).getImm();
   switch (Imm) {
   case 0: O << "UNUSED_PAD"; break;
   case 1: O << "UNUSED_SEXT"; break;
   case 2: O << "UNUSED_PRESERVE"; break;
   default: llvm_unreachable("Invalid SDWA dest_unused operand");
   }
 }
 
 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNum).getImm();
 
   if (Imm == 2) {
     O << "P0";
   } else if (Imm == 1) {
     O << "P20";
   } else if (Imm == 0) {
     O << "P10";
   } else {
     llvm_unreachable("Invalid interpolation parameter slot");
   }
 }
 
 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  printOperand(MI, OpNo, O);
+  printOperand(MI, OpNo, STI, O);
   O  << ", ";
-  printOperand(MI, OpNo + 1, O);
+  printOperand(MI, OpNo + 1, STI, O);
 }
 
 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O, StringRef Asm,
                                    StringRef Default) {
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isImm());
   if (Op.getImm() == 1) {
     O << Asm;
   } else {
     O << Default;
   }
 }
 
 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O, char Asm) {
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isImm());
   if (Op.getImm() == 1)
     O << Asm;
 }
 
 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printIfSet(MI, OpNo, O, '|');
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printIfSet(MI, OpNo, STI, O, '|');
 }
 
 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
-  printIfSet(MI, OpNo, O, "_SAT");
+  printIfSet(MI, OpNo, STI, O, "_SAT");
 }
 
 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   if (MI->getOperand(OpNo).getImm())
     O << " clamp";
 }
 
 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
-                                     raw_ostream &O) {
+                                    const MCSubtargetInfo &STI,
   int Imm = MI->getOperand(OpNo).getImm();
   if (Imm == SIOutMods::MUL2)
     O << " mul:2";
   else if (Imm == SIOutMods::MUL4)
     O << " mul:4";
   else if (Imm == SIOutMods::DIV2)
     O << " div:2";
 }
 
 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isImm() || Op.isExpr());
   if (Op.isImm()) {
     int64_t Imm = Op.getImm();
     O << Imm << '(' << BitsToFloat(Imm) << ')';
   }
   if (Op.isExpr()) {
     Op.getExpr()->print(O << '@', &MAI);
   }
 }
 
 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
-  printIfSet(MI, OpNo, O, "*", " ");
+                                  const MCSubtargetInfo &STI, raw_ostream &O) {
+  printIfSet(MI, OpNo, STI, O, "*", " ");
 }
 
 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printIfSet(MI, OpNo, O, '-');
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printIfSet(MI, OpNo, STI, O, '-');
 }
 
 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
+                                  const MCSubtargetInfo &STI, raw_ostream &O) {
   switch (MI->getOperand(OpNo).getImm()) {
   default: break;
   case 1:
     O << " * 2.0";
     break;
   case 2:
     O << " * 4.0";
     break;
   case 3:
     O << " / 2.0";
     break;
   }
 }
 
 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
-                                 raw_ostream &O) {
-  printIfSet(MI, OpNo, O, '+');
+                                 const MCSubtargetInfo &STI, raw_ostream &O) {
+  printIfSet(MI, OpNo, STI, O, '+');
 }
 
 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
+                                            const MCSubtargetInfo &STI,
                                             raw_ostream &O) {
-  printIfSet(MI, OpNo, O, "ExecMask,");
+  printIfSet(MI, OpNo, STI, O, "ExecMask,");
 }
 
 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
+                                        const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  printIfSet(MI, OpNo, O, "Pred,");
+  printIfSet(MI, OpNo, STI, O, "Pred,");
 }
 
 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
-                                       raw_ostream &O) {
+                                   const MCSubtargetInfo &STI,
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.getImm() == 0) {
     O << " (MASKED)";
   }
 }
 
 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
+                                 const MCSubtargetInfo &STI,
   const char * chans = "XYZW";
   int sel = MI->getOperand(OpNo).getImm();
 
   int chan = sel & 3;
   sel >>= 2;
 
   if (sel >= 512) {
     sel -= 512;
     int cb = sel >> 12;
     sel &= 4095;
     O << cb << '[' << sel << ']';
   } else if (sel >= 448) {
     sel -= 448;
     O << sel;
   } else if (sel >= 0){
     O << sel;
   }
 
   if (sel >= 0)
     O << '.' << chans[chan];
 }
 
 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
+                                         const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   int BankSwizzle = MI->getOperand(OpNo).getImm();
   switch (BankSwizzle) {
   case 1:
     O << "BS:VEC_021/SCL_122";
     break;
   case 2:
     O << "BS:VEC_120/SCL_212";
case 5:
     break;
   default:
     break;
   }
   return;
 }
 
 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
+                                  const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Sel = MI->getOperand(OpNo).getImm();
   switch (Sel) {
   case 0:
     O << 'X';
     break;
   case 1:
     O << 'Y';
     break;
case 7:
     O << '_';
     break;
   default:
     break;
   }
 }
 
 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
-                                  raw_ostream &O) {
+                                const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned CT = MI->getOperand(OpNo).getImm();
   switch (CT) {
   case 0:
     O << 'U';
     break;
   case 1:
     O << 'N';
     break;
   default:
     break;
   }
 }
 
 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
+                                    const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
   int KCacheMode = MI->getOperand(OpNo).getImm();
   if (KCacheMode > 0) {
     int KCacheBank = MI->getOperand(OpNo - 2).getImm();
     O << "CB" << KCacheBank << ':';
     int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
     int LineSize = (KCacheMode == 1) ? 16 : 32;
     O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
   }
 }
 
 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   using namespace llvm::AMDGPU::SendMsg;
 
   const unsigned SImm16 = MI->getOperand(OpNo).getImm();
   const unsigned Id = SImm16 & ID_MASK_;
   do {
     if (Id == ID_INTERRUPT) {
       if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0.
if (Id == ID_SYSMSG) {
       O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')';
       return;
     }
   } while (0);
   O << SImm16; // Unknown simm16 code.
 }
 
 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
   unsigned SImm16 = MI->getOperand(OpNo).getImm();
   unsigned Vmcnt = SImm16 & 0xF;
   unsigned Expcnt = (SImm16 >> 4) & 0x7;
   unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
 
   bool NeedSpace = false;
 
void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
   if (Lgkmcnt != 0xF) {
     if (NeedSpace)
       O << ' ';
     O << "lgkmcnt(" << Lgkmcnt << ')';
   }
 }
 
 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
   using namespace llvm::AMDGPU::Hwreg;
 
   unsigned SImm16 = MI->getOperand(OpNo).getImm();
   const unsigned Id = (SImm16 & ID_MASK_) >> ID_SHIFT_;
   const unsigned Offset = (SImm16 & OFFSET_MASK_) >> OFFSET_SHIFT_;
   const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
 

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
     if (!AMDGPU::isSISrcOperand(Desc, i))
       continue;
 
     int RCID = Desc.OpInfo[i].RegClass;
     const MCRegisterClass &RC = MRI.getRegClass(RCID);
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, RC.getSize(), STI) != 255)
+    if (getLitEncoding(Op, MRI.getRegSize(RC.getID(), STI), STI) != 255)
       continue;
 
     // Yes! Encode it
     int64_t Imm = 0;
 
     if (Op.isImm())
       Imm = Op.getImm();
     else if (Op.isExpr()) {
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
   unsigned OpNo = 0;
   for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
     if (&MO == &MI.getOperand(OpNo))
       break;
   }
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
-    uint32_t Enc = getLitEncoding(MO,
-                                  AMDGPU::getRegOperandSize(&MRI, Desc, OpNo),
-                                  STI);
+    unsigned Size = AMDGPU::getRegOperandSize(&MRI, STI, Desc, OpNo);
+    uint32_t Enc = getLitEncoding(MO, Size, STI);
     if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
       return Enc;
 
   } else if (MO.isImm())
     return MO.getImm();
 
   llvm_unreachable("Encoding of this operand type is not supported yet.");
   return 0;
 }
 

lib/Target/AMDGPU/R600ISelLowering.cpp

R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
     : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
   addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
   addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
   addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
   addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
   addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
   addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
 
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 
   // Legalize loads and stores to the private address space.
   setOperationAction(ISD::LOAD, MVT::i32, Custom);
   setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
   setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
 
   // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
   // spaces, so it is custom lowered to handle those where it isn't.

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

 char &llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID;
 
 FunctionPass *llvm::createSIFixSGPRCopiesPass() {
   return new SIFixSGPRCopies();
 }
 
 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+  const TargetSubtargetInfo &STI = MRI.getTargetSubtargetInfo();
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     if (!MI.getOperand(i).isReg() ||
         !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
       continue;
 
-    if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
+    if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()), STI))
       return true;
   }
   return false;
 }
 
 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
 getCopyRegClasses(const MachineInstr &Copy,
                   const SIRegisterInfo &TRI,
const TargetRegisterClass *DstRC =
     MRI.getRegClass(DstReg) :
     TRI.getPhysRegClass(DstReg);
 
   return std::make_pair(SrcRC, DstRC);
 }
 
 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
                              const TargetRegisterClass *DstRC,
-                             const SIRegisterInfo &TRI) {
-  return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
+                             const SIRegisterInfo &TRI,
+                             const TargetSubtargetInfo &STI) {
+  return TRI.isSGPRClass(DstRC, STI) && TRI.hasVGPRs(SrcRC, STI);
 }
 
 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
                              const TargetRegisterClass *DstRC,
-                             const SIRegisterInfo &TRI) {
-  return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
+                             const SIRegisterInfo &TRI,
+                             const TargetSubtargetInfo &STI) {
+  return TRI.isSGPRClass(SrcRC, STI) && TRI.hasVGPRs(DstRC, STI);
 }
 
 // Distribute an SGPR->VGPR copy of a REG_SEQUENCE into a VGPR REG_SEQUENCE.
 //
 // SGPRx = ...
 // SGPRy = REG_SEQUENCE SGPRx, sub0 ...
 // VGPRz = COPY SGPRy
 //
 // ==>
 //
 // VGPRx = COPY SGPRx
 // VGPRz = REG_SEQUENCE VGPRx, sub0
 //
 // This exposes immediate folding opportunities when materializing 64-bit
 // immediates.
 static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI,
                                         const SIRegisterInfo *TRI,
                                         const SIInstrInfo *TII,
                                         MachineRegisterInfo &MRI) {
   assert(MI.isRegSequence());
+  const TargetSubtargetInfo &STI = MRI.getTargetSubtargetInfo();
 
   unsigned DstReg = MI.getOperand(0).getReg();
-  if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
+  if (!TRI->isSGPRClass(MRI.getRegClass(DstReg), STI))
     return false;
 
   if (!MRI.hasOneUse(DstReg))
     return false;
 
   MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
   if (!CopyUse.isCopy())
     return false;
 
   const TargetRegisterClass *SrcRC, *DstRC;
   std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
 
-  if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
+  if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI, STI))
     return false;
 
   // TODO: Could have multiple extracts?
   unsigned SubReg = CopyUse.getOperand(1).getSubReg();
   if (SubReg != AMDGPU::NoSubRegister)
     return false;
 
   MRI.setRegClass(DstReg, DstRC);
 
   // SGPRx = ...
   // SGPRy = REG_SEQUENCE SGPRx, sub0 ...
   // VGPRz = COPY SGPRy
 
   // =>
   // VGPRx = COPY SGPRx
   // VGPRz = REG_SEQUENCE VGPRx, sub0
 
   MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
 
   for (unsigned I = 1, N = MI.getNumOperands(); I != N; I += 2) {
     unsigned SrcReg = MI.getOperand(I).getReg();
     unsigned SrcSubReg = MI.getOperand(I).getSubReg();
 
     const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
-    assert(TRI->isSGPRClass(SrcRC) &&
+    assert(TRI->isSGPRClass(SrcRC, STI) &&
            "Expected SGPR REG_SEQUENCE to only have SGPR inputs");
 
-    SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg);
-    const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC);
+    SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg, STI);
+    const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC,
+                                                                      STI);
 
     unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC);
 
     BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg)
       .addOperand(MI.getOperand(I));
 
     MI.getOperand(I).setReg(TmpReg);
   }
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
       case AMDGPU::COPY: {
         // If the destination register is a physical register there isn't really
         // much we can do to fix this.
         if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()))
           continue;
 
         const TargetRegisterClass *SrcRC, *DstRC;
         std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
-        if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
+        if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI, ST)) {
           DEBUG(dbgs() << "Fixing VGPR -> SGPR copy: " << MI);
           TII->moveToVALU(MI);
         }
 
         break;
       }
       case AMDGPU::PHI: {
         DEBUG(dbgs() << "Fixing PHI: " << MI);
         unsigned Reg = MI.getOperand(0).getReg();
-        if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
+        if (!TRI->isSGPRClass(MRI.getRegClass(Reg), ST))
           break;
 
         // If a PHI node defines an SGPR and any of its operands are VGPRs,
         // then we need to move it to the VALU.
         //
         // Also, if a PHI node defines an SGPR and has all SGPR operands
         // we must move it to the VALU, because the SGPR operands will
         // all end up being assigned the same register, which means
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
         // instruction.  In this case, there we know the program will
         // never enter the second block (the loop) without entering
         // the first block (where the condition is computed), so there
         // is no chance for values to be over-written.
 
         bool HasBreakDef = false;
         for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
           unsigned Reg = MI.getOperand(i).getReg();
-          if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
+          if (TRI->hasVGPRs(MRI.getRegClass(Reg), ST)) {
             TII->moveToVALU(MI);
             break;
           }
           MachineInstr *DefInstr = MRI.getUniqueVRegDef(Reg);
           assert(DefInstr);
           switch(DefInstr->getOpcode()) {
 
           case AMDGPU::SI_BREAK:
           case AMDGPU::SI_IF_BREAK:
           case AMDGPU::SI_ELSE_BREAK:
           // If we see a PHI instruction that defines an SGPR, then that PHI
           // instruction has already been considered and should have
           // a *_BREAK as an operand.
           case AMDGPU::PHI:
             HasBreakDef = true;
             break;
           }
         }
 
         if (!SGPRBranch && !HasBreakDef)
           TII->moveToVALU(MI);
         break;
       }
       case AMDGPU::REG_SEQUENCE: {
-        if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
+        if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0), ST) ||
             !hasVGPROperands(MI, TRI)) {
           foldVGPRCopyIntoRegSequence(MI, TRI, TII, MRI);
           continue;
         }
 
         DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
 
         TII->moveToVALU(MI);
         break;
       }
       case AMDGPU::INSERT_SUBREG: {
         const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
         DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
         Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
         Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
-        if (TRI->isSGPRClass(DstRC) &&
-            (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
+        if (TRI->isSGPRClass(DstRC, ST) &&
+            (TRI->hasVGPRs(Src0RC, ST) || TRI->hasVGPRs(Src1RC, ST))) {
           DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
           TII->moveToVALU(MI);
         }
         break;
       }
       }
     }
   }
 
   return true;
 }

lib/Target/AMDGPU/SIFoldOperands.cpp

if (FoldingImm) {
 
     Imm = APInt(64, OpToFold.getImm());
 
     const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
     const TargetRegisterClass *FoldRC =
         TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
 
     // Split 64-bit constants into 32-bits for folding.
-    if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
-      if (UseRC->getSize() != 8)
+    if (MRI.getRegSize(FoldRC) == 8 && UseOp.getSubReg()) {
+      if (MRI.getRegSize(UseRC) != 8)
         return;
 
       if (UseOp.getSubReg() == AMDGPU::sub0) {
         Imm = Imm.getLoBits(32);
       } else {
         assert(UseOp.getSubReg() == AMDGPU::sub1);
         Imm = Imm.getHiBits(32);
       }

lib/Target/AMDGPU/SIFrameLowering.cpp

if (!MFI.hasStackObjects())
     return;
 
   bool MayNeedScavengingEmergencySlot = MFI.hasStackObjects();
 
   assert((RS || !MayNeedScavengingEmergencySlot) &&
          "RegScavenger required if spilling");
 
   if (MayNeedScavengingEmergencySlot) {
+    MachineRegisterInfo &MRI = MF.getRegInfo();
     int ScavengeFI = MFI.CreateStackObject(
-      AMDGPU::SGPR_32RegClass.getSize(),
-      AMDGPU::SGPR_32RegClass.getAlignment(), false);
+      MRI.getSpillSize(&AMDGPU::SGPR_32RegClass),
+      MRI.getSpillAlignment(&AMDGPU::SGPR_32RegClass), false);
     RS->addScavengingFrameIndex(ScavengeFI);
   }
 }
 
 void SIFrameLowering::emitDebuggerPrologue(MachineFunction &MF,
                                            MachineBasicBlock &MBB) const {
   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
   const SIInstrInfo *TII = ST.getInstrInfo();

lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::SITargetLowering(const TargetMachine &TM,
   addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
   addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
   addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
   addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
 
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 
   // We need to custom lower vector stores from local memory
   setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
   setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
   setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
   setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
   setOperationAction(ISD::LOAD, MVT::i1, Custom);
 
static MachineBasicBlock *loadM0FromVGPR(const SIInstrInfo *TII,
   MI.eraseFromParent();
 
   return RemainderBB;
 }
 
 // Returns subreg index, offset
 static std::pair<unsigned, int>
 computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
+                            const TargetSubtargetInfo &ST,
                             const TargetRegisterClass *SuperRC,
                             unsigned VecReg,
                             int Offset) {
-  int NumElts = SuperRC->getSize() / 4;
+  int NumElts = TRI.getRegSize(SuperRC->getID(), ST) / 4;
 
   // Skip out of bounds offsets, or else we would end up using an undefined
   // register.
   if (Offset >= NumElts || Offset < 0)
     return std::make_pair(AMDGPU::sub0, Offset);
 
   return std::make_pair(AMDGPU::sub0 + Offset, 0);
 }
 
 // Return true if the index is an SGPR and was set.
 static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
                                  MachineRegisterInfo &MRI,
                                  MachineInstr &MI,
                                  int Offset) {
   MachineBasicBlock *MBB = MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
   MachineBasicBlock::iterator I(&MI);
 
   const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
   const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
 
   assert(Idx->getReg() != AMDGPU::NoRegister);
 
-  if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
+  if (!TII->getRegisterInfo().isSGPRClass(IdxRC, MRI.getTargetSubtargetInfo()))
     return false;
 
   if (Offset == 0) {
     BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
       .addOperand(*Idx);
   } else {
     BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
       .addOperand(*Idx)
static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
   unsigned Dst = MI.getOperand(0).getReg();
   const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
   int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
 
   const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
 
   unsigned SubReg;
   std::tie(SubReg, Offset)
-    = computeIndirectRegAndOffset(TRI, VecRC, SrcVec->getReg(), Offset);
+    = computeIndirectRegAndOffset(TRI, MF->getSubtarget(), VecRC,
+                                  SrcVec->getReg(), Offset);
 
   if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) {
     MachineBasicBlock::iterator I(&MI);
     const DebugLoc &DL = MI.getDebugLoc();
 
     BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
       .addReg(SrcVec->getReg(), RegState::Undef, SubReg)
       .addReg(SrcVec->getReg(), RegState::Implicit);
static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
   const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
   int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
   const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
 
   // This can be an immediate, but will be folded later.
   assert(Val->getReg());
 
   unsigned SubReg;
-  std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
-                                                         SrcVec->getReg(),
-                                                         Offset);
+  std::tie(SubReg, Offset)
+    = computeIndirectRegAndOffset(TRI, MF->getSubtarget(), VecRC,
+                                  SrcVec->getReg(), Offset);
   if (Idx->getReg() == AMDGPU::NoRegister) {
     MachineBasicBlock::iterator I(&MI);
     const DebugLoc &DL = MI.getDebugLoc();
 
     assert(Offset == 0);
 
     BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
       .addOperand(*SrcVec)

lib/Target/AMDGPU/SIInsertWaits.cpp

if (TSFlags & SIInstrFlags::LGKM_CNT) {
     if (TII->isSMRD(MI)) {
 
       if (MI.getNumOperands() != 0) {
         assert(MI.getOperand(0).isReg() &&
                "First LGKM operand must be a register!");
 
         // XXX - What if this is a write into a super register?
         const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0);
-        unsigned Size = RC->getSize();
+        unsigned Size = TRI->getSpillSize(RC->getID(), *ST);
         Result.Named.LGKM = Size > 4 ? 2 : 1;
       } else {
         // s_dcache_inv etc. do not have a a destination register. Assume we
         // want a wait on these.
         // XXX - What is the right value?
         Result.Named.LGKM = 1;
       }
     } else {
if (I->isReg() && I->isUse())
       return Op.isIdenticalTo(*I);
   }
 
   return false;
 }
 
 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC,
                                           const MachineOperand &Reg) const {
-  unsigned Size = RC->getSize();
+  unsigned Size = TRI->getRegSize(RC->getID(), *ST);
   assert(Size >= 4);
 
   RegInterval Result;
   Result.first = TRI->getEncodingValue(Reg.getReg());
   Result.second = Result.first + Size / 4;
 
   return Result;
 }

lib/Target/AMDGPU/SIInstrInfo.h

public:
   /// in tablegen.  For generic instructions, like REG_SEQUENCE it will return
   /// the register class of its machine operand.
   /// to infer the correct register class base on the other operands.
   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
                                            unsigned OpNo) const;
 
   /// \brief Return the size in bytes of the operand OpNo on the given
   // instruction opcode.
-  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
-    const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
-
-    if (OpInfo.RegClass == -1) {
-      // If this is an immediate operand, this must be a 32-bit literal.
-      assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
-      return 4;
-    }
-
-    return RI.getRegClass(OpInfo.RegClass)->getSize();
-  }
+  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const;
 
   /// \brief This form should usually be preferred since it handles operands
   /// with unknown register classes.
-  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
-    return getOpRegClass(MI, OpNo)->getSize();
-  }
+  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const;
 
   /// \returns true if it is legal for the operand at index \p OpNo
   /// to read a VGPR.
   bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
 
   /// \brief Legalize the \p OpIndex operand of this instruction by inserting
   /// a MOV.  For example:
   /// ADD_I32_e32 VGPR0, 15

lib/Target/AMDGPU/SIInstrInfo.cpp

if (isDS(LdSt)) {
     uint8_t Offset1 = Offset1Imm->getImm();
 
     if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
       // Each of these offsets is in element sized units, so we need to convert
       // to bytes of the individual reads.
 
       unsigned EltSize;
       if (LdSt.mayLoad())
-        EltSize = getOpRegClass(LdSt, 0)->getSize() / 2;
+        EltSize = TRI->getRegSize(getOpRegClass(LdSt, 0)->getID(), ST) / 2;
       else {
         assert(LdSt.mayStore());
         int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
-        EltSize = getOpRegClass(LdSt, Data0Idx)->getSize();
+        EltSize = TRI->getRegSize(getOpRegClass(LdSt, Data0Idx)->getID(), ST);
       }
 
       if (isStride64(Opc))
         EltSize *= 64;
 
       const MachineOperand *AddrReg =
           getNamedOperand(LdSt, AMDGPU::OpName::addr);
       BaseReg = AddrReg->getReg();
bool SIInstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt,
   // The unit of this value is bytes.
   // FIXME: This needs finer tuning.
   unsigned LoadClusterThreshold = 16;
 
   const MachineRegisterInfo &MRI =
       FirstLdSt.getParent()->getParent()->getRegInfo();
   const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg());
 
-  return (NumLoads * DstRC->getSize()) <= LoadClusterThreshold;
+  return (NumLoads * MRI.getSpillSize(DstRC)) <= LoadClusterThreshold;
 }
 
 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MI,
                               const DebugLoc &DL, unsigned DestReg,
                               unsigned SrcReg, bool KillSrc) const {
 
   static const int16_t Sub0_15[] = {
int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
   if (NewOpc != -1)
     // Check if the original (non-REV) opcode exists on the target.
     return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
 
   return Opcode;
 }
 
 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
-
-  if (DstRC->getSize() == 4) {
-    return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
-  } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
+  unsigned Size = RI.getRegSize(DstRC->getID(), ST);
+  if (Size == 4) {
+    return RI.isSGPRClass(DstRC, ST) ? AMDGPU::S_MOV_B32
+                                     : AMDGPU::V_MOV_B32_e32;
+  } else if (Size == 8 && RI.isSGPRClass(DstRC, ST)) {
     return AMDGPU::S_MOV_B64;
-  } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
+  } else if (Size == 8 && !RI.isSGPRClass(DstRC, ST)) {
     return  AMDGPU::V_MOV_B64_PSEUDO;
   }
   return AMDGPU::COPY;
 }
 
 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
   switch (Size) {
   case 4:
void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   unsigned Size = FrameInfo.getObjectSize(FrameIndex);
   unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
   MachinePointerInfo PtrInfo
     = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
   MachineMemOperand *MMO
     = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
                                Size, Align);
 
-  if (RI.isSGPRClass(RC)) {
+  if (RI.isSGPRClass(RC, ST)) {
     MFI->setHasSpilledSGPRs();
+    MachineRegisterInfo &MRI = MF->getRegInfo();
 
     // We are only allowed to create one new instruction when spilling
     // registers, so we need to use pseudo instruction for spilling SGPRs.
-    const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(RC->getSize()));
+    unsigned Size = MRI.getSpillSize(RC);
+    const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(Size));
 
     // The SGPR spill/restore instructions only work on number sgprs, so we need
     // to make sure we are using the correct register class.
-    if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) {
-      MachineRegisterInfo &MRI = MF->getRegInfo();
+    if (TargetRegisterInfo::isVirtualRegister(SrcReg) && Size == 4) {
       MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
     }
 
     BuildMI(MBB, MI, DL, OpDesc)
       .addReg(SrcReg, getKillRegState(isKill)) // data
       .addFrameIndex(FrameIndex)               // addr
       .addMemOperand(MMO);
 
     return;
   }
 
   if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
     LLVMContext &Ctx = MF->getFunction()->getContext();
     Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
                   " spill register");
     BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
       .addReg(SrcReg);
 
     return;
   }
 
-  assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
+  assert(RI.hasVGPRs(RC, ST) && "Only VGPR spilling expected");
 
-  unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
+  unsigned Opcode = getVGPRSpillSaveOpcode(MF->getRegInfo().getSpillSize(RC));
   MFI->setHasSpilledVGPRs();
   BuildMI(MBB, MI, DL, get(Opcode))
     .addReg(SrcReg, getKillRegState(isKill)) // data
     .addFrameIndex(FrameIndex)               // addr
     .addReg(MFI->getScratchRSrcReg())        // scratch_rsrc
     .addReg(MFI->getScratchWaveOffsetReg())  // scratch_offset
     .addImm(0)                               // offset
     .addMemOperand(MMO);
void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   unsigned Size = FrameInfo.getObjectSize(FrameIndex);
 
   MachinePointerInfo PtrInfo
     = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
 
   MachineMemOperand *MMO = MF->getMachineMemOperand(
     PtrInfo, MachineMemOperand::MOLoad, Size, Align);
 
-  if (RI.isSGPRClass(RC)) {
+  if (RI.isSGPRClass(RC, ST)) {
+    MachineRegisterInfo &MRI = MF->getRegInfo();
+    unsigned Size = MRI.getSpillSize(RC);
     // FIXME: Maybe this should not include a memoperand because it will be
     // lowered to non-memory instructions.
-    const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(RC->getSize()));
-    if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC->getSize() == 4) {
-      MachineRegisterInfo &MRI = MF->getRegInfo();
+    const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(Size));
+    if (TargetRegisterInfo::isVirtualRegister(DestReg) && Size == 4) {
       MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
     }
 
     BuildMI(MBB, MI, DL, OpDesc, DestReg)
       .addFrameIndex(FrameIndex) // addr
       .addMemOperand(MMO);
 
     return;
   }
 
   if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
     LLVMContext &Ctx = MF->getFunction()->getContext();
     Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
                   " restore register");
     BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
 
     return;
   }
 
-  assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
+  assert(RI.hasVGPRs(RC, ST) && "Only VGPR spilling expected");
 
-  unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
+  unsigned Opcode = getVGPRSpillRestoreOpcode(
+                      MF->getRegInfo().getSpillSize(RC));
   BuildMI(MBB, MI, DL, get(Opcode), DestReg)
     .addFrameIndex(FrameIndex)              // vaddr
     .addReg(MFI->getScratchRSrcReg())       // scratch_rsrc
     .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
     .addImm(0)                              // offset
     .addMemOperand(MMO);
 }
 
if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
 
     MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
     MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
     MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
 
     // Multiplied part is the constant: Use v_madmk_f32
     // We should only expect these to be on src0 due to canonicalizations.
     if (Src0->isReg() && Src0->getReg() == Reg) {
-      if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
+      if (!Src1->isReg() ||
+          RI.isSGPRClass(MRI->getRegClass(Src1->getReg()), ST))
         return false;
 
-      if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
+      if (!Src2->isReg() ||
+          RI.isSGPRClass(MRI->getRegClass(Src2->getReg()), ST))
         return false;
 
       // We need to swap operands 0 and 1 since madmk constant is at operand 1.
 
       const int64_t Imm = DefMI.getOperand(1).getImm();
 
       // FIXME: This would be a lot easier if we could return a new instruction
       // instead of having to modify in place.
if (Src0->isReg() && Src0->getReg() == Reg) {
 
       return true;
     }
 
     // Added part is the constant: Use v_madak_f32
     if (Src2->isReg() && Src2->getReg() == Reg) {
       // Not allowed to use constant bus for another operand.
       // We can however allow an inline immediate as src0.
-      if (!Src0->isImm() &&
-          (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
+      if (!Src0->isImm() && Src0->isReg() &&
+          RI.isSGPRClass(MRI->getRegClass(Src0->getReg()), ST))
         return false;
 
-      if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
+      if (!Src1->isReg() ||
+          RI.isSGPRClass(MRI->getRegClass(Src1->getReg()), ST))
         return false;
 
       const int64_t Imm = DefMI.getOperand(1).getImm();
 
       // FIXME: This would be a lot easier if we could return a new instruction
       // instead of having to modify in place.
 
       // Remove these first since they are at the end.
bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
   assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
 
   if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
     return true;
 
   if (OpInfo.RegClass < 0)
     return false;
 
-  unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
+  const MachineFunction &MF = *MI.getParent()->getParent();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned OpSize = MRI.getRegSize(RI.getRegClass(OpInfo.RegClass));
   if (isLiteralConstant(MO, OpSize))
     return RI.opCanUseLiteralConstant(OpInfo.OperandType);
 
   return RI.opCanUseInlineConstant(OpInfo.OperandType);
 }
 
 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
   int Op32 = AMDGPU::getVOPe32(Opcode);
bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
   // Literal constants use the constant bus.
   if (isLiteralConstant(MO, OpSize))
     return true;
 
   if (!MO.isReg() || !MO.isUse())
     return false;
 
   if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
-    return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
+    return RI.isSGPRClass(MRI.getRegClass(MO.getReg()), ST);
 
   // FLAT_SCR is just an SGPR pair.
   if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
     return true;
 
   // EXEC register uses the constant bus.
   if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
     return true;
case MCOI::OPERAND_REGISTER:
       }
       break;
     case AMDGPU::OPERAND_REG_IMM32_INT:
     case AMDGPU::OPERAND_REG_IMM32_FP:
       break;
     case AMDGPU::OPERAND_REG_INLINE_C_INT:
     case AMDGPU::OPERAND_REG_INLINE_C_FP:
       if (isLiteralConstant(MI.getOperand(i),
-                            RI.getRegClass(RegClass)->getSize())) {
+                            MRI.getRegSize(RI.getRegClass(RegClass)))) {
         ErrInfo = "Illegal immediate value for operand.";
         return false;
       }
       break;
     case MCOI::OPERAND_IMMEDIATE:
     case AMDGPU::OPERAND_KIMM32:
       // Check if this operand is an immediate.
       // FrameIndex operands will be replaced by immediates, so they are
if (TargetRegisterInfo::isVirtualRegister(Reg))
       return MRI.getRegClass(Reg);
     return RI.getPhysRegClass(Reg);
   }
 
   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
   return RI.getRegClass(RCID);
 }
 
+unsigned SIInstrInfo::getOpSize(uint16_t Opcode, unsigned OpNo) const {
+  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
+
+  if (OpInfo.RegClass == -1) {
+    // If this is an immediate operand, this must be a 32-bit literal.
+    assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
+    return 4;
+  }
+
+  return RI.getRegSize(RI.getRegClass(OpInfo.RegClass)->getID(), ST);
+}
+
+unsigned SIInstrInfo::getOpSize(const MachineInstr &MI, unsigned OpNo) const {
+  return RI.getRegSize(getOpRegClass(MI, OpNo)->getID(), ST);
+}
+
 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
   switch (MI.getOpcode()) {
   case AMDGPU::COPY:
   case AMDGPU::REG_SEQUENCE:
   case AMDGPU::PHI:
   case AMDGPU::INSERT_SUBREG:
-    return RI.hasVGPRs(getOpRegClass(MI, 0));
+    return RI.hasVGPRs(getOpRegClass(MI, 0), ST);
   default:
-    return RI.hasVGPRs(getOpRegClass(MI, OpNo));
+    return RI.hasVGPRs(getOpRegClass(MI, OpNo), ST);
   }
 }
 
 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
   MachineBasicBlock::iterator I = MI;
   MachineBasicBlock *MBB = MI.getParent();
   MachineOperand &MO = MI.getOperand(OpIdx);
   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
   unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
   const TargetRegisterClass *RC = RI.getRegClass(RCID);
   unsigned Opcode = AMDGPU::V_MOV_B32_e32;
   if (MO.isReg())
     Opcode = AMDGPU::COPY;
-  else if (RI.isSGPRClass(RC))
+  else if (RI.isSGPRClass(RC, ST))
     Opcode = AMDGPU::S_MOV_B32;
 
-  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
+  const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC, ST);
   if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
     VRC = &AMDGPU::VReg_64RegClass;
   else
     VRC = &AMDGPU::VGPR_32RegClass;
 
   unsigned Reg = MRI.createVirtualRegister(VRC);
   DebugLoc DL = MBB->findDebugLoc(I);
   BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).addOperand(MO);
bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
   unsigned Reg = MO.getReg();
   const TargetRegisterClass *RC =
     TargetRegisterInfo::isVirtualRegister(Reg) ?
     MRI.getRegClass(Reg) :
     RI.getPhysRegClass(Reg);
 
   const SIRegisterInfo *TRI =
       static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
-  RC = TRI->getSubRegClass(RC, MO.getSubReg());
+  RC = TRI->getSubRegClass(RC, MO.getSubReg(), ST);
 
   // In order to be legal, the common sub-class must be equal to the
   // class of the current operand.  For example:
   //
   // v_mov_b32 s0 ; Operand defined as vsrc_b32
   //              ; RI.getCommonSubClass(s0,vsrc_b32) = sgpr ; LEGAL
   //
   // s_sendmsg 0, s0 ; Operand defined as m0reg
bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   const MCInstrDesc &InstDesc = MI.getDesc();
   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
   const TargetRegisterClass *DefinedRC =
       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
   if (!MO)
     MO = &MI.getOperand(OpIdx);
 
-  if (isVALU(MI) && usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
+  if (isVALU(MI) && usesConstantBus(MRI, *MO, MRI.getRegSize(DefinedRC))) {
 
     RegSubRegPair SGPRUsed;
     if (MO->isReg())
       SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg());
 
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       if (i == OpIdx)
         continue;
for (unsigned i = 0; i < 3; ++i) {
     if (Idx == -1)
       break;
     MachineOperand &MO = MI.getOperand(Idx);
 
     // We should never see a VOP3 instruction with an illegal immediate operand.
     if (!MO.isReg())
       continue;
 
-    if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
+    if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()), ST))
       continue; // VGPRs are legal
 
     if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
       SGPRReg = MO.getReg();
       // We can use one SGPR in each VOP3 instruction.
       continue;
     }
 
     // If we make it this far, then the operand is not legal and we must
     // legalize it.
     legalizeOpWithMove(MI, Idx);
   }
 }
 
 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
                                          MachineRegisterInfo &MRI) const {
   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
-  const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
+  const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC, ST);
   unsigned DstReg = MRI.createVirtualRegister(SRC);
-  unsigned SubRegs = VRC->getSize() / 4;
+  unsigned SubRegs = MRI.getRegSize(VRC) / 4;
 
   SmallVector<unsigned, 8> SRegs;
   for (unsigned i = 0; i < SubRegs; ++i) {
     unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
             get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
         .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
     SRegs.push_back(SGPR);

 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
                                        MachineInstr &MI) const {
 
   // If the pointer is store in VGPRs, then we need to move them to
   // SGPRs using v_readfirstlane.  This is safe because we only select
   // loads with uniform pointers to SMRD instruction so we know the
   // pointer value is uniform.
   MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
-  if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
+  if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()), ST)) {
       unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
       SBase->setReg(SGPR);
   }
 }
 
 void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
 
void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
   if (MI.getOpcode() == AMDGPU::PHI) {
     const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
     for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
       if (!MI.getOperand(i).isReg() ||
           !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
         continue;
       const TargetRegisterClass *OpRC =
           MRI.getRegClass(MI.getOperand(i).getReg());
-      if (RI.hasVGPRs(OpRC)) {
+      if (RI.hasVGPRs(OpRC, ST)) {
         VRC = OpRC;
       } else {
         SRC = OpRC;
       }
     }
 
     // If any of the operands are VGPR registers, then they all most be
     // otherwise we will create illegal VGPR->SGPR copies when legalizing
     // them.
-    if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
+    if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0), ST)) {
       if (!VRC) {
         assert(SRC);
-        VRC = RI.getEquivalentVGPRClass(SRC);
+        VRC = RI.getEquivalentVGPRClass(SRC, ST);
       }
       RC = VRC;
     } else {
       RC = SRC;
     }
 
     // Update all the operands so they have the same type.
     for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
   }
 
   // REG_SEQUENCE doesn't really require operand legalization, but if one has a
   // VGPR dest type and SGPR sources, insert copies so all operands are
   // VGPRs. This seems to help operand folding / the register coalescer.
   if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) {
     MachineBasicBlock *MBB = MI.getParent();
     const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
-    if (RI.hasVGPRs(DstRC)) {
+    if (RI.hasVGPRs(DstRC, ST)) {
       // Update all the operands so they are VGPR register classes. These may
       // not be the same register class because REG_SEQUENCE supports mixing
       // subregister index types e.g. sub0_sub1 + sub2 + sub3
       for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
         MachineOperand &Op = MI.getOperand(I);
         if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
           continue;
 
         const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
-        const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
+        const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC, ST);
         if (VRC == OpRC)
           continue;
 
         unsigned DstReg = MRI.createVirtualRegister(VRC);
 
         BuildMI(*MBB, MI, MI.getDebugLoc(), get(AMDGPU::COPY), DstReg)
             .addOperand(Op);
 
if (DstRC != Src0RC) {
       MI.getOperand(1).setReg(NewSrc0);
     }
     return;
   }
 
   // Legalize MIMG
   if (isMIMG(MI)) {
     MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
-    if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
+    if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()), ST)) {
       unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
       SRsrc->setReg(SGPR);
     }
 
     MachineOperand *SSamp = getNamedOperand(MI, AMDGPU::OpName::ssamp);
-    if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
+    if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()), ST)) {
       unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI);
       SSamp->setReg(SGPR);
     }
     return;
   }
 
   // Legalize MUBUF* instructions
   // FIXME: If we start using the non-addr64 instructions for compute, we
void SIInstrInfo::splitScalar64BitUnaryOp(
 
   MachineBasicBlock::iterator MII = Inst;
 
   const MCInstrDesc &InstDesc = get(Opcode);
   const TargetRegisterClass *Src0RC = Src0.isReg() ?
     MRI.getRegClass(Src0.getReg()) :
     &AMDGPU::SGPR_32RegClass;
 
-  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
+  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC,
+                                                           AMDGPU::sub0, ST);
 
   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
                                                        AMDGPU::sub0, Src0SubRC);
 
   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
-  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
-  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
+  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC, ST);
+  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC,
+                                                              AMDGPU::sub0, ST);
 
   unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
   BuildMI(MBB, MII, DL, InstDesc, DestSub0)
     .addOperand(SrcReg0Sub0);
 
   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
                                                        AMDGPU::sub1, Src0SubRC);
 
void SIInstrInfo::splitScalar64BitBinaryOp(
 
   MachineBasicBlock::iterator MII = Inst;
 
   const MCInstrDesc &InstDesc = get(Opcode);
   const TargetRegisterClass *Src0RC = Src0.isReg() ?
     MRI.getRegClass(Src0.getReg()) :
     &AMDGPU::SGPR_32RegClass;
 
-  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
+  const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC,
+                                                           AMDGPU::sub0, ST);
   const TargetRegisterClass *Src1RC = Src1.isReg() ?
     MRI.getRegClass(Src1.getReg()) :
     &AMDGPU::SGPR_32RegClass;
 
-  const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
+  const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC,
+                                                           AMDGPU::sub0, ST);
 
   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
                                                        AMDGPU::sub0, Src0SubRC);
   MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
                                                        AMDGPU::sub0, Src1SubRC);
 
   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
-  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
-  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
+  const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC, ST);
+  const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC,
+                                                              AMDGPU::sub0, ST);
 
   unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
                               .addOperand(SrcReg0Sub0)
                               .addOperand(SrcReg1Sub0);
 
   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
                                                        AMDGPU::sub1, Src0SubRC);
void SIInstrInfo::splitScalar64BitBCNT(
   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
   const TargetRegisterClass *SrcRC = Src.isReg() ?
     MRI.getRegClass(Src.getReg()) :
     &AMDGPU::SGPR_32RegClass;
 
   unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
   unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
 
-  const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
+  const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0,
+                                                          ST);
 
   MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
                                                       AMDGPU::sub0, SrcSubRC);
   MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
                                                       AMDGPU::sub1, SrcSubRC);
 
   BuildMI(MBB, MII, DL, InstDesc, MidReg)
     .addOperand(SrcRegSub0)
const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
   switch (Inst.getOpcode()) {
   // For target instructions, getOpRegClass just returns the virtual register
   // class associated with the operand, so we need to find an equivalent VGPR
   // register class in order to move the instruction to the VALU.
   case AMDGPU::COPY:
   case AMDGPU::PHI:
   case AMDGPU::REG_SEQUENCE:
   case AMDGPU::INSERT_SUBREG:
-    if (RI.hasVGPRs(NewDstRC))
+    if (RI.hasVGPRs(NewDstRC, ST))
       return nullptr;
 
-    NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
+    NewDstRC = RI.getEquivalentVGPRClass(NewDstRC, ST);
     if (!NewDstRC)
       return nullptr;
     return NewDstRC;
   default:
     return NewDstRC;
   }
 }
 
for (unsigned i = 0; i < 3; ++i) {
 
     const MachineOperand &MO = MI.getOperand(Idx);
     if (!MO.isReg())
       continue;
 
     // Is this operand statically required to be an SGPR based on the operand
     // constraints?
     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
-    bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
+    bool IsRequiredSGPR = RI.isSGPRClass(OpRC, ST);
     if (IsRequiredSGPR)
       return MO.getReg();
 
     // If this could be a VGPR or an SGPR, Check the dynamic register class.
     unsigned Reg = MO.getReg();
     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
-    if (RI.isSGPRClass(RegRC))
+    if (RI.isSGPRClass(RegRC, ST))
       UsedSGPRs[i] = Reg;
   }
 
   // We don't have a required SGPR operand, so we have a bit more freedom in
   // selecting operands to move.
 
   // Try to select the most used SGPR. If an SGPR is equal to one of the
   // others, we choose that.

lib/Target/AMDGPU/SIInstrInfo.td

class SGPRImm <dag frag> : PatLeaf<frag, [{
   if (Subtarget->getGeneration() < SISubtarget::SOUTHERN_ISLANDS) {
     return false;
   }
   const SIRegisterInfo *SIRI =
       static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
   for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
                                                 U != E; ++U) {
     const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
-    if (RC && SIRI->isSGPRClass(RC))
+    if (RC && SIRI->isSGPRClass(RC, *Subtarget))
       return true;
   }
   return false;
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Custom Operands
 //===----------------------------------------------------------------------===//

lib/Target/AMDGPU/SIRegisterInfo.h

unsigned getHWRegIndex(unsigned Reg) const {
     return getEncodingValue(Reg) & 0xff;
   }
 
   /// \brief Return the 'base' register class for this register.
   /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
   const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
 
   /// \returns true if this class contains only SGPR registers
-  bool isSGPRClass(const TargetRegisterClass *RC) const {
-    return !hasVGPRs(RC);
+  bool isSGPRClass(const TargetRegisterClass *RC,
+                   const TargetSubtargetInfo &STI) const {
+    return !hasVGPRs(RC, STI);
   }
 
   /// \returns true if this class ID contains only SGPR registers
-  bool isSGPRClassID(unsigned RCID) const {
-    return isSGPRClass(getRegClass(RCID));
+  bool isSGPRClassID(unsigned RCID, const TargetSubtargetInfo &STI) const {
+    return isSGPRClass(getRegClass(RCID), STI);
   }
 
   bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
     const TargetRegisterClass *RC;
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       RC = MRI.getRegClass(Reg);
     else
       RC = getPhysRegClass(Reg);
-    return isSGPRClass(RC);
+    return isSGPRClass(RC, MRI.getTargetSubtargetInfo());
   }
 
   /// \returns true if this class contains VGPR registers.
-  bool hasVGPRs(const TargetRegisterClass *RC) const;
+  bool hasVGPRs(const TargetRegisterClass *RC,
+                const TargetSubtargetInfo &STI) const;
 
   /// \returns A VGPR reg class with the same width as \p SRC
   const TargetRegisterClass *getEquivalentVGPRClass(
-                                          const TargetRegisterClass *SRC) const;
+                                          const TargetRegisterClass *SRC,
+                                          const TargetSubtargetInfo &STI) const;
 
   /// \returns A SGPR reg class with the same width as \p SRC
   const TargetRegisterClass *getEquivalentSGPRClass(
-                                           const TargetRegisterClass *VRC) const;
+                                          const TargetRegisterClass *VRC,
+                                          const TargetSubtargetInfo &STI) const;
 
   /// \returns The register class that is used for a sub-register of \p RC for
   /// the given \p SubIdx.  If \p SubIdx equals NoSubRegister, \p RC will
   /// be returned.
   const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
-                                            unsigned SubIdx) const;
+                                            unsigned SubIdx,
+                                            const TargetSubtargetInfo &STI)
+                                            const;
 
-  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+  bool shouldRewriteCopySrc(const TargetSubtargetInfo &STI,
+                            const TargetRegisterClass *DefRC,
                             unsigned DefSubReg,
                             const TargetRegisterClass *SrcRC,
                             unsigned SrcSubReg) const override;
 
   /// \returns True if operands defined with this operand type can accept
   /// a literal constant (i.e. any 32-bit immediate).
   bool opCanUseLiteralConstant(unsigned OpType) const;
 

lib/Target/AMDGPU/SIRegisterInfo.cpp

if (BaseClass->contains(Reg)) {
       return BaseClass;
     }
   }
   return nullptr;
 }
 
 // TODO: It might be helpful to have some target specific flags in
 // TargetRegisterClass to mark which classes are VGPRs to make this trivial.
-bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
-  switch (RC->getSize()) {
+bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC,
+                              const TargetSubtargetInfo &STI) const {
+  switch (getRegSize(RC->getID(), STI)) {
   case 0: return false;
   case 1: return false;
   case 4:
     return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
   case 8:
     return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
   case 12:
     return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr;
   case 16:
     return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr;
   case 32:
     return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr;
   case 64:
     return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
   default:
     llvm_unreachable("Invalid register class size");
   }
 }
 
 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
-                                         const TargetRegisterClass *SRC) const {
-  switch (SRC->getSize()) {
+                                         const TargetRegisterClass *SRC,
+                                         const TargetSubtargetInfo &STI) const {
+  switch (getRegSize(SRC->getID(), STI)) {
   case 4:
     return &AMDGPU::VGPR_32RegClass;
   case 8:
     return &AMDGPU::VReg_64RegClass;
   case 12:
     return &AMDGPU::VReg_96RegClass;
   case 16:
     return &AMDGPU::VReg_128RegClass;
   case 32:
     return &AMDGPU::VReg_256RegClass;
   case 64:
     return &AMDGPU::VReg_512RegClass;
   default:
     llvm_unreachable("Invalid register class size");
   }
 }
 
 const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
-                                         const TargetRegisterClass *VRC) const {
-  switch (VRC->getSize()) {
+                                         const TargetRegisterClass *VRC,
+                                         const TargetSubtargetInfo &STI) const {
+  switch (getRegSize(VRC->getID(), STI)) {
   case 4:
     return &AMDGPU::SGPR_32RegClass;
   case 8:
     return &AMDGPU::SReg_64RegClass;
   case 16:
     return &AMDGPU::SReg_128RegClass;
   case 32:
     return &AMDGPU::SReg_256RegClass;
   case 64:
     return &AMDGPU::SReg_512RegClass;
   default:
     llvm_unreachable("Invalid register class size");
   }
 }
 
 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
-                         const TargetRegisterClass *RC, unsigned SubIdx) const {
+                         const TargetRegisterClass *RC, unsigned SubIdx,
+                         const TargetSubtargetInfo &STI) const {
   if (SubIdx == AMDGPU::NoSubRegister)
     return RC;
 
   // We can assume that each lane corresponds to one 32-bit register.
   unsigned Count = countPopulation(getSubRegIndexLaneMask(SubIdx));
-  if (isSGPRClass(RC)) {
+  if (isSGPRClass(RC, STI)) {
     switch (Count) {
     case 1:
       return &AMDGPU::SGPR_32RegClass;
     case 2:
       return &AMDGPU::SReg_64RegClass;
     case 4:
       return &AMDGPU::SReg_128RegClass;
     case 8:
if (isSGPRClass(RC, STI)) {
     case 16: /* fall-through */
     default:
       llvm_unreachable("Invalid sub-register class size");
     }
   }
 }
 
 bool SIRegisterInfo::shouldRewriteCopySrc(
+  const TargetSubtargetInfo &STI,
   const TargetRegisterClass *DefRC,
   unsigned DefSubReg,
   const TargetRegisterClass *SrcRC,
   unsigned SrcSubReg) const {
   // We want to prefer the smallest register class possible, so we don't want to
   // stop and rewrite on anything that looks like a subregister
   // extract. Operations mostly don't care about the super register class, so we
   // only want to stop on the most basic of copies between the smae register

 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI,
                             unsigned Reg) const {
   const TargetRegisterClass *RC;
   if (TargetRegisterInfo::isVirtualRegister(Reg))
     RC = MRI.getRegClass(Reg);
   else
     RC = getPhysRegClass(Reg);
 
-  return hasVGPRs(RC);
+  return hasVGPRs(RC, MRI.getTargetSubtargetInfo());
 }
 
 unsigned SIRegisterInfo::getTotalNumSGPRs(const SISubtarget &ST) const {
   if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
     return 800;
   return 512;
 }
 

lib/Target/AMDGPU/SIShrinkInstructions.cpp

FunctionPass *llvm::createSIShrinkInstructionsPass() {
   return new SIShrinkInstructions();
 }
 
 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
                    const MachineRegisterInfo &MRI) {
   if (!MO->isReg())
     return false;
 
+  const TargetSubtargetInfo &STI = MRI.getTargetSubtargetInfo();
   if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
-    return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
+    return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()), STI);
 
-  return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
+  return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()), STI);
 }
 
 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
                       const SIRegisterInfo &TRI,
                       const MachineRegisterInfo &MRI) {
 
   const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
   // Can't shrink instruction with three operands.

lib/Target/AMDGPU/SIWholeQuadMode.cpp

for (auto II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
           // only used, outputs are only defined.
           for (const MachineOperand &MO : MI.defs()) {
             if (!MO.isReg())
               continue;
 
             unsigned Reg = MO.getReg();
 
             if (!TRI->isVirtualRegister(Reg) &&
-                TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) {
+                TRI->hasVGPRs(TRI->getPhysRegClass(Reg), MF.getSubtarget())) {
               Flags = StateWQM;
               break;
             }
           }
         }
 
         if (!Flags)
           continue;

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 
 /// \brief Is this floating-point operand?
 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// \brief Does this opearnd support only inlinable literals?
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// \brief Get size of register operand
-unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
+unsigned getRegOperandSize(const MCRegisterInfo *MRI,
+                           const MCSubtargetInfo &STI,
+                           const MCInstrDesc &Desc,
                            unsigned OpNo);
 
 /// \brief Is this literal inlinable
 bool isInlinableLiteral64(int64_t Literal, bool IsVI);
 bool isInlinableLiteral32(int32_t Literal, bool IsVI);
 
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
 
   return OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
 }
 
-unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
+unsigned getRegOperandSize(const MCRegisterInfo *MRI,
+                           const MCSubtargetInfo &STI,
+                           const MCInstrDesc &Desc,
                            unsigned OpNo) {
   int RCID = Desc.OpInfo[OpNo].RegClass;
   const MCRegisterClass &RC = MRI->getRegClass(RCID);
-  return RC.getSize();
+  return MRI->getRegSize(RC.getID(), STI);
 }
 
 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
   if (Literal >= -16 && Literal <= 64)
     return true;
 
   double D = BitsToDouble(Literal);
 

lib/Target/ARM/ARMBaseInstrInfo.cpp

storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   if (I != MBB.end()) DL = I->getDebugLoc();
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
       MFI.getObjectSize(FI), Align);
-
-  switch (RC->getSize()) {
+  unsigned StoreSize = TRI->getSpillSize(RC->getID(), Subtarget);
+  switch (StoreSize) {
     case 4:
       if (ARM::GPRRegClass.hasSubClassEq(RC)) {
         AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
                    .addReg(SrcReg, getKillRegState(isKill))
                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
         AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
                    .addReg(SrcReg, getKillRegState(isKill))
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   if (I != MBB.end()) DL = I->getDebugLoc();
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
       MFI.getObjectSize(FI), Align);
 
-  switch (RC->getSize()) {
+  unsigned LoadSize = TRI->getSpillSize(RC->getID(), Subtarget);
+  switch (LoadSize) {
   case 4:
     if (ARM::GPRRegClass.hasSubClassEq(RC)) {
       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
 
     } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
       AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
                    .addFrameIndex(FI).addImm(0).addMemOperand(MMO));

lib/Target/ARM/ARMBaseRegisterInfo.cpp

bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
   auto MBB = MI->getParent();
   auto MF = MBB->getParent();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   // If not copying into a sub-register this should be ok because we shouldn't
   // need to split the reg.
   if (!DstSubReg)
     return true;
   // Small registers don't frequently cause a problem, so we can coalesce them.
-  if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
+  if (MRI.getRegSize(NewRC) < 32 && MRI.getRegSize(DstRC) < 32 &&
+      MRI.getRegSize(SrcRC) < 32)
     return true;
 
   auto NewRCWeight =
               MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
   auto SrcRCWeight =
               MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
   auto DstRCWeight =
               MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);

lib/Target/ARM/ARMFrameLowering.cpp

if (BigStack && !ExtraCSSpill) {
         for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
           SavedRegs.set(Extras[i]);
         }
       } else if (!AFI->isThumb1OnlyFunction()) {
         // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
         // closest to SP or frame pointer.
         assert(RS && "Register scavenging not provided");
         const TargetRegisterClass *RC = &ARM::GPRRegClass;
-        RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
-                                                          RC->getAlignment(),
-                                                          false));
+        unsigned Size = MRI.getSpillSize(RC);
+        unsigned Align = MRI.getSpillAlignment(RC);
+        RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
       }
     }
   }
 
   if (ForceLRSpill) {
     SavedRegs.set(ARM::LR);
     AFI->setLRIsSpilledForFarJump(true);
   }

lib/Target/ARM/ARMISelLowering.h

public:
     }
 
     bool hasStandaloneRem(EVT VT) const override {
       return HasStandaloneRem;
     }
 
   protected:
     std::pair<const TargetRegisterClass *, uint8_t>
-    findRepresentativeClass(const TargetRegisterInfo *TRI,
+    findRepresentativeClass(const TargetSubtargetInfo &STI,
                             MVT VT) const override;
 
   private:
     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     /// make the right decision when generating code for different targets.
     const ARMSubtarget *Subtarget;
 
     const TargetRegisterInfo *RegInfo;

lib/Target/ARM/ARMISelLowering.cpp

if (Subtarget->isFPOnlySP()) {
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
     setOperationAction(ISD::FP_ROUND,   MVT::f32, Custom);
     setOperationAction(ISD::FP_EXTEND,  MVT::f64, Custom);
   }
 
-  computeRegisterProperties(Subtarget->getRegisterInfo());
+  computeRegisterProperties(*Subtarget);
 
   // ARM does not have floating-point extending loads.
   for (MVT VT : MVT::fp_valuetypes()) {
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
   }
 
   // ... or truncating stores

 // SPR's representative would be DPR_VFP2. This should work well if register
 // pressure tracking were modified such that a register use would increment the
 // pressure of the register class's representative and all of it's super
 // classes' representatives transitively. We have not implemented this because
 // of the difficulty prior to coalescing of modeling operand register classes
 // due to the common occurrence of cross class copies and subregister insertions
 // and extractions.
 std::pair<const TargetRegisterClass *, uint8_t>
-ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
+ARMTargetLowering::findRepresentativeClass(const TargetSubtargetInfo &STI,
                                            MVT VT) const {
   const TargetRegisterClass *RRC = nullptr;
   uint8_t Cost = 1;
   switch (VT.SimpleTy) {
   default:
-    return TargetLowering::findRepresentativeClass(TRI, VT);
+    return TargetLowering::findRepresentativeClass(STI, VT);
   // Use DPR as representative register class for all floating point
   // and vector types. Since there are 32 SPR registers and 32 DPR registers so
   // the cost is 1 for both f32 and f64.
   case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
   case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
     RRC = &ARM::DPRRegClass;
     // When NEON is used for SP, only half of the register file is available
     // because operations that define both SP and DP results will be constrained

lib/Target/BPF/BPFISelLowering.cpp

 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
                                      const BPFSubtarget &STI)
     : TargetLowering(TM) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i64, &BPF::GPRRegClass);
 
   // Compute derived properties from the register classes
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 
   setStackPointerRegisterToSaveRestore(BPF::R11);
 
   setOperationAction(ISD::BR_CC, MVT::i64, Custom);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BRIND, MVT::Other, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
   setOperationAction(ISD::SETCC, MVT::i64, Expand);

lib/Target/Hexagon/BitTracker.h

 //===--- BitTracker.h -----------------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef BITTRACKER_H
 #define BITTRACKER_H
 
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 
 #include <map>
 #include <queue>
 #include <set>
 
 namespace llvm {
   class ConstantInt;
-  class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineInstr;
   class MachineOperand;
   class raw_ostream;
 
 struct BitTracker {
   struct BitRef;
   struct RegisterRef;
BitTracker::RegisterCell::ref(const RegisterCell &C) {
   return RC;
 }
 
 // A class to evaluate target's instructions and update the cell maps.
 // This is used internally by the bit tracker.  A target that wants to
 // utilize this should implement the evaluation functions (noted below)
 // in a subclass of this class.
 struct BitTracker::MachineEvaluator {
-  MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
-      : TRI(T), MRI(M) {}
+  MachineEvaluator(MachineRegisterInfo &M)
+      : STI(M.getTargetSubtargetInfo()), TRI(*M.getTargetRegisterInfo()),
+        MRI(M) {}
   virtual ~MachineEvaluator() {}
 
   uint16_t getRegBitWidth(const RegisterRef &RR) const;
 
   RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
   void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
   // A result of any operation should use refs to the source cells, not
   // the cells directly. This function is a convenience wrapper to quickly
virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
                         CellMapType &Outputs) const;
   // Evaluate a branch, given the cell map with the input values. Fill out
   // a list of all possible branch targets and indicate (through a flag)
   // whether the branch could fall-through. Return "true" if this information
   // has been successfully computed, "false" otherwise.
   virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
                         BranchTargetList &Targets, bool &FallsThru) const = 0;
 
+  const TargetSubtargetInfo &STI;
   const TargetRegisterInfo &TRI;
   MachineRegisterInfo &MRI;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/Hexagon/BitTracker.cpp

if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
     PhysR = *VC->begin();
   } else {
     assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
     PhysR = RR.Reg;
   }
 
   unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS);
-  uint16_t BW = RC->getSize()*8;
+  uint16_t BW = TRI.getRegSize(RC->getID(), STI)*8;
   return BW;
 }
 
 
 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
       const CellMapType &M) const {
   uint16_t BW = getRegBitWidth(RR);
 

lib/Target/Hexagon/HexagonBitSimplify.cpp

 
 
 // For a register ref (pair Reg:Sub), set Begin to the position of the LSB
 // of Sub in Reg, and set Width to the size of Sub in bits. Return true,
 // if this succeeded, otherwise return false.
 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
       unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI) {
   const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
+  unsigned RegSize = MRI.getRegSize(RC);
   if (RR.Sub == 0) {
     Begin = 0;
-    Width = RC->getSize()*8;
+    Width = RegSize*8;
     return true;
   }
 
   assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
   if (RR.Sub == Hexagon::subreg_loreg)
     Begin = 0;
 
   switch (RC->getID()) {
     case Hexagon::DoubleRegsRegClassID:
     case Hexagon::VecDblRegsRegClassID:
     case Hexagon::VecDblRegs128BRegClassID:
-      Width = RC->getSize()*8 / 2;
+      Width = RegSize*8 / 2;
       if (RR.Sub == Hexagon::subreg_hireg)
         Begin = Width;
       break;
     default:
       return false;
   }
   return true;
 }
bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI,
   // Even if we don't have bits yet, we could still provide some information
   // if the instruction is a lossy shift: the lost bits will be marked as
   // not used.
   unsigned LB, LE;
   if (isLossyShiftLeft(MI, OpN, LB, LE) || isLossyShiftRight(MI, OpN, LB, LE)) {
     assert(MI.getOperand(OpN).isReg());
     BitTracker::RegisterRef RR = MI.getOperand(OpN);
     const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
-    uint16_t Width = RC->getSize()*8;
+    uint16_t Width = MRI.getRegSize(RC)*8;
 
     if (!GotBits)
       T.set(Begin, Begin+Width);
     assert(LB <= LE && LB < Width && LE <= Width);
     T.reset(Begin+LB, Begin+LE);
     GotBits = true;
   }
   if (GotBits)
bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
   auto &HII = *HST.getInstrInfo();
 
   MDT = &getAnalysis<MachineDominatorTree>();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   bool Changed;
 
   Changed = DeadCodeElimination(MF, *MDT).run();
 
-  const HexagonEvaluator HE(HRI, MRI, HII, MF);
+  const HexagonEvaluator HE(MRI, HII, MF);
   BitTracker BT(HE, MF);
   DEBUG(BT.trace(true));
   BT.run();
 
   MachineBasicBlock &Entry = MF.front();
 
   RegisterSet AIG;  // Available registers for IG.
   ConstGeneration ImmG(BT, HII, MRI);

 bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(*MF.getFunction()))
     return false;
 
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
   HII = HST.getInstrInfo();
   HRI = HST.getRegisterInfo();
   MRI = &MF.getRegInfo();
-  const HexagonEvaluator HE(*HRI, *MRI, *HII, MF);
+  const HexagonEvaluator HE(*MRI, *HII, MF);
   BitTracker BT(HE, MF);
   DEBUG(BT.trace(true));
   BT.run();
   BTP = &BT;
 
   std::vector<LoopCand> Cand;
 
   for (auto &B : MF) {

lib/Target/Hexagon/HexagonBitTracker.h

namespace llvm {
   class HexagonRegisterInfo;
 
 struct HexagonEvaluator : public BitTracker::MachineEvaluator {
   typedef BitTracker::CellMapType CellMapType;
   typedef BitTracker::RegisterRef RegisterRef;
   typedef BitTracker::RegisterCell RegisterCell;
   typedef BitTracker::BranchTargetList BranchTargetList;
 
-  HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
+  HexagonEvaluator(MachineRegisterInfo &mri,
                    const HexagonInstrInfo &tii, MachineFunction &mf);
 
   bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
                 CellMapType &Outputs) const override;
   bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
                 BranchTargetList &Targets, bool &FallsThru) const override;
 
   BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;

lib/Target/Hexagon/HexagonBitTracker.cpp

 #include "HexagonRegisterInfo.h"
 #include "HexagonTargetMachine.h"
 #include "HexagonBitTracker.h"
 
 using namespace llvm;
 
 typedef BitTracker BT;
 
-HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
-                                   MachineRegisterInfo &mri,
+HexagonEvaluator::HexagonEvaluator(MachineRegisterInfo &mri,
                                    const HexagonInstrInfo &tii,
                                    MachineFunction &mf)
-    : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
+    : MachineEvaluator(mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
   // Populate the VRX map (VR to extension-type).
   // Go over all the formal parameters of the function. If a given parameter
   // P is sign- or zero-extended, locate the virtual register holding that
   // parameter and create an entry in the VRX map indicating the type of ex-
   // tension (and the source type).
   // This is a bit complicated to do accurately, since the memory layout in-
   // formation is necessary to precisely determine whether an aggregate para-
   // meter will be passed in a register or in memory. What is given in MRI

lib/Target/Hexagon/HexagonExpandCondsets.cpp

if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
       assert(VC->begin() != VC->end() && "Empty register class");
       PhysR = *VC->begin();
     } else {
       assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
       PhysR = RS.Reg;
     }
     unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
-    switch (RC->getSize()) {
+    switch (MRI->getRegSize(RC)) {
       case 4:
         return IfTrue ? A2_tfrt : A2_tfrf;
       case 8:
         return IfTrue ? A2_tfrpt : A2_tfrpf;
     }
     llvm_unreachable("Invalid register operand");
   }
   if (SO.isImm() || SO.isFPImm())

lib/Target/Hexagon/HexagonFrameLowering.cpp

 #endif
 
 
 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
       const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
   DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on "
                << MF.getFunction()->getName() << '\n');
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   BitVector SRegs(Hexagon::NUM_TARGET_REGS);
 
   // Generate a set of unique, callee-saved registers (SRegs), where each
   // register in the set is maximal in terms of sub-/super-register relation,
   // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
 
   // (1) For each callee-saved register, add that register and all of its
   // sub-registers to SRegs.
bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
   typedef TargetFrameLowering::SpillSlot SpillSlot;
   unsigned NumFixed;
   int MinOffset = 0;  // CS offsets are negative.
   const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
   for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
     if (!SRegs[S->Reg])
       continue;
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
-    int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), S->Offset);
+    int FI = MFI.CreateFixedSpillStackObject(MRI.getSpillSize(RC), S->Offset);
     MinOffset = std::min(MinOffset, S->Offset);
     CSI.push_back(CalleeSavedInfo(S->Reg, FI));
     SRegs[S->Reg] = false;
   }
 
   // There can be some registers that don't have fixed slots. For example,
   // we need to store R0-R3 in functions with exception handling. For each
   // such register, create a non-fixed stack object.
   for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
     unsigned R = x;
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
-    int Off = MinOffset - RC->getSize();
-    unsigned Align = std::min(RC->getAlignment(), getStackAlignment());
+    int Off = MinOffset - MRI.getSpillSize(RC);
+    unsigned Align = std::min(MRI.getSpillAlignment(RC), getStackAlignment());
     assert(isPowerOf2_32(Align));
     Off &= -Align;
-    int FI = MFI.CreateFixedSpillStackObject(RC->getSize(), Off);
+    int FI = MFI.CreateFixedSpillStackObject(MRI.getSpillSize(RC), Off);
     MinOffset = std::min(MinOffset, Off);
     CSI.push_back(CalleeSavedInfo(R, FI));
     SRegs[R] = false;
   }
 
   DEBUG({
     dbgs() << "CS information: {";
     for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
   unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg);
   unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg);
   bool IsKill = MI->getOperand(2).isKill();
   int FI = MI->getOperand(0).getIndex();
 
   bool Is128B = HST.useHVXDblOps();
   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
                      : &Hexagon::VectorRegs128BRegClass;
-  unsigned Size = RC->getSize();
-  unsigned NeedAlign = RC->getAlignment();
+  unsigned Size = MRI.getSpillSize(RC);
+  unsigned NeedAlign = MRI.getSpillAlignment(RC);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned StoreOpc;
 
   // Store low part.
   if (NeedAlign <= HasAlign)
     StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai  : Hexagon::V6_vS32b_ai_128B;
   else
     StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
   unsigned DstR = MI->getOperand(0).getReg();
   unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg);
   unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg);
   int FI = MI->getOperand(1).getIndex();
 
   bool Is128B = HST.useHVXDblOps();
   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
                      : &Hexagon::VectorRegs128BRegClass;
-  unsigned Size = RC->getSize();
-  unsigned NeedAlign = RC->getAlignment();
+  unsigned Size = MRI.getSpillSize(RC);
+  unsigned NeedAlign = MRI.getSpillAlignment(RC);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned LoadOpc;
 
   // Load low part.
   if (NeedAlign <= HasAlign)
     LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai  : Hexagon::V6_vL32b_ai_128B;
   else
     LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
   unsigned SrcR = MI->getOperand(2).getReg();
   bool IsKill = MI->getOperand(2).isKill();
   int FI = MI->getOperand(0).getIndex();
 
   bool Is128B = HST.useHVXDblOps();
   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
                      : &Hexagon::VectorRegs128BRegClass;
 
-  unsigned NeedAlign = RC->getAlignment();
+  unsigned NeedAlign = MRI.getSpillAlignment(RC);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned StoreOpc;
 
   if (NeedAlign <= HasAlign)
     StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
   else
     StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
 
bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
   DebugLoc DL = MI->getDebugLoc();
   unsigned DstR = MI->getOperand(0).getReg();
   int FI = MI->getOperand(1).getIndex();
 
   bool Is128B = HST.useHVXDblOps();
   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass
                      : &Hexagon::VectorRegs128BRegClass;
 
-  unsigned NeedAlign = RC->getAlignment();
+  unsigned NeedAlign = MRI.getSpillAlignment(RC);
   unsigned HasAlign = MFI.getObjectAlignment(FI);
   unsigned LoadOpc;
 
   if (NeedAlign <= HasAlign)
     LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;
   else
     LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;
 
if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
 
     for (unsigned VR : NewRegs)
       SpillRCs.insert(MRI.getRegClass(VR));
 
     for (auto *RC : SpillRCs) {
       if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
         continue;
       unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
-      unsigned S = RC->getSize(), A = RC->getAlignment();
+      unsigned S = MRI.getSpillSize(RC), A = MRI.getSpillAlignment(RC);
       for (unsigned i = 0; i < Num; i++) {
         int NewFI = MFI.CreateSpillStackObject(S, A);
         RS->addScavengingFrameIndex(NewFI);
       }
     }
   }
 
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);

lib/Target/Hexagon/HexagonGenInsert.cpp

bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
 
   // Clean up before any further processing, so that dead code does not
   // get used in a newly generated "insert" instruction. Have a custom
   // version of DCE that preserves lifetime markers. Without it, merging
   // of stack objects can fail to recognize and merge disjoint objects
   // leading to unnecessary stack growth.
   Changed = removeDeadCode(MDT->getRootNode());
 
-  const HexagonEvaluator HE(*HRI, *MRI, *HII, MF);
+  const HexagonEvaluator HE(*MRI, *HII, MF);
   BitTracker BTLoc(HE, MF);
   BTLoc.trace(isDebug());
   BTLoc.run();
   CellMapShadow MS(BTLoc);
   CMS = &MS;
 
   buildOrderingMF(BaseOrd);
   buildOrderingBT(BaseOrd, CellOrd);

lib/Target/Hexagon/HexagonISelLowering.h

public:
 
     AtomicExpansionKind
     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
       return AtomicExpansionKind::LLSC;
     }
 
   protected:
     std::pair<const TargetRegisterClass*, uint8_t>
-    findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
+    findRepresentativeClass(const TargetSubtargetInfo &STI, MVT VT)
         const override;
   };
 } // end namespace llvm
 
 #endif    // Hexagon_ISELLOWERING_H

lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   } else if (UseHVXDbl) {
     for (MVT VT : {MVT::v128i8, MVT::v64i16,  MVT::v32i32, MVT::v16i64,
                    MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
       setIndexedLoadAction(ISD::POST_INC, VT, Legal);
       setIndexedStoreAction(ISD::POST_INC, VT, Legal);
     }
   }
 
-  computeRegisterProperties(&HRI);
+  computeRegisterProperties(Subtarget);
 
   //
   // Library calls for unsupported operations
   //
   bool FastMath  = EnableFastMath;
 
   setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
   setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
   case MVT::v32i64:
     return true;
   }
   return false;
 }
 
 
 std::pair<const TargetRegisterClass*, uint8_t>
-HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
+HexagonTargetLowering::findRepresentativeClass(const TargetSubtargetInfo &STI,
       MVT VT) const {
   const TargetRegisterClass *RRC = nullptr;
 
   uint8_t Cost = 1;
   switch (VT.SimpleTy) {
   default:
-    return TargetLowering::findRepresentativeClass(TRI, VT);
+    return TargetLowering::findRepresentativeClass(STI, VT);
   case MVT::v64i8:
   case MVT::v32i16:
   case MVT::v16i32:
   case MVT::v8i64:
     RRC = &Hexagon::VectorRegsRegClass;
     break;
   case MVT::v128i8:
   case MVT::v64i16:

lib/Target/Lanai/LanaiISelLowering.cpp

 static cl::opt<int> LanaiLowerConstantMulThreshold(
     "lanai-constant-mul-threshold", cl::Hidden,
     cl::desc("Maximum number of instruction to generate when lowering constant "
              "multiplication instead of calling library function [default=14]"),
     cl::init(14));
 
 LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
                                          const LanaiSubtarget &STI)
-    : TargetLowering(TM) {
+    : TargetLowering(TM), TRI(STI.getRegisterInfo()) {
   // Set up the register classes.
   addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
 
   // Compute derived properties from the register classes
-  TRI = STI.getRegisterInfo();
-  computeRegisterProperties(TRI);
+  computeRegisterProperties(STI);
 
   setStackPointerRegisterToSaveRestore(Lanai::SP);
 
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
   setOperationAction(ISD::SETCC, MVT::i32, Custom);
   setOperationAction(ISD::SETCCE, MVT::i32, Custom);

lib/Target/MSP430/MSP430ISelLowering.cpp

MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
                                            const MSP430Subtarget &STI)
     : TargetLowering(TM) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
 
   // Compute derived properties from the register classes
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 
   // Provide all sorts of operation actions
   setStackPointerRegisterToSaveRestore(MSP430::SP);
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // We have post-incremented loads / stores.
   setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);

lib/Target/Mips/Mips16ISelLowering.cpp

Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::ATOMIC_LOAD_UMIN,   MVT::i32,   Expand);
   setOperationAction(ISD::ATOMIC_LOAD_UMAX,   MVT::i32,   Expand);
 
   setOperationAction(ISD::ROTR, MVT::i32,  Expand);
   setOperationAction(ISD::ROTR, MVT::i64,  Expand);
   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
 
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 }
 
 const MipsTargetLowering *
 llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
                                  const MipsSubtarget &STI) {
   return new Mips16TargetLowering(TM, STI);
 }
 

lib/Target/Mips/MipsAsmPrinter.cpp

 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
 void MipsAsmPrinter::printSavedRegsBitmask() {
   // CPU and FPU Saved Registers Bitmasks
   unsigned CPUBitmask = 0, FPUBitmask = 0;
   int CPUTopSavedRegOff, FPUTopSavedRegOff;
 
   // Set the CPU and FPU Bitmasks
   const MachineFrameInfo &MFI = MF->getFrameInfo();
-  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+  const TargetSubtargetInfo &STI = MF->getSubtarget();
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
   // size of stack area to which FP callee-saved regs are saved.
-  unsigned CPURegSize = Mips::GPR32RegClass.getSize();
-  unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
-  unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
+  unsigned CPURegSize = TRI->getRegSize(Mips::GPR32RegClass.getID(), STI);
+  unsigned FGR32RegSize = TRI->getRegSize(Mips::FGR32RegClass.getID(), STI);
+  unsigned AFGR64RegSize = TRI->getRegSize(Mips::AFGR64RegClass.getID(), STI);
   bool HasAFGR64Reg = false;
   unsigned CSFPRegsSize = 0;
 
   for (const auto &I : CSI) {
     unsigned Reg = I.getReg();
     unsigned RegNum = TRI->getEncodingValue(Reg);
 
     // If it's a floating point register, set the FPU Bitmask.

lib/Target/Mips/MipsFrameLowering.cpp

bool MipsFrameLowering::hasBP(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
   return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
 }
 
 uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 
   int64_t Offset = 0;
 
   // Iterate over fixed sized objects.
   for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
     Offset = std::max(Offset, -MFI.getObjectOffset(I));
 
   // Conservatively assume all callee-saved registers will be saved.
   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
-    unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
+    unsigned Size = MRI.getSpillSize(TRI.getMinimalPhysRegClass(*R));
     Offset = alignTo(Offset + Size, Size);
   }
 
   unsigned MaxAlign = MFI.getMaxAlignment();
 
   // Check that MaxAlign is not zero if there is a stack object that is not a
   // callee-saved spill.
   assert(!MFI.getObjectIndexEnd() || MaxAlign);

lib/Target/Mips/MipsMachineFunction.cpp

const TargetRegisterClass *RC =
                           .getABI()
                           .IsN64()
                       ? &Mips::GPR64RegClass
                       : &Mips::GPR32RegClass;
   return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
 }
 
 void MipsFunctionInfo::createEhDataRegsFI() {
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (int I = 0; I < 4; ++I) {
     const TargetRegisterClass *RC =
         static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
             ? &Mips::GPR64RegClass
             : &Mips::GPR32RegClass;
 
-    EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(RC->getSize(),
-        RC->getAlignment(), false);
+    EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
+        MRI.getSpillSize(RC), MRI.getSpillAlignment(RC), false);
   }
 }
 
 void MipsFunctionInfo::createISRRegFI() {
   // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
   // The current implementation only supports Mips32r2+ not Mips64rX. Status
   // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture,
   // however Mips32r2+ is the supported architecture.
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
 
   for (int I = 0; I < 2; ++I)
     ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
-        RC->getSize(), RC->getAlignment(), false);
+        MRI.getSpillSize(RC), MRI.getSpillAlignment(RC), false);
 }
 
 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
   return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
                         || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
 }
 
 bool MipsFunctionInfo::isISRRegFI(int FI) const {
   return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
 }
 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
   return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
 }
 
 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) {
   return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
 }
 
 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   if (MoveF64ViaSpillFI == -1) {
     MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
-        RC->getSize(), RC->getAlignment(), false);
+        MRI.getSpillSize(RC), MRI.getSpillAlignment(RC), false);
   }
   return MoveF64ViaSpillFI;
 }
 
 void MipsFunctionInfo::anchor() { }

lib/Target/Mips/MipsSEFrameLowering.cpp

 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
                                  unsigned MFHiOpc, unsigned MFLoOpc) {
   //  mflo $vr0, src
   //  copy dst_lo, $vr0
   //  mfhi $vr1, src
   //  copy dst_hi, $vr1
 
   unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
-  unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
+  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+  unsigned VRegSize = MRI.getSpillSize(RegInfo.getMinimalPhysRegClass(Dst)) / 2;
   const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
   unsigned VR0 = MRI.createVirtualRegister(RC);
   unsigned VR1 = MRI.createVirtualRegister(RC);
   unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
   unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
   unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
   DebugLoc DL = I->getDebugLoc();
 

 }
 
 void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                                BitVector &SavedRegs,
                                                RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
   MipsABIInfo ABI = STI.getABI();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   unsigned FP = ABI.GetFramePtr();
   unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
 
   // Mark $fp as used if function has dedicated frame pointer.
   if (hasFP(MF))
     setAliasRegs(MF, SavedRegs, FP);
   // Mark $s7 as used if function has dedicated base pointer.
   if (hasBP(MF))
void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
 
   // Expand pseudo instructions which load, store or copy accumulators.
   // Add an emergency spill slot if a pseudo was expanded.
   if (ExpandPseudo(MF).expand()) {
     // The spill slot should be half the size of the accumulator. If target is
     // mips64, it should be 64-bit, otherwise it should be 32-bt.
     const TargetRegisterClass *RC = STI.hasMips64() ?
       &Mips::GPR64RegClass : &Mips::GPR32RegClass;
-    int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(),
-                                                  RC->getAlignment(), false);
+    int FI = MF.getFrameInfo().CreateStackObject(MRI.getSpillSize(RC),
+                                                 MRI.getSpillAlignment(RC),
+                                                 false);
     RS->addScavengingFrameIndex(FI);
   }
 
   // Set scavenging frame index if necessary.
   uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
     estimateStackSize(MF);
 
   if (isInt<16>(MaxSPOffset))
     return;
 
   const TargetRegisterClass *RC =
       ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
-  int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(),
-                                                RC->getAlignment(), false);
+  int FI = MF.getFrameInfo().CreateStackObject(MRI.getSpillSize(RC),
+                                               MRI.getSpillAlignment(RC),
+                                               false);
   RS->addScavengingFrameIndex(FI);
 }
 
 const MipsFrameLowering *
 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
   return new MipsSEFrameLowering(ST);
 }

lib/Target/Mips/MipsSEISelLowering.cpp

if (Subtarget.hasMips64r6()) {
 
     // MIPS64r6 replaces conditional moves with an equivalent that removes the
     // need for three GPR read ports.
     setOperationAction(ISD::SETCC, MVT::i64, Legal);
     setOperationAction(ISD::SELECT, MVT::i64, Legal);
     setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
   }
 
-  computeRegisterProperties(Subtarget.getRegisterInfo());
+  computeRegisterProperties(Subtarget);
 }
 
 const MipsTargetLowering *
 llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
                                  const MipsSubtarget &STI) {
   return new MipsSETargetLowering(TM, STI);
 }
 

lib/Target/Mips/MipsSEInstrInfo.cpp

 }
 
 std::pair<bool, bool>
 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
                                  const MachineFunction &MF) const {
   const MCInstrDesc &Desc = get(Opc);
   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
   const MipsRegisterInfo *RI = &getRegisterInfo();
-  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
-  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const TargetRegisterClass *DstRC = getRegClass(Desc, 0, RI, MF);
+  const TargetRegisterClass *SrcRC = getRegClass(Desc, 1, RI, MF);
+  unsigned DstRegSize = RI->getRegSize(DstRC->getID(), STI);
+  unsigned SrcRegSize = RI->getRegSize(SrcRC->getID(), STI);
 
   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
 }
 
 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator I,
                                          unsigned NewOpc) const {
   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());

lib/Target/NVPTX/NVPTXISelLowering.cpp

NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
   setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
 
   // No FEXP2, FLOG2.  The PTX ex2 and log2 functions are always approximate.
   // No FPOW or FREM in PTX.
 
   // Now deduce the information based on the above mentioned
   // actions
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 }
 
 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((NVPTXISD::NodeType)Opcode) {
   case NVPTXISD::FIRST_NUMBER:
     break;
   case NVPTXISD::CALL:
     return "NVPTXISD::CALL";

lib/Target/NVPTX/NVPTXInstrInfo.cpp

 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, unsigned DestReg,
                                  unsigned SrcReg, bool KillSrc) const {
   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
 
-  if (DestRC->getSize() != SrcRC->getSize())
+  if (MRI.getRegSize(DestRC) != MRI.getRegSize(SrcRC))
     report_fatal_error("Copy one register into another with a different width");
 
   unsigned Op;
   if (DestRC == &NVPTX::Int1RegsRegClass) {
     Op = NVPTX::IMOV1rr;
   } else if (DestRC == &NVPTX::Int16RegsRegClass) {
     Op = NVPTX::IMOV16rr;
   } else if (DestRC == &NVPTX::Int32RegsRegClass) {

lib/Target/PowerPC/PPCFrameLowering.cpp

PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
   // this slot is used for the necessary emergency spill. Also, we need the
   // slot for dynamic stack allocations.
 
   // The scavenger might be invoked if the frame offset does not fit into
   // the 16-bit immediate. We don't know the complete frame size here
   // because we've not yet computed callee-saved register spills or the
   // needed alignment padding.
   unsigned StackSize = determineFrameLayout(MF, false, true);
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
       hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
     const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
     const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
     const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
-    RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
-                                                      RC->getAlignment(),
+    RS->addScavengingFrameIndex(MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                                      MRI.getSpillAlignment(RC),
                                                       false));
 
     // Might we have over-aligned allocas?
     bool HasAlVars = MFI.hasVarSizedObjects() &&
                      MFI.getMaxAlignment() > getStackAlignment();
 
     // These kinds of spills might need two registers.
     if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
-      RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
-                                                        RC->getAlignment(),
-                                                        false));
+      RS->addScavengingFrameIndex(
+            MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                  MRI.getSpillAlignment(RC),
 
   }
 }
 
 bool
 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MI,
                                      const std::vector<CalleeSavedInfo> &CSI,

lib/Target/PowerPC/PPCISelLowering.cpp

case PPC::DIR_PWR9:
     break;
   }
 
   if (Subtarget.enableMachineScheduler())
     setSchedulingPreference(Sched::Source);
   else
     setSchedulingPreference(Sched::Hybrid);
 
-  computeRegisterProperties(STI.getRegisterInfo());
+  computeRegisterProperties(STI);
 
   // The Freescale cores do better with aggressive inlining of memcpy and
   // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
   if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
       Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
     MaxStoresPerMemset = 32;
     MaxStoresPerMemsetOptSize = 16;
     MaxStoresPerMemcpy = 32;

lib/Target/Sparc/SparcISelLowering.cpp

if (Subtarget->replaceFMULS()) {
     // the former instructions generate errata on LEON processors.
     setOperationAction(ISD::FMUL, MVT::f32, Promote);
   }
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   setMinFunctionAlignment(2);
 
-  computeRegisterProperties(Subtarget->getRegisterInfo());
+  computeRegisterProperties(*Subtarget);
 }
 
 bool SparcTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }
 
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {

lib/Target/SystemZ/SystemZISelLowering.cpp

if (Subtarget.hasVector()) {
     addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
     addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
     addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
     addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
     addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
   }
 
   // Compute derived properties from the register classes
-  computeRegisterProperties(Subtarget.getRegisterInfo());
+  computeRegisterProperties(Subtarget);
 
   // Set up special registers.
   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
 
   // TODO: It may be better to default to latency-oriented scheduling, however
   // LLVM's current latency-oriented scheduler can't handle physreg definitions
   // such as SystemZ has with CC, so set this to the register-pressure
   // scheduler, because it can.

lib/Target/SystemZ/SystemZInstrInfo.cpp

if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
     return nullptr;
   }
 
   // All other cases require a single operand.
   if (Ops.size() != 1)
     return nullptr;
 
   unsigned OpNum = Ops[0];
-  assert(Size ==
-             MF.getRegInfo()
-                 .getRegClass(MI.getOperand(OpNum).getReg())
-                 ->getSize() &&
-         "Invalid size combination");
+  assert(Size == MF.getRegInfo().getSpillSize(
+                    MF.getRegInfo().getRegClass(MI.getOperand(OpNum).getReg()))
+         && "Invalid size combination");
 
   if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
       isInt<8>(MI.getOperand(2).getImm())) {
     // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
     Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
     MachineInstr *BuiltMI =
         BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
             .addFrameIndex(FrameIndex)

lib/Target/X86/X86FastISel.cpp

bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
   bool RHSIsKill = hasTrivialKill(RHS);
 
   unsigned LHSReg = getRegForValue(LHS);
   bool LHSIsKill = hasTrivialKill(LHS);
 
   if (!LHSReg || !RHSReg)
     return false;
 
-  unsigned Opc = X86::getCMovFromCond(CC, RC->getSize());
+  unsigned Opc = X86::getCMovFromCond(CC, MRI.getSpillSize(RC));
   unsigned ResultReg = fastEmitInst_rr(Opc, RC, RHSReg, RHSIsKill,
                                        LHSReg, LHSIsKill);
   updateValueMap(I, ResultReg);
   return true;
 }
 
 /// \brief Emit SSE or AVX instructions to lower the select.
 ///

lib/Target/X86/X86FrameLowering.cpp

X86FrameLowering::getFrameIndexReferencePreferSP(const MachineFunction &MF,
 
   return Offset + StackSize;
 }
 
 bool X86FrameLowering::assignCalleeSavedSpillSlots(
     MachineFunction &MF, const TargetRegisterInfo *TRI,
     std::vector<CalleeSavedInfo> &CSI) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 
   unsigned CalleeSavedFrameSize = 0;
   int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
 
   if (hasFP(MF)) {
     // emitPrologue always spills frame register the first thing.
     SpillSlotOffset -= SlotSize;
bool X86FrameLowering::assignCalleeSavedSpillSlots(
   // Assign slots for XMMs.
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i - 1].getReg();
     if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
       continue;
 
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
     // ensure alignment
-    SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
+    unsigned Size = MRI.getSpillSize(RC);
+    unsigned Align = MRI.getSpillAlignment(RC);
+    SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
     // spill into slot
-    SpillSlotOffset -= RC->getSize();
-    int SlotIndex =
-        MFI.CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
+    SpillSlotOffset -= Size;
+    int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
     CSI[i - 1].setFrameIdx(SlotIndex);
-    MFI.ensureMaxAlignment(RC->getAlignment());
+    MFI.ensureMaxAlignment(Align);
   }
 
   return true;
 }
 
 bool X86FrameLowering::spillCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     const std::vector<CalleeSavedInfo> &CSI,

lib/Target/X86/X86ISelLowering.h

public:
     bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
 
     bool supportSwiftError() const override {
       return true;
     }
 
   protected:
     std::pair<const TargetRegisterClass *, uint8_t>
-    findRepresentativeClass(const TargetRegisterInfo *TRI,
+    findRepresentativeClass(const TargetSubtargetInfo &STI,
                             MVT VT) const override;
 
   private:
     /// Keep a reference to the X86Subtarget around so that we can
     /// make the right decision when generating code for different targets.
     const X86Subtarget &Subtarget;
 
     /// Select between SSE or x87 floating point ops.

lib/Target/X86/X86ISelLowering.cpp

   setTargetDAGCombine(ISD::SINT_TO_FP);
   setTargetDAGCombine(ISD::UINT_TO_FP);
   setTargetDAGCombine(ISD::SETCC);
   setTargetDAGCombine(ISD::MUL);
   setTargetDAGCombine(ISD::XOR);
   setTargetDAGCombine(ISD::MSCATTER);
   setTargetDAGCombine(ISD::MGATHER);
 
-  computeRegisterProperties(Subtarget.getRegisterInfo());
+  computeRegisterProperties(Subtarget);
 
   MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
   MaxStoresPerMemsetOptSize = 8;
   MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
   MaxStoresPerMemcpyOptSize = 4;
   MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
   MaxStoresPerMemmoveOptSize = 4;
   setPrefLoopAlignment(4); // 2^4 bytes.
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
   if (Subtarget.isPICStyleRIPRel())
     return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
 
   // Otherwise, the reference is relative to the PIC base.
   return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
 }
 
 std::pair<const TargetRegisterClass *, uint8_t>
-X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
+X86TargetLowering::findRepresentativeClass(const TargetSubtargetInfo &STI,
                                            MVT VT) const {
   const TargetRegisterClass *RRC = nullptr;
   uint8_t Cost = 1;
   switch (VT.SimpleTy) {
   default:
-    return TargetLowering::findRepresentativeClass(TRI, VT);
+    return TargetLowering::findRepresentativeClass(STI, VT);
   case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
     RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
     break;
   case MVT::x86mmx:
     RRC = &X86::VR64RegClass;
     break;
   case MVT::f32: case MVT::f64:
   case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:

lib/Target/X86/X86InstrInfo.cpp

 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL, unsigned DstReg,
                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
                                 unsigned FalseReg) const {
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   assert(Cond.size() == 1 && "Invalid Cond array");
   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
-                                 MRI.getRegClass(DstReg)->getSize(),
+                                 MRI.getSpillSize(MRI.getRegClass(DstReg)),
                                  false /*HasMemoryOperand*/);
   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
 }
 
 /// Test if the given register is a physical h register.
 static bool isHReg(unsigned Reg) {
   return X86::GR8_ABCD_HRegClass.contains(Reg);
 }
static unsigned getLoadStoreRegOpcode(unsigned Reg,
                                       const TargetRegisterClass *RC,
                                       bool isStackAligned,
                                       const X86Subtarget &STI,
                                       bool load) {
   bool HasAVX = STI.hasAVX();
   bool HasAVX512 = STI.hasAVX512();
   bool HasVLX = STI.hasVLX();
 
-  switch (RC->getSize()) {
+  switch (STI.getRegisterInfo()->getSpillSize(RC->getID(), STI)) {
   default:
     llvm_unreachable("Unknown spill size");
   case 1:
     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
     if (STI.is64Bit())
       // Copying to or from a physical H register on x86-64 requires a NOREX
       // move.  Otherwise use a normal move.
       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))

 }
 
 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, bool isKill, int FrameIdx,
                                        const TargetRegisterClass *RC,
                                        const TargetRegisterInfo *TRI) const {
   const MachineFunction &MF = *MBB.getParent();
-  assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned SpillSize = MRI.getSpillSize(RC);
+  assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= SpillSize &&
          "Stack slot too small for store");
-  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
+  unsigned Alignment = std::max<uint32_t>(SpillSize, 16);
   bool isAligned =
       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
       RI.canRealignStack(MF);
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
   DebugLoc DL = MBB.findDebugLoc(MI);
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
     .addReg(SrcReg, getKillRegState(isKill));
 }
 
 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
                                   bool isKill,
                                   SmallVectorImpl<MachineOperand> &Addr,
                                   const TargetRegisterClass *RC,
                                   MachineInstr::mmo_iterator MMOBegin,
                                   MachineInstr::mmo_iterator MMOEnd,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned Alignment = std::max<uint32_t>(MRI.getSpillSize(RC), 16);
   bool isAligned = MMOBegin != MMOEnd &&
                    (*MMOBegin)->getAlignment() >= Alignment;
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
   DebugLoc DL;
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
     MIB.addOperand(Addr[i]);
   MIB.addReg(SrcReg, getKillRegState(isKill));
   (*MIB).setMemRefs(MMOBegin, MMOEnd);
   NewMIs.push_back(MIB);
 }
 
 
 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx,
                                         const TargetRegisterClass *RC,
                                         const TargetRegisterInfo *TRI) const {
   const MachineFunction &MF = *MBB.getParent();
-  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned Alignment = std::max<uint32_t>(MRI.getSpillSize(RC), 16);
   bool isAligned =
       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
       RI.canRealignStack(MF);
   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
   DebugLoc DL = MBB.findDebugLoc(MI);
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
 }
 
 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                                  SmallVectorImpl<MachineOperand> &Addr,
                                  const TargetRegisterClass *RC,
                                  MachineInstr::mmo_iterator MMOBegin,
                                  MachineInstr::mmo_iterator MMOEnd,
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned Alignment = std::max<uint32_t>(MRI.getSpillSize(RC), 16);
   bool isAligned = MMOBegin != MMOEnd &&
                    (*MMOBegin)->getAlignment() >= Alignment;
   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
   DebugLoc DL;
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
     MIB.addOperand(Addr[i]);
   (*MIB).setMemRefs(MMOBegin, MMOEnd);
if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
       bool HasMemoryOperand = Instr.hasOneMemOperand();
       unsigned NewOpc;
       if (Instr.isBranch())
         NewOpc = GetCondBranchFromCond(NewCC);
       else if(OpcIsSET)
         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
       else {
         unsigned DstReg = Instr.getOperand(0).getReg();
-        NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
+        const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
+        NewOpc = getCMovFromCond(NewCC, MRI->getSpillSize(DstRC),
                                  HasMemoryOperand);
       }
 
       // Push the MachineInstr to OpsToUpdate.
       // If it is safe to remove CmpInstr, the condition code of these
       // instructions will be modified.
       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
     }
case X86::VINSERTPSZrr:
     // Attempt to convert the load of inserted vector into a fold load
     // of a single float.
     if (OpNum == 2) {
       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
       unsigned ZMask = Imm & 15;
       unsigned DstIdx = (Imm >> 4) & 3;
       unsigned SrcIdx = (Imm >> 6) & 3;
 
-      unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
+      MachineRegisterInfo &MRI = MF.getRegInfo();
+      const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
+      unsigned RCSize = MRI.getSpillSize(RC);
       if (Size <= RCSize && 4 <= Align) {
         int PtrOffset = SrcIdx * 4;
         unsigned NewImm = (DstIdx << 4) | ZMask;
         unsigned NewOpCode =
             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
                                                     X86::INSERTPSrm;
         MachineInstr *NewMI =
             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
         return NewMI;
       }
     }
     break;
   case X86::MOVHLPSrr:
   case X86::VMOVHLPSrr:
   case X86::VMOVHLPSZrr:
     // Move the upper 64-bits of the second operand to the lower 64-bits.
     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
     if (OpNum == 2) {
-      unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
+      MachineRegisterInfo &MRI = MF.getRegInfo();
+      const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
+      unsigned RCSize = MRI.getSpillSize(RC);
       if (Size <= RCSize && 8 <= Align) {
         unsigned NewOpCode =
             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
                                                    X86::MOVLPSrm;
         MachineInstr *NewMI =
             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
         return NewMI;
if (OpcodeTablePtr) {
     auto I = OpcodeTablePtr->find(MI.getOpcode());
     if (I != OpcodeTablePtr->end()) {
       unsigned Opcode = I->second.first;
       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
       if (Align < MinAlign)
         return nullptr;
       bool NarrowToMOV32rm = false;
       if (Size) {
-        unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
+        MachineRegisterInfo &MRI = MF.getRegInfo();
+        const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
+                                                    &RI, MF);
+        unsigned RCSize = MRI.getSpillSize(RC);
         if (Size < RCSize) {
           // Check if it's safe to fold the load. If the size of the object is
           // narrower than the load width, then it's not.
           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
             return nullptr;
           // If this is a 64-bit load, but the spill slot is 32, then we can do
           // a 32-bit load which is implicitly zero-extended. This likely is
           // due to live interval analysis remat'ing a load from stack slot.

 /// ->
 ///   addss (%rdi), %xmm0
 ///
 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
                                              const MachineInstr &UserMI,
                                              const MachineFunction &MF) {
   unsigned Opc = LoadMI.getOpcode();
   unsigned UserOpc = UserMI.getOpcode();
-  unsigned RegSize =
-      MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const TargetRegisterClass *RC =
+      MRI.getRegClass(LoadMI.getOperand(0).getReg());
+  unsigned RegSize = MRI.getSpillSize(RC);
 
   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
       RegSize > 4) {
     // These instructions only load 32 bits, we can't fold them if the
     // destination register is wider than 32 bits (4 bytes), and its user
     // instruction isn't scalar (SS).
     switch (UserOpc) {
     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   if (I == MemOp2RegOpTable.end())
     return false;
   unsigned Opc = I->second.first;
   unsigned Index = I->second.second & TB_INDEX_MASK;
   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   const MCInstrDesc &MCID = get(Opc);
   MachineFunction &MF = DAG.getMachineFunction();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
   unsigned NumDefs = MCID.NumDefs;
   std::vector<SDValue> AddrOps;
   std::vector<SDValue> BeforeOps;
   std::vector<SDValue> AfterOps;
   SDLoc dl(N);
   unsigned NumOps = N->getNumOperands();
   for (unsigned i = 0; i != NumOps-1; ++i) {
std::pair<MachineInstr::mmo_iterator,
                             cast<MachineSDNode>(N)->memoperands_end());
     if (!(*MMOs.first) &&
         RC == &X86::VR128RegClass &&
         Subtarget.isUnalignedMem16Slow())
       // Do not introduce a slow unaligned load.
       return false;
     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
     // memory access is slow above.
-    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
+    unsigned Alignment = MRI.getSpillSize(RC) == 32 ? 32 : 16;
     bool isAligned = (*MMOs.first) &&
                      (*MMOs.first)->getAlignment() >= Alignment;
     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
                               VT, MVT::Other, AddrOps);
     NewNodes.push_back(Load);
 
     // Preserve memory reference information.
     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
std::pair<MachineInstr::mmo_iterator,
                              cast<MachineSDNode>(N)->memoperands_end());
     if (!(*MMOs.first) &&
         RC == &X86::VR128RegClass &&
         Subtarget.isUnalignedMem16Slow())
       // Do not introduce a slow unaligned store.
       return false;
     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
     // memory access is slow above.
-    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
+    unsigned Alignment = MRI.getSpillSize(RC) == 32 ? 32 : 16;
     bool isAligned = (*MMOs.first) &&
                      (*MMOs.first)->getAlignment() >= Alignment;
     SDNode *Store =
         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
                            dl, MVT::Other, AddrOps);
     NewNodes.push_back(Store);
 
     // Preserve memory reference information.

lib/Target/X86/X86RegisterInfo.cpp

X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
   //
   // The GR8_NOREX class is always used in a way that won't be constrained to a
   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
   // full GR8 class.
   if (RC == &X86::GR8_NOREXRegClass)
     return RC;
 
   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned RCSize = MRI.getSpillSize(RC);
 
   const TargetRegisterClass *Super = RC;
   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
   do {
+    unsigned SuperSize = MRI.getSpillSize(Super);
     switch (Super->getID()) {
     case X86::FR32RegClassID:
     case X86::FR64RegClassID:
       // If AVX-512 isn't supported we should only inflate to these classes.
-      if (!Subtarget.hasAVX512() && Super->getSize() == RC->getSize())
+      if (!Subtarget.hasAVX512() && SuperSize == RCSize)
         return Super;
       break;
     case X86::VR128RegClassID:
     case X86::VR256RegClassID:
       // If VLX isn't supported we should only inflate to these classes.
-      if (!Subtarget.hasVLX() && Super->getSize() == RC->getSize())
+      if (!Subtarget.hasVLX() && SuperSize == RCSize)
         return Super;
       break;
     case X86::FR32XRegClassID:
     case X86::FR64XRegClassID:
       // If VLX isn't support we shouldn't inflate to these classes.
       if (!Subtarget.hasVLX())
         break;
       // The VLX check above passed, AVX512 check below will pass.
do {
     case X86::GR32RegClassID:
     case X86::GR64RegClassID:
     case X86::RFP32RegClassID:
     case X86::RFP64RegClassID:
     case X86::RFP80RegClassID:
     case X86::VR512RegClassID:
       // Don't return a super-class that would shrink the spill size.
       // That can happen with the vector and float classes.
-      if (Super->getSize() == RC->getSize())
+      if (SuperSize == RCSize)
         return Super;
     }
     Super = *I++;
   } while (Super);
   return RC;
 }
 
 const TargetRegisterClass *

lib/Target/XCore/XCoreFrameLowering.cpp

if (hasFP(MF))
     XFI->createFPSpillSlot(MF);
 }
 
 void XCoreFrameLowering::
 processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                     RegScavenger *RS) const {
   assert(RS && "requiresRegisterScavenging failed");
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
   // Reserve slots close to SP or frame pointer for Scavenging spills.
   // When using SP for small frames, we don't need any scratch registers.
   // When using SP for large frames, we may need 2 scratch registers.
   // When using FP, for large or small frames, we may need 1 scratch register.
   if (XFI->isLargeFrame(MF) || hasFP(MF))
-    RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
-                                                      RC->getAlignment(),
+    RS->addScavengingFrameIndex(MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                                      MRI.getSpillAlignment(RC),
                                                       false));
   if (XFI->isLargeFrame(MF) && !hasFP(MF))
-    RS->addScavengingFrameIndex(MFI.CreateStackObject(RC->getSize(),
-                                                      RC->getAlignment(),
+    RS->addScavengingFrameIndex(MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                                      MRI.getSpillAlignment(RC),
                                                       false));
 }

lib/Target/XCore/XCoreISelLowering.cpp

 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
                                          const XCoreSubtarget &Subtarget)
     : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
 
   // Compute derived properties from the register classes
-  computeRegisterProperties(Subtarget.getRegisterInfo());
+  computeRegisterProperties(Subtarget);
 
   setStackPointerRegisterToSaveRestore(XCore::SP);
 
   setSchedulingPreference(Sched::Source);
 
   // Use i32 for setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?

lib/Target/XCore/XCoreMachineFunctionInfo.cpp

 //===-- XCoreMachineFunctionInfo.cpp - XCore machine function info --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "XCoreMachineFunctionInfo.h"
 #include "XCoreInstrInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/Function.h"
 
 using namespace llvm;
 
 void XCoreFunctionInfo::anchor() { }
 
 bool XCoreFunctionInfo::isLargeFrame(const MachineFunction &MF) const {
   if (CachedEStackSize == -1) {

 }
 
 int XCoreFunctionInfo::createLRSpillSlot(MachineFunction &MF) {
   if (LRSpillSlotSet) {
     return LRSpillSlot;
   }
   const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   if (! MF.getFunction()->isVarArg()) {
     // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
-    LRSpillSlot = MFI.CreateFixedObject(RC->getSize(), 0, true);
+    LRSpillSlot = MFI.CreateFixedObject(MRI.getSpillSize(RC), 0, true);
   } else {
-    LRSpillSlot = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
+    LRSpillSlot = MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                        MRI.getSpillAlignment(RC), true);
   }
   LRSpillSlotSet = true;
   return LRSpillSlot;
 }
 
 int XCoreFunctionInfo::createFPSpillSlot(MachineFunction &MF) {
   if (FPSpillSlotSet) {
     return FPSpillSlot;
   }
   const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  FPSpillSlot = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  FPSpillSlot = MFI.CreateStackObject(MRI.getSpillSize(RC),
+                                      MRI.getSpillAlignment(RC), true);
   FPSpillSlotSet = true;
   return FPSpillSlot;
 }
 
 const int* XCoreFunctionInfo::createEHSpillSlot(MachineFunction &MF) {
   if (EHSpillSlotSet) {
     return EHSpillSlot;
   }
   const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
   MachineFrameInfo &MFI = MF.getFrameInfo();
-  EHSpillSlot[0] = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
-  EHSpillSlot[1] = MFI.CreateStackObject(RC->getSize(), RC->getAlignment(), true);
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  unsigned Size = MRI.getSpillSize(RC), Align = MRI.getSpillAlignment(RC);
+  EHSpillSlot[0] = MFI.CreateStackObject(Size, Align, true);
+  EHSpillSlot[1] = MFI.CreateStackObject(Size, Align, true);
   EHSpillSlotSet = true;
   return EHSpillSlot;
 }