[AMDGPU] Stop using MCRegisterClass::getSize()

[kparzysz]

Summary

The register size determination will be implemented directly in TargetRegisterInfo, to support register classes with variable-sized registers. See D24631 for further discussion.

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

217

Space around /

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

I would prefer to add a new field in the register class than introducing more giant switches that need updates. Most of these register classes should be omitted also since only a handful are actually allocatable. VS_32RegClass for example is only used for operand constraints

[arsenm]

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

Besides the unallocatable point, I guess this isn't so bad right now. I think we're going to need to do something different in these cases anyway to support 16-bit immediates in a 32-bit register class

[arsenm]

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

Oh, this is looking directly at the operand class. In that case, you can remove all of the R600_* classes, VReg_1,and TTMP*

[kparzysz]

Removed unnecessary register classes from the switch statement.

Applied other inline comments.

[kparzysz]

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

Also removed SCC_CLASS. However I kept VS_32 and VS_64, even though they are not allocatable, because without VS_32 I had assertions in check-llvm.

[• tstellarAMD]

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

So will this function be replaced with a TargetRegisterInfo query in the future? That's my impression from the description in the summary.

[kparzysz]

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

231–233

No. Unfortunately, there is no TargetRegisterInfo available at the places where this function is used.

[kparzysz]

What do you think about this change, specifically, about moving the register size queries out of the MC layer?

Whether it's this patch or another one is not quite as important, but if we make a decision about that aspect, I will be able to move on with the implementation.

[kparzysz]

This is the context:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html

[kparzysz]

Ping.

[arsenm]

LGTM

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 // \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUInstPrinter.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
 #include "Utils/AMDGPUAsmUtils.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <string>
if (Op.isReg()) {
     default:
       printRegOperand(Op.getReg(), O, MRI);
       break;
     }
   } else if (Op.isImm()) {
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     int RCID = Desc.OpInfo[OpNo].RegClass;
     if (RCID != -1) {
-      const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
-      if (ImmRC.getSize() == 4)
+      unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
+      if (RCBits == 32)
         printImmediate32(Op.getImm(), O);
-      else if (ImmRC.getSize() == 8)
+      else if (RCBits == 64)
         printImmediate64(Op.getImm(), O);
       else
         llvm_unreachable("Invalid register class size");
     } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
       printImmediate32(Op.getImm(), O);
     } else {
       // We hit this for the immediate instruction bits that don't yet have a
       // custom printer.
       // TODO: Eventually this should be unnecessary.
       O << formatDec(Op.getImm());
     }
   } else if (Op.isFPImm()) {
     // We special case 0.0 because otherwise it will be printed as an integer.
     if (Op.getFPImm() == 0.0)
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
-      const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
-
-      if (ImmRC.getSize() == 4)
+      int RCID = Desc.OpInfo[OpNo].RegClass;
+      unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
+      if (RCBits == 32)
         printImmediate32(FloatToBits(Op.getFPImm()), O);
-      else if (ImmRC.getSize() == 8)
+      else if (RCBits == 64)
         printImmediate64(DoubleToBits(Op.getFPImm()), O);
       else
         llvm_unreachable("Invalid register class size");
     }
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O, &MAI);
   } else {

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
     if (!AMDGPU::isSISrcOperand(Desc, i))
       continue;
 
     int RCID = Desc.OpInfo[i].RegClass;
     const MCRegisterClass &RC = MRI.getRegClass(RCID);
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, RC.getSize(), STI) != 255)
+    if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC) / 8, STI) != 255)
       continue;
 
     // Yes! Encode it
     int64_t Imm = 0;
 
     if (Op.isImm())
       Imm = Op.getImm();
     else if (Op.isExpr()) {

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 
 namespace llvm {
 
 class FeatureBitset;
 class Function;
 class GlobalValue;
 class MCContext;
 class MCInstrDesc;
+class MCRegisterClass;
 class MCRegisterInfo;
 class MCSection;
 class MCSubtargetInfo;
 
 namespace AMDGPU {
 
 struct IsaVersion {
   unsigned Major;

 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// \brief Is this floating-point operand?
 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// \brief Does this opearnd support only inlinable literals?
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
+/// \brief Get the size in bits of a register from the register class \p RC.
+unsigned getRegBitWidth(const MCRegisterClass &RC);
+
 /// \brief Get size of register operand
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo);
 
 /// \brief Is this literal inlinable
 bool isInlinableLiteral64(int64_t Literal, bool IsVI);
 bool isInlinableLiteral32(int32_t Literal, bool IsVI);
 
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
   unsigned OpType = Desc.OpInfo[OpNo].OperandType;
 
   return OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
 }
 
+// Avoid using MCRegisterClass::getSize, since that function will go away
+// (move from MC* level to Target* level). Return size in bits.
+unsigned getRegBitWidth(const MCRegisterClass &RC) {
+  switch (RC.getID()) {
+  case AMDGPU::SGPR_32RegClassID:
+  case AMDGPU::VGPR_32RegClassID:
+  case AMDGPU::VS_32RegClassID:
+  case AMDGPU::SReg_32RegClassID:
+  case AMDGPU::SReg_32_XM0RegClassID:
+    return 32;
+  case AMDGPU::SGPR_64RegClassID:
+  case AMDGPU::VS_64RegClassID:
+  case AMDGPU::SReg_64RegClassID:
+  case AMDGPU::VReg_64RegClassID:
+    return 64;
+  case AMDGPU::VReg_96RegClassID:
+    return 96;
+  case AMDGPU::SGPR_128RegClassID:
+  case AMDGPU::SReg_128RegClassID:
+  case AMDGPU::VReg_128RegClassID:
+    return 128;
+  case AMDGPU::SReg_256RegClassID:
+  case AMDGPU::VReg_256RegClassID:
+    return 256;
+  case AMDGPU::SReg_512RegClassID:
+  case AMDGPU::VReg_512RegClassID:
+    return 512;
+  default:
+    llvm_unreachable("Unexpected register class");
+  }
+}
+
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo) {
-  int RCID = Desc.OpInfo[OpNo].RegClass;
-  const MCRegisterClass &RC = MRI->getRegClass(RCID);
-  return RC.getSize();
+  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
+  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
 }
 
 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
   if (Literal >= -16 && Literal <= 64)
     return true;
 
   double D = BitsToDouble(Literal);