[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

[dtcxzyw]

Summary

When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass RISCVDeadRegisterDefinitions. It rewrites rd to x0 when rd is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec

[craig.topper]

This also applies to volatile regular loads.

[dtcxzyw]

In D158759#4614563, @craig.topper wrote:

This also applies to volatile regular loads.

Indeed. But I could not find any pattern like lw\tzero in the GCC testsuite. Actually it also applies to sc.w/d and amocas.w/d/q. This pass doesn't handle them since they are not common.
Could you please show me some real-world examples?

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

409

Does this depend on DetectDeadLanes?

AArch64 has a pass called AArch64DeadRegisterDefinitions that is inserted in addPreRegAlloc.

[dtcxzyw]

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

409

Yes, it currently depends on DetectDeadLanes to mark dead defs.
AArch64DeadRegisterDefinitions is better than this implementation.
I will update the implementation soon. Thank you!

[dtcxzyw]

• Rebase
• Handle volatile loads

[reames]

At a macro level, this could be generalized to be target independent (as AArch64 also has a zero register), but I support generalizing this within RISCV first.

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

66

I don't think we need to worry about the reserved nops, as they won't have an MI representation will they? Unless we've implemented one, and we could just guard explicitly for the reserved nop cases?

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

400–403

If you place your new pass after InsertVSETVLI, you should be able to delete this block of code from that pass.

// Once we're fully done rewriting all the instructions, do a final pass
// through to check for VSETVLIs which write to an unused destination.
// For the non X0, X0 variant, we can replace the destination register
// with X0 to reduce register pressure.  This is really a generic
// optimization which can be applied to any dead def (TODO: generalize).
for (MachineBasicBlock &MBB : MF) {
  for (MachineInstr &MI : MBB) {
    if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
        MI.getOpcode() == RISCV::PseudoVSETIVLI) {
      Register VRegDef = MI.getOperand(0).getReg();
      if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))
        MI.getOperand(0).setReg(RISCV::X0);
    }
  }
}

llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll

1

Please go ahead and precommit the new test file so that we can see the change being made in this review.

[craig.topper]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

66

I think this was trying to prevent turning a regular instruction like add into a reserved nop encoding? If for some reason dead code elimination didn't already delete a dead add.

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

400–403

We'd have to remove the mayLoad check I think, but then we'd have to block changing PseudoVSETVLIX0?

[dtcxzyw]

• Rebase
• Handle computational instrs

[dtcxzyw]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

67

I cannot handle PseudoVSETVLI/PseudoVSETIVLI now since the diff is too large (about 300+ KLOCs with full context).
Could I remove this check after committing this patch?

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

12396 ↗

(On Diff #554599)

I don't know why DCE does not remove this dead instruction.

[dtcxzyw]

• Rebase on the top of pre-commit tests
• Drop curly braces

[craig.topper]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

67

If you're getting a lot of changes, it's probably a bug. It's not safe to change the destination to X0 for RISCV::PseudoVSETVLIX0 which is a different instruction than PseudoVSETVLI/PseudoVSETIVLI. Without an explicit check for it, that instruction it would be included.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

12396 ↗

(On Diff #554622)

I don't know why it didn't get removed either, but its not ok for this pass to change this instruction.

[reames]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

12396 ↗

(On Diff #554622)

It only became dead after InsertVSETVLI and we don't run DCE after that.

@craig.topper Why isn't this legal? If the instruction is dead, this does appear to be a valid instruction encoding? I don't see anything in the spec about addi zero, zero, imm being reserved or anything.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

12396 ↗

(On Diff #554622)

Isn't it one of the hint encodings? It won't crash, but it might cause unintended effects from hint. If it was an ORI it could be a non-temporal hint for example. If it was an AUIPC it would become a landing pad from the CFI proposal.

[asb]

This may not be much of an issue in practice, but I'd note that rewriting rd to x0 can sometimes result in a non-compressible instruction when previously it was compressible (e.g. rewriting loads).

I agree with the concern about this unwittingly introducing new HINT instructions. Although we expect instructions without side-effects that aren't caught elsewhere to be very rare, wouldn't it make sense to go ahead and delete them in this case? That said, I'm not sure our current modeling of CSR instructions would handle this properly for a theoretical architecture that had side-effecting CSR reads (e.g. a FIFO accessed via a CSR).

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

12396 ↗

(On Diff #554622)

Agreed this is undesirable for HINT instructions. These are standard RV32I instructions that do not alter architectural state, so of course very commonly have rd==x0.

[dtcxzyw]

• Rebase
• Skip computational instrs
• Handle PseudoVSETVLIs (related patch: D124961)

[dtcxzyw]

Ping.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

365

This looks like a regression

[dtcxzyw]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

365

It will be addressed by the following pass RISCVDeadRegisterDefinitions. This test only runs the pass RISCVInsertVSETVLI.

[craig.topper]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

93

Why are we using MRI->getRegClass instead of TII->getRegClass like AArch64?

[dtcxzyw]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

93

It protects defs with reg class GPRNoX0 being rewritten to x0.
See also https://reviews.llvm.org/D158759?id=554599#inline-1539364.
For inst li a3, 32, MRI->getRegClass returns GPRNoX0 while TTI->getRegClass returns GPR.

I have a separate patch to address this: https://github.com/llvm/llvm-project/pull/65934

[craig.topper]

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

93

Does the `!Desc.mayLoad() && !Desc.mayStore() &&

!Desc.hasUnmodeledSideEffects()` check already prevent that?

[dtcxzyw]

• Rebase
• Use TargetInstrInfo::getRegClass

[craig.topper]

LGTM

[dtcxzyw]

Rebase.

llvm/lib/Target/RISCV/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
 add_llvm_target(RISCVCodeGen
   RISCVAsmPrinter.cpp
   RISCVCodeGenPrepare.cpp
+  RISCVDeadRegisterDefinitions.cpp
   RISCVMakeCompressible.cpp
   RISCVExpandAtomicPseudoInsts.cpp
   RISCVExpandPseudoInsts.cpp
   RISCVFrameLowering.cpp
   RISCVGatherScatterLowering.cpp
   RISCVInsertVSETVLI.cpp
   RISCVInsertReadWriteCSR.cpp
   RISCVInstrInfo.cpp

llvm/lib/Target/RISCV/RISCV.h

 class PassRegistry;
 class RISCVRegisterBankInfo;
 class RISCVSubtarget;
 class RISCVTargetMachine;
 
 FunctionPass *createRISCVCodeGenPreparePass();
 void initializeRISCVCodeGenPreparePass(PassRegistry &);
 
+FunctionPass *createRISCVDeadRegisterDefinitionsPass();
+void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &);
+
 FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
                                  CodeGenOptLevel OptLevel);
 
 FunctionPass *createRISCVMakeCompressibleOptPass();
 void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
 
 FunctionPass *createRISCVGatherScatterLoweringPass();
 void initializeRISCVGatherScatterLoweringPass(PassRegistry &);

llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp

+//===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// This pass rewrites Rd to x0 for instrs whose return values are unused.
+//
+//===---------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+#define DEBUG_TYPE "riscv-dead-defs"
+#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
+
+STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
+
+namespace {
+class RISCVDeadRegisterDefinitions : public MachineFunctionPass {
+public:
+  static char ID;
+
+  RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {
+    initializeRISCVDeadRegisterDefinitionsPass(
+        *PassRegistry::getPassRegistry());
+  }
+  bool runOnMachineFunction(MachineFunction &MF) override;
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }
+};
+} // end anonymous namespace
+
+char RISCVDeadRegisterDefinitions::ID = 0;
+INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,
+                RISCV_DEAD_REG_DEF_NAME, false, false)
+
+FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() {
+  return new RISCVDeadRegisterDefinitions();
+}
+
+bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(MF.getFunction()))
+    return false;
+
+  const MachineRegisterInfo *MRI = &MF.getRegInfo();
+  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");
+
+  bool MadeChange = false;
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      // We only handle non-computational instructions since some NOP encodings
+      // are reserved for HINT instructions.
+      const MCInstrDesc &Desc = MI.getDesc();
+      if (!Desc.mayLoad() && !Desc.mayStore() &&
+          !Desc.hasUnmodeledSideEffects())
+        continue;
+      // For PseudoVSETVLIX0, Rd = X0 has special meaning.
+      if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
+        continue;
+      for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
+        MachineOperand &MO = MI.getOperand(I);
+        if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
+          continue;
+        // Be careful not to change the register if it's a tied operand.
+        if (MI.isRegTiedToUseOperand(I)) {
+          LLVM_DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
+          continue;
+        }
+        // We should not have any relevant physreg defs that are replacable by
+        // zero before register allocation. So we just check for dead vreg defs.
+        Register Reg = MO.getReg();
+        if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
+          continue;
+        LLVM_DEBUG(dbgs() << "    Dead def operand #" << I << " in:\n      ";
+                   MI.print(dbgs()));
+        const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
+        if (!(RC && RC->contains(RISCV::X0))) {
+          LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
+          continue;
+        }
+        MO.setReg(RISCV::X0);
+        MO.setIsDead();
+        LLVM_DEBUG(dbgs() << "    Replacing with zero register. New:\n      ";
+                   MI.print(dbgs()));
+        ++NumDeadDefsReplaced;
+        MadeChange = true;
+      }
+    }
+  }
+
+  return MadeChange;
+}

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   // DSE and peephole based demanded fields based transforms.  Note that
   // this *must* be done outside the main dataflow so long as we allow
   // any cross block analysis within the dataflow.  We can't have both
   // demanded fields based mutation and non-local analysis in the
   // dataflow at the same time without introducing inconsistencies.
   for (MachineBasicBlock &MBB : MF)
     doLocalPostpass(MBB);
 
-  // Once we're fully done rewriting all the instructions, do a final pass
-  // through to check for VSETVLIs which write to an unused destination.
-  // For the non X0, X0 variant, we can replace the destination register
-  // with X0 to reduce register pressure.  This is really a generic
-  // optimization which can be applied to any dead def (TODO: generalize).
-  for (MachineBasicBlock &MBB : MF) {
-    for (MachineInstr &MI : MBB) {
-      if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
-          MI.getOpcode() == RISCV::PseudoVSETIVLI) {
-        Register VRegDef = MI.getOperand(0).getReg();
-        if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))
-          MI.getOperand(0).setReg(RISCV::X0);
-      }
-    }
-  }
-
   // Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
   // of VLEFF/VLSEGFF.
   for (MachineBasicBlock &MBB : MF)
     insertReadVL(MBB);
 
   BlockInfo.clear();
   return HaveVectorOp;
 }
 
 /// Returns an instance of the Insert VSETVLI pass.
 FunctionPass *llvm::createRISCVInsertVSETVLIPass() {
   return new RISCVInsertVSETVLI();
 }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

cl::desc("Assume V extension vector registers are at least this big, "
              "autovectorization with fixed width vectors."),
     cl::init(-1), cl::Hidden);
 
 static cl::opt<bool> EnableRISCVCopyPropagation(
     "riscv-enable-copy-propagation",
     cl::desc("Enable the copy propagation with RISC-V copy instr"),
     cl::init(true), cl::Hidden);
 
+static cl::opt<bool> EnableRISCVDeadRegisterElimination(
+    "riscv-enable-dead-defs", cl::Hidden,
+    cl::desc("Enable the pass that removes dead"
+             " definitons and replaces stores to"
+             " them with stores to x0"),
+    cl::init(true));
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeKCFIPass(*PR);
+  initializeRISCVDeadRegisterDefinitionsPass(*PR);
   initializeRISCVMakeCompressibleOptPass(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVCodeGenPreparePass(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVOptWInstrsPass(*PR);
   initializeRISCVPreRAExpandPseudoPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
   initializeRISCVInsertVSETVLIPass(*PR);
if (TM->getTargetTriple().getArch() == Triple::riscv64) {
     addPass(createRISCVOptWInstrsPass());
   }
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
   addPass(createRISCVPreRAExpandPseudoPass());
   if (TM->getOptLevel() != CodeGenOptLevel::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());
+  if (TM->getOptLevel() != CodeGenOptLevel::None &&
+      EnableRISCVDeadRegisterElimination)
+    addPass(createRISCVDeadRegisterDefinitionsPass());
   addPass(createRISCVInsertReadWriteCSRPass());
 }
 
 void RISCVPassConfig::addOptimizedRegAlloc() {
   insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
 
   TargetPassConfig::addOptimizedRegAlloc();
 }
 
 void RISCVPassConfig::addFastRegAlloc() {
   addPass(createRISCVInitUndefPass());
   TargetPassConfig::addFastRegAlloc();
 }
 

llvm/test/CodeGen/RISCV/O3-pipeline.ll

 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       Machine Trace Metrics
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine InstCombiner
 ; RV64-NEXT:        RISC-V Optimize W Instructions
 ; CHECK-NEXT:       RISC-V Pre-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       RISC-V Merge Base Offset
 ; CHECK-NEXT:       RISC-V Insert VSETVLI pass
+; CHECK-NEXT:       RISC-V Dead register definitions
 ; CHECK-NEXT:       RISC-V Insert Read/Write CSR Pass
 ; CHECK-NEXT:       Detect Dead Lanes
 ; CHECK-NEXT:       RISC-V init undef pass
 ; CHECK-NEXT:       Process Implicit Definitions
 ; CHECK-NEXT:       Remove unreachable machine basic blocks
 ; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass

llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32 %s
 ; RUN: llc -O3 -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64 %s
 
 define void @amoswap_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amoswap_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amoswap.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amoswap.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoswap_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoswap.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoswap.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw xchg ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amoswap_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amoswap_d_discard:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a3, 5
 ; RV32-NEXT:    call __atomic_exchange_8@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoswap_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoswap.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoswap.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw xchg ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amoadd_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amoadd_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amoadd.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoadd_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoadd.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw add ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amoadd_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amoadd_d_discard:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a3, 5
 ; RV32-NEXT:    call __atomic_fetch_add_8@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoadd_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoadd.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoadd.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw add ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amoand_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amoand_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amoand.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoand_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoand.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amoand_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amoand_d_discard:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a3, 5
 ; RV32-NEXT:    call __atomic_fetch_and_8@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoand_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoand.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoand.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amoor_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amoor_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amoor.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoor_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoor.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amoor_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amoor_d_discard:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a3, 5
 ; RV32-NEXT:    call __atomic_fetch_or_8@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoor_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoor.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoor.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amoxor_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amoxor_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amoor.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoxor_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoor.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amoxor_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amoxor_d_discard:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    li a3, 5
 ; RV32-NEXT:    call __atomic_fetch_or_8@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amoxor_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amoor.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amoor.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amomax_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amomax_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amomax.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amomax.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomax_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomax.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomax.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw max ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amomax_d_discard:
 ; RV32:       # %bb.0:

 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomax_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomax.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomax.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw max ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amomaxu_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amomaxu_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amomaxu.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomaxu_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomaxu.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw umax ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amomaxu_d_discard:
 ; RV32:       # %bb.0:

 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomaxu_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomaxu.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomaxu.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw umax ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amomin_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amomin_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amomin.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amomin.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomin_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomin.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomin.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw min ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amomin_d_discard:
 ; RV32:       # %bb.0:

 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amomin_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amomin.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amomin.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw min ptr %a, i64 %b seq_cst
   ret void
 }
 
 define void @amominu_w_discard(ptr %a, i32 %b) nounwind {
 ; RV32-LABEL: amominu_w_discard:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    amominu.w.aqrl a0, a1, (a0)
+; RV32-NEXT:    amominu.w.aqrl zero, a1, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amominu_w_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amominu.w.aqrl a0, a1, (a0)
+; RV64-NEXT:    amominu.w.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw umin ptr %a, i32 %b seq_cst
   ret void
 }
 
 define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
 ; RV32-LABEL: amominu_d_discard:
 ; RV32:       # %bb.0:

 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: amominu_d_discard:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    amominu.d.aqrl a0, a1, (a0)
+; RV64-NEXT:    amominu.d.aqrl zero, a1, (a0)
 ; RV64-NEXT:    ret
   %1 = atomicrmw umin ptr %a, i64 %b seq_cst
   ret void
 }

llvm/test/CodeGen/RISCV/branch.ll

 ; RV32I-NEXT:    bge a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.8: # %test9
 ; RV32I-NEXT:    lw a3, 0(a1)
 ; RV32I-NEXT:    bltu a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.9: # %test10
 ; RV32I-NEXT:    lw a3, 0(a1)
 ; RV32I-NEXT:    bgeu a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.10: # %test11
-; RV32I-NEXT:    lw a0, 0(a1)
+; RV32I-NEXT:    lw zero, 0(a1)
 ; RV32I-NEXT:    andi a2, a2, 1
 ; RV32I-NEXT:    bnez a2, .LBB0_14
 ; RV32I-NEXT:  # %bb.11: # %test12
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    bgez a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.12: # %test13
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    blez a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.13: # %test14
-; RV32I-NEXT:    lw a0, 0(a1)
+; RV32I-NEXT:    lw zero, 0(a1)
 ; RV32I-NEXT:  .LBB0_14: # %end
 ; RV32I-NEXT:    ret
   %val1 = load volatile i32, ptr %b
   %tst1 = icmp eq i32 %val1, %a
   br i1 %tst1, label %end, label %test2
 
 test2:
   %val2 = load volatile i32, ptr %b

llvm/test/CodeGen/RISCV/double-mem.ll

 ; RV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: fld_fsd_global:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fadd.d a0, a0, a1
 ; RV64IZFINXZDINX-NEXT:    lui a1, %hi(G)
-; RV64IZFINXZDINX-NEXT:    ld a2, %lo(G)(a1)
+; RV64IZFINXZDINX-NEXT:    ld zero, %lo(G)(a1)
 ; RV64IZFINXZDINX-NEXT:    addi a2, a1, %lo(G)
 ; RV64IZFINXZDINX-NEXT:    sd a0, %lo(G)(a1)
-; RV64IZFINXZDINX-NEXT:    ld a1, 72(a2)
+; RV64IZFINXZDINX-NEXT:    ld zero, 72(a2)
 ; RV64IZFINXZDINX-NEXT:    sd a0, 72(a2)
 ; RV64IZFINXZDINX-NEXT:    ret
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
   %1 = fadd double %a, %b
   %2 = load volatile double, ptr @G
   store double %1, ptr @G
   %3 = getelementptr double, ptr @G, i32 9

llvm/test/CodeGen/RISCV/float-mem.ll

 ; CHECKIF-NEXT:    flw fa5, 36(a1)
 ; CHECKIF-NEXT:    fsw fa0, 36(a1)
 ; CHECKIF-NEXT:    ret
 ;
 ; CHECKIZFINX-LABEL: flw_fsw_global:
 ; CHECKIZFINX:       # %bb.0:
 ; CHECKIZFINX-NEXT:    fadd.s a0, a0, a1
 ; CHECKIZFINX-NEXT:    lui a1, %hi(G)
-; CHECKIZFINX-NEXT:    lw a2, %lo(G)(a1)
+; CHECKIZFINX-NEXT:    lw zero, %lo(G)(a1)
 ; CHECKIZFINX-NEXT:    addi a2, a1, %lo(G)
 ; CHECKIZFINX-NEXT:    sw a0, %lo(G)(a1)
-; CHECKIZFINX-NEXT:    lw a1, 36(a2)
+; CHECKIZFINX-NEXT:    lw zero, 36(a2)
 ; CHECKIZFINX-NEXT:    sw a0, 36(a2)
 ; CHECKIZFINX-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = load volatile float, ptr @G
   store float %1, ptr @G
   %3 = getelementptr float, ptr @G, i32 9
   %4 = load volatile float, ptr %3
   store float %1, ptr %3

llvm/test/CodeGen/RISCV/half-mem.ll

 ; CHECKIZFH-NEXT:    fsh fa0, 18(a1)
 ; CHECKIZFH-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: flh_fsh_global:
 ; CHECKIZHINX:       # %bb.0:
 ; CHECKIZHINX-NEXT:    fadd.h a0, a0, a1
 ; CHECKIZHINX-NEXT:    lui a1, %hi(G)
 ; CHECKIZHINX-NEXT:    addi a1, a1, %lo(G)
-; CHECKIZHINX-NEXT:    lh a2, 0(a1)
+; CHECKIZHINX-NEXT:    lh zero, 0(a1)
 ; CHECKIZHINX-NEXT:    sh a0, 0(a1)
 ; CHECKIZHINX-NEXT:    addi a1, a1, 18
-; CHECKIZHINX-NEXT:    lh a2, 0(a1)
+; CHECKIZHINX-NEXT:    lh zero, 0(a1)
 ; CHECKIZHINX-NEXT:    sh a0, 0(a1)
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: flh_fsh_global:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5

 ; CHECKIZHINXMIN-LABEL: flh_fsh_global:
 ; CHECKIZHINXMIN:       # %bb.0:
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; CHECKIZHINXMIN-NEXT:    fadd.s a0, a0, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; CHECKIZHINXMIN-NEXT:    lui a1, %hi(G)
 ; CHECKIZHINXMIN-NEXT:    addi a1, a1, %lo(G)
-; CHECKIZHINXMIN-NEXT:    lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT:    lh zero, 0(a1)
 ; CHECKIZHINXMIN-NEXT:    sh a0, 0(a1)
 ; CHECKIZHINXMIN-NEXT:    addi a1, a1, 18
-; CHECKIZHINXMIN-NEXT:    lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT:    lh zero, 0(a1)
 ; CHECKIZHINXMIN-NEXT:    sh a0, 0(a1)
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = load volatile half, ptr @G
   store half %1, ptr @G
   %3 = getelementptr half, ptr @G, i32 9
   %4 = load volatile half, ptr %3
   store half %1, ptr %3

llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 24
 ; RV32I-NEXT:    addi a0, a0, 1712
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    .cfi_def_cfa_offset 100016
 ; RV32I-NEXT:    lui a0, 24
 ; RV32I-NEXT:    addi a0, a0, 1704
 ; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lbu a1, 4(a0)
-; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    lbu zero, 4(a0)
+; RV32I-NEXT:    lbu zero, 0(a0)
 ; RV32I-NEXT:    lui a0, 24
 ; RV32I-NEXT:    addi a0, a0, 1712
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: use_frame_base_reg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 24
 ; RV64I-NEXT:    addiw a0, a0, 1712
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    .cfi_def_cfa_offset 100016
 ; RV64I-NEXT:    lui a0, 24
 ; RV64I-NEXT:    addiw a0, a0, 1704
 ; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    lbu a1, 4(a0)
-; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    lbu zero, 4(a0)
+; RV64I-NEXT:    lbu zero, 0(a0)
 ; RV64I-NEXT:    lui a0, 24
 ; RV64I-NEXT:    addiw a0, a0, 1712
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
 
   %va = alloca i8, align 4
   %va1 = alloca i8, align 4
   %large = alloca [ 100000 x i8 ]
   %argp.cur = load volatile i8, ptr %va, align 4
   %argp.next = load volatile i8, ptr %va1, align 4
   ret void
 }
 
 ; Test containing a load with its own local offset. Make sure isFrameOffsetLegal
 ; considers it and does not create a virtual base register.
 define void @load_with_offset() {
 ; RV32I-LABEL: load_with_offset:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 25
 ; RV32I-NEXT:    addi a0, a0, -1792
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    .cfi_def_cfa_offset 100608
 ; RV32I-NEXT:    lui a0, 25
 ; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lbu a0, -292(a0)
+; RV32I-NEXT:    lbu zero, -292(a0)
 ; RV32I-NEXT:    lui a0, 24
 ; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lbu a0, 1704(a0)
+; RV32I-NEXT:    lbu zero, 1704(a0)
 ; RV32I-NEXT:    lui a0, 25
 ; RV32I-NEXT:    addi a0, a0, -1792
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_with_offset:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 25
 ; RV64I-NEXT:    addiw a0, a0, -1792
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    .cfi_def_cfa_offset 100608
 ; RV64I-NEXT:    lui a0, 25
 ; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    lbu a0, -292(a0)
+; RV64I-NEXT:    lbu zero, -292(a0)
 ; RV64I-NEXT:    lui a0, 24
 ; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    lbu a0, 1704(a0)
+; RV64I-NEXT:    lbu zero, 1704(a0)
 ; RV64I-NEXT:    lui a0, 25
 ; RV64I-NEXT:    addiw a0, a0, -1792
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
 
   %va = alloca [100 x i8], align 4
   %va1 = alloca [500 x i8], align 4
   %large = alloca [100000 x i8]
   %va_gep = getelementptr [100 x i8], ptr %va, i64 16
   %va1_gep = getelementptr [100 x i8], ptr %va1, i64 0
   %load = load volatile i8, ptr %va_gep, align 4
   %load1 = load volatile i8, ptr %va1_gep, align 4
   ret void
 }

llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

 define void @test_lla(i32 signext %n) {
 ; RV32I-LABEL: test_lla:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:  .Lpcrel_hi0:
 ; RV32I-NEXT:    auipc a2, %pcrel_hi(l)
 ; RV32I-NEXT:  .LBB0_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
+; RV32I-NEXT:    lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    blt a1, a0, .LBB0_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_lla:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:  .Lpcrel_hi0:
 ; RV64I-NEXT:    auipc a2, %pcrel_hi(l)
 ; RV64I-NEXT:  .LBB0_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
+; RV64I-NEXT:    lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    blt a1, a0, .LBB0_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ret
 entry:
   br label %loop
 
 loop:

 ; RV32I-LABEL: test_la:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .Lpcrel_hi1:
 ; RV32I-NEXT:    auipc a1, %got_pcrel_hi(g)
 ; RV32I-NEXT:    lw a1, %pcrel_lo(.Lpcrel_hi1)(a1)
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:  .LBB1_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    lw a3, 0(a1)
+; RV32I-NEXT:    lw zero, 0(a1)
 ; RV32I-NEXT:    addi a2, a2, 1
 ; RV32I-NEXT:    blt a2, a0, .LBB1_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_la:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .Lpcrel_hi1:
 ; RV64I-NEXT:    auipc a1, %got_pcrel_hi(g)
 ; RV64I-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
 ; RV64I-NEXT:    li a2, 0
 ; RV64I-NEXT:  .LBB1_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    lw a3, 0(a1)
+; RV64I-NEXT:    lw zero, 0(a1)
 ; RV64I-NEXT:    addiw a2, a2, 1
 ; RV64I-NEXT:    blt a2, a0, .LBB1_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ret
 entry:
   br label %loop
 
 loop:

 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .Lpcrel_hi2:
 ; RV32I-NEXT:    auipc a1, %tls_ie_pcrel_hi(ie)
 ; RV32I-NEXT:    lw a2, %pcrel_lo(.Lpcrel_hi2)(a1)
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    add a2, a2, tp
 ; RV32I-NEXT:  .LBB2_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    lw a3, 0(a2)
+; RV32I-NEXT:    lw zero, 0(a2)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    blt a1, a0, .LBB2_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_la_tls_ie:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .Lpcrel_hi2:
 ; RV64I-NEXT:    auipc a1, %tls_ie_pcrel_hi(ie)
 ; RV64I-NEXT:    ld a2, %pcrel_lo(.Lpcrel_hi2)(a1)
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    add a2, a2, tp
 ; RV64I-NEXT:  .LBB2_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    lw a3, 0(a2)
+; RV64I-NEXT:    lw zero, 0(a2)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    blt a1, a0, .LBB2_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ret
 entry:
   br label %loop
 
 loop:

 ; RV32I-NEXT:    li s2, 0
 ; RV32I-NEXT:  .Lpcrel_hi3:
 ; RV32I-NEXT:    auipc a0, %tls_gd_pcrel_hi(gd)
 ; RV32I-NEXT:    addi s1, a0, %pcrel_lo(.Lpcrel_hi3)
 ; RV32I-NEXT:  .LBB3_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __tls_get_addr@plt
-; RV32I-NEXT:    lw a0, 0(a0)
+; RV32I-NEXT:    lw zero, 0(a0)
 ; RV32I-NEXT:    addi s2, s2, 1
 ; RV32I-NEXT:    blt s2, s0, .LBB3_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    li s2, 0
 ; RV64I-NEXT:  .Lpcrel_hi3:
 ; RV64I-NEXT:    auipc a0, %tls_gd_pcrel_hi(gd)
 ; RV64I-NEXT:    addi s1, a0, %pcrel_lo(.Lpcrel_hi3)
 ; RV64I-NEXT:  .LBB3_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    call __tls_get_addr@plt
-; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    lw zero, 0(a0)
 ; RV64I-NEXT:    addiw s2, s2, 1
 ; RV64I-NEXT:    blt s2, s0, .LBB3_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32

llvm/test/CodeGen/RISCV/mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; Check indexed and unindexed, sext, zext and anyext loads
 
 define dso_local i32 @lb(ptr %a) nounwind {
 ; RV32I-LABEL: lb:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lb a1, 1(a0)
-; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    lbu zero, 0(a0)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i32 1
   %2 = load i8, ptr %1
   %3 = sext i8 %2 to i32
   ; the unused load will produce an anyext for selection
   %4 = load volatile i8, ptr %a
   ret i32 %3
 }
 
 define dso_local i32 @lh(ptr %a) nounwind {
 ; RV32I-LABEL: lh:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lh a1, 4(a0)
-; RV32I-NEXT:    lh a0, 0(a0)
+; RV32I-NEXT:    lh zero, 0(a0)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i32 2
   %2 = load i16, ptr %1
   %3 = sext i16 %2 to i32
   ; the unused load will produce an anyext for selection
   %4 = load volatile i16, ptr %a
   ret i32 %3
 }
 
 define dso_local i32 @lw(ptr %a) nounwind {
 ; RV32I-LABEL: lw:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a1, 12(a0)
-; RV32I-NEXT:    lw a0, 0(a0)
+; RV32I-NEXT:    lw zero, 0(a0)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i32 3
   %2 = load i32, ptr %1
   %3 = load volatile i32, ptr %a
   ret i32 %2
 }
 

 }
 
 ; Check load and store to an i1 location
 define dso_local i32 @load_sext_zext_anyext_i1(ptr %a) nounwind {
 ; RV32I-LABEL: load_sext_zext_anyext_i1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 2(a0)
-; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    lbu zero, 0(a0)
 ; RV32I-NEXT:    sub a0, a2, a1
 ; RV32I-NEXT:    ret
   ; sextload i1
   %1 = getelementptr i1, ptr %a, i32 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i32
   ; zextload i1
   %4 = getelementptr i1, ptr %a, i32 2
   %5 = load i1, ptr %4
   %6 = zext i1 %5 to i32
   %7 = add i32 %3, %6
   ; extload i1 (anyext). Produced as the load is unused.
   %8 = load volatile i1, ptr %a
   ret i32 %7
 }
 
 define dso_local i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
 ; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 2(a0)
-; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    lbu zero, 0(a0)
 ; RV32I-NEXT:    sub a0, a2, a1
 ; RV32I-NEXT:    ret
   ; sextload i1
   %1 = getelementptr i1, ptr %a, i32 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i16
   ; zextload i1
   %4 = getelementptr i1, ptr %a, i32 2

 
 define dso_local i32 @lw_sw_global(i32 %a) nounwind {
 ; RV32I-LABEL: lw_sw_global:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, %hi(G)
 ; RV32I-NEXT:    lw a1, %lo(G)(a2)
 ; RV32I-NEXT:    addi a3, a2, %lo(G)
 ; RV32I-NEXT:    sw a0, %lo(G)(a2)
-; RV32I-NEXT:    lw a2, 36(a3)
+; RV32I-NEXT:    lw zero, 36(a3)
 ; RV32I-NEXT:    sw a0, 36(a3)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
   %1 = load volatile i32, ptr @G
   store i32 %a, ptr @G
   %2 = getelementptr i32, ptr @G, i32 9
   %3 = load volatile i32, ptr %2
   store i32 %a, ptr %2

llvm/test/CodeGen/RISCV/mem64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; Check indexed and unindexed, sext, zext and anyext loads
 
 define dso_local i64 @lb(ptr %a) nounwind {
 ; RV64I-LABEL: lb:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lb a1, 1(a0)
-; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    lbu zero, 0(a0)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i32 1
   %2 = load i8, ptr %1
   %3 = sext i8 %2 to i64
   ; the unused load will produce an anyext for selection
   %4 = load volatile i8, ptr %a
   ret i64 %3
 }
 
 define dso_local i64 @lh(ptr %a) nounwind {
 ; RV64I-LABEL: lh:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lh a1, 4(a0)
-; RV64I-NEXT:    lh a0, 0(a0)
+; RV64I-NEXT:    lh zero, 0(a0)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i32 2
   %2 = load i16, ptr %1
   %3 = sext i16 %2 to i64
   ; the unused load will produce an anyext for selection
   %4 = load volatile i16, ptr %a
   ret i64 %3
 }
 
 define dso_local i64 @lw(ptr %a) nounwind {
 ; RV64I-LABEL: lw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a1, 12(a0)
-; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    lw zero, 0(a0)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i32 3
   %2 = load i32, ptr %1
   %3 = sext i32 %2 to i64
   ; the unused load will produce an anyext for selection
   %4 = load volatile i32, ptr %a
   ret i64 %3

 }
 
 ; 64-bit loads and stores
 
 define dso_local i64 @ld(ptr %a) nounwind {
 ; RV64I-LABEL: ld:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ld a1, 80(a0)
-; RV64I-NEXT:    ld a0, 0(a0)
+; RV64I-NEXT:    ld zero, 0(a0)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = getelementptr i64, ptr %a, i32 10
   %2 = load i64, ptr %1
   %3 = load volatile i64, ptr %a
   ret i64 %2
 }
 

 }
 
 ; Check load and store to an i1 location
 define dso_local i64 @load_sext_zext_anyext_i1(ptr %a) nounwind {
 ; RV64I-LABEL: load_sext_zext_anyext_i1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 2(a0)
-; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    lbu zero, 0(a0)
 ; RV64I-NEXT:    sub a0, a2, a1
 ; RV64I-NEXT:    ret
   ; sextload i1
   %1 = getelementptr i1, ptr %a, i32 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i64
   ; zextload i1
   %4 = getelementptr i1, ptr %a, i32 2
   %5 = load i1, ptr %4
   %6 = zext i1 %5 to i64
   %7 = add i64 %3, %6
   ; extload i1 (anyext). Produced as the load is unused.
   %8 = load volatile i1, ptr %a
   ret i64 %7
 }
 
 define dso_local i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
 ; RV64I-LABEL: load_sext_zext_anyext_i1_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 2(a0)
-; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    lbu zero, 0(a0)
 ; RV64I-NEXT:    sub a0, a2, a1
 ; RV64I-NEXT:    ret
   ; sextload i1
   %1 = getelementptr i1, ptr %a, i32 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i16
   ; zextload i1
   %4 = getelementptr i1, ptr %a, i32 2

 
 define dso_local i64 @ld_sd_global(i64 %a) nounwind {
 ; RV64I-LABEL: ld_sd_global:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, %hi(G)
 ; RV64I-NEXT:    ld a1, %lo(G)(a2)
 ; RV64I-NEXT:    addi a3, a2, %lo(G)
 ; RV64I-NEXT:    sd a0, %lo(G)(a2)
-; RV64I-NEXT:    ld a2, 72(a3)
+; RV64I-NEXT:    ld zero, 72(a3)
 ; RV64I-NEXT:    sd a0, 72(a3)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = load volatile i64, ptr @G
   store i64 %a, ptr @G
   %2 = getelementptr i64, ptr @G, i64 9
   %3 = load volatile i64, ptr %2
   store i64 %a, ptr %2

llvm/test/CodeGen/RISCV/rvv/localvar.ll

 ; RV64IV-LABEL: local_var_m2_mix_local_scalar:
 ; RV64IV:       # %bb.0:
 ; RV64IV-NEXT:    addi sp, sp, -16
 ; RV64IV-NEXT:    .cfi_def_cfa_offset 16
 ; RV64IV-NEXT:    csrr a0, vlenb
 ; RV64IV-NEXT:    slli a0, a0, 2
 ; RV64IV-NEXT:    sub sp, sp, a0
 ; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
-; RV64IV-NEXT:    lw a0, 12(sp)
+; RV64IV-NEXT:    lw zero, 12(sp)
 ; RV64IV-NEXT:    csrr a0, vlenb
 ; RV64IV-NEXT:    slli a0, a0, 1
 ; RV64IV-NEXT:    add a0, sp, a0
 ; RV64IV-NEXT:    addi a0, a0, 16
 ; RV64IV-NEXT:    vl2r.v v8, (a0)
 ; RV64IV-NEXT:    addi a0, sp, 16
 ; RV64IV-NEXT:    vl2r.v v8, (a0)
-; RV64IV-NEXT:    lw a0, 8(sp)
+; RV64IV-NEXT:    lw zero, 8(sp)
 ; RV64IV-NEXT:    csrr a0, vlenb
 ; RV64IV-NEXT:    slli a0, a0, 2
 ; RV64IV-NEXT:    add sp, sp, a0
 ; RV64IV-NEXT:    addi sp, sp, 16
 ; RV64IV-NEXT:    ret
   %local_scalar0 = alloca i32
   %local0 = alloca <vscale x 16 x i8>
   %local1 = alloca <vscale x 16 x i8>

 ; RV64IV-NEXT:    slli a2, a2, 1
 ; RV64IV-NEXT:    add a2, s1, a2
 ; RV64IV-NEXT:    addi a2, a2, 224
 ; RV64IV-NEXT:    csrr s2, vlenb
 ; RV64IV-NEXT:    slli s2, s2, 1
 ; RV64IV-NEXT:    add s2, s1, s2
 ; RV64IV-NEXT:    addi s2, s2, 224
 ; RV64IV-NEXT:    call notdead2@plt
-; RV64IV-NEXT:    lw a0, 124(s1)
+; RV64IV-NEXT:    lw zero, 124(s1)
 ; RV64IV-NEXT:    vl2r.v v8, (s2)
 ; RV64IV-NEXT:    addi a0, s1, 224
 ; RV64IV-NEXT:    vl2r.v v8, (a0)
-; RV64IV-NEXT:    lw a0, 120(s1)
+; RV64IV-NEXT:    lw zero, 120(s1)
 ; RV64IV-NEXT:    addi sp, s0, -256
 ; RV64IV-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
 ; RV64IV-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
 ; RV64IV-NEXT:    ld s1, 232(sp) # 8-byte Folded Reload
 ; RV64IV-NEXT:    ld s2, 224(sp) # 8-byte Folded Reload
 ; RV64IV-NEXT:    addi sp, sp, 256
 ; RV64IV-NEXT:    ret
   %1 = alloca i8, i64 %n

llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll

 ; CHECK-NEXT:    vl1re64.v v8, (a2)
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 2
 ; CHECK-NEXT:    sub a2, s0, a2
 ; CHECK-NEXT:    addi a2, a2, -32
 ; CHECK-NEXT:    vl2re64.v v8, (a2)
 ; CHECK-NEXT:    slli a1, a1, 2
 ; CHECK-NEXT:    add a0, a0, a1
-; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    lw zero, 0(a0)
 ; CHECK-NEXT:    addi sp, s0, -32
 ; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %vla.addr = alloca i32, i64 %n
 
   %v1.addr = alloca <vscale x 1 x i64>

 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a1, a0, 1
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 112
 ; CHECK-NEXT:    vl1re64.v v8, (a0)
 ; CHECK-NEXT:    addi a0, sp, 112
 ; CHECK-NEXT:    vl2re64.v v8, (a0)
-; CHECK-NEXT:    lw a0, 64(sp)
+; CHECK-NEXT:    lw zero, 64(sp)
 ; CHECK-NEXT:    addi sp, s0, -128
 ; CHECK-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 128
 ; CHECK-NEXT:    ret
   %overaligned = alloca i32, align 64
 
   %v1.addr = alloca <vscale x 1 x i64>

 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a3, a2, 1
 ; CHECK-NEXT:    add a2, a3, a2
 ; CHECK-NEXT:    add a2, s1, a2
 ; CHECK-NEXT:    addi a2, a2, 112
 ; CHECK-NEXT:    vl1re64.v v8, (a2)
 ; CHECK-NEXT:    addi a2, s1, 112
 ; CHECK-NEXT:    vl2re64.v v8, (a2)
-; CHECK-NEXT:    lw a2, 64(s1)
+; CHECK-NEXT:    lw zero, 64(s1)
 ; CHECK-NEXT:    slli a1, a1, 2
 ; CHECK-NEXT:    add a0, a0, a1
-; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    lw zero, 0(a0)
 ; CHECK-NEXT:    addi sp, s0, -144
 ; CHECK-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s1, 120(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 144
 ; CHECK-NEXT:    ret
   %overaligned = alloca i32, align 64
   %vla.addr = alloca i32, i64 %n

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc %s -o - -mtriple=riscv64 -mattr=v \
 # RUN:     -run-pass=riscv-insert-vsetvli | FileCheck %s
 
 --- |
-  ; ModuleID = 'vsetvli-insert.ll'
   source_filename = "vsetvli-insert.ll"
   target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
   target triple = "riscv64"
 
   define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
   entry:
     %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2)
     %tobool = icmp eq i8 %cond, 0
if.else:                                          ; preds = %entry
     br label %if.end
 
   if.end:                                           ; preds = %if.else, %if.then
     %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
     call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, <vscale x 1 x i64>* %1, i64 %2)
     ret void
   }
 
-  ; Function Attrs: nounwind readnone
   declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
 
   define i64 @vmv_x_s(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
   entry:
     %tobool = icmp eq i8 %cond, 0
     br i1 %tobool, label %if.else, label %if.then
 
   if.then:                                          ; preds = %entry
     %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
     br label %if.end
 
   if.else:                                          ; preds = %entry
     %b = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %1, i64 %2)
     br label %if.end
 
   if.end:                                           ; preds = %if.else, %if.then
     %c = phi <vscale x 1 x i64> [ %a, %if.then ], [ %b, %if.else ]
     %d = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %c)
     ret i64 %d
   }
 
-  ; Function Attrs: nounwind
   declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #2
 
   define <vscale x 1 x i64> @vsetvli_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
   entry:
     %vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
     %tobool = icmp eq i8 %cond, 0
     br i1 %tobool, label %if.else, label %if.then
 
--- |
   define void @vsetvli_vluxei64_regression() {
     ret void
   }
 
   define void @if_in_loop() {
     ret void
   }
 
-  ; Function Attrs: nofree nosync nounwind readnone willreturn
   declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
 
-  ; Function Attrs: nounwind readnone
   declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
 
-  ; Function Attrs: nounwind readnone
   declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
 
-  ; Function Attrs: nounwind readonly
   declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #3
 
-  ; Function Attrs: nounwind readonly
   declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #3
 
-  ; Function Attrs: nounwind writeonly
   declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
 
-  ; Function Attrs: nounwind readnone
   declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
 
-  ; Function Attrs: nounwind readnone
   declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
 
   attributes #0 = { "target-features"="+v" }
   attributes #1 = { nounwind readnone }
   attributes #2 = { nounwind }
   attributes #3 = { nounwind readonly }
   attributes #4 = { nounwind writeonly }
 
body:             |
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; CHECK-NEXT:   liveins: $x10, $v8, $v9, $x11
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr = COPY $v9
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vr = COPY $v8
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr = COPY $x10
-  ; CHECK-NEXT:   $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+  ; CHECK-NEXT:   [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr = COPY $x0
   ; CHECK-NEXT:   BEQ [[COPY3]], [[COPY4]], %bb.2
   ; CHECK-NEXT:   PseudoBR %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.if.then:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   %pt:vr = IMPLICIT_DEF

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

bb.0.entry:
     liveins: $v8, $v9, $x10
 
     ; CHECK-LABEL: name: vsetvli_add
     ; CHECK: liveins: $v8, $v9, $x10
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
-    ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+    ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
     ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
     ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
     ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
     ; CHECK-NEXT: PseudoRET implicit $v8
     %2:gprnox0 = COPY $x10
     %1:vr = COPY $v9
     %0:vr = COPY $v8
     %3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype