[RFC][GlobalISel] Remove const from most MatchTableExecutor methods

[Pierre-vh]

Summary

It's an internal API, there is no need to have const functions.
We often unintentionally work around constness anyway by using T& data members which can be modified in const functions.

[Pierre-vh]

Additional context: While refactoring this area for some upcoming diffs (removing the deprecated GICombiner backend), I changed some data members from T& to T and got a lot of errors due to this.
While I usually favor const-correctness as much as possible, it's really never respected here. We always use references or pointers, which means we can always call non-const functions on those even in a const function.

Example:

struct Foo {
    int foo() {
        return 0;
    }
};

struct Bar {
    Foo &F;
    void bar() const {
        F.foo();
    }
};

So there's two solutions, the first one is for me to use mutable whenever I run into a case like this when refactoring, or we can just eliminate const where it doesn't make sense.
I'm fine with both, but I think it's cleaner to just eliminate these "fake const" that don't really guarantee anything in terms of semantics. Hence why this diff is a RFC.
e.g. we constantly mutate state - directly or indirectly - in those functions through the MIR builder, MRI, Observers, etc.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

102

I'm not seeing the context how this helps. I think things should be kept const, especially since all the others here are

[arsenm]

In D158598#4609625, @Pierre-vh wrote:

Additional context: While refactoring this area for some upcoming diffs (removing the deprecated GICombiner backend), I changed some data members from T& to T and got a lot of errors due to this.
While I usually favor const-correctness as much as possible, it's really never respected here. We always use references or pointers, which means we can always call non-const functions on those even in a const function.

Example:

struct Foo {
    int foo() {
        return 0;
    }
};

The foo here would just have to be const? don't see the issue

[Pierre-vh]

In D158598#4611871, @arsenm wrote:

In D158598#4609625, @Pierre-vh wrote:

Additional context: While refactoring this area for some upcoming diffs (removing the deprecated GICombiner backend), I changed some data members from T& to T and got a lot of errors due to this.
While I usually favor const-correctness as much as possible, it's really never respected here. We always use references or pointers, which means we can always call non-const functions on those even in a const function.

Example:

struct Foo {
    int foo() {
        return 0;
    }
};

The foo here would just have to be const? don't see the issue

It's a trivial example, in most cases we'd be calling CombinerHelper functions or GlobalISelObserver functions.
I'll double check if I can make the offending function consts, and keep mutable around for now. I'll come back to this if I still think it makes sense afterwards

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
             class CustomRendererFn>
   bool executeMatchTable(
       TgtExecutor &Exec, NewMIVector &OutMIs, MatcherState &State,
       const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
           &ISelInfo,
       const int64_t *MatchTable, const TargetInstrInfo &TII,
       MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
       const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
-      CodeGenCoverage *CoverageInfo,
-      GISelChangeObserver *Observer = nullptr) const;
+      CodeGenCoverage *CoverageInfo, GISelChangeObserver *Observer = nullptr);
 
   virtual const int64_t *getMatchTable() const {
     llvm_unreachable("Should have been overridden by tablegen if used");
   }
 
-  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
+  virtual bool testImmPredicate_I64(unsigned, int64_t) {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
-  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
+  virtual bool testImmPredicate_APInt(unsigned, const APInt &) {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
-  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
+  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
   virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
-                                  const MatcherState &State) const {
+                                  const MatcherState &State) {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
 
-  virtual bool testSimplePredicate(unsigned) const {
+  virtual bool testSimplePredicate(unsigned) {
     llvm_unreachable("Subclass does not implement testSimplePredicate!");
   }
 
   virtual void runCustomAction(unsigned, const MatcherState &State,
-                               NewMIVector &OutMIs) const {
+                               NewMIVector &OutMIs) {
     llvm_unreachable("Subclass does not implement runCustomAction!");
   }
 
   bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
                          const MachineRegisterInfo &MRI,
                          bool Splat = false) const;
 
   /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
           class CustomRendererFn>
 bool GIMatchTableExecutor::executeMatchTable(
     TgtExecutor &Exec, NewMIVector &OutMIs, MatcherState &State,
     const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
         &ExecInfo,
     const int64_t *MatchTable, const TargetInstrInfo &TII,
     MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
     const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
-    CodeGenCoverage *CoverageInfo, GISelChangeObserver *Observer) const {
+    CodeGenCoverage *CoverageInfo, GISelChangeObserver *Observer) {
 
   uint64_t CurrentIdx = 0;
   SmallVector<uint64_t, 4> OnFailResumeAt;
 
   // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
   bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
 
   const uint16_t Flags = State.MIs[0]->getFlags();

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

void setupMF(MachineFunction &MF, GISelKnownBits *KB,
     MFReturnAddr = Register();
 
     processPHIs(MF);
   }
 
 private:
   /// tblgen-erated 'select' implementation, used as the initial selector for
   /// the patterns that don't require complex C++.
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   // A lowering phase that runs before any selection attempts.
   // Returns true if the instruction was modified.
   bool preISelLower(MachineInstr &I);
 
   // An early selection function that runs before the selectImpl() call.
   bool earlySelect(MachineInstr &I);
 

llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp

 public:
   AArch64O0PreLegalizerCombinerImpl(
       const AArch64O0PreLegalizerCombinerImplRuleConfig &RuleConfig,
       GISelChangeObserver &Observer, MachineIRBuilder &B,
       CombinerHelper &Helper);
 
   static const char *getName() { return "AArch64O0PreLegalizerCombiner"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
 #include "AArch64GenO0PreLegalizeGICombiner.inc"
 #undef GET_GICOMBINER_CLASS_MEMBERS
 };
 
 #define GET_GICOMBINER_IMPL

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

 public:
   AArch64PostLegalizerCombinerImpl(
       const AArch64PostLegalizerCombinerImplRuleConfig &RuleConfig,
       const AArch64Subtarget &STI, GISelChangeObserver &Observer,
       MachineIRBuilder &B, CombinerHelper &Helper);
 
   static const char *getName() { return "AArch64PostLegalizerCombiner"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
 #include "AArch64GenPostLegalizeGICombiner.inc"
 #undef GET_GICOMBINER_CLASS_MEMBERS
 };
 
 #define GET_GICOMBINER_IMPL

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

 public:
   AArch64PostLegalizerLoweringImpl(
       const AArch64PostLegalizerLoweringImplRuleConfig &RuleConfig,
       const AArch64Subtarget &STI, GISelChangeObserver &Observer,
       MachineIRBuilder &B, CombinerHelper &Helper);
 
   static const char *getName() { return "AArch6400PreLegalizerCombiner"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
 #include "AArch64GenPostLegalizeGILowering.inc"
 #undef GET_GICOMBINER_CLASS_MEMBERS
 };
 
 #define GET_GICOMBINER_IMPL

llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp

 public:
   AArch64PreLegalizerCombinerImpl(
       const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig,
       const AArch64Subtarget &STI, GISelChangeObserver &Observer,
       MachineIRBuilder &B, CombinerHelper &Helper);
 
   static const char *getName() { return "AArch6400PreLegalizerCombiner"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
 #include "AArch64GenPreLegalizeGICombiner.inc"
 #undef GET_GICOMBINER_CLASS_MEMBERS
 };
 
 #define GET_GICOMBINER_IMPL

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
   bool isInstrUniform(const MachineInstr &MI) const;
   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
 
   const RegisterBank *getArtifactRegBank(
     Register Reg, const MachineRegisterInfo &MRI,
     const TargetRegisterInfo &TRI) const;
 
   /// tblgen-erated 'select' implementation.
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   MachineOperand getSubOperand64(MachineOperand &MO,
                                  const TargetRegisterClass &SubRC,
                                  unsigned SubIdx) const;
 
   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectPHI(MachineInstr &I) const;
   bool selectG_TRUNC(MachineInstr &I) const;
   bool selectG_SZA_EXT(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_FNEG(MachineInstr &I) const;
   bool selectG_FABS(MachineInstr &I) const;
   bool selectG_AND_OR_XOR(MachineInstr &I) const;
   bool selectG_ADD_SUB(MachineInstr &I) const;
   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
   bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
   bool selectG_EXTRACT(MachineInstr &I) const;
   bool selectG_FMA_FMAD(MachineInstr &I) const;
-  bool selectG_MERGE_VALUES(MachineInstr &I) const;
+  bool selectG_MERGE_VALUES(MachineInstr &I);
   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
-  bool selectG_BUILD_VECTOR(MachineInstr &I) const;
+  bool selectG_BUILD_VECTOR(MachineInstr &I);
   bool selectG_PTR_ADD(MachineInstr &I) const;
   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
   bool selectG_INSERT(MachineInstr &I) const;
   bool selectG_SBFX_UBFX(MachineInstr &I) const;
 
-  bool selectInterpP1F16(MachineInstr &MI) const;
-  bool selectWritelane(MachineInstr &MI) const;
+  bool selectInterpP1F16(MachineInstr &MI);
+  bool selectWritelane(MachineInstr &MI);
   bool selectDivScale(MachineInstr &MI) const;
   bool selectIntrinsicCmp(MachineInstr &MI) const;
   bool selectBallot(MachineInstr &I) const;
   bool selectInverseBallot(MachineInstr &I) const;
   bool selectRelocConstant(MachineInstr &I) const;
   bool selectGroupStaticSize(MachineInstr &I) const;
   bool selectReturnAddress(MachineInstr &I) const;
-  bool selectG_INTRINSIC(MachineInstr &I) const;
+  bool selectG_INTRINSIC(MachineInstr &I);
 
   bool selectEndCfIntrinsic(MachineInstr &MI) const;
   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
-  bool selectSBarrier(MachineInstr &MI) const;
+  bool selectSBarrier(MachineInstr &MI);
   bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
 
   bool selectImageIntrinsic(MachineInstr &MI,
                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
-  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
+  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I);
   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
   bool selectG_ICMP(MachineInstr &I) const;
   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
 
   void initM0(MachineInstr &I) const;
-  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
-  bool selectG_SELECT(MachineInstr &I) const;
+  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I);
+  bool selectG_SELECT(MachineInstr &I);
   bool selectG_BRCOND(MachineInstr &I) const;
   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
   bool selectG_PTRMASK(MachineInstr &I) const;
   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
   bool selectBufferLoadLds(MachineInstr &MI) const;
   bool selectGlobalLoadLds(MachineInstr &MI) const;
   bool selectBVHIntrinsic(MachineInstr &I) const;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
   const DebugLoc &DL = I.getDebugLoc();
   BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY), DstReg)
     .addReg(SrcReg, 0, SubReg);
 
   I.eraseFromParent();
   return true;
 }
 
-bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
+bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) {
   MachineBasicBlock *BB = MI.getParent();
   Register DstReg = MI.getOperand(0).getReg();
   LLT DstTy = MRI->getType(DstReg);
   LLT SrcTy = MRI->getType(MI.getOperand(1).getReg());
 
   const unsigned SrcSize = SrcTy.getSizeInBits();
   if (SrcSize < 32)
     return selectImpl(MI, *CoverageInfo);
for (int I = 0, E = NumDst; I != E; ++I) {
     if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
       return false;
   }
 
   MI.eraseFromParent();
   return true;
 }
 
-bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
+bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) {
   assert(MI.getOpcode() == AMDGPU::G_BUILD_VECTOR_TRUNC ||
          MI.getOpcode() == AMDGPU::G_BUILD_VECTOR);
 
   Register Src0 = MI.getOperand(1).getReg();
   Register Src1 = MI.getOperand(2).getReg();
   LLT SrcTy = MRI->getType(Src0);
   const unsigned SrcSize = SrcTy.getSizeInBits();
 
bool AMDGPUInstructionSelector::selectG_SBFX_UBFX(MachineInstr &MI) const {
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg)
                  .addReg(SrcReg)
                  .addReg(OffsetReg)
                  .addReg(WidthReg);
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 }
 
-bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) const {
+bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) {
   if (STI.getLDSBankCount() != 16)
     return selectImpl(MI, *CoverageInfo);
 
   Register Dst = MI.getOperand(0).getReg();
   Register Src0 = MI.getOperand(2).getReg();
   Register M0Val = MI.getOperand(6).getReg();
   if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) ||
       !RBI.constrainGenericRegister(Dst, AMDGPU::VGPR_32RegClass, *MRI) ||
bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) {
   return true;
 }
 
 // Writelane is special in that it can use SGPR and M0 (which would normally
 // count as using the constant bus twice - but in this case it is allowed since
 // the lane selector doesn't count as a use of the constant bus). However, it is
 // still required to abide by the 1 SGPR rule. Fix this up if we might have
 // multiple SGPRs.
-bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) const {
+bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) {
   // With a constant bus limit of at least 2, there's no issue.
   if (STI.getConstantBusLimit(AMDGPU::V_WRITELANE_B32) > 1)
     return selectImpl(MI, *CoverageInfo);
 
   MachineBasicBlock *MBB = MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
   Register VDst = MI.getOperand(0).getReg();
   Register Val = MI.getOperand(2).getReg();
auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
     .addUse(Numer) // $src2
     .addImm(0)     // $clamp
     .addImm(0);    // $omod
 
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 }
 
-bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
+bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) {
   unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
   switch (IntrinsicID) {
   case Intrinsic::amdgcn_if_break: {
     MachineBasicBlock *BB = I.getParent();
 
     // FIXME: Manually selecting to avoid dealing with the SReg_1 trick
     // SelectionDAG uses for wave32 vs wave64.
     BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg())
     .addImm(Offset)
     .addImm(IsGDS ? -1 : 0)
     .cloneMemRefs(MI);
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 }
 
-bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) const {
+bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) {
   if (TM.getOptLevel() > CodeGenOpt::None) {
     unsigned WGSize = STI.getFlatWorkGroupSizes(MF->getFunction()).second;
     if (WGSize <= STI.getWavefrontSize()) {
       MachineBasicBlock *MBB = MI.getParent();
       const DebugLoc &DL = MI.getDebugLoc();
       BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::WAVE_BARRIER));
       MI.eraseFromParent();
       return true;
auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_BVH_STACK_RTN_B32), Dst0)
                  .addImm(Offset)
                  .cloneMemRefs(MI);
 
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
 }
 
 bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
-    MachineInstr &I) const {
+    MachineInstr &I) {
   unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
   switch (IntrinsicID) {
   case Intrinsic::amdgcn_end_cf:
     return selectEndCfIntrinsic(I);
   case Intrinsic::amdgcn_ds_ordered_add:
   case Intrinsic::amdgcn_ds_ordered_swap:
     return selectDSOrderedIntrinsic(I, IntrinsicID);
   case Intrinsic::amdgcn_ds_gws_init:
case Intrinsic::amdgcn_exp_compr:
     }
     break;
   case Intrinsic::amdgcn_ds_bvh_stack_rtn:
     return selectDSBvhStackIntrinsic(I);
   }
   return selectImpl(I, *CoverageInfo);
 }
 
-bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
+bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) {
   if (selectImpl(I, *CoverageInfo))
     return true;
 
   MachineBasicBlock *BB = I.getParent();
   const DebugLoc &DL = I.getDebugLoc();
 
   Register DstReg = I.getOperand(0).getReg();
   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) &&
     MachineBasicBlock *BB = I.getParent();
 
     // If DS instructions require M0 initialization, insert it before selecting.
     BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
       .addImm(-1);
   }
 }
 
-bool AMDGPUInstructionSelector::selectG_LOAD_STORE_ATOMICRMW(
-  MachineInstr &I) const {
+bool AMDGPUInstructionSelector::selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) {
   initM0(I);
   return selectImpl(I, *CoverageInfo);
 }
 
 static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
   if (Reg.isPhysical())
     return false;
 

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

 public:
   AMDGPUPostLegalizerCombinerImpl(
       const AMDGPUPostLegalizerCombinerImplRuleConfig &RuleConfig,
       MachineIRBuilder &B, AMDGPUCombinerHelper &Helper,
       GISelChangeObserver &Observer);
 
   static const char *getName() { return "AMDGPUPostLegalizerCombinerImpl"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
   struct FMinFMaxLegacyInfo {
     Register LHS;
     Register RHS;
     Register True;
     Register False;
     CmpInst::Predicate Pred;
   };

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

 public:
   AMDGPUPreLegalizerCombinerImpl(
       const AMDGPUPreLegalizerCombinerImplRuleConfig &RuleConfig,
       const GCNSubtarget &STI, GISelChangeObserver &Observer,
       MachineIRBuilder &B, AMDGPUCombinerHelper &Helper);
 
   static const char *getName() { return "AMDGPUPreLegalizerCombinerImpl"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
   struct ClampI64ToI16MatchInfo {
     int64_t Cmp1 = 0;
     int64_t Cmp2 = 0;
     Register Origin;
   };
 
   bool matchClampI64ToI16(MachineInstr &MI, const MachineRegisterInfo &MRI,

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

 public:
   AMDGPURegBankCombinerImpl(
       const AMDGPURegBankCombinerImplRuleConfig &RuleConfig,
       MachineIRBuilder &B, CombinerHelper &Helper,
       GISelChangeObserver &Observer);
 
   static const char *getName() { return "AMDGPURegBankCombinerImpl"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
   bool isVgprRegBank(Register Reg) const;
   Register getAsVgpr(Register Reg) const;
 
   struct MinMaxMedOpc {
     unsigned Min, Max, Med;
   };
 

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

 public:
   ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
                          const ARMRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   struct CmpConstants;
   struct InsertInfo;
 
   bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
                  MachineRegisterInfo &MRI) const;
 
   // Helper for inserting a comparison sequence that sets \p ResReg to either 1

llvm/lib/Target/M68k/GISel/M68kInstructionSelector.cpp

 public:
   M68kInstructionSelector(const M68kTargetMachine &TM, const M68kSubtarget &STI,
                           const M68kRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   const M68kTargetMachine &TM;
   const M68kInstrInfo &TII;
   const M68kRegisterInfo &TRI;
   const M68kRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "M68kGenGlobalISel.inc"

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

 public:
   MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
                           const MipsRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
   bool isRegInGprb(Register Reg, MachineRegisterInfo &MRI) const;
   bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
   bool materialize32BitImm(Register DestReg, APInt Imm,
                            MachineIRBuilder &B) const;
   bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
   const TargetRegisterClass *
   getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
   unsigned selectLoadStoreOpCode(MachineInstr &I,

llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp

 public:
   MipsPostLegalizerCombinerImpl(
       const MipsPostLegalizerCombinerImplRuleConfig &RuleConfig,
       const MipsSubtarget &STI, GISelChangeObserver &Observer,
       MachineIRBuilder &B, CombinerHelper &Helper);
 
   static const char *getName() { return "MipsPostLegalizerCombiner"; }
 
-  bool tryCombineAll(MachineInstr &I) const;
+  bool tryCombineAll(MachineInstr &I);
 
 private:
 #define GET_GICOMBINER_CLASS_MEMBERS
 #include "MipsGenPostLegalizeGICombiner.inc"
 #undef GET_GICOMBINER_CLASS_MEMBERS
 };
 
 #define GET_GICOMBINER_IMPL

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

PPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &STI,
                          const PPCRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   /// tblgen generated 'select' implementation that is used as the initial
   /// selector for the patterns that do not require complex C++.
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
   bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;
 
   bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
                   MachineRegisterInfo &MRI) const;

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

public:
   RISCVInstructionSelector(const RISCVTargetMachine &TM,
                            const RISCVSubtarget &STI,
                            const RISCVRegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   const RISCVSubtarget &STI;
   const RISCVInstrInfo &TII;
   const RISCVRegisterInfo &TRI;
   const RISCVRegisterBankInfo &RBI;
 
   // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
   // uses "STI." in the code generated by TableGen. We need to unify the name of

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

 
 #define GET_GLOBALISEL_TEMPORARIES_DECL
 #include "SPIRVGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_DECL
 
 private:
   // tblgen-erated 'select' implementation, used as the initial selector for
   // the patterns that don't require complex C++.
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   // All instruction-specific selection that didn't happen in "select()".
   // Is basically a large Switch/Case delegating to all other select method.
   bool spvSelect(Register ResVReg, const SPIRVType *ResType,
                  MachineInstr &I) const;
 
   bool selectGlobalValue(Register ResVReg, MachineInstr &I,
                          const MachineInstr *Init = nullptr) const;

llvm/lib/Target/X86/X86InstructionSelector.cpp

X86InstructionSelector(const X86TargetMachine &TM, const X86Subtarget &STI,
                          const X86RegisterBankInfo &RBI);
 
   bool select(MachineInstr &I) override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   /// tblgen-erated 'select' implementation, used as the initial selector for
   /// the patterns that don't require complex C++.
-  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo);
 
   // TODO: remove after supported by Tablegen-erated instruction selection.
   unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
                           Align Alignment) const;
 
   bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
                          MachineFunction &MF) const;
   bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,

llvm/test/TableGen/GlobalISelCombinerMatchTableEmitter/match-table-permutations.td

(match (G_AND $dst, $cst0, $tmp),
          (MatchFooPerms $cst2, (i32 30)):$c
   ),
   (apply (COPY $dst, (i32 0)), "APPLY ${cst0}")>;
 
 def MyCombiner: GICombinerHelper<"GenMyCombiner", [
   Test0
 ]>;
 
-// CHECK:      bool GenMyCombiner::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
+// CHECK:      bool GenMyCombiner::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) {
 // CHECK-NEXT:   switch (PredicateID) {
 // CHECK-NEXT:   case GICXXPred_MI_Predicate_GICombiner0: {
 // CHECK-NEXT:     // Pattern Alternatives: [a[0], b[0], c[0]]
 // CHECK-NEXT:     return foo(State.MIs[2]->getOperand(1), 10)
 // CHECK-NEXT:     llvm_unreachable("GICombiner0 should have returned");
 // CHECK-NEXT:   }
 // CHECK-NEXT:   case GICXXPred_MI_Predicate_GICombiner1: {
 // CHECK-NEXT:     // Pattern Alternatives: [a[0], b[0], c[0]]

llvm/test/TableGen/GlobalISelCombinerMatchTableEmitter/match-table.td

 // CHECK-NEXT: case GICXXPred_MI_Predicate_GICombiner0: {
 // CHECK-NEXT:   return CHECK State.MIs[0]->getOperand(0), State.MIs[0]->getOperand(1), State.MIs[1]->getOperand(1), State.MIs[0]
 // CHECK-NEXT: }
 // CHECK-NEXT: case GICXXPred_MI_Predicate_GICombiner1: {
 // CHECK-NEXT:   return matchIConstant(State.MIs[0]->getOperand(1), 0);
 // CHECK-NEXT: }
 
 // Verify we reset MatchData on each tryCombineAll
-// CHECK:      bool GenMyCombiner::tryCombineAll(MachineInstr &I) const {
+// CHECK:      bool GenMyCombiner::tryCombineAll(MachineInstr &I) {
 // CHECK-NEXT:   const TargetSubtargetInfo &ST = MF.getSubtarget();
 // CHECK-NEXT:   const PredicateBitset AvailableFeatures = getAvailableFeatures();
 // CHECK-NEXT:   NewMIVector OutMIs;
 // CHECK-NEXT:   State.MIs.clear();
 // CHECK-NEXT:   State.MIs.push_back(&I);
 // CHECK-NEXT:   MatchInfos = MatchInfosTy();
 // CHECK-EMPTY:
 // CHECK-NEXT:   if (executeMatchTable(*this, OutMIs, State, ExecInfo, getMatchTable(), *ST.getInstrInfo(), MRI, *MRI.getTargetRegisterInfo(), *ST.getRegBankInfo(), AvailableFeatures, /*CoverageInfo*/ nullptr, &Observer))
 // CHECK-NEXT:     return true;
 // CHECK-NEXT:   }
 // CHECK-EMPTY:
 // CHECK-NEXT:   return false;
 // CHECK-NEXT: }
 
 // Check apply
 // CHECK:      enum {
 // CHECK-NEXT:   GICXXCustomAction_CombineApplyGICombiner0 = GICXXCustomAction_Invalid + 1,
 // CHECK-NEXT:   GICXXCustomAction_CombineApplyGICombiner1,
 // CHECK-NEXT:   GICXXCustomAction_CombineApplyGICombiner2,
 // CHECK-NEXT: };
-// CHECK-NEXT: void GenMyCombiner::runCustomAction(unsigned ApplyID, const MatcherState &State, NewMIVector &OutMIs) const {
+// CHECK-NEXT: void GenMyCombiner::runCustomAction(unsigned ApplyID, const MatcherState &State, NewMIVector &OutMIs) {
 // CHECK-NEXT:   switch(ApplyID) {
 // CHECK-NEXT:   case GICXXCustomAction_CombineApplyGICombiner0:{
 // CHECK-NEXT:     APPLY
 // CHECK-NEXT:     return;
 // CHECK-NEXT:   }
 // CHECK-NEXT:   case GICXXCustomAction_CombineApplyGICombiner1:{
 // CHECK-NEXT:     APPLY MatchInfos.MDInfo0, MatchInfos.MDInfo1
 // CHECK-NEXT:     return;

llvm/test/TableGen/GlobalISelEmitter.td

 
 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
 // CHECK-NEXT:    mutable MatcherState State;
 // CHECK-NEXT:    typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
 // CHECK-NEXT:    typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
 // CHECK-NEXT:    const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
 // CHECK-NEXT:    static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
 // CHECK-NEXT:    static MyTargetInstructionSelector::CustomRendererFn CustomRenderers[];
-// CHECK-NEXT:    bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
-// CHECK-NEXT:    bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
-// CHECK-NEXT:    bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
+// CHECK-NEXT:    bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) override;
+// CHECK-NEXT:    bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) override;
+// CHECK-NEXT:    bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) override;
 // CHECK-NEXT:    const int64_t *getMatchTable() const override;
-// CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
-// CHECK-NEXT:    bool testSimplePredicate(unsigned PredicateID) const override;
-// CHECK-NEXT:    void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
+// CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) override;
+// CHECK-NEXT:    bool testSimplePredicate(unsigned PredicateID) override;
+// CHECK-NEXT:    void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) override;
 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
 
 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
 // CHECK-NEXT:    , State(3),
 // CHECK-NEXT:    ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
 
 // CHECK-LABEL: // LLT Objects.

 // CHECK-NEXT:  };
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
 // CHECK-NEXT:    GICXXPred_I64_Predicate_cimm8 = GICXXPred_Invalid + 1,
 // CHECK-NEXT:    GICXXPred_I64_Predicate_simm8,
 // CHECK-NEXT:  };
 
-// CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
+// CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) {
 // CHECK-NEXT:   switch (PredicateID) {
 // CHECK-NEXT:   case GICXXPred_I64_Predicate_cimm8: {
 // CHECK-NEXT:     return isInt<8>(Imm);
 // CHECK-NEXT:   }
 // CHECK-NEXT:   case GICXXPred_I64_Predicate_simm8: {
 // CHECK-NEXT:     return isInt<8>(Imm);
 // CHECK-NEXT:   }
 // CHECK-NEXT:   }
 // CHECK-NEXT:   llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:   return false;
 // CHECK-NEXT: }
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
 // CHECK-NEXT:    GICXXPred_APFloat_Predicate_fpimmz = GICXXPred_Invalid + 1,
 // CHECK-NEXT:  };
-// CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
+// CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) {
 // CHECK-NEXT:    switch (PredicateID) {
 // CHECK-NEXT:    case GICXXPred_APFloat_Predicate_fpimmz: {
 // CHECK-NEXT:      return Imm->isExactlyValue(0.0);
 // CHECK-NEXT:    }
 // CHECK-NEXT:    }
 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:    return false;
 // CHECK-NEXT:  }
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
 // CHECK-NEXT:    GICXXPred_APInt_Predicate_simm9 = GICXXPred_Invalid + 1,
 // CHECK-NEXT:  };
-// CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
+// CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) {
 // CHECK-NEXT:    switch (PredicateID) {
 // CHECK-NEXT:    case GICXXPred_APInt_Predicate_simm9: {
 // CHECK-NEXT:      return isInt<9>(Imm->getSExtValue());
 // CHECK-NEXT:    }
 // CHECK-NEXT:    }
 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:    return false;
 // CHECK-NEXT:  }
 
 // CHECK-LABEL: // Custom renderers.
 // CHECK-NEXT: enum {
 // CHECK-NEXT:   GICR_Invalid,
 // CHECK-NEXT:   GICR_renderImm,
 // CHECK-NEXT: };
 // CHECK-NEXT: MyTargetInstructionSelector::CustomRendererFn
 // CHECK-NEXT: MyTargetInstructionSelector::CustomRenderers[] = {
 // CHECK-NEXT:   nullptr, // GICR_Invalid
 // CHECK-NEXT:   &MyTargetInstructionSelector::renderImm,
 // CHECK-NEXT: };
 
-// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
+// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) {
 // CHECK-NEXT: const PredicateBitset AvailableFeatures = getAvailableFeatures();
 // CHECK-NEXT: NewMIVector OutMIs;
 // CHECK-NEXT: State.MIs.clear();
 // CHECK-NEXT: State.MIs.push_back(&I);
 
 // CHECK:      if (executeMatchTable(*this, OutMIs, State, ExecInfo, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
 // CHECK-NEXT:   return true;
 // CHECK-NEXT: }

llvm/utils/TableGen/GlobalISelCombinerMatchTableEmitter.cpp

OS << "static std::vector<std::string> " << Name << "Option;\n"
      << "    if (!Enabled && !setRuleDisabled(Identifier))\n"
      << "      return false;\n"
      << "  }\n"
      << "  return true;\n"
      << "}\n\n";
 }
 
 void GICombinerEmitter::emitAdditionalImpl(raw_ostream &OS) {
-  OS << "bool " << getClassName()
-     << "::tryCombineAll(MachineInstr &I) const {\n"
+  OS << "bool " << getClassName() << "::tryCombineAll(MachineInstr &I) {\n"
      << "  const TargetSubtargetInfo &ST = MF.getSubtarget();\n"
      << "  const PredicateBitset AvailableFeatures = "
         "getAvailableFeatures();\n"
      << "  NewMIVector OutMIs;\n"
      << "  State.MIs.clear();\n"
      << "  State.MIs.push_back(&I);\n"
      << "  " << MatchDataInfo::StructName << " = "
      << MatchDataInfo::StructTypeName << "();\n\n"
for (const auto &ID : keys(AllCombineRules)) {
       assert(ExpectedID++ == ID && "combine rules are not ordered!");
       OS << "  " << getIsEnabledPredicateEnumName(ID) << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }
     OS << "};\n\n";
   }
 
   OS << "bool " << getClassName()
-     << "::testSimplePredicate(unsigned Predicate) const {\n"
+     << "::testSimplePredicate(unsigned Predicate) {\n"
      << "    return RuleConfig.isRuleEnabled(Predicate - "
         "GICXXPred_Invalid - "
         "1);\n"
      << "}\n";
 }
 
 void GICombinerEmitter::emitRunCustomAction(raw_ostream &OS) {
   const auto ApplyCode = CXXPredicateCode::getAllApplyCode();
 
   if (!ApplyCode.empty()) {
     OS << "enum {\n";
     std::string EnumeratorSeparator = " = GICXXCustomAction_Invalid + 1,\n";
     for (const auto &Apply : ApplyCode) {
       OS << "  " << Apply->getEnumNameWithPrefix(CXXApplyPrefix)
          << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }
     OS << "};\n";
   }
 
   OS << "void " << getClassName()
      << "::runCustomAction(unsigned ApplyID, const MatcherState &State, "
-        "NewMIVector &OutMIs) const "
+        "NewMIVector &OutMIs) "
         "{\n";
   if (!ApplyCode.empty()) {
     OS << "  switch(ApplyID) {\n";
     for (const auto &Apply : ApplyCode) {
       OS << "  case " << Apply->getEnumNameWithPrefix(CXXApplyPrefix) << ":{\n"
          << "    " << join(split(Apply->Code, "\n"), "\n    ") << "\n"
          << "    return;\n";
       OS << "  }\n";

llvm/utils/TableGen/GlobalISelEmitter.cpp

GlobalISelEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules,
   OptRules = optimizeRules<SwitchMatcher>(OptRules, MatcherStorage);
 
   return MatchTable::buildTable(OptRules, WithCoverage);
 }
 
 void GlobalISelEmitter::emitAdditionalImpl(raw_ostream &OS) {
   OS << "bool " << getClassName()
      << "::selectImpl(MachineInstr &I, CodeGenCoverage "
-        "&CoverageInfo) const {\n"
+        "&CoverageInfo) {\n"
      << "  const PredicateBitset AvailableFeatures = "
         "getAvailableFeatures();\n"
      << "  NewMIVector OutMIs;\n"
      << "  State.MIs.clear();\n"
      << "  State.MIs.push_back(&I);\n\n"
      << "  if (executeMatchTable(*this, OutMIs, State, ExecInfo"
      << ", getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures"
      << ", &CoverageInfo)) {\n"
void GlobalISelEmitter::emitAPIntImmPredicateFns(raw_ostream &OS) {
   emitImmPredicateFnsImpl<Record *>(
       OS, "APInt", "const APInt &", ArrayRef<Record *>(MatchedRecords),
       &getPatFragPredicateEnumName,
       [&](Record *R) { return R->getValueAsString("ImmediateCode"); },
       "PatFrag predicates.");
 }
 
 void GlobalISelEmitter::emitTestSimplePredicate(raw_ostream &OS) {
-  OS << "bool " << getClassName() << "::testSimplePredicate(unsigned) const {\n"
+  OS << "bool " << getClassName() << "::testSimplePredicate(unsigned) {\n"
      << "    llvm_unreachable(\"" + getClassName() +
             " does not support simple predicates!\");\n"
      << "  return false;\n"
      << "}\n";
 }
 
 void GlobalISelEmitter::emitRunCustomAction(raw_ostream &OS) {
   OS << "void " << getClassName()
-     << "::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const "
+     << "::runCustomAction(unsigned, const MatcherState&, NewMIVector &) "
         "{\n"
      << "    llvm_unreachable(\"" + getClassName() +
             " does not support custom C++ actions!\");\n"
      << "}\n";
 }
 
 void GlobalISelEmitter::postProcessRule(RuleMatcher &M) {
   SmallPtrSet<Record *, 16> UsedRegs;

llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.h

if (!Predicates.empty()) {
            << GetPredEnumName(Pred) << EnumeratorSeparator;
         EnumeratorSeparator = ",\n";
       }
       OS << "};\n";
     }
 
     OS << "bool " << getClassName() << "::test" << ArgName << "Predicate_"
        << TypeIdentifier << "(unsigned PredicateID, " << ArgType << " "
-       << ArgName << AdditionalArgs << ") const {\n"
+       << ArgName << AdditionalArgs << ") {\n"
        << AdditionalDeclarations;
     if (!AdditionalDeclarations.empty())
       OS << "\n";
     if (!Predicates.empty()) {
       OS << "  switch (PredicateID) {\n";
       for (const auto &Pred : Predicates) {
         // Ensure all code is indented.
         const auto Code = join(split(GetPredCode(Pred).str(), "\n"), "\n    ");

llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp

<< "::*CustomRendererFn)(MachineInstrBuilder &, const "
         "const;\n"
      << "  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, "
         "CustomRendererFn> "
         "ExecInfo;\n"
      << "  static " << getClassName()
      << "::ComplexMatcherMemFn ComplexPredicateFns[];\n"
      << "  static " << getClassName()
      << "::CustomRendererFn CustomRenderers[];\n"
-     << "  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const "
+     << "  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) "
         "override;\n"
      << "  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) "
-        "const override;\n"
+        "override;\n"
      << "  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat "
-        "&Imm) const override;\n"
+        "&Imm) override;\n"
      << "  const int64_t *getMatchTable() const override;\n"
      << "  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI"
         ", const MatcherState &State) "
-        "const override;\n"
-     << "  bool testSimplePredicate(unsigned PredicateID) const override;\n"
+        "override;\n"
+     << "  bool testSimplePredicate(unsigned PredicateID) override;\n"
      << "  void runCustomAction(unsigned FnID, const MatcherState &State, "
         "NewMIVector &OutMIs) "
-        "const override;\n";
+        "override;\n";
   emitAdditionalTemporariesDecl(OS, "  ");
   OS << "#endif // ifdef " << IfDefName << "\n\n";
 }
 
 void GlobalISelMatchTableExecutorEmitter::emitTemporariesInit(
     raw_ostream &OS, unsigned MaxTemporaries, StringRef IfDefName) {
   OS << "#ifdef " << IfDefName << "\n"
      << ", State(" << MaxTemporaries << "),\n"