According to gcc, fcsr should be spill and restore in interrupt, which is missed in llvm.
This patch added fcsr spill and restore when has interrupt and standard extension f on.
Details
- Reviewers
craig.topper asb kito-cheng
Diff Detail
- Repository
- rG LLVM Github Monorepo
Unit Tests
Time | Test | |
---|---|---|
60,030 ms | x64 debian > MLIR.Examples/standalone::test.toy |
Event Timeline
I am not against this patch, just one thought: is it possible that we add FCSR as a RISCVReg in RISCVRegisterInfo.td (new RegisterClass may be needed), and add it to CSR_Interrupt in RISCVCallingConv.td? The spill/restore can be done by CSRRS for this kind of CSRs.
This may reduce the code if we need spill/restore more CSRs in the future.
I posted the patch D158492 though I'm not sure it's worthy as it increases stack size and adds complexity to code.
Relevant context would be this clarification to the riscv-c-api-doc. It doesn't look like anyone has given much thought to vectors so far.
I need to take a look at the patch with the alternate approach, but so I don't forget it: this patch needs to be extended to handle the zfinx case as well (with appropriate test too of course).
Can we use the WriteFRM and ReadFRM pseudo instructions?