[RISCV] Bump vector crypto to v1.0.0-rc1

[4vtomat]

Summary

No extension changes from v0.9, so just modifying the version information.

[asb]

Agreed that looking at https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are no changes that need to be reflected on the LLVM side beyond the version bump here. LGTM

[4vtomat]

In D153836#4452236, @asb wrote:

Agreed that looking at https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are no changes that need to be reflected on the LLVM side beyond the version bump here. LGTM

Thanks for reviewing!

clang/test/Preprocessor/riscv-target-features.c

 // RUN: -march=rv32izfa0p2 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izfa0p2 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
 // CHECK-ZFA-EXT: __riscv_zfa 2000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvbb0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvbb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvbb0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvbb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
-// CHECK-ZVBB-EXT: __riscv_zvbb  9000{{$}}
+// CHECK-ZVBB-EXT: __riscv_zvbb  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvbc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvbc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvbc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvbc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
-// CHECK-ZVBC-EXT: __riscv_zvbc  9000{{$}}
+// CHECK-ZVBC-EXT: __riscv_zvbc  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkg0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkg0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
-// CHECK-ZVKG-EXT: __riscv_zvkg  9000{{$}}
+// CHECK-ZVKG-EXT: __riscv_zvkg  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkn0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvkn1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkn0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvkn1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
-// CHECK-ZVKN-EXT: __riscv_zvkn 9000{{$}}
+// CHECK-ZVKN-EXT: __riscv_zvkn 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvknc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvknc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvknc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvknc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
-// CHECK-ZVKNC-EXT: __riscv_zvknc 9000{{$}}
+// CHECK-ZVKNC-EXT: __riscv_zvknc 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkng0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvkng1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkng0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvkng1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
-// CHECK-ZVKNG-EXT: __riscv_zvkng 9000{{$}}
+// CHECK-ZVKNG-EXT: __riscv_zvkng 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvknha0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvknha1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvknha0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvknha1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
-// CHECK-ZVKNHA-EXT: __riscv_zvknha 9000{{$}}
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvknhb0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvknhb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvknhb0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvknhb1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
-// CHECK-ZVKNHB-EXT: __riscv_zvknhb  9000{{$}}
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkned0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkned1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkned0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkned1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
-// CHECK-ZVKNED-EXT: __riscv_zvkned 9000{{$}}
+// CHECK-ZVKNED-EXT: __riscv_zvkned 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvks0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvks1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvks0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvks1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
-// CHECK-ZVKS-EXT: __riscv_zvks 9000{{$}}
+// CHECK-ZVKS-EXT: __riscv_zvks 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvksc0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvksc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvksc0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvksc1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
-// CHECK-ZVKSC-EXT: __riscv_zvksc 9000{{$}}
+// CHECK-ZVKSC-EXT: __riscv_zvksc 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksed0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksed1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksed0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksed1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
-// CHECK-ZVKSED-EXT: __riscv_zvksed  9000{{$}}
+// CHECK-ZVKSED-EXT: __riscv_zvksed  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvksg0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvksg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvksg0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvksg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
-// CHECK-ZVKSG-EXT: __riscv_zvksg 9000{{$}}
+// CHECK-ZVKSG-EXT: __riscv_zvksg 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksh0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksh1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksh0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksh1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
-// CHECK-ZVKSH-EXT: __riscv_zvksh  9000{{$}}
+// CHECK-ZVKSH-EXT: __riscv_zvksh  1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkt0p9 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkt1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkt0p9 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
-// CHECK-ZVKT-EXT: __riscv_zvkt 9000{{$}}
+// CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}}
 
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
 // RUN: %clang -target riscv64 -menable-experimental-extensions \
 // RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
 // CHECK-ZICOND-EXT: __riscv_zicond  1000000{{$}}

llvm/docs/RISCVUsage.rst

 
 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25).  The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document.  There are multiple possible mappings, and they are *not* mutually ABI compatible.  The mapping LLVM implements is ABI compatible with the default WMO mapping.  This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status.  User beware.
 
 ``experimental-zvfh``
   LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`__.
 
 ``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
-  LLVM implements the `0.9.7 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230531/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+  LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
 
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 
 Vendor Extensions
 =================
 
 Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor.  The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification.  In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions.
 

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zfbfmin", RISCVExtensionVersion{0, 6}},
 
     {"zicond", RISCVExtensionVersion{1, 0}},
 
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"ztso", RISCVExtensionVersion{0, 1}},
 
-    {"zvbb", RISCVExtensionVersion{0, 9}},
-    {"zvbc", RISCVExtensionVersion{0, 9}},
+    {"zvbb", RISCVExtensionVersion{1, 0}},
+    {"zvbc", RISCVExtensionVersion{1, 0}},
 
     {"zvfbfmin", RISCVExtensionVersion{0, 6}},
     {"zvfbfwma", RISCVExtensionVersion{0, 6}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
 
     // vector crypto
-    {"zvkg", RISCVExtensionVersion{0, 9}},
-    {"zvkn", RISCVExtensionVersion{0, 9}},
-    {"zvknc", RISCVExtensionVersion{0, 9}},
-    {"zvkned", RISCVExtensionVersion{0, 9}},
-    {"zvkng", RISCVExtensionVersion{0, 9}},
-    {"zvknha", RISCVExtensionVersion{0, 9}},
-    {"zvknhb", RISCVExtensionVersion{0, 9}},
-    {"zvks", RISCVExtensionVersion{0, 9}},
-    {"zvksc", RISCVExtensionVersion{0, 9}},
-    {"zvksed", RISCVExtensionVersion{0, 9}},
-    {"zvksg", RISCVExtensionVersion{0, 9}},
-    {"zvksh", RISCVExtensionVersion{0, 9}},
-    {"zvkt", RISCVExtensionVersion{0, 9}},
+    {"zvkg", RISCVExtensionVersion{1, 0}},
+    {"zvkn", RISCVExtensionVersion{1, 0}},
+    {"zvknc", RISCVExtensionVersion{1, 0}},
+    {"zvkned", RISCVExtensionVersion{1, 0}},
+    {"zvkng", RISCVExtensionVersion{1, 0}},
+    {"zvknha", RISCVExtensionVersion{1, 0}},
+    {"zvknhb", RISCVExtensionVersion{1, 0}},
+    {"zvks", RISCVExtensionVersion{1, 0}},
+    {"zvksc", RISCVExtensionVersion{1, 0}},
+    {"zvksed", RISCVExtensionVersion{1, 0}},
+    {"zvksg", RISCVExtensionVersion{1, 0}},
+    {"zvksh", RISCVExtensionVersion{1, 0}},
+    {"zvkt", RISCVExtensionVersion{1, 0}},
 };
 
 static void verifyTables() {
 #ifndef NDEBUG
   static std::atomic<bool> TableChecked(false);
   if (!TableChecked.load(std::memory_order_relaxed)) {
     assert(llvm::is_sorted(SupportedExtensions) &&
            "Extensions are not sorted by name");

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

 //===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the RISC-V instructions from the standard 'Zvk',
-// Vector Cryptography Instructions extension, version 0.9.7.
+// Vector Cryptography Instructions extension, version 1.0.0-rc1.
 //
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
            Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
                   ReadVIALUV_WorstCase, ReadVMask]>;

llvm/test/CodeGen/RISCV/attributes.ll

 ; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0"
 ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
 ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
 ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
 ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
-; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
-; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
-; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
-; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
-; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
-; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
+; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
+; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
+; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
+; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
 ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
 ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"

 ; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0"
 ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
 ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
 ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
 ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
-; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
-; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
-; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
-; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
-; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
-; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
-; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
-; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
-; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
+; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvl32b1p0"
+; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
+; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
+; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
+; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
 ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
 ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p6"
 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
 ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p1_zba1p0"
 
 .attribute arch, "rv32izbb1p0"
 # CHECK: attribute      5, "rv32i2p1_zbb1p0"
 
 .attribute arch, "rv32izbc1p0"
 # CHECK: attribute      5, "rv32i2p1_zbc1p0"
 
-.attribute arch, "rv32i_zve64x_zvbb0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbb1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvbc0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbc1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkg0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkg1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkn0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkn1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
     
-.attribute arch, "rv32i_zve64x_zvknc0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknc1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkng0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkng1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvknha0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvknha1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvknhb0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknhb1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkned0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkned1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvks0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvks1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksc0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksc1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksg0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksg1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvksed0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvksed1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve32x_zvksh0p9"
-# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvksh1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zvkt0p9"
-# CHECK: attribute      5, "rv32i2p1_zvkt0p9"
+.attribute arch, "rv32i_zvkt1p0"
+# CHECK: attribute      5, "rv32i2p1_zvkt1p0"
 
 .attribute arch, "rv32izbs1p0"
 # CHECK: attribute      5, "rv32i2p1_zbs1p0"
 
 .attribute arch, "rv32ifzfhmin1p0"
 # CHECK: attribute      5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
 
 .attribute arch, "rv32ifzfh1p0"