This is an archive of the discontinued LLVM Phabricator instance.

Differential D152928

[RFC][DAG] Initially add nodes in the worklist in topological order.
Needs ReviewPublic

Authored by deadalnix on Jun 14 2023, 8:52 AM.

Details

Reviewers
efriedma
craig.topper
spatel
foad
pengfei
lebedev.ri
RKSimon
Summary

In the same vein as D127115, this is step toward processing the dag in topological order.

This is a bit of a shotgun diff and will require many issue to be fixed before proceeding.

Diff Detail

Event Timeline

deadalnix created this revision.Jun 14 2023, 8:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 14 2023, 8:52 AM
Herald added subscribers: armkevincheng, sjarus, eric-k256 and 3 others. · View Herald Transcript
deadalnix requested review of this revision.Jun 14 2023, 8:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 14 2023, 8:52 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
deadalnix retitled this revision from [RFX][DAG] Initially add nodes in the worklist in topological order. to [RFC][DAG] Initially add nodes in the worklist in topological order..Jun 14 2023, 8:53 AM
Harbormaster completed remote builds in B238828: Diff 531362.Jun 14 2023, 9:30 AM
n-omer added a subscriber: n-omer.Jun 14 2023, 12:39 PM
RKSimon added a comment.Jun 15 2023, 6:10 AM

oh no, not again :) A lot of these seem to be related to changes in extension/truncations - although I haven't noticed any common pattern

deadalnix added a comment.Jun 15 2023, 1:30 PM
In D152928#4424415, @RKSimon wrote:

oh no, not again :) A lot of these seem to be related to changes in extension/truncations - although I haven't noticed any common pattern

This one should be the most disruptive one. After that, it's mostly in topological order, and there will be a couple of patch up to ensure this is always the case, but disturbance should be minimal.

deadalnix updated this revision to Diff 532126.Jun 16 2023, 6:41 AM

Fix numerous tests

Herald added subscribers: wangpc, luke, pmatos and 34 others. · View Herald TranscriptJun 16 2023, 6:41 AM
Harbormaster completed remote builds in B239401: Diff 532126.Jun 16 2023, 7:14 AM
foad added a comment.Jun 20 2023, 3:40 AM

This causes many interesting regressions for AMDGPU!

Herald added a subscriber: davidegrohmann. · View Herald TranscriptJun 20 2023, 3:40 AM
RKSimon added inline comments.Jun 20 2023, 4:28 AM
llvm/test/CodeGen/X86/abds.ll
31
t0: ch,glue = EntryToken
            t2: i32,ch = CopyFromReg t0, Register:i32 %0
          t3: i8 = truncate t2
        t7: i64 = sign_extend t3
            t5: i32,ch = CopyFromReg t0, Register:i32 %1
          t6: i8 = truncate t5
        t8: i64 = sign_extend t6
      t9: i64 = sub t7, t8
    t10: i64 = abs t9
  t11: i8 = truncate t10

This has regressed because the sign_extend(truncate()) have already been folded to sign_extend_inreg(any_extend()) before foldABSToABD is called via visitTRUNCATE, meaning we only call it later via visitABS directly and lose the smaller types.

deadalnix updated this revision to Diff 534335.Jun 25 2023, 7:18 AM

Another batch of tests

Herald added a subscriber: nemanjai. · View Herald TranscriptJun 25 2023, 7:18 AM
deadalnix updated this revision to Diff 534352.Jun 25 2023, 8:58 AM

More tests, notably a lot of RISCV ones.

Harbormaster completed remote builds in B241035: Diff 534352.Jun 25 2023, 10:23 AM
deadalnix added a comment.Jun 25 2023, 12:34 PM

As I go on, the changeset is becoming so big that phabricator is unable to display it. Maybe this isn't the right approach, but then, what's the right approach?

RKSimon added a comment.Jun 26 2023, 1:48 AM

I'd probably focus initially on x86 only as that will have the most test changes and the most overlap with other targets.

RKSimon mentioned this in rG63f1ca11a6fe: [X86] Generalize combineVectorTruncationWithPACKUS/combineVectorTruncationWithP….Jun 26 2023, 4:40 AM
deadalnix updated this revision to Diff 534517.Jun 26 2023, 6:18 AM

Revert to showing X86 tests only for now.

Harbormaster completed remote builds in B241149: Diff 534517.Jun 26 2023, 6:55 AM
RKSimon added inline comments.Jun 28 2023, 6:13 AM
llvm/test/CodeGen/X86/avx2-shift.ll
416

Many of the vector regressions are due to X86's combineVectorTruncation fold that is destroying truncate patterns too soon. We should be able to get rid of it with a little more work.

dmgreen mentioned this in D153972: [AArch64] Fold tree of offset loads combine.Jun 29 2023, 12:45 AM
deadalnix mentioned this in D154522: [DAG] Improve combineCarryDiamond to accept (uaddo_carry X, 0, Carry).Jul 5 2023, 9:30 AM
deadalnix updated this revision to Diff 537407.Jul 5 2023, 10:07 AM

rebase on top of D154522

Harbormaster completed remote builds in B243254: Diff 537407.Jul 5 2023, 11:42 AM
RKSimon mentioned this in D154592: [X86] LowerTRUNCATE - improve handling during type legalization to PACKSS/PACKUS patterns.Jul 6 2023, 3:33 AM
deadalnix updated this revision to Diff 538066.Jul 7 2023, 3:54 AM

Rebase on top of D154592

Harbormaster completed remote builds in B243725: Diff 538066.Jul 7 2023, 3:55 AM
RKSimon mentioned this in rG842a6728d950: [X86] LowerTRUNCATE - improve handling during type legalization to….Jul 11 2023, 2:40 AM
RKSimon mentioned this in D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits.Jul 12 2023, 2:39 AM
RKSimon mentioned this in rG8d598531b3f5: Revert rGf269877dc30777354be8a512e871aba1b1f9fd7a "[X86]….Jul 13 2023, 6:12 AM
deadalnix updated this revision to Diff 540381.Jul 14 2023, 5:36 AM

Rebase on top of variosu patches by @RKSimon

Harbormaster completed remote builds in B245365: Diff 540381.Jul 14 2023, 5:54 AM
deadalnix updated this revision to Diff 540422.Jul 14 2023, 8:03 AM

Fix tests

Harbormaster completed remote builds in B245393: Diff 540422.Jul 14 2023, 8:31 AM
deadalnix updated this revision to Diff 543234.Jul 22 2023, 4:24 PM

Rebase and regenrate a bunch of tests

Harbormaster completed remote builds in B247447: Diff 543234.Jul 22 2023, 5:01 PM
RKSimon added a comment.Aug 16 2023, 9:58 AM

@deadalnix Please can you rebase? A lot of the vector truncate issues should be fixed now

RKSimon mentioned this in rG3c2432690ad2: [X86] Remove combineVectorSignBitsTruncation and leave TRUNCATE ->….Aug 17 2023, 4:23 AM
RKSimon added inline comments.Aug 20 2023, 9:14 AM
llvm/test/CodeGen/X86/vselect.ll
5

We need to add AVX1/AVX2 prefixes back here:

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
deadalnix updated this revision to Diff 557805.Oct 20 2023, 3:14 AM

rebase

Harbormaster completed remote builds in B257889: Diff 557805.Oct 20 2023, 3:18 AM
RKSimon added a comment.Oct 20 2023, 6:07 AM

Given that this is not going to be resolved anytime soon and we're relatively early into the review, would you be open to moving this to a GitHub PR?

deadalnix added a comment.Oct 20 2023, 9:51 AM
In D152928#4654624, @RKSimon wrote:

Given that this is not going to be resolved anytime soon and we're relatively early into the review, would you be open to moving this to a GitHub PR?

If this is what it takes, but I'm really not thrilled by the move to be honest. It's way harder to keep track of changes, notification are basically useless, and there is no kind of useful dashboard of what one need to pay attention to either.

RKSimon mentioned this in rGac534d2a16bb: [X86] combineArithReduction - use PACKUSWB directly for PSADBW(TRUNCATE(v8i16….Oct 25 2023, 6:57 AM
RKSimon added a comment.Oct 25 2023, 9:03 AM
In D152928#4654641, @deadalnix wrote:
In D152928#4654624, @RKSimon wrote:

Given that this is not going to be resolved anytime soon and we're relatively early into the review, would you be open to moving this to a GitHub PR?

If this is what it takes, but I'm really not thrilled by the move to be honest. It's way harder to keep track of changes, notification are basically useless, and there is no kind of useful dashboard of what one need to pay attention to either.

Yes its as much fun as a tooth extraction :| But I'm worried that Phab will not get much love going forward and we're months away from getting the x86 regressions fixed, let alone any other backend.

I've started my own WIP branch of this patch at https://github.com/RKSimon/llvm-project/tree/perf/D152928 so I can more easily work though addressing issues; I'll be rebasing + forcing pushes so don't rely on git history if you track it. But wherever you decide to keep the main patch will remain the reference.

RKSimon mentioned this in rG432649700db1: [X86] vec_insert-5.ll - ensure we build with +mmx as we reference x86_mmx types.Oct 30 2023, 5:43 AM
RKSimon mentioned this in rGde4139689519: [DAG] foldABSToABD - add support for abs(sub(sign_extend_inreg()….Nov 15 2023, 7:50 AM
GitHub <noreply@github.com> mentioned this in rG761a963dfc8f: [DAG] narrowExtractedVectorBinOp - ensure we limit late node creation to….Nov 20 2023, 2:56 AM
GitHub <noreply@github.com> mentioned this in rG7b1e4239b396: [DAG] Fold (vt trunc (extload (vt x))) -> (vt load x) (#75229).Dec 18 2023, 8:21 AM
GitHub <noreply@github.com> mentioned this in rGd460c1de3b98: [DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1….Mon, Jan 15, 1:19 PM

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Diff 532126

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-outline_atomics.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-rcpc.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-v8a.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll

llvm/test/CodeGen/AArch64/aarch64-addv.ll

llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll

llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll

llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

llvm/test/CodeGen/AArch64/addr-of-ret-addr.ll

llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll

llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll

llvm/test/CodeGen/AArch64/arm64-build-vector.ll

llvm/test/CodeGen/AArch64/arm64-ccmp.ll

llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll

llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

llvm/test/CodeGen/AArch64/arm64-ld-from-st.ll

llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll

llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll

llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll

llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll

llvm/test/CodeGen/AArch64/arm64-rev.ll

llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll

llvm/test/CodeGen/AArch64/arm64-vabs.ll

llvm/test/CodeGen/AArch64/arm64-vhadd.ll

llvm/test/CodeGen/AArch64/arm64-virtual_base.ll

llvm/test/CodeGen/AArch64/arm64-vmul.ll

llvm/test/CodeGen/AArch64/arm64-windows-calls.ll

llvm/test/CodeGen/AArch64/arm64-xaluo.ll

llvm/test/CodeGen/AArch64/arm64_32-neon.ll

llvm/test/CodeGen/AArch64/arm64_32.ll

llvm/test/CodeGen/AArch64/arm64ec-varargs.ll

llvm/test/CodeGen/AArch64/atomicrmw-O0.ll

llvm/test/CodeGen/AArch64/bcmp.ll

llvm/test/CodeGen/AArch64/bfis-in-loop.ll

llvm/test/CodeGen/AArch64/bitfield-insert.ll

llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll

llvm/test/CodeGen/AArch64/build-vector-two-dup.ll

llvm/test/CodeGen/AArch64/cmp-bool.ll

llvm/test/CodeGen/AArch64/cmp-const-max.ll

llvm/test/CodeGen/AArch64/combine-andintoload.ll

llvm/test/CodeGen/AArch64/combine-mul.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll

llvm/test/CodeGen/AArch64/dag-ReplaceAllUsesOfValuesWith.ll

llvm/test/CodeGen/AArch64/dag-combine-mul-shl.ll

llvm/test/CodeGen/AArch64/dag-combine-select.ll

llvm/test/CodeGen/AArch64/expand-select.ll

llvm/test/CodeGen/AArch64/fadd-combines.ll

llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll

llvm/test/CodeGen/AArch64/fold-global-offsets.ll

llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll

llvm/test/CodeGen/AArch64/fpclamptosat.ll

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

llvm/test/CodeGen/AArch64/funnel-shift.ll

llvm/test/CodeGen/AArch64/icmp-shift-opt.ll

llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll

llvm/test/CodeGen/AArch64/insertshuffleload.ll

llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

llvm/test/CodeGen/AArch64/neon-abd.ll

llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

llvm/test/CodeGen/AArch64/neon-dotreduce.ll

llvm/test/CodeGen/AArch64/neon-sad.ll

llvm/test/CodeGen/AArch64/nontemporal-load.ll

llvm/test/CodeGen/AArch64/nzcv-save.ll

llvm/test/CodeGen/AArch64/pr61111.ll

llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll

llvm/test/CodeGen/AArch64/pull-negations-after-concat-of-truncates.ll

llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

llvm/test/CodeGen/AArch64/reduce-shuffle.ll

llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll

llvm/test/CodeGen/AArch64/rotate-extract.ll

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

llvm/test/CodeGen/AArch64/sat-add.ll

llvm/test/CodeGen/AArch64/select_fmf.ll

llvm/test/CodeGen/AArch64/setcc-fsh.ll

llvm/test/CodeGen/AArch64/shift-accumulate.ll

llvm/test/CodeGen/AArch64/shift-amount-mod.ll

llvm/test/CodeGen/AArch64/shift-by-signext.ll

llvm/test/CodeGen/AArch64/shiftregister-from-and.ll

llvm/test/CodeGen/AArch64/shuffle-tbl34.ll

llvm/test/CodeGen/AArch64/signbit-shift.ll

llvm/test/CodeGen/AArch64/signbit-test.ll

llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

llvm/test/CodeGen/AArch64/srem-lkk.ll

llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll

llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll

llvm/test/CodeGen/AArch64/srem-seteq.ll

llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll

llvm/test/CodeGen/AArch64/sve-aba.ll

llvm/test/CodeGen/AArch64/sve-abd.ll

llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll

llvm/test/CodeGen/AArch64/sve-fixed-vector-zext.ll

llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll

llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll

llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll

llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll

llvm/test/CodeGen/AArch64/sve-vl-arith.ll

llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/swifterror.ll

llvm/test/CodeGen/AArch64/trunc-to-tbl.ll

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll

llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll

llvm/test/CodeGen/AArch64/urem-seteq.ll

llvm/test/CodeGen/AArch64/ushl_sat.ll

llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-add.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll

llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll

llvm/test/CodeGen/AArch64/zext-to-tbl.ll

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

llvm/test/CodeGen/AMDGPU/idot4u.ll

llvm/test/CodeGen/AMDGPU/idot8s.ll

llvm/test/CodeGen/AMDGPU/store-local.96.ll

llvm/test/CodeGen/Mips/atomic.ll

llvm/test/CodeGen/Mips/cconv/byval.ll

llvm/test/CodeGen/Mips/cconv/vector.ll

llvm/test/CodeGen/Mips/dins.ll

llvm/test/CodeGen/Mips/load-store-left-right.ll

llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll

llvm/test/CodeGen/Mips/mips64-f128.ll

llvm/test/CodeGen/Mips/o32_cc_byval.ll

llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll

llvm/test/CodeGen/Mips/v2i16tof32.ll

llvm/test/CodeGen/RISCV/rvv/combine-store.ll

llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1down.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1up.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

llvm/test/CodeGen/RISCV/rvv/variant-cc.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll

llvm/test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll

llvm/test/CodeGen/SystemZ/fp-move-02.ll

llvm/test/CodeGen/SystemZ/frame-24.ll

llvm/test/CodeGen/SystemZ/fshl.ll

llvm/test/CodeGen/SystemZ/inline-asm-i128.ll

llvm/test/CodeGen/SystemZ/int-cmp-47.ll

llvm/test/CodeGen/SystemZ/int-move-10.ll

llvm/test/CodeGen/SystemZ/memset-08.ll

llvm/test/CodeGen/SystemZ/pr36164.ll

llvm/test/CodeGen/SystemZ/pr42606.ll

llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll

llvm/test/CodeGen/SystemZ/risbg-01.ll

llvm/test/CodeGen/SystemZ/risbg-04.ll

llvm/test/CodeGen/SystemZ/shift-04.ll

llvm/test/CodeGen/SystemZ/shift-08.ll

llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll

llvm/test/CodeGen/SystemZ/store-replicated-vals.ll

llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll

llvm/test/CodeGen/SystemZ/vec-args-04.ll

llvm/test/CodeGen/SystemZ/vec-args-05.ll

llvm/test/CodeGen/SystemZ/vec-bswap-05.ll

llvm/test/CodeGen/SystemZ/vec-bswap-06.ll

llvm/test/CodeGen/SystemZ/vec-bswap-07.ll

llvm/test/CodeGen/SystemZ/vec-perm-12.ll

llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll

llvm/test/CodeGen/Thumb2/2013-03-02-vduplane-nonconstant-source-index.ll

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll

llvm/test/CodeGen/Thumb2/active_lane_mask.ll

llvm/test/CodeGen/Thumb2/csel.ll

llvm/test/CodeGen/Thumb2/lsll0.ll

llvm/test/CodeGen/Thumb2/mve-be.ll

llvm/test/CodeGen/Thumb2/mve-blockplacement.ll

llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f16-add.ll

llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f16-mul.ll

llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll

llvm/test/CodeGen/Thumb2/mve-doublereduct.ll

llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll

llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll

llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll

llvm/test/CodeGen/Thumb2/mve-gather-increment.ll

llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll

llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll

llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll

llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll

llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll

llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

llvm/test/CodeGen/Thumb2/mve-masked-load.ll

llvm/test/CodeGen/Thumb2/mve-masked-store.ll

llvm/test/CodeGen/Thumb2/mve-minmax.ll

llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll

llvm/test/CodeGen/Thumb2/mve-phireg.ll

llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll

llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll

llvm/test/CodeGen/Thumb2/mve-pred-ext.ll

llvm/test/CodeGen/Thumb2/mve-pred-not.ll

llvm/test/CodeGen/Thumb2/mve-pred-xor.ll

llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll

llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll

llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll

llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll

llvm/test/CodeGen/Thumb2/mve-sext.ll

llvm/test/CodeGen/Thumb2/mve-shuffleext.ll

llvm/test/CodeGen/Thumb2/mve-vabdus.ll

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll

llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll

llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll

llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

llvm/test/CodeGen/Thumb2/mve-vecreduce-slp.ll

llvm/test/CodeGen/Thumb2/mve-vld2-post.ll

llvm/test/CodeGen/Thumb2/mve-vld2.ll

llvm/test/CodeGen/Thumb2/mve-vld3.ll

llvm/test/CodeGen/Thumb2/mve-vldst4.ll

llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll

llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll

llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll

llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll

llvm/test/CodeGen/Thumb2/mve-vst2.ll

llvm/test/CodeGen/Thumb2/mve-vst3.ll

llvm/test/CodeGen/Thumb2/mve-vst4.ll

llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll

llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll

llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll

llvm/test/CodeGen/Thumb2/umulo-128-legalisation-lowering.ll

llvm/test/CodeGen/Thumb2/urem-seteq-illegal-types.ll

llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll

llvm/test/CodeGen/VE/Scalar/atomic_swap.ll

llvm/test/CodeGen/VE/Scalar/br_cc.ll

llvm/test/CodeGen/VE/Scalar/brcond.ll

llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll

llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll

llvm/test/CodeGen/WebAssembly/pr59626.ll

llvm/test/CodeGen/WebAssembly/simd-build-vector.ll

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll

llvm/test/CodeGen/WebAssembly/xor_reassociate.ll

llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll

llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll

llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll

llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll

llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll

llvm/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll

llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll

llvm/test/CodeGen/X86/MergeConsecutiveStores.ll

llvm/test/CodeGen/X86/WidenArith.ll

llvm/test/CodeGen/X86/abds.ll

Show All 14 Lines
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: negl %eax ; X86-NEXT: negl %eax
; X86-NEXT: cmovsl %ecx, %eax ; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i8: ; X64-LABEL: abd_ext_i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movsbl %sil, %eax ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movsbl %dil, %ecx ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: subl %eax, %ecx ; X64-NEXT: movsbq %dil, %rcx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: negl %eax ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: cmovsl %ecx, %eax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rcx, %rax
; X64-NEXT: # kill: def $al killed $al killed $rax
RKSimonUnsubmitted
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t0: ch,glue = EntryToken
            t2: i32,ch = CopyFromReg t0, Register:i32 %0
          t3: i8 = truncate t2
        t7: i64 = sign_extend t3
            t5: i32,ch = CopyFromReg t0, Register:i32 %1
          t6: i8 = truncate t5
        t8: i64 = sign_extend t6
      t9: i64 = sub t7, t8
    t10: i64 = abs t9
  t11: i8 = truncate t10

This has regressed because the sign_extend(truncate()) have already been folded to sign_extend_inreg(any_extend()) before foldABSToABD is called via visitTRUNCATE, meaning we only call it later via visitABS directly and lose the smaller types.

RKSimon: ``` t0: ch,glue = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %0…
; X64-NEXT: retq ; X64-NEXT: retq
%aext = sext i8 %a to i64 %aext = sext i8 %a to i64
%bext = sext i8 %b to i64 %bext = sext i8 %b to i64
%sub = sub i64 %aext, %bext %sub = sub i64 %aext, %bext
%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false) %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
%trunc = trunc i64 %abs to i8 %trunc = trunc i64 %abs to i8
ret i8 %trunc ret i8 %trunc
} }
define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind { define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
; X86-LABEL: abd_ext_i8_undef: ; X86-LABEL: abd_ext_i8_undef:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subl %eax, %ecx ; X86-NEXT: subl %eax, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: negl %eax ; X86-NEXT: negl %eax
; X86-NEXT: cmovsl %ecx, %eax ; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i8_undef: ; X64-LABEL: abd_ext_i8_undef:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movsbl %sil, %eax ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movsbl %dil, %ecx ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: subl %eax, %ecx ; X64-NEXT: movsbq %dil, %rcx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: negl %eax ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: cmovsl %ecx, %eax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rcx, %rax
; X64-NEXT: # kill: def $al killed $al killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%aext = sext i8 %a to i64 %aext = sext i8 %a to i64
%bext = sext i8 %b to i64 %bext = sext i8 %b to i64
%sub = sub i64 %aext, %bext %sub = sub i64 %aext, %bext
%abs = call i64 @llvm.abs.i64(i64 %sub, i1 true) %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
%trunc = trunc i64 %abs to i8 %trunc = trunc i64 %abs to i8
ret i8 %trunc ret i8 %trunc
} }
define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind { define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; X86-LABEL: abd_ext_i16: ; X86-LABEL: abd_ext_i16:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subl %eax, %ecx ; X86-NEXT: subl %eax, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: negl %eax ; X86-NEXT: negl %eax
; X86-NEXT: cmovsl %ecx, %eax ; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i16: ; X64-LABEL: abd_ext_i16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movswl %si, %eax ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movswl %di, %ecx ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: subl %eax, %ecx ; X64-NEXT: movswq %di, %rcx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movswq %si, %rax
; X64-NEXT: negl %eax ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: cmovsl %ecx, %eax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rcx, %rax
; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%aext = sext i16 %a to i64 %aext = sext i16 %a to i64
%bext = sext i16 %b to i64 %bext = sext i16 %b to i64
%sub = sub i64 %aext, %bext %sub = sub i64 %aext, %bext
%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false) %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
%trunc = trunc i64 %abs to i16 %trunc = trunc i64 %abs to i16
ret i16 %trunc ret i16 %trunc
} }
define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind { define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; X86-LABEL: abd_ext_i16_undef: ; X86-LABEL: abd_ext_i16_undef:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subl %eax, %ecx ; X86-NEXT: subl %eax, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: negl %eax ; X86-NEXT: negl %eax
; X86-NEXT: cmovsl %ecx, %eax ; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i16_undef: ; X64-LABEL: abd_ext_i16_undef:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movswl %si, %eax ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movswl %di, %ecx ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: subl %eax, %ecx ; X64-NEXT: movswq %di, %rcx
; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movswq %si, %rax
; X64-NEXT: negl %eax ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: cmovsl %ecx, %eax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rcx, %rax
; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%aext = sext i16 %a to i64 %aext = sext i16 %a to i64
%bext = sext i16 %b to i64 %bext = sext i16 %b to i64
%sub = sub i64 %aext, %bext %sub = sub i64 %aext, %bext
%abs = call i64 @llvm.abs.i64(i64 %sub, i1 true) %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
%trunc = trunc i64 %abs to i16 %trunc = trunc i64 %abs to i16
ret i16 %trunc ret i16 %trunc
} }
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind { define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; X86-LABEL: abd_ext_i32: ; X86-LABEL: abd_ext_i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %edx ; X86-NEXT: movl %eax, %esi
; X86-NEXT: subl %ecx, %edx ; X86-NEXT: sarl $31, %esi
; X86-NEXT: negl %edx
; X86-NEXT: subl %ecx, %eax ; X86-NEXT: subl %ecx, %eax
; X86-NEXT: cmovlel %edx, %eax ; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: sarl $31, %esi
; X86-NEXT: xorl %esi, %eax
; X86-NEXT: subl %esi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i32: ; X64-LABEL: abd_ext_i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movslq %esi, %rax ; X64-NEXT: movslq %esi, %rax
; X64-NEXT: movslq %edi, %rcx ; X64-NEXT: movslq %edi, %rcx
; X64-NEXT: subq %rax, %rcx ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: movq %rcx, %rax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: negq %rax ; X64-NEXT: negq %rax
; X64-NEXT: cmovsq %rcx, %rax ; X64-NEXT: cmovsq %rcx, %rax
; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%aext = sext i32 %a to i64 %aext = sext i32 %a to i64
%bext = sext i32 %b to i64 %bext = sext i32 %b to i64
%sub = sub i64 %aext, %bext %sub = sub i64 %aext, %bext
%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false) %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
%trunc = trunc i64 %abs to i32 %trunc = trunc i64 %abs to i32
ret i32 %trunc ret i32 %trunc
} }
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind { define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; X86-LABEL: abd_ext_i32_undef: ; X86-LABEL: abd_ext_i32_undef:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: sarl $31, %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %edx ; X86-NEXT: movl %eax, %esi
; X86-NEXT: subl %ecx, %edx ; X86-NEXT: sarl $31, %esi
; X86-NEXT: negl %edx
; X86-NEXT: subl %ecx, %eax ; X86-NEXT: subl %ecx, %eax
; X86-NEXT: cmovlel %edx, %eax ; X86-NEXT: sbbl %edx, %esi
; X86-NEXT: sarl $31, %esi
; X86-NEXT: xorl %esi, %eax
; X86-NEXT: subl %esi, %eax
; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: abd_ext_i32_undef: ; X64-LABEL: abd_ext_i32_undef:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movslq %esi, %rax ; X64-NEXT: movslq %esi, %rax
; X64-NEXT: movslq %edi, %rcx ; X64-NEXT: movslq %edi, %rcx
; X64-NEXT: subq %rax, %rcx ; X64-NEXT: subq %rax, %rcx
; X64-NEXT: movq %rcx, %rax ; X64-NEXT: movq %rcx, %rax
▲ Show 20 Lines • Show All 606 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/abdu.ll

llvm/test/CodeGen/X86/absolute-constant.ll

llvm/test/CodeGen/X86/add-cmov.ll

llvm/test/CodeGen/X86/add-of-mul.ll

llvm/test/CodeGen/X86/add-sub-bool.ll

llvm/test/CodeGen/X86/addcarry.ll

llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll

llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll

llvm/test/CodeGen/X86/atomic-fp.ll

llvm/test/CodeGen/X86/atomic-idempotent.ll

llvm/test/CodeGen/X86/atomic-mi.ll

llvm/test/CodeGen/X86/atomic-non-integer.ll

llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll

llvm/test/CodeGen/X86/atomic-xor.ll

llvm/test/CodeGen/X86/atomic128.ll

llvm/test/CodeGen/X86/avg.ll

llvm/test/CodeGen/X86/avoid-sfb.ll

llvm/test/CodeGen/X86/avx-logic.ll

llvm/test/CodeGen/X86/avx-shift.ll

llvm/test/CodeGen/X86/avx-vbroadcast.ll

llvm/test/CodeGen/X86/avx-vextractf128.ll

llvm/test/CodeGen/X86/avx1-logical-load-folding.ll

llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll

llvm/test/CodeGen/X86/avx2-shift.ll

Show First 20 Lines • Show All 389 Lines • ▼ Show 20 Lines
; X64-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B ret <32 x i8> %B
} }
define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind { define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
; CHECK-LABEL: sext_v16i16: ; X86-LABEL: sext_v16i16:
; CHECK: # %bb.0: ; X86: # %bb.0:
; CHECK-NEXT: vpsllw $8, %ymm0, %ymm0 ; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; CHECK-NEXT: vpsraw $8, %ymm0, %ymm0 ; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: ret{{[l|q]}} ; X86-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X86-NEXT: vpmovsxbw %xmm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: sext_v16i16:
; X64: # %bb.0:
; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X64-NEXT: vpmovsxbw %xmm0, %ymm0
; X64-NEXT: retq
%b = trunc <16 x i16> %a to <16 x i8> %b = trunc <16 x i16> %a to <16 x i8>
%c = sext <16 x i8> %b to <16 x i16> %c = sext <16 x i8> %b to <16 x i16>
ret <16 x i16> %c ret <16 x i16> %c
} }
RKSimonUnsubmitted
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Many of the vector regressions are due to X86's combineVectorTruncation fold that is destroying truncate patterns too soon. We should be able to get rid of it with a little more work.

RKSimon: Many of the vector regressions are due to X86's combineVectorTruncation fold that is destroying…
define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind { define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
; CHECK-LABEL: sext_v8i32: ; CHECK-LABEL: sext_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpslld $16, %ymm0, %ymm0 ; CHECK-NEXT: vpslld $16, %ymm0, %ymm0
; CHECK-NEXT: vpsrad $16, %ymm0, %ymm0 ; CHECK-NEXT: vpsrad $16, %ymm0, %ymm0
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
%b = trunc <8 x i32> %a to <8 x i16> %b = trunc <8 x i32> %a to <8 x i16>
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512-broadcast-arith.ll

llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll

llvm/test/CodeGen/X86/avx512-build-vector.ll

llvm/test/CodeGen/X86/avx512-ext.ll

llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll

llvm/test/CodeGen/X86/avx512-hadd-hsub.ll

llvm/test/CodeGen/X86/avx512-insert-extract.ll

llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512-mask-op.ll

llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll

llvm/test/CodeGen/X86/avx512-trunc.ll

llvm/test/CodeGen/X86/avx512-vbroadcast.ll

llvm/test/CodeGen/X86/avx512-vec-cmp.ll

llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512bw-mask-op.ll

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512dq-mask-op.ll

llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512f-vec-test-testn.ll

llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll

llvm/test/CodeGen/X86/avx512fp16-mov.ll

llvm/test/CodeGen/X86/avx512vbmi2-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512vbmi2-intrinsics.ll

llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

llvm/test/CodeGen/X86/bit-test-shift.ll

llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll

llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll

llvm/test/CodeGen/X86/bitcast-setcc-128.ll

llvm/test/CodeGen/X86/bitcast-setcc-256.ll

llvm/test/CodeGen/X86/bitcast-setcc-512.ll

llvm/test/CodeGen/X86/bitcast-vector-bool.ll

llvm/test/CodeGen/X86/bitselect.ll

llvm/test/CodeGen/X86/bool-ext-inc.ll

llvm/test/CodeGen/X86/bool-math.ll

llvm/test/CodeGen/X86/bswap.ll

llvm/test/CodeGen/X86/bswap_tree2.ll

llvm/test/CodeGen/X86/bt.ll

llvm/test/CodeGen/X86/btc_bts_btr.ll

llvm/test/CodeGen/X86/buildvec-insertvec.ll

llvm/test/CodeGen/X86/bypass-slow-division-32.ll

llvm/test/CodeGen/X86/cast-vsel.ll

llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll

llvm/test/CodeGen/X86/clz.ll

llvm/test/CodeGen/X86/cmov-promotion.ll

llvm/test/CodeGen/X86/cmov.ll

llvm/test/CodeGen/X86/cmp-bool.ll

llvm/test/CodeGen/X86/cmp-concat.ll

llvm/test/CodeGen/X86/cmp.ll

llvm/test/CodeGen/X86/combine-and.ll

llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll

llvm/test/CodeGen/X86/combine-bitreverse.ll

llvm/test/CodeGen/X86/combine-bitselect.ll

llvm/test/CodeGen/X86/combine-bswap.ll

llvm/test/CodeGen/X86/combine-concatvectors.ll

llvm/test/CodeGen/X86/combine-multiplies.ll

llvm/test/CodeGen/X86/combine-or.ll

llvm/test/CodeGen/X86/combine-pmuldq.ll

llvm/test/CodeGen/X86/combine-rotates.ll

llvm/test/CodeGen/X86/combine-sdiv.ll

llvm/test/CodeGen/X86/combine-shl.ll

llvm/test/CodeGen/X86/combine-sra.ll

llvm/test/CodeGen/X86/combine-srem.ll

llvm/test/CodeGen/X86/combine-sse41-intrinsics.ll

llvm/test/CodeGen/X86/combine-sub-usat.ll

llvm/test/CodeGen/X86/combine-sub.ll

llvm/test/CodeGen/X86/commute-blend-sse41.ll

llvm/test/CodeGen/X86/conditional-tailcall.ll

llvm/test/CodeGen/X86/const-shift-of-constmasked.ll

llvm/test/CodeGen/X86/dagcombine-cse.ll

llvm/test/CodeGen/X86/dagcombine-select.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll

llvm/test/CodeGen/X86/divide-by-constant.ll

llvm/test/CodeGen/X86/divmod128.ll

llvm/test/CodeGen/X86/dont-trunc-store-double-to-float.ll

llvm/test/CodeGen/X86/dpbusd.ll

llvm/test/CodeGen/X86/dpbusd_const.ll

llvm/test/CodeGen/X86/dpbusd_i4.ll

llvm/test/CodeGen/X86/elementwise-store-of-scalar-splat.ll

llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll

llvm/test/CodeGen/X86/extract-bits.ll

llvm/test/CodeGen/X86/extract-concat.ll

llvm/test/CodeGen/X86/extract-fp.ll

llvm/test/CodeGen/X86/extract-insert.ll

llvm/test/CodeGen/X86/extract-lowbits.ll

llvm/test/CodeGen/X86/extractelement-fp.ll

llvm/test/CodeGen/X86/extractelement-load.ll

llvm/test/CodeGen/X86/f16c-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/fdiv.ll

llvm/test/CodeGen/X86/fma-fneg-combine-2.ll

llvm/test/CodeGen/X86/fma.ll

llvm/test/CodeGen/X86/fma_patterns.ll

llvm/test/CodeGen/X86/fma_patterns_wide.ll

llvm/test/CodeGen/X86/fmul-combines.ll

llvm/test/CodeGen/X86/fold-call-3.ll

llvm/test/CodeGen/X86/fold-masked-merge.ll

llvm/test/CodeGen/X86/fold-rmw-ops.ll

llvm/test/CodeGen/X86/fp-intrinsics.ll

llvm/test/CodeGen/X86/fp-logic.ll

llvm/test/CodeGen/X86/fp128-cast-strict.ll

llvm/test/CodeGen/X86/fp128-cast.ll

llvm/test/CodeGen/X86/fp128-libcalls-strict.ll

llvm/test/CodeGen/X86/fp128-libcalls.ll

llvm/test/CodeGen/X86/fpclamptosat.ll

llvm/test/CodeGen/X86/fpclamptosat_vec.ll

llvm/test/CodeGen/X86/fpenv-combine.ll

llvm/test/CodeGen/X86/fpenv.ll

llvm/test/CodeGen/X86/freeze-unary.ll

llvm/test/CodeGen/X86/freeze-vector.ll

llvm/test/CodeGen/X86/funnel-shift.ll

llvm/test/CodeGen/X86/h-registers-2.ll

llvm/test/CodeGen/X86/haddsub-2.ll

llvm/test/CodeGen/X86/haddsub-3.ll

llvm/test/CodeGen/X86/haddsub-4.ll

llvm/test/CodeGen/X86/haddsub-shuf.ll

llvm/test/CodeGen/X86/haddsub-undef.ll

llvm/test/CodeGen/X86/haddsub.ll

llvm/test/CodeGen/X86/half.ll

llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll

llvm/test/CodeGen/X86/horizontal-reduce-smax.ll

llvm/test/CodeGen/X86/horizontal-reduce-smin.ll

llvm/test/CodeGen/X86/horizontal-reduce-umax.ll

llvm/test/CodeGen/X86/horizontal-reduce-umin.ll

llvm/test/CodeGen/X86/horizontal-sum.ll

llvm/test/CodeGen/X86/i128-add.ll

llvm/test/CodeGen/X86/i64-to-float.ll

llvm/test/CodeGen/X86/iabs.ll

llvm/test/CodeGen/X86/icmp-abs-C-vec.ll

llvm/test/CodeGen/X86/icmp-abs-C.ll

llvm/test/CodeGen/X86/icmp-pow2-logic-npow2.ll

llvm/test/CodeGen/X86/icmp-shift-opt.ll

llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll

llvm/test/CodeGen/X86/insertelement-duplicates.ll

llvm/test/CodeGen/X86/insertelement-var-index.ll

llvm/test/CodeGen/X86/insertelement-zero.ll

llvm/test/CodeGen/X86/is_fpclass-fp80.ll

llvm/test/CodeGen/X86/ispow2.ll

llvm/test/CodeGen/X86/jump_sign.ll

llvm/test/CodeGen/X86/known-bits-vector.ll

llvm/test/CodeGen/X86/known-signbits-vector.ll

llvm/test/CodeGen/X86/lea-recursion.ll

llvm/test/CodeGen/X86/legalize-shift.ll

llvm/test/CodeGen/X86/lifetime-alias.ll

llvm/test/CodeGen/X86/load-chain.ll

llvm/test/CodeGen/X86/load-combine.ll

llvm/test/CodeGen/X86/load-local-v3i1.ll

llvm/test/CodeGen/X86/load-local-v3i129.ll

llvm/test/CodeGen/X86/load-partial.ll

llvm/test/CodeGen/X86/load-scalar-as-vector.ll

llvm/test/CodeGen/X86/madd.ll

llvm/test/CodeGen/X86/mask-negated-bool.ll

llvm/test/CodeGen/X86/masked_compressstore.ll

llvm/test/CodeGen/X86/masked_expandload.ll

llvm/test/CodeGen/X86/masked_gather.ll

llvm/test/CodeGen/X86/masked_gather_scatter.ll

llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll

llvm/test/CodeGen/X86/masked_load.ll

llvm/test/CodeGen/X86/masked_store.ll

llvm/test/CodeGen/X86/masked_store_trunc.ll

llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll

llvm/test/CodeGen/X86/masked_store_trunc_usat.ll

llvm/test/CodeGen/X86/matrix-multiply.ll

llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll

llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll

llvm/test/CodeGen/X86/memcmp-optsize-x32.ll

llvm/test/CodeGen/X86/memcmp-optsize.ll

llvm/test/CodeGen/X86/memcmp-pgso-x32.ll

llvm/test/CodeGen/X86/memcmp-pgso.ll

llvm/test/CodeGen/X86/memcmp-x32.ll

llvm/test/CodeGen/X86/memcmp.ll

llvm/test/CodeGen/X86/memset-zero.ll

llvm/test/CodeGen/X86/memset64-on-x86-32.ll

llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll

llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll

llvm/test/CodeGen/X86/merge-consecutive-stores-nt.ll

llvm/test/CodeGen/X86/merge-store-constants.ll

llvm/test/CodeGen/X86/midpoint-int-vec-128.ll

llvm/test/CodeGen/X86/midpoint-int-vec-256.ll

llvm/test/CodeGen/X86/midpoint-int-vec-512.ll

llvm/test/CodeGen/X86/min-legal-vector-width.ll

llvm/test/CodeGen/X86/mmx-cvt.ll

llvm/test/CodeGen/X86/movmsk-cmp.ll

llvm/test/CodeGen/X86/mul128.ll

llvm/test/CodeGen/X86/mulvi32.ll

llvm/test/CodeGen/X86/musttail-varargs.ll

llvm/test/CodeGen/X86/neg-abs.ll

llvm/test/CodeGen/X86/neg_fp.ll

llvm/test/CodeGen/X86/no-wide-load.ll

llvm/test/CodeGen/X86/nontemporal-loads.ll

llvm/test/CodeGen/X86/oddshuffles.ll

llvm/test/CodeGen/X86/oddsubvector.ll

llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll

llvm/test/CodeGen/X86/overflow.ll

llvm/test/CodeGen/X86/parity-vec.ll

llvm/test/CodeGen/X86/phaddsub-extract.ll

llvm/test/CodeGen/X86/phaddsub.ll

llvm/test/CodeGen/X86/pmaddubsw.ll

llvm/test/CodeGen/X86/pmulh.ll

llvm/test/CodeGen/X86/pr15267.ll

llvm/test/CodeGen/X86/pr22338.ll

llvm/test/CodeGen/X86/pr23258.ll

llvm/test/CodeGen/X86/pr28472.ll

llvm/test/CodeGen/X86/pr31045.ll

llvm/test/CodeGen/X86/pr32284.ll

llvm/test/CodeGen/X86/pr32345.ll

llvm/test/CodeGen/X86/pr33290.ll

llvm/test/CodeGen/X86/pr33828.ll

llvm/test/CodeGen/X86/pr34137.ll

llvm/test/CodeGen/X86/pr34592.ll

llvm/test/CodeGen/X86/pr35316.ll

llvm/test/CodeGen/X86/pr35443.ll

llvm/test/CodeGen/X86/pr35765.ll

llvm/test/CodeGen/X86/pr35982.ll

llvm/test/CodeGen/X86/pr38185.ll

llvm/test/CodeGen/X86/pr38217.ll

llvm/test/CodeGen/X86/pr38539.ll

llvm/test/CodeGen/X86/pr38639.ll

llvm/test/CodeGen/X86/pr38738.ll

llvm/test/CodeGen/X86/pr39666.ll

llvm/test/CodeGen/X86/pr40730.ll

llvm/test/CodeGen/X86/pr42727.ll

llvm/test/CodeGen/X86/pr42905.ll

llvm/test/CodeGen/X86/pr44976.ll

llvm/test/CodeGen/X86/pr45563-2.ll

llvm/test/CodeGen/X86/pr45833.ll

llvm/test/CodeGen/X86/pr46820.ll

llvm/test/CodeGen/X86/pr46877.ll

llvm/test/CodeGen/X86/pr47517.ll

llvm/test/CodeGen/X86/pr49162.ll

llvm/test/CodeGen/X86/pr49451.ll

llvm/test/CodeGen/X86/pr50609.ll

llvm/test/CodeGen/X86/pr51615.ll

llvm/test/CodeGen/X86/pr53419.ll

llvm/test/CodeGen/X86/pr53842.ll

llvm/test/CodeGen/X86/pr56103.ll

llvm/test/CodeGen/X86/pr57340.ll

llvm/test/CodeGen/X86/pr57402.ll

llvm/test/CodeGen/X86/pr57658.ll

llvm/test/CodeGen/X86/pr61923.ll

llvm/test/CodeGen/X86/pr62286.ll

llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll

llvm/test/CodeGen/X86/promote-cmp.ll

llvm/test/CodeGen/X86/psubus.ll

llvm/test/CodeGen/X86/pull-binop-through-shift.ll

llvm/test/CodeGen/X86/rotate-extract-vector.ll

llvm/test/CodeGen/X86/rotate-extract.ll

llvm/test/CodeGen/X86/rotate.ll

llvm/test/CodeGen/X86/rotate4.ll

llvm/test/CodeGen/X86/rotate_vec.ll

llvm/test/CodeGen/X86/sad.ll

llvm/test/CodeGen/X86/sad_variations.ll

llvm/test/CodeGen/X86/sadd_sat.ll

llvm/test/CodeGen/X86/sadd_sat_plus.ll

llvm/test/CodeGen/X86/sadd_sat_vec.ll

llvm/test/CodeGen/X86/sandybridge-loads.ll

llvm/test/CodeGen/X86/sat-add.ll

llvm/test/CodeGen/X86/scalar_widen_div.ll

llvm/test/CodeGen/X86/scalarize-fp.ll

llvm/test/CodeGen/X86/sdiv-exact.ll

llvm/test/CodeGen/X86/sdiv_fix.ll

llvm/test/CodeGen/X86/sdiv_fix_sat.ll

llvm/test/CodeGen/X86/select-sra.ll

llvm/test/CodeGen/X86/setcc-combine.ll

llvm/test/CodeGen/X86/setcc-freeze.ll

llvm/test/CodeGen/X86/setcc-fsh.ll

llvm/test/CodeGen/X86/setcc-logic.ll

llvm/test/CodeGen/X86/setcc-wide-types.ll

llvm/test/CodeGen/X86/setcc.ll

llvm/test/CodeGen/X86/shift-amount-mod.ll

llvm/test/CodeGen/X86/shift-and.ll

llvm/test/CodeGen/X86/shift-by-signext.ll

llvm/test/CodeGen/X86/shift-combine.ll

llvm/test/CodeGen/X86/shift-i128.ll

llvm/test/CodeGen/X86/shift-i256.ll

llvm/test/CodeGen/X86/shift-mask.ll

llvm/test/CodeGen/X86/shift-parts.ll

llvm/test/CodeGen/X86/shl_elim.ll

llvm/test/CodeGen/X86/shrink_vmul.ll

llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll

llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll

llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll

llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll

llvm/test/CodeGen/X86/signbit-shift.ll

llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll

llvm/test/CodeGen/X86/smul-with-overflow.ll

llvm/test/CodeGen/X86/splat-for-size.ll

llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll

llvm/test/CodeGen/X86/srem-seteq-optsize.ll

llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll

llvm/test/CodeGen/X86/srem-seteq.ll

llvm/test/CodeGen/X86/srem-vector-lkk.ll

llvm/test/CodeGen/X86/sse-intel-ocl.ll

llvm/test/CodeGen/X86/sse2-vector-shifts.ll

llvm/test/CodeGen/X86/sse2.ll

llvm/test/CodeGen/X86/sse41.ll

llvm/test/CodeGen/X86/sshl_sat.ll

llvm/test/CodeGen/X86/sshl_sat_vec.ll

llvm/test/CodeGen/X86/ssub_sat_vec.ll

llvm/test/CodeGen/X86/store-narrow.ll

llvm/test/CodeGen/X86/stores-merging.ll

llvm/test/CodeGen/X86/subcarry.ll

llvm/test/CodeGen/X86/subvector-broadcast.ll

llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll

llvm/test/CodeGen/X86/switch.ll

llvm/test/CodeGen/X86/test-shrink-bug.ll

llvm/test/CodeGen/X86/test-shrink.ll

llvm/test/CodeGen/X86/test-vs-bittest.ll

llvm/test/CodeGen/X86/udiv_fix.ll

llvm/test/CodeGen/X86/udiv_fix_sat.ll

llvm/test/CodeGen/X86/umax.ll

llvm/test/CodeGen/X86/umul-with-overflow.ll

llvm/test/CodeGen/X86/umul_fix.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll

llvm/test/CodeGen/X86/unfold-masked-merge-scalar-variablemask.ll

llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll

llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll

llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll

llvm/test/CodeGen/X86/urem-seteq-nonzero.ll

llvm/test/CodeGen/X86/urem-seteq-optsize.ll

llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll

llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll

llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll

llvm/test/CodeGen/X86/urem-seteq.ll

llvm/test/CodeGen/X86/ushl_sat.ll

llvm/test/CodeGen/X86/ushl_sat_vec.ll

llvm/test/CodeGen/X86/usub_sat_vec.ll

llvm/test/CodeGen/X86/v8i1-masks.ll

llvm/test/CodeGen/X86/var-permute-128.ll

llvm/test/CodeGen/X86/var-permute-512.ll

llvm/test/CodeGen/X86/vastart-defs-eflags.ll

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

llvm/test/CodeGen/X86/vec_ext_inreg.ll

llvm/test/CodeGen/X86/vec_fneg.ll

llvm/test/CodeGen/X86/vec_fpext.ll

llvm/test/CodeGen/X86/vec_int_to_fp.ll

llvm/test/CodeGen/X86/vec_saddo.ll

llvm/test/CodeGen/X86/vec_setcc-2.ll

llvm/test/CodeGen/X86/vec_smulo.ll

llvm/test/CodeGen/X86/vec_ssubo.ll

llvm/test/CodeGen/X86/vec_uaddo.ll

llvm/test/CodeGen/X86/vec_umulo.ll

llvm/test/CodeGen/X86/vec_usubo.ll

llvm/test/CodeGen/X86/vector-bitreverse.ll

llvm/test/CodeGen/X86/vector-bo-select.ll

llvm/test/CodeGen/X86/vector-compare-all_of.ll

llvm/test/CodeGen/X86/vector-compare-any_of.ll

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

llvm/test/CodeGen/X86/vector-ext-logic.ll

llvm/test/CodeGen/X86/vector-fshl-256.ll

llvm/test/CodeGen/X86/vector-fshl-rot-128.ll

llvm/test/CodeGen/X86/vector-fshl-rot-256.ll

llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll

llvm/test/CodeGen/X86/vector-fshr-512.ll

llvm/test/CodeGen/X86/vector-fshr-rot-128.ll

llvm/test/CodeGen/X86/vector-fshr-rot-256.ll

llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll

llvm/test/CodeGen/X86/vector-half-conversions.ll

llvm/test/CodeGen/X86/vector-interleave.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll

llvm/test/CodeGen/X86/vector-intrinsics.ll

llvm/test/CodeGen/X86/vector-narrow-binop.ll

llvm/test/CodeGen/X86/vector-pcmp.ll

llvm/test/CodeGen/X86/vector-popcnt-128.ll

llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll

llvm/test/CodeGen/X86/vector-popcnt-256.ll

llvm/test/CodeGen/X86/vector-reduce-add-mask.ll

llvm/test/CodeGen/X86/vector-reduce-add-sext.ll

llvm/test/CodeGen/X86/vector-reduce-add-zext.ll

llvm/test/CodeGen/X86/vector-reduce-add.ll

llvm/test/CodeGen/X86/vector-reduce-and-bool.ll

llvm/test/CodeGen/X86/vector-reduce-and-cmp.ll

llvm/test/CodeGen/X86/vector-reduce-and.ll

llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

llvm/test/CodeGen/X86/vector-reduce-fmax-fmin-fast.ll

llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll

llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll

llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll

llvm/test/CodeGen/X86/vector-reduce-mul.ll

llvm/test/CodeGen/X86/vector-reduce-or-bool.ll

llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll

llvm/test/CodeGen/X86/vector-reduce-or.ll

llvm/test/CodeGen/X86/vector-reduce-smax.ll

llvm/test/CodeGen/X86/vector-reduce-smin.ll

llvm/test/CodeGen/X86/vector-reduce-umax.ll

llvm/test/CodeGen/X86/vector-reduce-umin.ll

llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll

llvm/test/CodeGen/X86/vector-reduce-xor.ll

llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll

llvm/test/CodeGen/X86/vector-rotate-128.ll

llvm/test/CodeGen/X86/vector-rotate-256.ll

llvm/test/CodeGen/X86/vector-sext.ll

llvm/test/CodeGen/X86/vector-shift-ashr-128.ll

llvm/test/CodeGen/X86/vector-shift-ashr-256.ll

llvm/test/CodeGen/X86/vector-shift-lshr-128.ll

llvm/test/CodeGen/X86/vector-shift-lshr-256.ll

llvm/test/CodeGen/X86/vector-shift-shl-128.ll

llvm/test/CodeGen/X86/vector-shift-shl-256.ll

llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll

llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll

llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll

llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll

llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll

llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll

llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll

llvm/test/CodeGen/X86/vector-shuffle-avx512.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll

llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll

llvm/test/CodeGen/X86/vector-shuffle-combining.ll

llvm/test/CodeGen/X86/vector-shuffle-concatenation.ll

llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll

llvm/test/CodeGen/X86/vector-shuffle-v192.ll

llvm/test/CodeGen/X86/vector-shuffle-v48.ll

llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll

llvm/test/CodeGen/X86/vector-trunc-math.ll

llvm/test/CodeGen/X86/vector-trunc-packus.ll

llvm/test/CodeGen/X86/vector-trunc-ssat.ll

llvm/test/CodeGen/X86/vector-trunc-usat.ll

llvm/test/CodeGen/X86/vector-trunc.ll

llvm/test/CodeGen/X86/vector-tzcnt-256.ll

llvm/test/CodeGen/X86/vector-tzcnt-512.ll

llvm/test/CodeGen/X86/vector-unsigned-cmp.ll

llvm/test/CodeGen/X86/vector-zext.ll

llvm/test/CodeGen/X86/viabs.ll

llvm/test/CodeGen/X86/vselect-avx.ll

llvm/test/CodeGen/X86/vselect-zero.ll

llvm/test/CodeGen/X86/vselect.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
RKSimonUnsubmitted
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We need to add AVX1/AVX2 prefixes back here:

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
RKSimon: We need to add AVX1/AVX2 prefixes back here: ``` ; RUN: llc < %s -mtriple=x86_64-unknown…
; Verify that we don't emit packed vector shifts instructions if the ; Verify that we don't emit packed vector shifts instructions if the
; condition used by the vector select is a vector of constants. ; condition used by the vector select is a vector of constants.
define <4 x float> @test1(<4 x float> %a, <4 x float> %b) { define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
; SSE2-LABEL: test1: ; SSE2-LABEL: test1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
▲ Show 20 Lines • Show All 550 Lines • ▼ Show 20 Lines
; SSE2-LABEL: simplify_select: ; SSE2-LABEL: simplify_select:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pslld $31, %xmm0 ; SSE2-NEXT: pslld $31, %xmm0
; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: movd %edi, %xmm1 ; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1]
; SSE2-NEXT: por %xmm1, %xmm2 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0,0] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[1,1]
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: simplify_select: ; SSE41-LABEL: simplify_select:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE41-NEXT: pslld $31, %xmm0 ; SSE41-NEXT: pslld $31, %xmm0
; SSE41-NEXT: movd %edi, %xmm1 ; SSE41-NEXT: movd %edi, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1]
; SSE41-NEXT: por %xmm1, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm2
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,1,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE41-NEXT: pinsrd $1, %edi, %xmm1
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1 ; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movaps %xmm1, %xmm0 ; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
;
; AVX-LABEL: simplify_select:
; AVX: # %bb.0:
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX-NEXT: vpslld $31, %xmm0, %xmm0
; AVX-NEXT: vmovd %edi, %xmm1
; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,0,1,1]
; AVX-NEXT: vpor %xmm1, %xmm2, %xmm1
; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
; AVX-NEXT: vpinsrd $1, %edi, %xmm2, %xmm2
; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
; AVX-NEXT: retq
%a = insertelement <2 x i32> <i32 0, i32 undef>, i32 %x, i32 1 %a = insertelement <2 x i32> <i32 0, i32 undef>, i32 %x, i32 1
%b = insertelement <2 x i32> <i32 undef, i32 0>, i32 %x, i32 0 %b = insertelement <2 x i32> <i32 undef, i32 0>, i32 %x, i32 0
%y = or <2 x i32> %a, %b %y = or <2 x i32> %a, %b
%p16 = extractelement <2 x i32> %y, i32 1 %p16 = extractelement <2 x i32> %y, i32 1
%p17 = insertelement <2 x i32> undef, i32 %p16, i32 0 %p17 = insertelement <2 x i32> undef, i32 %p16, i32 0
%p18 = insertelement <2 x i32> %p17, i32 %x, i32 1 %p18 = insertelement <2 x i32> %p17, i32 %x, i32 1
%r = select <2 x i1> %z, <2 x i32> %y, <2 x i32> %p18 %r = select <2 x i1> %z, <2 x i32> %y, <2 x i32> %p18
ret <2 x i32> %r ret <2 x i32> %r
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llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll

llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll

llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll

llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll

llvm/test/CodeGen/X86/widen_bitops-1.ll

llvm/test/CodeGen/X86/widen_cast-2.ll

llvm/test/CodeGen/X86/widen_fdiv.ll

llvm/test/CodeGen/X86/widen_load-2.ll

llvm/test/CodeGen/X86/win64-byval.ll

llvm/test/CodeGen/X86/win64_frame.ll

llvm/test/CodeGen/X86/x86-64-baseptr.ll

llvm/test/CodeGen/X86/x86-interleaved-access.ll

llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

llvm/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll

llvm/test/CodeGen/X86/xop-shifts.ll

llvm/test/CodeGen/X86/xor.ll

llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll

llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll

llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll

llvm/test/CodeGen/X86/zext-demanded.ll

llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

llvm/test/CodeGen/X86/zext-lshr.ll

llvm/test/CodeGen/X86/zext-shl.ll