[1/3][RISCV] Define machine instruction to write an immediate into vxrm

[eopXD]

Summary

This patch-set wants to model rounding mode for the fixed-point
intrinsics of the RVV C intrinsics.

The specification PR: riscv-non-isa/rvv-intrinsic-doc#222

The 3 patches is a proof-of-concept with a bottom-up approach
Going from machine instruction to LLVM intrinsics, then to the C
intrinsics. The 3 patches applies the rounding mode control on the
vaadd instruction. Proceeding patches will extend the change to all
other fixed-point computations.

---

This is the 1st commit of the patch-set. This patch gives a name to
the machine instruction that writes an immediate into the CSR vxrm.

[craig.topper]

LGTM

[eopXD]

Rebase to latest main.

[eopXD]

Update to latest main.

[eopXD]

Rebase to latest main.

[eopXD]

Bump CI.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

class SwapSysRegImm<SysReg SR, list<Register> Regs>
   let Defs = Regs;
 }
 
 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
 
+def WriteVXRMImm : WriteSysRegImm<SysRegVXRM, [VXRM]>;
+
 let hasSideEffects = true in {
 def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
 def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
 }
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
 let Defs = [X2], Uses = [X2] in {

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
 
 //===----------------------------------------------------------------------===//
 // User Vector CSRs
 //===----------------------------------------------------------------------===//
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;
-def : SysReg<"vxrm", 0x00A>;
+def SysRegVXRM : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vcsr", 0x00F>;
 def SysRegVL : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def SysRegVLENB: SysReg<"vlenb", 0xC22>;
 
 //===----------------------------------------------------------------------===//
 // State Enable Extension (Smstateen)
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/vxrm.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM
+
+---
+name:    verify_vxrm
+tracksRegLiveness: true
+body:     |
+  bb.0.entry:
+    liveins: $v8, $v9, $x10
+
+    ; MIR-LABEL: name: verify_vxrm
+    ; MIR: liveins: $v8, $v9, $x10
+    ; MIR-NEXT: {{  $}}
+    ; MIR-NEXT: dead $x0 = PseudoVSETVLI renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
+    ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm
+    ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 renamable $v8, renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype
+    ; MIR-NEXT: PseudoRET implicit $v8
+    ; ASM-LABEL: verify_vxrm:
+    ; ASM:        # %bb.0:
+    ; ASM-NEXT:    vsetvli  zero, a0, e8, mf8, ta, ma
+    ; ASM-NEXT:    csrwi  vxrm, 0
+    ; ASM-NEXT:    vaadd.vv v8, v8, v9
+    ; ASM-NEXT:    ret
+    %0:vr = COPY $v8
+    %1:vr = COPY $v9
+    dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
+    WriteVXRMImm 0, implicit-def $vxrm
+    renamable $v8 = PseudoVAADD_VV_MF8 killed renamable $v8, killed renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype
+    PseudoRET implicit $v8
+...