[clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

[asb]

Summary

Now that codegen support for zhinx in landed (D149811), we should set HasLegalHalfType=true for zhinx (see D145071 for the patch doing this for zfh).

[craig.topper]

LGTM

clang/lib/Basic/Targets/RISCV.cpp

if (!ParseResult) {
     return false;
   } else {
     ISAInfo = std::move(*ParseResult);
   }
 
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   return true;
 }
 
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);

clang/test/CodeGen/RISCV/Float16-arith.c

 // ZFH-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
 // ZFH-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZFH-NEXT:    ret void
 //
 // ZHINX-LABEL: define dso_local void @f16_add
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:    [[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:    [[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:    [[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:    [[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:    [[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:    store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:    ret void
 //
 void f16_add() {
   x = y + z;
 }