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Differential D149496

[RISCV][llvm-mca] Add mca tests for riscv lmul instruments
ClosedPublic

Authored by michaelmaitland on Apr 28 2023, 4:11 PM.

Details

Reviewers
craig.topper
kito-cheng
reames
• pcwang-thead
myhsu
andreadb
Commits
rG60d36ef096ce: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments
rG1e317c3f819c: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments
rG1dedc96d04c8: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments
Summary

Add llvm-mca tests for RISCV LMUL instruments to show that llvm-mca RISCV LMUL
instruments work.

Diff Detail

Unit TestsFailed

TimeTest
30 msx64 debian > LLVM.tools/llvm-mca/RISCV::different-instruments.s
50 msx64 debian > LLVM.tools/llvm-mca/RISCV::disable-im.s
70 msx64 debian > LLVM.tools/llvm-mca/RISCV::instrument-at-start.s
50 msx64 debian > LLVM.tools/llvm-mca/RISCV::instrument-in-middle.s
50 msx64 debian > LLVM.tools/llvm-mca/RISCV::instrument-in-region.s
View Full Test Results (7 Failed)

Event Timeline

michaelmaitland created this revision.Apr 28 2023, 4:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2023, 4:11 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
michaelmaitland requested review of this revision.Apr 28 2023, 4:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2023, 4:11 PM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
michaelmaitland added a parent revision: D149495: [RISCV] Add support for V extension in SiFive7.Apr 28 2023, 4:13 PM
Harbormaster completed remote builds in B228946: Diff 518082.Apr 28 2023, 4:24 PM
andreadb accepted this revision.May 1 2023, 9:51 PM

LGTM

This revision is now accepted and ready to land.May 1 2023, 9:51 PM
michaelmaitland added a parent revision: D149710: [RISCV] Add sifive-x280 processor with all of its extensions.May 2 2023, 5:53 PM
michaelmaitland updated this revision to Diff 521033.May 10 2023, 10:38 AM

Rebase.

Harbormaster completed remote builds in B231122: Diff 521033.May 10 2023, 11:26 AM
michaelmaitland updated this revision to Diff 521065.May 10 2023, 11:50 AM

Regenerate test checks.

michaelmaitland added inline comments.May 10 2023, 11:55 AM
llvm/test/tools/llvm-mca/RISCV/different-instruments.s
64

I don't think this is expected behavior for the vadds to take the same amount of time, so I'm going to need to take another look at whats going on.

Harbormaster completed remote builds in B231145: Diff 521065.May 10 2023, 1:52 PM
Closed by commit rG1dedc96d04c8: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments (authored by michaelmaitland). · Explain WhyMay 12 2023, 9:07 AM
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rG1dedc96d04c8: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments.
michaelmaitland added a reverting change: rGad8765a0c8f4: Revert "[RISCV][llvm-mca] Add mca tests for riscv lmul instruments".May 12 2023, 9:23 AM
michaelmaitland added a commit: rG1e317c3f819c: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments.May 12 2023, 9:52 AM
vitalybuka added a reverting change: rG847789d45712: Revert "[RISCV][llvm-mca] Add mca tests for riscv lmul instruments".May 12 2023, 11:30 PM
vitalybuka reopened this revision.May 12 2023, 11:31 PM
This revision is now accepted and ready to land.May 12 2023, 11:31 PM
michaelmaitland updated this revision to Diff 521903.May 13 2023, 7:56 AM

Add lit config

michaelmaitland added a comment.May 13 2023, 8:00 AM

It looks like this patch failed on "sanitizer-x86_64-linux-fast" even though lit config only supposed to run on riscv.

Harbormaster completed remote builds in B231783: Diff 521903.May 13 2023, 8:41 AM
michaelmaitland added a parent revision: D150816: [llvm-mca][RISCV] Fix llvm-mca RISCVInstrument memory leak.May 17 2023, 1:57 PM
michaelmaitland updated this revision to Diff 524344.May 22 2023, 9:00 AM

Rebase.

Harbormaster completed remote builds in B233605: Diff 524344.May 22 2023, 10:33 AM
Closed by commit rG60d36ef096ce: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments (authored by michaelmaitland). · Explain WhyMay 22 2023, 10:37 AM
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rG60d36ef096ce: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments.
thakis added a subscriber: thakis.May 22 2023, 11:56 AM

These tests don't seem to pass: http://45.33.8.238/linux/107615/step_12.txt

Please take a look and revert for now if it takes a while to fix.

michaelmaitland added a comment.EditedMay 22 2023, 12:03 PM
In D149496#4361765, @thakis wrote:

These tests don't seem to pass: http://45.33.8.238/linux/107615/step_12.txt

Please take a look and revert for now if it takes a while to fix.

Can you please share what cmake options you used? I'm unable to reproduce on my end and not getting any messages from buildbot failures.

myhsu added a comment.May 22 2023, 1:09 PM
In D149496#4361807, @michaelmaitland wrote:
In D149496#4361765, @thakis wrote:

These tests don't seem to pass: http://45.33.8.238/linux/107615/step_12.txt

Please take a look and revert for now if it takes a while to fix.

Can you please share what cmake options you used? I'm unable to reproduce on my end and not getting any messages from buildbot failures.

I think it's GN not cmake, the instruction is here: https://github.com/llvm/llvm-project/tree/main/llvm/utils/gn

michaelmaitland added a comment.May 22 2023, 1:26 PM
In D149496#4362088, @myhsu wrote:
In D149496#4361807, @michaelmaitland wrote:
In D149496#4361765, @thakis wrote:

These tests don't seem to pass: http://45.33.8.238/linux/107615/step_12.txt

Please take a look and revert for now if it takes a while to fix.

Can you please share what cmake options you used? I'm unable to reproduce on my end and not getting any messages from buildbot failures.

I think it's GN not cmake, the instruction is here: https://github.com/llvm/llvm-project/tree/main/llvm/utils/gn

@thakis are you able to share gn arguments? I have not been able to reproduce the issue. Please let me know if you'd like me to revert while we sort this out.

aeubanks added a subscriber: aeubanks.May 22 2023, 1:30 PM
In D149496#4362088, @myhsu wrote:
In D149496#4361807, @michaelmaitland wrote:
In D149496#4361765, @thakis wrote:

These tests don't seem to pass: http://45.33.8.238/linux/107615/step_12.txt

Please take a look and revert for now if it takes a while to fix.

Can you please share what cmake options you used? I'm unable to reproduce on my end and not getting any messages from buildbot failures.

I think it's GN not cmake, the instruction is here: https://github.com/llvm/llvm-project/tree/main/llvm/utils/gn

I can't repro this in a cmake build, so it's a gn-specific thing which is unsupported (I'll take a look myself)

evandro removed a subscriber: evandro.May 22 2023, 5:24 PM
thakis added a comment.May 22 2023, 5:36 PM

Apologies, this ended up being a configuration issue over here.

Revision Contents

Diff 521033

llvm/test/tools/llvm-mca/RISCV/different-instruments.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu
# LLVM-MCA-RISCV-LMUL M8
vadd.vv v12, v12, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12
# CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 18.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 2.00 - 18.00 18.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
michaelmaitlandAuthorUnsubmitted
Done
ReplyInline Actions

I don't think this is expected behavior for the vadds to take the same amount of time, so I'm going to need to take another look at whats going on.

michaelmaitland: I don't think this is expected behavior for the vadds to take the same amount of time, so I'm…
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/disable-im.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s
vsetvli zero, a0, e8, m2, tu, mu
# LLVM-MCA-RISCV-LMUL M2
vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu
# LLVM-MCA-RISCV-LMUL M8
vadd.vv v12, v12, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 6
# CHECK-NEXT: Total Cycles: 40
# CHECK-NEXT: Total uOps: 6
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.15
# CHECK-NEXT: IPC: 0.15
# CHECK-NEXT: Block RThroughput: 48.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 3.00 - 48.00 48.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: - - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789
# CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 1.00 - 2.00 2.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu
# LLVM-MCA-RISCV-LMUL MF8
vadd.vv v12, v12, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 17.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 1.00 - 17.00 17.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - - 1.00 1.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
# LLVM-MCA-BEGIN foo
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
# LLVM-MCA-END foo
# CHECK: [0] Code Region - foo
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 1.00 - 2.00 2.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
# LLVM-MCA-BEGIN foo
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
# LLVM-MCA-END foo
vadd.vv v12, v12, v12
# CHECK: [0] Code Region - foo
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 1.00 - 2.00 2.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12
vsub.vv v12, v12, v12
vsetvli zero, a0, e8, m2, tu, mu
# LLVM-MCA-RISCV-LMUL M4
vadd.vv v12, v12, v12
vsub.vv v12, v12, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 28
# CHECK-NEXT: Total uOps: 8
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.29
# CHECK-NEXT: IPC: 0.29
# CHECK-NEXT: Block RThroughput: 22.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7NFDiv
# CHECK-NEXT: [1] - SiFive7NIDiv
# CHECK-NEXT: [2] - SiFive7NMem
# CHECK-NEXT: [3] - SiFive7NPipeA
# CHECK-NEXT: [4] - SiFive7NPipeB
# CHECK-NEXT: [5] - SiFive7NPipeV
# CHECK-NEXT: [6] - SiFive7NVA
# CHECK-NEXT: [7] - SiFive7NVL
# CHECK-NEXT: [8] - SiFive7NVS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
# CHECK-NEXT: - - - 3.00 - 22.00 22.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - - 2.00 2.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: - - - - - 8.00 8.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - - 8.00 8.00 - - vsub.vv v12, v12, v12
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 01234567
# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s

  • This file was added.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL
vadd.vv v12, v12, v12
# CHECK: error: Failed to create RISCV-LMUL instrument with no data
# CHECK: # LLVM-MCA-RISCV-LMUL
# CHECK: ^
# CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s

  • This file was added.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s 2>&1 | FileCheck %s
# LLVM-MCA-UNKNOWN M1
vsetvli zero, a0, e8, m1, tu, mu
vadd.vv v12, v12, v12
# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: UNKNOWN
# CHECK: # LLVM-MCA-UNKNOWN M1
# CHECK: ^
# CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s

  • This file was added.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-V MF9
vadd.vv v12, v12, v12
# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
# CHECK: # LLVM-MCA-RISCV-V MF9
# CHECK: ^
# CHECK: error: There was an error parsing comments.