[SelectionDAG][WIP] Add support for evaluating SetCC based on knownbits

[goldstein.w.n]

Summary

In some cases folds done through ISel/DAGCombining result in SetCC
conditions that we can easily simplify using known bits.

This patch adds support for that.

NB: The medium-term goal is to get this patch in, then use comparisons
against zero for testing future improvements to isKnownNeverZero as
there are issues using cttz/ctlz for that.

[goldstein.w.n]

llvm/test/CodeGen/X86/avx512-mask-op.ll

615

Why do we emit any code here?

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1359

These movb $1, %al; testb %al, %al's (here and in many other cases) are unnecessary. I assume its because SelectionDAG only has BB view, so even if we can rule out some BBs (based on known true/false br-cond), there is no pass for that. Is there anything we can/should do about that?

Also NB, we really should never emit movb $1, %al; testb %al, %al just grabbing any gpr (I guess least recently used to minimize potential latency) and do cmpb %gpr8, gpr8 then jne/je depending if we want it to be always true/false.

[goldstein.w.n]

Fix some typos

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2472

I would not do this in FoldSetCC. FoldSetCC is called from getNode and I don't think we want to call to computeKnownBits hidden in that.

You you can do it in SimplifySetCC in TargetLowering.cpp I think.

[craig.topper]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1359

Hopefully most of these are just tests that should have been folded by InstCombine or other passes earlier and not really cases that originate in SelectionDAG.

[craig.topper]

llvm/test/CodeGen/X86/avx512-mask-op.ll

615

I'm guesting we started with a conditional branch and it got optimized out?

[goldstein.w.n]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1359

Do you think these regressions are something to worry about? Or acceptable as cases we would never expect to get from the middle-end.

[RKSimon]

This is very similar to a patch I tried a while ago: D86578 - one of the blockers for which was all the over-reduced test cases that it broke

[goldstein.w.n]

In D149383#4305324, @RKSimon wrote:

This is very similar to a patch I tried a while ago: D86578 - one of the blockers for which was all the over-reduced test cases that it broke

What do you mean over-reduces?
But nikic has a point that realistic backend code shouldn't be affected by this much.
I think there are some cases that benefit like cttz/ctlz cases if zero is no poison AND target doesn't have tzcnt/lzcnt
but thats niche.

It may also be able to help with intermediate select statement introduced during lowering that are
actually constant foldable.

Maybe a different way to test isKnownNeverZero is better?

[RKSimon]

llvm/test/CodeGen/AArch64/cmp-const-max.ll

1

regenerate + commit this file and rebase to show the diffs from the patch

llvm/test/CodeGen/ARM/sub-cmp-peephole.ll

1

regenerate this file first so you show any diffs

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

comparing against zero in all these or-with-imm tests just seems to be a copy+paste from the other logic ops in this file - maybe change it to something that isn't constant foldable (test for -ve?)

[goldstein.w.n]

Rebase + move impl to simplifysetcc

[goldstein.w.n]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

re: 'test for -ve?' hmm?

But would generally prefer to add new tests than modify existing.

[RKSimon]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

'test for -ve' === 'test for negative'

Adding additional tests would be fine.

[goldstein.w.n]

Rebase

[foad]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4288–4289 ↗

(On Diff #523267)

Just curious: does "strengthening" conditions like this actually generate better code? Is it something we do elsewhere in the compiler?

[RKSimon]

llvm/test/CodeGen/X86/avx512-mask-op.ll

4708

Whats going on here?

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4302 ↗

(On Diff #523267)

I'm not sure this is always false?

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4288–4289 ↗

(On Diff #523267)

No worse in fact. This was really motivated by wanting to improve the knownbits analysis in selectiondag but having no good way to test it.

I think at the moment, since we don't have the infrastructure to fold basic blocks when icmp; br conditions are known true/false we end up with regressions.

Not sure exactly where this is going to go unless we add that infrastructure.

llvm/test/CodeGen/X86/avx512-mask-op.ll

4708

Its what you thought was a bad merge in the knownbits impl.

if (computeKnownBits(Op.getOperand(0)).One[0], Depth + 1)
  return true;

See the bug?

Should be:

if (computeKnownBits(Op.getOperand(0), Depth + 1).One[0])
  return true;

Suprised the former is accepted as an expression (not a clang warning/error). Its

if (expr_A, expr_B)

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

As in add a new test file? This isn't a new file for the series, its just affected by the change.

[goldstein.w.n]

Rebase (fixed bug in KnownBitsIsNeverZero)

[goldstein.w.n]

rebase

[RKSimon]

There's still a lot of tests in here that need adjusting so that they still test what we want them to test

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

I'd prefer that these tests were adjusted, the icmp_eq vs 0 was just a dumb copy + paste - but if you don't want to do that, duplicating these OR tests immediately below with a icmp_sgt 0 would be OK

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

801

this needs adjusting

llvm/test/CodeGen/X86/or-with-overflow.ll

6

All these tests need adjusting

llvm/test/CodeGen/X86/pr16031.ll

9

not sure what to do with this test - either we try to fix it so it still matches what the original bug was about, or we delete it

llvm/test/CodeGen/X86/shrink-compare.ll

128

This is no longer a shrink-compare test

[foad]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4288–4289 ↗

(On Diff #523267)

You're adding code to the compiler to change these setcc conditions, but not actually make anything better? I do not think that is a good idea.

4302 ↗

(On Diff #523267)

It's confusing but I think it's correct. From this point onwards, Res represents whether LHS and RHS are equal, irrespective of Cond.

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4288–4289 ↗

(On Diff #523267)

So worse might be a bit of a exageration. It's worse for some IR that the middle-end would never pass to us.

I was thinking maybe we could do this for SETCC not used by br. That case we see improvement. What I need to do I think though, do a little work seeing if any of the cases this changes are cases generated by the backend (i.e cases that wouldn't normally be cleaned up by the middle-end).

But I agree, in the current state its not submitable.

4302 ↗

(On Diff #523267)

I'll make it a new variable.

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1372

Ah, okay. Will do.

[goldstein.w.n]

Abandoning this revision. Still doesn't seem feasible to add this in the backend.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (OpVT.isInteger()) {
     // icmp undef, undef -> undef.
     if (N1.isUndef() && N2.isUndef())
       return getUNDEF(VT);
 
     // icmp X, X -> true/false
     // icmp X, undef -> true/false because undef could be X.
     if (N1 == N2)
       return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT);
+
+    KnownBits KnownRHS = computeKnownBits(N2);
+    if (!KnownRHS.isUnknown()) {
+      KnownBits KnownLHS = computeKnownBits(N1);
+      std::optional<bool> Res;
+      // Check if we can constant fold this with knownbits.
+      switch (Cond) {
+      case ISD::SETEQ:
+        Res = KnownBits::eq(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETNE:
+        Res = KnownBits::ne(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETLT:
+        Res = KnownBits::slt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETULT:
+        Res = KnownBits::ult(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETGT:
+        Res = KnownBits::sgt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETUGT:
+        Res = KnownBits::ugt(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETLE:
+        Res = KnownBits::sle(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETULE:
+        Res = KnownBits::ule(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETGE:
+        Res = KnownBits::sge(KnownLHS, KnownRHS);
+        break;
+      case ISD::SETUGE:
+        Res = KnownBits::uge(KnownLHS, KnownRHS);
+        break;
+      default:
+        break;
+      }
+
+      if (Res)
+        return getBoolConstant(*Res, dl, VT, OpVT);
+
+      // We aren't able to constant fold with known bits but can either 1) make
+      // conditions stronger (i.e ule -> ult) or 2) simplify with
+      // isKnownNeverZero if RHS is zero.
+      switch (Cond) {
+      case ISD::SETLE:
+      case ISD::SETULE:
+      case ISD::SETGE:
+      case ISD::SETUGE:
+        Res = KnownBits::eq(KnownLHS, KnownRHS);
+        [[fallthrough]];
+      case ISD::SETEQ:
+      case ISD::SETNE:
+        // isKnownNeverZero is able to prove cases computeKnownBits can't.
+        if (!Res && KnownRHS.isZero() && isKnownNeverZero(N1))
+          Res = false;
+        break;
+      default:
+        break;
+      }
+
+      if (Res) {
+        assert(*Res == false &&
+               "There is a bug in KnownBits::{sge,uge,sle,ule}");
+        ISD::CondCode NewCond = Cond;
+        // NB: We could remove this switch and just do `Cond ^ ISD::SETEQ` for
+        // the new opcode.
+        switch (Cond) {
+          // Remove the or eq portion of the condition.
+        case ISD::SETULE:
+          NewCond = ISD::SETULT;
+          break;
+        case ISD::SETLE:
+          NewCond = ISD::SETLT;
+          break;
+        case ISD::SETUGE:
+          NewCond = ISD::SETUGT;
+          break;
+        case ISD::SETGE:
+          NewCond = ISD::SETGT;
+          break;
+          // Evaluate to true/false.
+        case ISD::SETNE:
+          return getBoolConstant(true, dl, VT, OpVT);
+        case ISD::SETEQ:
+          return getBoolConstant(false, dl, VT, OpVT);
+        default:
+          break;
+        }
+        if (Cond != NewCond)
+          return getSetCC(dl, VT, N1, N2, NewCond);
+      }
+    }
   }
 
   if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2)) {
     const APInt &C2 = N2C->getAPIntValue();
     if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
       const APInt &C1 = N1C->getAPIntValue();
 
       return getBoolConstant(ICmpInst::compare(C1, C2, getICmpCondCode(Cond)),

llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll

entry:
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because it can be handled by one mov.
 define i8 @test2(i32 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and w8, w0, w8
-; CHECK-NEXT:    cmp w8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %a, 135
   %cmp = icmp eq i32 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because the split immediate is not valid
 ; bitmask immediate.
 define i8 @test3(i32 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #1024
+; CHECK-NEXT:    mov w8, #1024 // =0x400
 ; CHECK-NEXT:    movk w8, #33, lsl #16
 ; CHECK-NEXT:    and w8, w0, w8
 ; CHECK-NEXT:    cmp w8, #1024
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %a, 2163712
   %cmp = icmp eq i32 %and, 1024
entry:
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 define i8 @test5(i64 %a) {
 ; CHECK-LABEL: test5:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and x8, x0, #0x3ffffc000
-; CHECK-NEXT:    and x8, x8, #0xfffffffe00007fff
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 8589950976
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because it can be handled by one mov.
 define i8 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 135
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because the split immediate is not valid
 ; bitmask immediate.
 define i8 @test7(i64 %a) {
 ; CHECK-LABEL: test7:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #1024
+; CHECK-NEXT:    mov w8, #1024 // =0x400
 ; CHECK-NEXT:    movk w8, #33, lsl #16
 ; CHECK-NEXT:    and x8, x0, x8
 ; CHECK-NEXT:    cmp x8, #1024
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 2163712
   %cmp = icmp eq i64 %and, 1024

 
 ; This constant should not be split because the `and` is not loop invariant.
 define i32 @test9(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
 ; CHECK-LABEL: test9:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp w2, #1
 ; CHECK-NEXT:    b.lt .LBB8_3
 ; CHECK-NEXT:  // %bb.1: // %for.body.preheader
-; CHECK-NEXT:    mov w9, #1024
+; CHECK-NEXT:    mov w9, #1024 // =0x400
 ; CHECK-NEXT:    mov w8, w2
 ; CHECK-NEXT:    movk w9, #32, lsl #16
 ; CHECK-NEXT:  .LBB8_2: // %for.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldr w10, [x1], #4
 ; CHECK-NEXT:    subs x8, x8, #1
 ; CHECK-NEXT:    and w10, w10, w9
 ; CHECK-NEXT:    str w10, [x0], #4

 ; %7:gpr32 = ORRWrr killed %6:gpr32, %4:gpr32
 ;
 ; In this case, the constant should not be split because it causes more
 ; instructions.
 define void @test10(ptr nocapture %x, ptr nocapture readonly %y, ptr nocapture %z) {
 ; CHECK-LABEL: test10:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldr w8, [x1]
-; CHECK-NEXT:    mov w9, #1024
+; CHECK-NEXT:    mov w9, #1024 // =0x400
 ; CHECK-NEXT:    movk w9, #32, lsl #16
 ; CHECK-NEXT:    and w8, w8, w9
 ; CHECK-NEXT:    str w8, [x0]
 ; CHECK-NEXT:    ldr w8, [x1]
 ; CHECK-NEXT:    orr w8, w8, w9
 ; CHECK-NEXT:    str w8, [x2]
 ; CHECK-NEXT:    ret
 entry:

 ;
 ; MOVi32imm -1610612736
 ; SUBREG_TO_REG
 ;
 ; The constant should be zero-extended to 64 bit and it should not be split.
 define i8 @test11(i64 %a) {
 ; CHECK-LABEL: test11:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #-1610612736
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 2684354560
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }

llvm/test/CodeGen/AArch64/andcompare.ll

 ; SDISEL-LABEL: cmp_to_ands3:
 ; SDISEL:       // %bb.0:
 ; SDISEL-NEXT:    tst w0, #0x10
 ; SDISEL-NEXT:    csel w0, w1, wzr, ne
 ; SDISEL-NEXT:    ret
 ;
 ; GISEL-LABEL: cmp_to_ands3:
 ; GISEL:       // %bb.0:
-; GISEL-NEXT:    mov w8, #23
+; GISEL-NEXT:    mov w8, #23 // =0x17
 ; GISEL-NEXT:    and w8, w0, w8
 ; GISEL-NEXT:    cmp w8, #7
 ; GISEL-NEXT:    csel w0, w1, wzr, hi
 ; GISEL-NEXT:    ret
   %and = and i32 %num, 23
   %cmp = icmp ugt i32 %and, 7
   %r = select i1 %cmp, i32 %a, i32 0
   ret i32 %r
 }
 
 define i32 @cmp_to_ands4(i32 %num, i32 %a) {
 ; SDISEL-LABEL: cmp_to_ands4:
 ; SDISEL:       // %bb.0:
 ; SDISEL-NEXT:    and w8, w0, #0x30
-; SDISEL-NEXT:    tst w0, #0x20
-; SDISEL-NEXT:    csel w0, w8, w1, eq
+; SDISEL-NEXT:    cmp w8, #31
+; SDISEL-NEXT:    csel w0, w8, w1, lo
 ; SDISEL-NEXT:    ret
 ;
 ; GISEL-LABEL: cmp_to_ands4:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    and w8, w0, #0x30
 ; GISEL-NEXT:    cmp w8, #31
 ; GISEL-NEXT:    csel w0, w8, w1, ls
 ; GISEL-NEXT:    ret

llvm/test/CodeGen/AArch64/cmp-const-max.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
 
 
 define i32 @ule_64_max(i64 %p) {
-entry:
 ; CHECK-LABEL: ule_64_max:
-; CHECK: cmn x0, #1
-; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cbnz wzr, .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %ret_one
+; CHECK-NEXT:    mov w0, #1 // =0x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: // %ret_zero
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ret
+entry:
   %cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff
   br i1 %cmp, label %ret_one, label %ret_zero
 
 ret_one:
   ret i32 1
 
 ret_zero:
-; CHECK: [[RET_ZERO]]:
-; CHECK-NEXT: mov w0, wzr
   ret i32 0
 }
 
 define i32 @ugt_64_max(i64 %p) {
-entry:
 ; CHECK-LABEL: ugt_64_max:
-; CHECK: cmn x0, #1
-; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    cbnz w8, .LBB1_2
+; CHECK-NEXT:  // %bb.1: // %ret_one
+; CHECK-NEXT:    mov w0, #1 // =0x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB1_2: // %ret_zero
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ret
+entry:
   %cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff
   br i1 %cmp, label %ret_one, label %ret_zero
 
 ret_one:
   ret i32 1
 
 ret_zero:
-; CHECK: [[RET_ZERO]]:
-; CHECK-NEXT: mov w0, wzr
   ret i32 0
 }

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

 
 ;------------------------------------------------------------------------------;
 ; What if X is a constant too?
 ;------------------------------------------------------------------------------;
 
 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
 ; CHECK-LABEL: scalar_i32_x_is_const_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43605
+; CHECK-NEXT:    mov w8, #43605 // =0xaa55
 ; CHECK-NEXT:    movk w8, #43605, lsl #16
 ; CHECK-NEXT:    lsl w8, w8, w0
 ; CHECK-NEXT:    tst w8, #0x1
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t0 = shl i32 2857740885, %y
   %t1 = and i32 %t0, 1
   %res = icmp eq i32 %t1, 0
   ret i1 %res
 }
 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
 ; CHECK-LABEL: scalar_i32_x_is_const2_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1
-; CHECK-NEXT:    mov w9, #43605
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    mov w9, #43605 // =0xaa55
 ; CHECK-NEXT:    lsl w8, w8, w0
 ; CHECK-NEXT:    movk w9, #43605, lsl #16
 ; CHECK-NEXT:    tst w8, w9
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t0 = shl i32 1, %y
   %t1 = and i32 %t0, 2857740885
   %res = icmp eq i32 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #24
+; CHECK-NEXT:    mov w8, #24 // =0x18
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    and w8, w8, w0
 ; CHECK-NEXT:    ubfx w0, w8, #7, #1
 ; CHECK-NEXT:    ret
   %t0 = shl i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-128
-; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    lsl w8, w8, w1
-; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    and w8, w8, #0x80
-; CHECK-NEXT:    cmp w8, #1
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/AArch64/pr59902.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 ; This used to miscompile because foldCSELOfCSEL function
 ; doesn't check const x != y
 define i1 @test() {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #9007199254740990
-; CHECK-NEXT:    movk x8, #65503, lsl #16
-; CHECK-NEXT:    movk x8, #65407, lsl #32
-; CHECK-NEXT:    cmp x8, x8
-; CHECK-NEXT:    csel x9, x8, x8, gt
-; CHECK-NEXT:    cmp x9, x8
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %1 = select i1 false, i64 0, i64 9006649496829950
   %2 = call i64 @llvm.smax.i64(i64 %1, i64 9006649496829950)
   %3 = icmp eq i64 %2, 9006649496829950
   ret i1 %3
 }
 
 declare i64 @llvm.smax.i64(i64, i64)

llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll

; CHECK-NEXT:    ret
   %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 2>
   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i1> %cmp
 }
 
 define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_eq:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
 ; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
 ; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
   %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
   %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
   ret <4 x i1> %cmp
 }
 
 define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
 ; CHECK-LABEL: t1_all_odd_ne:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    movk w8, #43690, lsl #16
 ; CHECK-NEXT:    dup v1.4s, w8
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
 ; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
 ; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
 ; CHECK-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
   %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
   %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
   ret <4 x i1> %cmp
 }
 
 define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
 ; CHECK-LABEL: t2_narrow:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #43691
+; CHECK-NEXT:    mov w8, #43691 // =0xaaab
 ; CHECK-NEXT:    dup v1.8h, w8
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
 ; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    cmhs v0.8h, v1.8h, v0.8h
 ; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
 ; CHECK-NEXT:    xtn v0.8b, v0.8h
 ; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
   %urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>
   %cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>
   ret <8 x i1> %cmp
 }
 
 define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
 ; CHECK-LABEL: t3_wide:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-6148914691236517206
+; CHECK-NEXT:    mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
 ; CHECK-NEXT:    fmov x9, d0
 ; CHECK-NEXT:    movk x8, #43691
 ; CHECK-NEXT:    mov x10, v0.d[1]
 ; CHECK-NEXT:    mul x9, x9, x8
 ; CHECK-NEXT:    mul x8, x10, x8
 ; CHECK-NEXT:    fmov d0, x9
 ; CHECK-NEXT:    adrp x9, .LCPI4_0
 ; CHECK-NEXT:    mov v0.d[1], x8

llvm/test/CodeGen/ARM/bfi.ll

; CHECK-NEXT:    bx lr
   %cmp = icmp eq i32 %and, 0
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }
 
 define i32 @f13(i32 %x, i32 %y) {
 ; CHECK-LABEL: f13:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r2, r0, #4
-; CHECK-NEXT:    bic r0, r1, #255
-; CHECK-NEXT:    cmp r2, #42
-; CHECK-NEXT:    orrne r0, r0, #16
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    mov r1, #16
+; CHECK-NEXT:    bfi r0, r1, #0, #8
 ; CHECK-NEXT:    bx lr
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 16
   %cmp = icmp eq i32 %and, 42 ; Not comparing against zero!
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }

llvm/test/CodeGen/ARM/cmp-peephole.ll

; THUMB2-NEXT:    bx lr
   %or = or i32 %a, %b
   %res = icmp ne i32 %or, 0
   ret i1 %res
 }
 
 define i1 @cmp_ne_zero_or_ri(i32 %a) {
 ; ARM-LABEL: cmp_ne_zero_or_ri:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    orrs r0, r0, #42
-; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    mov r0, #1
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: cmp_ne_zero_or_ri:
 ; THUMB:       @ %bb.0:
-; THUMB-NEXT:    movs r1, #42
-; THUMB-NEXT:    orrs r0, r1
-; THUMB-NEXT:    subs r1, r0, #1
-; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    movs r0, #1
 ; THUMB-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: cmp_ne_zero_or_ri:
 ; THUMB2:       @ %bb.0:
-; THUMB2-NEXT:    orrs r0, r0, #42
-; THUMB2-NEXT:    it ne
-; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    movs r0, #1
 ; THUMB2-NEXT:    bx lr
   %or = or i32 %a, 42
   %res = icmp ne i32 %or, 0
   ret i1 %res
 }
 
 define i1 @cmp_ne_zero_or_rsr(i32 %a, i32 %b, i32 %c) {
 ; ARM-LABEL: cmp_ne_zero_or_rsr:

 define i1 @cmp_eq_zero_or_ri(i32 %a) {
 ; ARM-LABEL: cmp_eq_zero_or_ri:
 ; ARM:       @ %bb.0:
 ; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: cmp_eq_zero_or_ri:
 ; THUMB:       @ %bb.0:
-; THUMB-NEXT:    movs r1, #42
-; THUMB-NEXT:    orrs r0, r1
-; THUMB-NEXT:    rsbs r1, r0, #0
-; THUMB-NEXT:    adcs r0, r1
+; THUMB-NEXT:    movs r0, #0
 ; THUMB-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: cmp_eq_zero_or_ri:
 ; THUMB2:       @ %bb.0:
 ; THUMB2-NEXT:    movs r0, #0
 ; THUMB2-NEXT:    bx lr
   %or = or i32 %a, 42
   %res = icmp eq i32 %or, 0
true_br:
     br label %exit
 exit:
     ret void
 }
 
 define void @br_on_binop_lt_zero(i32 %a, i32 %b) {
 ; ARM-LABEL: br_on_binop_lt_zero:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    orr r1, r0, r1
+; ARM-NEXT:    mov r1, #1
 ; ARM-NEXT:    cmp r1, #0
-; ARM-NEXT:    bxhs lr
+; ARM-NEXT:    bxne lr
 ; ARM-NEXT:  .LBB46_1: @ %true_br
 ; ARM-NEXT:    push {r11, lr}
 ; ARM-NEXT:    bl consume
 ; ARM-NEXT:    pop {r11, lr}
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: br_on_binop_lt_zero:
 ; THUMB:       @ %bb.0:
 ; THUMB-NEXT:    push {r7, lr}
-; THUMB-NEXT:    orrs r1, r0
+; THUMB-NEXT:    movs r1, #1
 ; THUMB-NEXT:    cmp r1, #0
-; THUMB-NEXT:    bhs .LBB46_2
+; THUMB-NEXT:    bne .LBB46_2
 ; THUMB-NEXT:  @ %bb.1: @ %true_br
 ; THUMB-NEXT:    bl consume
 ; THUMB-NEXT:  .LBB46_2: @ %exit
 ; THUMB-NEXT:    pop {r7, pc}
 ;
 ; THUMB2-LABEL: br_on_binop_lt_zero:
 ; THUMB2:       @ %bb.0:
-; THUMB2-NEXT:    orrs r1, r0
+; THUMB2-NEXT:    movs r1, #1
 ; THUMB2-NEXT:    cmp r1, #0
-; THUMB2-NEXT:    it hs
-; THUMB2-NEXT:    bxhs lr
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    bxne lr
 ; THUMB2-NEXT:  .LBB46_1: @ %true_br
 ; THUMB2-NEXT:    push {r7, lr}
 ; THUMB2-NEXT:    bl consume
 ; THUMB2-NEXT:    pop.w {r7, lr}
 ; THUMB2-NEXT:    bx lr
     %or = or i32 %a, %b
     %cmp = icmp ult i32 %or, 0
     br i1 %cmp, label %true_br, label %exit
true_br:
     br label %exit
 exit:
     ret void
 }
 
 define void @br_on_shift_lt_zero(i32 %a, i32 %b) {
 ; ARM-LABEL: br_on_shift_lt_zero:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    asr r1, r0, r1
+; ARM-NEXT:    mov r1, #1
 ; ARM-NEXT:    cmp r1, #0
-; ARM-NEXT:    bxhs lr
+; ARM-NEXT:    bxne lr
 ; ARM-NEXT:  .LBB53_1: @ %true_br
 ; ARM-NEXT:    push {r11, lr}
 ; ARM-NEXT:    bl consume
 ; ARM-NEXT:    pop {r11, lr}
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB-LABEL: br_on_shift_lt_zero:
 ; THUMB:       @ %bb.0:
 ; THUMB-NEXT:    push {r7, lr}
-; THUMB-NEXT:    mov r2, r0
-; THUMB-NEXT:    asrs r2, r1
-; THUMB-NEXT:    cmp r2, #0
-; THUMB-NEXT:    bhs .LBB53_2
+; THUMB-NEXT:    movs r1, #1
+; THUMB-NEXT:    cmp r1, #0
+; THUMB-NEXT:    bne .LBB53_2
 ; THUMB-NEXT:  @ %bb.1: @ %true_br
 ; THUMB-NEXT:    bl consume
 ; THUMB-NEXT:  .LBB53_2: @ %exit
 ; THUMB-NEXT:    pop {r7, pc}
 ;
 ; THUMB2-LABEL: br_on_shift_lt_zero:
 ; THUMB2:       @ %bb.0:
-; THUMB2-NEXT:    asr.w r1, r0, r1
+; THUMB2-NEXT:    movs r1, #1
 ; THUMB2-NEXT:    cmp r1, #0
-; THUMB2-NEXT:    it hs
-; THUMB2-NEXT:    bxhs lr
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    bxne lr
 ; THUMB2-NEXT:  .LBB53_1: @ %true_br
 ; THUMB2-NEXT:    push {r7, lr}
 ; THUMB2-NEXT:    bl consume
 ; THUMB2-NEXT:    pop.w {r7, lr}
 ; THUMB2-NEXT:    bx lr
     %sh = ashr i32 %a, %b
     %cmp = icmp ult i32 %sh, 0
     br i1 %cmp, label %true_br, label %exit

llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

; THUMB78-NEXT:    bx lr
   ret i1 %res
 }
 
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
 
 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM6:       @ %bb.0:
-; ARM6-NEXT:    uxtb r1, r1
-; ARM6-NEXT:    mov r2, #24
-; ARM6-NEXT:    ands r0, r0, r2, lsr r1
-; ARM6-NEXT:    mov r0, #0
-; ARM6-NEXT:    movmi r0, #1
-; ARM6-NEXT:    bx lr
-;
-; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM78:       @ %bb.0:
-; ARM78-NEXT:    uxtb r1, r1
-; ARM78-NEXT:    mov r2, #24
-; ARM78-NEXT:    ands r0, r0, r2, lsr r1
-; ARM78-NEXT:    mov r0, #0
-; ARM78-NEXT:    movwmi r0, #1
-; ARM78-NEXT:    bx lr
-;
-; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #24
-; THUMB6-NEXT:    lsrs r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    bmi .LBB20_2
-; THUMB6-NEXT:  @ %bb.1:
-; THUMB6-NEXT:    movs r0, #0
-; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:  .LBB20_2:
-; THUMB6-NEXT:    movs r0, #1
-; THUMB6-NEXT:    bx lr
+; ARM-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mov r0, #0
+; ARM-NEXT:    bx lr
 ;
-; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    uxtb r1, r1
-; THUMB78-NEXT:    movs r2, #24
-; THUMB78-NEXT:    lsr.w r1, r2, r1
-; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    mov.w r0, #0
-; THUMB78-NEXT:    it mi
-; THUMB78-NEXT:    movmi r0, #1
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:

llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; ARM:       @ %bb.0:
 ; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
-; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #127
-; THUMB6-NEXT:    mvns r2, r2
-; THUMB6-NEXT:    lsls r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    uxtb r0, r2
-; THUMB6-NEXT:    subs r1, r0, #1
-; THUMB6-NEXT:    rsbs r0, r1, #0
-; THUMB6-NEXT:    adcs r0, r1
-; THUMB6-NEXT:    bx lr
-;
-; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    movs r0, #0
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: scalar_i8_signbit_eq_with_nonzero:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/ARM/sub-cmp-peephole.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
 
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: f:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    subs r0, r0, r1
+; V8-NEXT:    movle r0, #0
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: f:
-; CHECK: subs
-; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, %b
   %sub = sub nsw i32 %a, %b
   %sub. = select i1 %cmp, i32 %sub, i32 0
   ret i32 %sub.
 }
 
 define i32 @g(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: g:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    subs r0, r1, r0
+; V8-NEXT:    movle r0, #0
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: g:
-; CHECK: subs
-; CHECK-NOT: cmp
   %cmp = icmp slt i32 %a, %b
   %sub = sub nsw i32 %b, %a
   %sub. = select i1 %cmp, i32 %sub, i32 0
   ret i32 %sub.
 }
 
 define i32 @h(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: h:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    subs r0, r0, #3
+; V8-NEXT:    movle r0, r1
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: h:
-; CHECK: subs
-; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, 3
   %sub = sub nsw i32 %a, 3
   %sub. = select i1 %cmp, i32 %sub, i32 %b
   ret i32 %sub.
 }
 
 ; rdar://11725965
 define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
+; V8-LABEL: i:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    subs r0, r1, r0
+; V8-NEXT:    movls r0, #0
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: i:
-; CHECK: subs
-; CHECK-NOT: cmp
   %cmp = icmp ult i32 %a, %b
   %sub = sub i32 %b, %a
   %sub. = select i1 %cmp, i32 %sub, i32 0
   ret i32 %sub.
 }
 ; If CPSR is live-out, we can't remove cmp if there exists
 ; a swapped sub.
 define i32 @j(i32 %a, i32 %b) nounwind {
+; V8-LABEL: j:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    subs r1, r0, r1
+; V8-NEXT:    movlt r0, r1
+; V8-NEXT:    movne r0, r1
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: j:
-; CHECK: sub
-; CHECK: cmp
   %cmp = icmp eq i32 %b, %a
   %sub = sub nsw i32 %a, %b
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
   %cmp2 = icmp sgt i32 %b, %a
   %sel = select i1 %cmp2, i32 %sub, i32 %a
   ret i32 %sel
 
 if.else:
   ret i32 %sub
 }
 
 ; If the sub/rsb instruction is predicated, we can't use the flags.
 ; <rdar://problem/12263428>
 ; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
 ; CHECK: bc_raise
 ; CHECK: rsbeq
 ; CHECK: cmp
 define i32 @bc_raise(i1 %cond) nounwind ssp {
+; V8-LABEL: bc_raise:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    mov r1, #1
+; V8-NEXT:    tst r0, #1
+; V8-NEXT:    bic r1, r1, r0
+; V8-NEXT:    mov r0, #23
+; V8-NEXT:    rsbeq r1, r1, #0
+; V8-NEXT:    cmp r1, #0
+; V8-NEXT:    movweq r0, #17
+; V8-NEXT:    bx lr
 entry:
   %val.2.i = select i1 %cond, i32 0, i32 1
   %sub.i = sub nsw i32 0, %val.2.i
   %retval.0.i = select i1 %cond, i32 %val.2.i, i32 %sub.i
   %cmp1 = icmp eq i32 %retval.0.i, 0
   br i1 %cmp1, label %land.lhs.true, label %if.end11
 
 land.lhs.true:                                    ; preds = %num2long.exit
   ret i32 17
 
 if.end11:                                         ; preds = %num2long.exit
   ret i32 23
 }
 
 ; When considering the producer of cmp's src as the subsuming instruction,
 ; only consider that when the comparison is to 0.
 define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_src_nonzero:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    sub r0, r0, r1
+; V8-NEXT:    cmp r0, #17
+; V8-NEXT:    movne r2, r3
+; V8-NEXT:    mov r0, r2
+; V8-NEXT:    bx lr
 entry:
-; CHECK-LABEL: cmp_src_nonzero:
-; CHECK: sub
-; CHECK: cmp
   %sub = sub i32 %a, %b
   %cmp = icmp eq i32 %sub, 17
   %ret = select i1 %cmp, i32 %x, i32 %y
   ret i32 %ret
 }
 
 define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
-entry:
-; CHECK-LABEL: float_sel:
-; CHECK-NOT: cmp
 ; V8-LABEL: float_sel:
-; V8-NOT: cmp
-; V8: vseleq.f32
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    vmov s0, r3
+; V8-NEXT:    subs r0, r0, r1
+; V8-NEXT:    vmov s2, r2
+; V8-NEXT:    vseleq.f32 s0, s2, s0
+; V8-NEXT:    vmov r0, s0
+; V8-NEXT:    bx lr
+entry:
   %sub = sub i32 %a, %b
   %cmp = icmp eq i32 %sub, 0
   %ret = select i1 %cmp, float %x, float %y
   ret float %ret
 }
 
 define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; CHECK-LABEL: double_sel:
-; CHECK-NOT: cmp
 ; V8-LABEL: double_sel:
-; V8-NOT: cmp
-; V8: vseleq.f64
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    vldr d16, [sp]
+; V8-NEXT:    vmov d17, r2, r3
+; V8-NEXT:    subs r0, r0, r1
+; V8-NEXT:    vseleq.f64 d16, d17, d16
+; V8-NEXT:    vmov r0, r1, d16
+; V8-NEXT:    bx lr
+entry:
   %sub = sub i32 %a, %b
   %cmp = icmp eq i32 %sub, 0
   %ret = select i1 %cmp, double %x, double %y
   ret double %ret
 }
 
 @t = common global i32 0
 define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; CHECK-LABEL: double_sub:
-; CHECK: subs
-; CHECK-NOT: cmp
 ; V8-LABEL: double_sub:
-; V8: vsel
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    vldr d16, [sp]
+; V8-NEXT:    cmp r0, r1
+; V8-NEXT:    vmov d17, r2, r3
+; V8-NEXT:    sub r0, r0, r1
+; V8-NEXT:    vselgt.f64 d16, d17, d16
+; V8-NEXT:    movw r1, :lower16:t
+; V8-NEXT:    vmov r2, r3, d16
+; V8-NEXT:    movt r1, :upper16:t
+; V8-NEXT:    str r0, [r1]
+; V8-NEXT:    mov r0, r2
+; V8-NEXT:    mov r1, r3
+; V8-NEXT:    bx lr
+entry:
   %cmp = icmp sgt i32 %a, %b
   %sub = sub i32 %a, %b
   store i32 %sub, ptr @t
   %ret = select i1 %cmp, double %x, double %y
   ret double %ret
 }
 
 define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; V7-LABEL: double_sub_swap:
-; V7-NOT: cmp
-; V7: subs
 ; V8-LABEL: double_sub_swap:
-; V8-NOT: subs
-; V8: cmp
-; V8: vsel
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    vldr d16, [sp]
+; V8-NEXT:    cmp r1, r0
+; V8-NEXT:    vmov d17, r2, r3
+; V8-NEXT:    sub r0, r1, r0
+; V8-NEXT:    vselge.f64 d16, d16, d17
+; V8-NEXT:    movw r1, :lower16:t
+; V8-NEXT:    vmov r2, r3, d16
+; V8-NEXT:    movt r1, :upper16:t
+; V8-NEXT:    str r0, [r1]
+; V8-NEXT:    mov r0, r2
+; V8-NEXT:    mov r1, r3
+; V8-NEXT:    bx lr
+entry:
   %cmp = icmp sgt i32 %a, %b
   %sub = sub i32 %b, %a
   %ret = select i1 %cmp, double %x, double %y
   store i32 %sub, ptr @t
   ret double %ret
 }
 
 declare void @abort()
 declare void @exit(i32)
 
 ; If the comparison uses the V bit (signed overflow/underflow), we can't
 ; omit the comparison.
 define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_slt0:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    .save {r11, lr}
+; V8-NEXT:    push {r11, lr}
+; V8-NEXT:    movw r0, :lower16:t
+; V8-NEXT:    movt r0, :upper16:t
+; V8-NEXT:    ldr r0, [r0]
+; V8-NEXT:    sub r0, r0, #17
+; V8-NEXT:    cmn r0, #1
+; V8-NEXT:    ble .LBB11_2
+; V8-NEXT:  @ %bb.1: @ %if.else
+; V8-NEXT:    mov r0, #0
+; V8-NEXT:    bl exit
+; V8-NEXT:  .LBB11_2: @ %if.then
+; V8-NEXT:    bl abort
 entry:
-; CHECK-LABEL: cmp_slt0
-; CHECK: sub
-; CHECK: cmn
-; CHECK: ble
   %load = load i32, ptr @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp slt i32 %sub, 0
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
   call void @abort()
   unreachable
 
 if.else:
   call void @exit(i32 0)
   unreachable
 }
 
 ; Same for the C bit. (Note the ult X, 0 is trivially
 ; false, so the DAG combiner may or may not optimize it).
 define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_ult0:
+; V8:       @ %bb.0: @ %entry
+; V8-NEXT:    .save {r11, lr}
+; V8-NEXT:    push {r11, lr}
+; V8-NEXT:    mov r0, #1
+; V8-NEXT:    cmp r0, #0
+; V8-NEXT:    bne .LBB12_2
+; V8-NEXT:  @ %bb.1: @ %if.then
+; V8-NEXT:    bl abort
+; V8-NEXT:  .LBB12_2: @ %if.else
+; V8-NEXT:    mov r0, #0
+; V8-NEXT:    bl exit
 entry:
-; CHECK-LABEL: cmp_ult0
-; CHECK: sub
-; CHECK: cmp
-; CHECK: bhs
   %load = load i32, ptr @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp ult i32 %sub, 0
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:
   call void @abort()
   unreachable
 
 if.else:
   call void @exit(i32 0)
   unreachable
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; V7: {{.*}}

llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
 
 ; Check that this compiles successfully.
 
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon"
 
 define i32 @fred(ptr %a0) #0 {
 ; CHECK-LABEL: fred:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     if (p0) jump:nt .LBB0_2
-; CHECK-NEXT:    }
-; CHECK-NEXT:  // %bb.1: // %b2
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r3:2 = combine(#0,#0)
-; CHECK-NEXT:     r1:0 = memd(r0+#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = vcmph.eq(r1:0,r3:2)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r1:0 = mask(p0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = and(r0,#1)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = cmp.eq(r0,#11)
-; CHECK-NEXT:     r0 = #1
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
+; CHECK-NEXT:     if (!p0) r0 = #1
 ; CHECK-NEXT:     if (p0) r0 = #0
 ; CHECK-NEXT:     jumpr r31
 ; CHECK-NEXT:    }
-; CHECK-NEXT:  .LBB0_2: // %b14
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = #0
-; CHECK-NEXT:     jumpr r31
-; CHECK-NEXT:    }
 b0:
   switch i32 undef, label %b14 [
     i32 5, label %b2
     i32 3, label %b1
   ]
 
 b1:                                               ; preds = %b0
   br label %b14

llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll

 
 ; If the comparison uses the C bit (signed overflow/underflow), we can't
 ; omit the comparison.
 define i32 @cmp_ult0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {
 ; CHECK-LABEL: cmp_ult0:
 ; CHECK:       ! %bb.0: ! %entry
 ; CHECK-NEXT:    st %fp, [--%sp]
 ; CHECK-NEXT:    add %sp, 0x8, %fp
-; CHECK-NEXT:    mov hi(t), %r3
-; CHECK-NEXT:    or %r3, lo(t), %r3
-; CHECK-NEXT:    ld 0[%r3], %r3
-; CHECK-NEXT:    sub %r3, 0x11, %r3
+; CHECK-NEXT:    mov 0x1, %r3
 ; CHECK-NEXT:    sub.f %r3, 0x0, %r0
-; CHECK-NEXT:    buge .LBB5_2
+; CHECK-NEXT:    bne .LBB5_2
 ; CHECK-NEXT:    sub %sp, 0x10, %sp
 ; CHECK-NEXT:  .LBB5_1: ! %if.then
 ; CHECK-NEXT:    add %pc, 0x10, %rca
 ; CHECK-NEXT:    st %rca, [--%sp]
 ; CHECK-NEXT:    bt abort
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB5_2: ! %if.else
 ; CHECK-NEXT:    st %r0, 0[%sp]

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:    addi a0, sp, 8
 ; RV32IF-NEXT:    call __fixunsdfti@plt
 ; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    lw a1, 20(sp)
 ; RV32IF-NEXT:    lw a2, 12(sp)
 ; RV32IF-NEXT:    lw a3, 8(sp)
-; RV32IF-NEXT:    or a4, a1, a0
-; RV32IF-NEXT:    seqz a4, a4
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    or a0, a0, a1
-; RV32IF-NEXT:    seqz a0, a0
-; RV32IF-NEXT:    addi a0, a0, -1
-; RV32IF-NEXT:    and a0, a0, a4
-; RV32IF-NEXT:    neg a1, a0
+; RV32IF-NEXT:    or a0, a1, a0
+; RV32IF-NEXT:    snez a0, a0
+; RV32IF-NEXT:    addi a1, a0, -1
 ; RV32IF-NEXT:    and a0, a1, a3
 ; RV32IF-NEXT:    and a1, a1, a2
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f64i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixunsdfti@plt
 ; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    lw a1, 20(sp)
 ; RV32IFD-NEXT:    lw a2, 12(sp)
 ; RV32IFD-NEXT:    lw a3, 8(sp)
-; RV32IFD-NEXT:    or a4, a1, a0
-; RV32IFD-NEXT:    seqz a4, a4
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    or a0, a0, a1
-; RV32IFD-NEXT:    seqz a0, a0
-; RV32IFD-NEXT:    addi a0, a0, -1
-; RV32IFD-NEXT:    and a0, a0, a4
-; RV32IFD-NEXT:    neg a1, a0
+; RV32IFD-NEXT:    or a0, a1, a0
+; RV32IFD-NEXT:    snez a0, a0
+; RV32IFD-NEXT:    addi a1, a0, -1
 ; RV32IFD-NEXT:    and a0, a1, a3
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptoui double %x to i128
   %0 = icmp ult i128 %conv, 18446744073709551616

 ; RV32IF-NEXT:    beqz a1, .LBB20_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a2, a1, 0
 ; RV32IF-NEXT:    j .LBB20_3
 ; RV32IF-NEXT:  .LBB20_2:
 ; RV32IF-NEXT:    seqz a2, a0
 ; RV32IF-NEXT:  .LBB20_3: # %entry
 ; RV32IF-NEXT:    lw a3, 12(sp)
-; RV32IF-NEXT:    xori a4, a0, 1
-; RV32IF-NEXT:    or a4, a4, a1
-; RV32IF-NEXT:    seqz a4, a4
-; RV32IF-NEXT:    addi a4, a4, -1
-; RV32IF-NEXT:    and a2, a4, a2
 ; RV32IF-NEXT:    neg a4, a2
 ; RV32IF-NEXT:    bnez a2, .LBB20_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB20_5: # %entry
 ; RV32IF-NEXT:    lw a5, 8(sp)
 ; RV32IF-NEXT:    and a2, a4, a1
 ; RV32IF-NEXT:    and a1, a4, a3

 ; RV32IFD-NEXT:    beqz a1, .LBB20_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    slti a2, a1, 0
 ; RV32IFD-NEXT:    j .LBB20_3
 ; RV32IFD-NEXT:  .LBB20_2:
 ; RV32IFD-NEXT:    seqz a2, a0
 ; RV32IFD-NEXT:  .LBB20_3: # %entry
 ; RV32IFD-NEXT:    lw a3, 12(sp)
-; RV32IFD-NEXT:    xori a4, a0, 1
-; RV32IFD-NEXT:    or a4, a4, a1
-; RV32IFD-NEXT:    seqz a4, a4
-; RV32IFD-NEXT:    addi a4, a4, -1
-; RV32IFD-NEXT:    and a2, a4, a2
 ; RV32IFD-NEXT:    neg a4, a2
 ; RV32IFD-NEXT:    bnez a2, .LBB20_5
 ; RV32IFD-NEXT:  # %bb.4: # %entry
 ; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB20_5: # %entry
 ; RV32IFD-NEXT:    lw a5, 8(sp)
 ; RV32IFD-NEXT:    and a2, a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a3

 ; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixunssfti@plt
 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    or a4, a1, a0
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    xori a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    neg a1, a0
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    snez a0, a0
+; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a1, a1, a2
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f32i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32-NEXT:    beqz a1, .LBB23_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB23_3
 ; RV32-NEXT:  .LBB23_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB23_3: # %entry
 ; RV32-NEXT:    lw a3, 12(sp)
-; RV32-NEXT:    xori a4, a0, 1
-; RV32-NEXT:    or a4, a4, a1
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a2, a4, a2
 ; RV32-NEXT:    neg a4, a2
 ; RV32-NEXT:    bnez a2, .LBB23_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB23_5: # %entry
 ; RV32-NEXT:    lw a5, 8(sp)
 ; RV32-NEXT:    and a2, a4, a1
 ; RV32-NEXT:    and a1, a4, a3

 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixunssfti@plt
 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    or a4, a1, a0
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    xori a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    neg a1, a0
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    snez a0, a0
+; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
 ; RV32-NEXT:    and a1, a1, a2
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utesth_f16i64:
 ; RV64:       # %bb.0: # %entry

 ; RV32-NEXT:    beqz a1, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB26_3
 ; RV32-NEXT:  .LBB26_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB26_3: # %entry
 ; RV32-NEXT:    lw a3, 12(sp)
-; RV32-NEXT:    xori a4, a0, 1
-; RV32-NEXT:    or a4, a4, a1
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a2, a4, a2
 ; RV32-NEXT:    neg a4, a2
 ; RV32-NEXT:    bnez a2, .LBB26_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB26_5: # %entry
 ; RV32-NEXT:    lw a5, 8(sp)
 ; RV32-NEXT:    and a2, a4, a1
 ; RV32-NEXT:    and a1, a4, a3

llvm/test/CodeGen/RISCV/sextw-removal.ll

 
 declare i64 @llvm.ctpop.i64(i64)
 
 define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    sraw a0, a0, a1
+; CHECK-NEXT:    li s0, 1
 ; CHECK-NEXT:  .LBB7_1: # %bb2
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    call foo@plt
 ; CHECK-NEXT:    ori a0, a0, -256
-; CHECK-NEXT:    bnez a0, .LBB7_1
+; CHECK-NEXT:    bnez s0, .LBB7_1
 ; CHECK-NEXT:  # %bb.2: # %bb7
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
 ;
 ; NOREMOVAL-LABEL: test8:
 ; NOREMOVAL:       # %bb.0: # %bb
 ; NOREMOVAL-NEXT:    addi sp, sp, -16
 ; NOREMOVAL-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; NOREMOVAL-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; NOREMOVAL-NEXT:    sraw a0, a0, a1
+; NOREMOVAL-NEXT:    li s0, 1
 ; NOREMOVAL-NEXT:  .LBB7_1: # %bb2
 ; NOREMOVAL-NEXT:    # =>This Inner Loop Header: Depth=1
 ; NOREMOVAL-NEXT:    sext.w a0, a0
 ; NOREMOVAL-NEXT:    call foo@plt
 ; NOREMOVAL-NEXT:    ori a0, a0, -256
-; NOREMOVAL-NEXT:    bnez a0, .LBB7_1
+; NOREMOVAL-NEXT:    bnez s0, .LBB7_1
 ; NOREMOVAL-NEXT:  # %bb.2: # %bb7
 ; NOREMOVAL-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; NOREMOVAL-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; NOREMOVAL-NEXT:    addi sp, sp, 16
 ; NOREMOVAL-NEXT:    ret
 bb:
   %i = ashr i32 %arg, %arg1
   br label %bb2
 
 bb2:                                              ; preds = %bb2, %bb
   %i3 = phi i32 [ %i, %bb ], [ %i6, %bb2 ]

llvm/test/CodeGen/SystemZ/int-cmp-46.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; Test the use of TEST UNDER MASK for 32-bit operations.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 @g = global i32 0
 
 ; Check the lowest useful TMLL value.
 define void @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: tmll %r2, 1
-; CHECK: ber %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 1
+; CHECK-NEXT:    ber %r14
+; CHECK-NEXT:  .LBB0_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 1
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the high end of the TMLL range.
 define void @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: tmll %r2, 65535
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 65535
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB1_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 65535
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the lowest useful TMLH value, which is the next value up.
 define void @f3(i32 %a) {
 ; CHECK-LABEL: f3:
-; CHECK: tmlh %r2, 1
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmlh %r2, 1
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB2_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 65536
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the next value up again, which cannot use TM.
 define void @f4(i32 %a) {
 ; CHECK-LABEL: f4:
-; CHECK-NOT: {{tm[lh].}}
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    nilh %r2, 65534
+; CHECK-NEXT:    cibe %r2, 0, 0(%r14)
+; CHECK-NEXT:  .LBB3_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 4294901759
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the high end of the TMLH range.
 define void @f5(i32 %a) {
 ; CHECK-LABEL: f5:
-; CHECK: tmlh %r2, 65535
-; CHECK: ber %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmlh %r2, 65535
+; CHECK-NEXT:    ber %r14
+; CHECK-NEXT:  .LBB4_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 4294901760
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that are equivalent to
 ; an equality comparison with zero.
 define void @f6(i32 %a) {
 ; CHECK-LABEL: f6:
-; CHECK: tmll %r2, 240
-; CHECK: ber %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 240
+; CHECK-NEXT:    ber %r14
+; CHECK-NEXT:  .LBB5_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp slt i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f7(i32 %a) {
 ; CHECK-LABEL: f7:
-; CHECK: tmll %r2, 240
-; CHECK: ber %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 240
+; CHECK-NEXT:    ber %r14
+; CHECK-NEXT:  .LBB6_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp sle i32 %and, 15
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that are equivalent to
 ; an inequality comparison with zero.
 define void @f8(i32 %a) {
 ; CHECK-LABEL: f8:
-; CHECK: tmll %r2, 240
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 240
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB7_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp uge i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with GT.
 define void @f9(i32 %a) {
 ; CHECK-LABEL: f9:
-; CHECK: tmll %r2, 240
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 240
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB8_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp ugt i32 %and, 15
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that effectively
 ; test whether the top bit is clear.
 define void @f10(i32 %a) {
 ; CHECK-LABEL: f10:
-; CHECK: tmll %r2, 35
-; CHECK: bler %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 35
+; CHECK-NEXT:    bler %r14
+; CHECK-NEXT:  .LBB9_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 35
   %cmp = icmp ult i32 %and, 8
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f11(i32 %a) {
 ; CHECK-LABEL: f11:
-; CHECK: tmll %r2, 35
-; CHECK: bler %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 35
+; CHECK-NEXT:    bler %r14
+; CHECK-NEXT:  .LBB10_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 35
   %cmp = icmp ule i32 %and, 31
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that effectively test
 ; whether the top bit is set.
 define void @f12(i32 %a) {
 ; CHECK-LABEL: f12:
-; CHECK: tmll %r2, 140
-; CHECK: bnler %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 140
+; CHECK-NEXT:    bnler %r14
+; CHECK-NEXT:  .LBB11_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 140
   %cmp = icmp uge i32 %and, 128
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again for GT.
 define void @f13(i32 %a) {
 ; CHECK-LABEL: f13:
-; CHECK: tmll %r2, 140
-; CHECK: bnler %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 140
+; CHECK-NEXT:    bnler %r14
+; CHECK-NEXT:  .LBB12_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 140
   %cmp = icmp ugt i32 %and, 126
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons with the mask.
 define void @f14(i32 %a) {
 ; CHECK-LABEL: f14:
-; CHECK: tmll %r2, 101
-; CHECK: bor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 101
+; CHECK-NEXT:    bor %r14
+; CHECK-NEXT:  .LBB13_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 101
   %cmp = icmp eq i32 %and, 101
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons with the mask.
 define void @f15(i32 %a) {
 ; CHECK-LABEL: f15:
-; CHECK: tmll %r2, 65519
-; CHECK: bnor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 65519
+; CHECK-NEXT:    bnor %r14
+; CHECK-NEXT:  .LBB14_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 65519
   %cmp = icmp ne i32 %and, 65519
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that are equivalent
 ; to inequality comparisons with the mask.
 define void @f16(i32 %a) {
 ; CHECK-LABEL: f16:
-; CHECK: tmll %r2, 130
-; CHECK: bnor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 130
+; CHECK-NEXT:    bnor %r14
+; CHECK-NEXT:  .LBB15_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 130
   %cmp = icmp ult i32 %and, 129
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f17(i32 %a) {
 ; CHECK-LABEL: f17:
-; CHECK: tmll %r2, 130
-; CHECK: bnor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 130
+; CHECK-NEXT:    bnor %r14
+; CHECK-NEXT:  .LBB16_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 130
   %cmp = icmp ule i32 %and, 128
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that are equivalent
 ; to equality comparisons with the mask.
 define void @f18(i32 %a) {
 ; CHECK-LABEL: f18:
-; CHECK: tmll %r2, 194
-; CHECK: bor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 194
+; CHECK-NEXT:    bor %r14
+; CHECK-NEXT:  .LBB17_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 194
   %cmp = icmp uge i32 %and, 193
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again for GT.
 define void @f19(i32 %a) {
 ; CHECK-LABEL: f19:
-; CHECK: tmll %r2, 194
-; CHECK: bor %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 194
+; CHECK-NEXT:    bor %r14
+; CHECK-NEXT:  .LBB18_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 194
   %cmp = icmp ugt i32 %and, 192
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons for the low bit
 ; when the mask has two bits.
 define void @f20(i32 %a) {
 ; CHECK-LABEL: f20:
-; CHECK: tmll %r2, 20
-; CHECK: blr %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 20
+; CHECK-NEXT:    blr %r14
+; CHECK-NEXT:  .LBB19_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp eq i32 %and, 4
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons for the low bit
 ; when the mask has two bits.
 define void @f21(i32 %a) {
 ; CHECK-LABEL: f21:
-; CHECK: tmll %r2, 20
-; CHECK: bnlr %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 20
+; CHECK-NEXT:    bnlr %r14
+; CHECK-NEXT:  .LBB20_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp ne i32 %and, 4
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons for the high bit
 ; when the mask has two bits.
 define void @f22(i32 %a) {
 ; CHECK-LABEL: f22:
-; CHECK: tmll %r2, 20
-; CHECK: bhr %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 20
+; CHECK-NEXT:    bhr %r14
+; CHECK-NEXT:  .LBB21_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp eq i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons for the high bit
 ; when the mask has two bits.
 define void @f23(i32 %a) {
 ; CHECK-LABEL: f23:
-; CHECK: tmll %r2, 20
-; CHECK: bnhr %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 20
+; CHECK-NEXT:    bnhr %r14
+; CHECK-NEXT:  .LBB22_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp ne i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHL into a TMxx mask.
 define void @f24(i32 %a) {
 ; CHECK-LABEL: f24:
-; CHECK: tmll %r2, 255
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmll %r2, 255
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB23_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %shl = shl i32 %a, 12
   %and = and i32 %shl, 1044480
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHR into a TMxx mask.
 define void @f25(i32 %a) {
 ; CHECK-LABEL: f25:
-; CHECK: tmlh %r2, 512
-; CHECK: bner %r14
-; CHECK: br %r14
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    tmlh %r2, 512
+; CHECK-NEXT:    bner %r14
+; CHECK-NEXT:  .LBB24_1: # %store
+; CHECK-NEXT:    lgrl %r1, g@GOT
+; CHECK-NEXT:    mvhi 0(%r1), 1
+; CHECK-NEXT:    br %r14
 entry:
   %shr = lshr i32 %a, 25
   %and = and i32 %shr, 1
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, ptr@g
   br label %exit
 
 exit:
   ret void
 }

llvm/test/CodeGen/SystemZ/int-cmp-47.ll

exit:
   ret void
 }
 
 ; Check that we don't fold a shift if the comparison value
 ; would need to be shifted out of range
 define void @f19(i64 %a) {
 ; CHECK-LABEL: f19:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    srlg %r0, %r2, 63
-; CHECK-NEXT:    cgibl %r0, 3, 0(%r14)
+; CHECK-NEXT:    lhi %r0, 1
+; CHECK-NEXT:    ciblh %r0, 0, 0(%r14)
 ; CHECK-NEXT:  .LBB18_1: # %store
 ; CHECK-NEXT:    lgrl %r1, g@GOT
 ; CHECK-NEXT:    mvhi 0(%r1), 1
 ; CHECK-NEXT:    br %r14
 entry:
   %shr = lshr i64 %a, 63
   %cmp = icmp ult i64 %shr, 3
   br i1 %cmp, label %exit, label %store

llvm/test/CodeGen/Thumb/cmp-and-fold.ll

if.end:
   ret void
 }
 
 define void @test6(i32 %x, ptr %f)  {
 ; CHECK-LABEL: test6:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    movs r2, #32
-; CHECK-NEXT:    ands r2, r0
-; CHECK-NEXT:    cmp r2, #17
-; CHECK-NEXT:    beq .LBB5_2
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    bne .LBB5_2
 ; CHECK-NEXT:  @ %bb.1: @ %if.then
 ; CHECK-NEXT:    blx r1
 ; CHECK-NEXT:  .LBB5_2: @ %if.end
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %a = and i32 %x, 32
   %cmp = icmp eq i32 %a, 17
   br i1 %cmp, label %if.end, label %if.then

llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define signext i16 @f(ptr %bp, ptr %ss)   {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movb $1, %cl
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %cond_next127
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl (%eax), %edx
-; CHECK-NEXT:    movl (%ecx), %esi
 ; CHECK-NEXT:    andl $15, %edx
-; CHECK-NEXT:    andl $15, %esi
-; CHECK-NEXT:    addl %esi, (%ecx)
-; CHECK-NEXT:    cmpl $63, %edx
-; CHECK-NEXT:    jb .LBB0_1
+; CHECK-NEXT:    addl %edx, (%eax)
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %UnifiedReturnBlock
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    popl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 entry:
   br label %cond_next127
 
 cond_next127:   ; preds = %cond_next391, %entry
   %v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ]    ; <i32> [#uses=1]
   %tmp149 = mul i32 0, %v.1   ; <i32> [#uses=0]
   %tmpss = load i32, ptr %ss, align 4    ; <i32> [#uses=1]

llvm/test/CodeGen/X86/2012-08-17-legalizer-crash.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s | FileCheck %s
 ; Check that an overly large immediate created by SROA doesn't crash the
 ; legalizer.
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
 %struct._GtkSheetRow = type { ptr, i32, i32, i32, %struct._GtkSheetButton, i32, i32 }
 %struct._GtkSheetButton = type { i32, ptr, i32, ptr, i32 }
 
 @a = common global ptr null, align 8
 
 define void @fn1() nounwind uwtable ssp {
+; CHECK-LABEL: fn1:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq _a@GOTPCREL(%rip), %rax
+; CHECK-NEXT:    movq (%rax), %rax
+; CHECK-NEXT:    movq 64(%rax), %rcx
+; CHECK-NEXT:    movq %rcx, %rdx
+; CHECK-NEXT:    shrq $32, %rdx
+; CHECK-NEXT:    je LBB0_2
+; CHECK-NEXT:  ## %bb.1: ## %if.then
+; CHECK-NEXT:    movq 56(%rax), %rdx
+; CHECK-NEXT:    movq 48(%rax), %rsi
+; CHECK-NEXT:    movq 40(%rax), %rdi
+; CHECK-NEXT:    movq 32(%rax), %r8
+; CHECK-NEXT:    movq 24(%rax), %r9
+; CHECK-NEXT:    movq 16(%rax), %r10
+; CHECK-NEXT:    movq (%rax), %r11
+; CHECK-NEXT:    movq 8(%rax), %rbx
+; CHECK-NEXT:    movq %r11, (%rax)
+; CHECK-NEXT:    movq %rbx, 8(%rax)
+; CHECK-NEXT:    movq %r10, 16(%rax)
+; CHECK-NEXT:    movq %r9, 24(%rax)
+; CHECK-NEXT:    movq %r8, 32(%rax)
+; CHECK-NEXT:    movq %rdi, 40(%rax)
+; CHECK-NEXT:    movq %rsi, 48(%rax)
+; CHECK-NEXT:    movq %rdx, 56(%rax)
+; CHECK-NEXT:    movq %rcx, 64(%rax)
+; CHECK-NEXT:  LBB0_2: ## %if.end
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
 entry:
   %0 = load ptr, ptr @a, align 8
   %srcval2 = load i576, ptr %0, align 8
   %tobool = icmp ugt i576 %srcval2, 57586096570152913699974892898380567793532123114264532903689671329431521032595044740083720782129802971518987656109067457577065805510327036019308994315074097345724415
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   store i576 %srcval2, ptr %0, align 8
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 
-; CHECK-LABEL: fn1:
-; CHECK: jb
 }

llvm/test/CodeGen/X86/avx512-mask-op.ll

 true:
   ret void
 
 false:
   ret void
 }
 
 define void @test7(<8 x i1> %mask)  {
-; KNL-LABEL: test7:
-; KNL:       ## %bb.0: ## %allocas
-; KNL-NEXT:    vpmovsxwq %xmm0, %zmm0
-; KNL-NEXT:    vpsllq $63, %zmm0, %zmm0
-; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
-; KNL-NEXT:    kmovw %k0, %eax
-; KNL-NEXT:    orb $85, %al
-; KNL-NEXT:    vzeroupper
-; KNL-NEXT:    retq
-;
-; SKX-LABEL: test7:
-; SKX:       ## %bb.0: ## %allocas
-; SKX-NEXT:    vpsllw $15, %xmm0, %xmm0
-; SKX-NEXT:    vpmovw2m %xmm0, %k0
-; SKX-NEXT:    kmovd %k0, %eax
-; SKX-NEXT:    orb $85, %al
-; SKX-NEXT:    retq
-;
-; AVX512BW-LABEL: test7:
-; AVX512BW:       ## %bb.0: ## %allocas
-; AVX512BW-NEXT:    vpsllw $15, %xmm0, %xmm0
-; AVX512BW-NEXT:    vpmovw2m %zmm0, %k0
-; AVX512BW-NEXT:    kmovd %k0, %eax
-; AVX512BW-NEXT:    orb $85, %al
-; AVX512BW-NEXT:    vzeroupper
-; AVX512BW-NEXT:    retq
-;
-; AVX512DQ-LABEL: test7:
-; AVX512DQ:       ## %bb.0: ## %allocas
-; AVX512DQ-NEXT:    vpmovsxwq %xmm0, %zmm0
-; AVX512DQ-NEXT:    vpsllq $63, %zmm0, %zmm0
-; AVX512DQ-NEXT:    vpmovq2m %zmm0, %k0
-; AVX512DQ-NEXT:    kmovw %k0, %eax
-; AVX512DQ-NEXT:    orb $85, %al
-; AVX512DQ-NEXT:    vzeroupper
-; AVX512DQ-NEXT:    retq
+; CHECK-LABEL: test7:
+; CHECK:       ## %bb.0: ## %allocas
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    retq
 ;
 ; X86-LABEL: test7:
 ; X86:       ## %bb.0: ## %allocas
-; X86-NEXT:    vpsllw $15, %xmm0, %xmm0
-; X86-NEXT:    vpmovw2m %xmm0, %k0
-; X86-NEXT:    kmovd %k0, %eax
-; X86-NEXT:    orb $85, %al
+; X86-NEXT:    movb $1, %al
+; X86-NEXT:    testb %al, %al
 ; X86-NEXT:    retl
 allocas:
   %a= or <8 x i1> %mask, <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
   %b = bitcast <8 x i1> %a to i8
   %c = icmp eq i8 %b, 0
   br i1 %c, label %true, label %false
 
 true:

 ; KNL-NEXT:    vinserti64x4 $1, %ymm2, %zmm3, %zmm2
 ; KNL-NEXT:    vpternlogq $200, %zmm1, %zmm0, %zmm2
 ; KNL-NEXT:    vextracti64x4 $1, %zmm2, %ymm0
 ; KNL-NEXT:    vpor %ymm0, %ymm2, %ymm0
 ; KNL-NEXT:    vpmovsxwd %ymm0, %zmm0
 ; KNL-NEXT:    vpslld $31, %zmm0, %zmm0
 ; KNL-NEXT:    vptestmd %zmm0, %zmm0, %k0
 ; KNL-NEXT:    kortestw %k0, %k0
 ; KNL-NEXT:    je LBB77_1
 ; KNL-NEXT:  ## %bb.2: ## %exit
 ; KNL-NEXT:    vzeroupper
 ; KNL-NEXT:    retq
 ; KNL-NEXT:  LBB77_1: ## %bar
 ; KNL-NEXT:    pushq %rax
 ; KNL-NEXT:    .cfi_def_cfa_offset 16
 ; KNL-NEXT:    vzeroupper
 ; KNL-NEXT:    callq _foo

llvm/test/CodeGen/X86/cmp.ll

; CHECK-NEXT:    retq # encoding: [0xc3]
   %tobool = icmp ne i32 %and, 0
   %cond = select i1 %tobool, i32 %intra, i32 %base
   ret i32 %cond
 }
 
 define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
 ; CHECK-LABEL: test14:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %esi, %eax # encoding: [0x89,0xf0]
-; CHECK-NEXT:    shrl $7, %edi # encoding: [0xc1,0xef,0x07]
-; CHECK-NEXT:    cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2]
+; CHECK-NEXT:    movl %edx, %eax # encoding: [0x89,0xd0]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = lshr i32 %mask, 7
   %tobool = icmp sgt i32 %s, -1
   %cond = select i1 %tobool, i32 %intra, i32 %base
   ret i32 %cond
 }
 
 ; PR19964

llvm/test/CodeGen/X86/fold-rmw-ops.ll

 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_imm32_br() nounwind {
 ; CHECK-LABEL: or64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $16777215, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orl $16777215, g64(%rip) # encoding: [0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
   %load1 = load i64, ptr @g64
   ; Or 0x00FFFFFF, a positive immediate requiring 24-bits.
   %or = or i64 %load1, 16777215
   store i64 %or, ptr @g64
   %cond = icmp eq i64 %or, 0
   br i1 %cond, label %a, label %b
 
 a:
   tail call void @a()
   ret void
 
 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: or64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_imm8_br() nounwind {
 ; CHECK-LABEL: or64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $15, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g64(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
b:
   ret void
 }
 
 define void @or64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-4, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_imm_br() nounwind {
 ; CHECK-LABEL: or32_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $-2147483648, g32(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    orb $-128, g32+3(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g32+3)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_imm8_br() nounwind {
 ; CHECK-LABEL: or32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $15, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    orb $15, g32(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
b:
   ret void
 }
 
 define void @or32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $-4, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm_br() nounwind {
 ; CHECK-LABEL: or16_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $-32768, g16(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x8000
+; CHECK-NEXT:    orb $-128, g16+1(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g16+1)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm8_br() nounwind {
 ; CHECK-LABEL: or16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $15, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g16(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
b:
   ret void
 }
 
 define void @or16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $-4, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:
b:
   ret void
 }
 
 define void @or8_imm_br() nounwind {
 ; CHECK-LABEL: or8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orb $-4, g8(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    jne b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0x75,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: a-1, kind: FK_PCRel_1
 entry:

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

; X64-NEXT:    retq
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; X86-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X86:       # %bb.0:
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    movb $-128, %al
-; X86-NEXT:    shlb %cl, %al
-; X86-NEXT:    andb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    cmpb $1, %al
-; X86-NEXT:    sete %al
+; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    movb $-128, %al
-; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
-; X64-NEXT:    shlb %cl, %al
-; X64-NEXT:    andb %dil, %al
-; X64-NEXT:    cmpb $1, %al
-; X64-NEXT:    sete %al
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/X86/is_fpclass-fp80.ll

 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 4)  ; "-inf"
   ret i1 %0
 }
 
 define i1 @is_normal_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_normal_f80:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
-; CHECK-32-NEXT:    andl $32767, %ecx # imm = 0x7FFF
-; CHECK-32-NEXT:    decl %ecx
-; CHECK-32-NEXT:    movzwl %cx, %ecx
-; CHECK-32-NEXT:    xorl %edx, %edx
-; CHECK-32-NEXT:    cmpl $32766, %ecx # imm = 0x7FFE
-; CHECK-32-NEXT:    sbbl %edx, %edx
-; CHECK-32-NEXT:    setb %cl
-; CHECK-32-NEXT:    shrl $31, %eax
+; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    shrl $31, %ecx
+; CHECK-32-NEXT:    andl $32767, %eax # imm = 0x7FFF
+; CHECK-32-NEXT:    decl %eax
+; CHECK-32-NEXT:    movzwl %ax, %eax
+; CHECK-32-NEXT:    cmpl $32766, %eax # imm = 0x7FFE
+; CHECK-32-NEXT:    setb %al
 ; CHECK-32-NEXT:    andb %cl, %al
-; CHECK-32-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_normal_f80:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    movzwl {{[0-9]+}}(%rsp), %eax
 ; CHECK-64-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-64-NEXT:    shrq $63, %rcx
 ; CHECK-64-NEXT:    andl $32767, %eax # imm = 0x7FFF
 ; CHECK-64-NEXT:    decl %eax
 ; CHECK-64-NEXT:    movzwl %ax, %eax
 ; CHECK-64-NEXT:    cmpl $32766, %eax # imm = 0x7FFE
 ; CHECK-64-NEXT:    setb %al
 ; CHECK-64-NEXT:    andb %cl, %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 264)  ; 0x108 = "normal"
   ret i1 %0
 }
 
 define i1 @is_posnormal_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_posnormal_f80:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    pushl %esi
-; CHECK-32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-32-NEXT:    .cfi_offset %esi, -8
-; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
-; CHECK-32-NEXT:    movswl %dx, %ecx
-; CHECK-32-NEXT:    sarl $15, %ecx
+; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    movswl %cx, %eax
+; CHECK-32-NEXT:    sarl $15, %eax
 ; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    andl $32767, %edx # imm = 0x7FFF
-; CHECK-32-NEXT:    decl %edx
-; CHECK-32-NEXT:    movzwl %dx, %edx
-; CHECK-32-NEXT:    xorl %esi, %esi
-; CHECK-32-NEXT:    cmpl $32766, %edx # imm = 0x7FFE
-; CHECK-32-NEXT:    sbbl %esi, %esi
-; CHECK-32-NEXT:    setb %dl
-; CHECK-32-NEXT:    testl %ecx, %ecx
-; CHECK-32-NEXT:    setns %cl
+; CHECK-32-NEXT:    setns %dl
+; CHECK-32-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-32-NEXT:    decl %ecx
+; CHECK-32-NEXT:    movzwl %cx, %ecx
+; CHECK-32-NEXT:    cmpl $32766, %ecx # imm = 0x7FFE
+; CHECK-32-NEXT:    setb %cl
 ; CHECK-32-NEXT:    shrl $31, %eax
-; CHECK-32-NEXT:    andb %cl, %al
 ; CHECK-32-NEXT:    andb %dl, %al
+; CHECK-32-NEXT:    andb %cl, %al
 ; CHECK-32-NEXT:    # kill: def $al killed $al killed $eax
-; CHECK-32-NEXT:    popl %esi
-; CHECK-32-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_posnormal_f80:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; CHECK-64-NEXT:    movswq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-64-NEXT:    testq %rcx, %rcx
 ; CHECK-64-NEXT:    setns %dl

 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 256)  ; 0x100 = "+normal"
   ret i1 %0
 }
 
 define i1 @is_negnormal_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_negnormal_f80:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    pushl %esi
-; CHECK-32-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-32-NEXT:    .cfi_offset %esi, -8
-; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
-; CHECK-32-NEXT:    movswl %dx, %ecx
-; CHECK-32-NEXT:    sarl $15, %ecx
+; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT:    movswl %cx, %eax
+; CHECK-32-NEXT:    sarl $15, %eax
 ; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    andl $32767, %edx # imm = 0x7FFF
-; CHECK-32-NEXT:    decl %edx
-; CHECK-32-NEXT:    movzwl %dx, %edx
-; CHECK-32-NEXT:    xorl %esi, %esi
-; CHECK-32-NEXT:    cmpl $32766, %edx # imm = 0x7FFE
-; CHECK-32-NEXT:    sbbl %esi, %esi
-; CHECK-32-NEXT:    setb %dl
-; CHECK-32-NEXT:    testl %ecx, %ecx
-; CHECK-32-NEXT:    sets %cl
+; CHECK-32-NEXT:    sets %dl
+; CHECK-32-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-32-NEXT:    decl %ecx
+; CHECK-32-NEXT:    movzwl %cx, %ecx
+; CHECK-32-NEXT:    cmpl $32766, %ecx # imm = 0x7FFE
+; CHECK-32-NEXT:    setb %cl
 ; CHECK-32-NEXT:    shrl $31, %eax
-; CHECK-32-NEXT:    andb %cl, %al
 ; CHECK-32-NEXT:    andb %dl, %al
+; CHECK-32-NEXT:    andb %cl, %al
 ; CHECK-32-NEXT:    # kill: def $al killed $al killed $eax
-; CHECK-32-NEXT:    popl %esi
-; CHECK-32-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_negnormal_f80:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; CHECK-64-NEXT:    movswq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-64-NEXT:    testq %rcx, %rcx
 ; CHECK-64-NEXT:    sets %dl

llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll

 define i1 @p3_scalar_shifted2_urem_by_const(i32 %x, i32 %y) {
 ; CHECK-LABEL: p3_scalar_shifted2_urem_by_const:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %esi, %ecx
 ; CHECK-NEXT:    andl $2, %edi
 ; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; CHECK-NEXT:    shll %cl, %edi
 ; CHECK-NEXT:    imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
-; CHECK-NEXT:    cmpl $1431655766, %eax # imm = 0x55555556
+; CHECK-NEXT:    cmpl $1431655765, %eax # imm = 0x55555555
 ; CHECK-NEXT:    setb %al
 ; CHECK-NEXT:    retq
   %t0 = and i32 %x, 2 ; clearly a power-of-two or zero
   %t1 = shl i32 %t0, %y ; will still be a power-of-two or zero with any %y
   %t2 = urem i32 %t1, 3 ; '3' is clearly not a power of two
   %t3 = icmp eq i32 %t2, 0
   ret i1 %t3
 }

llvm/test/CodeGen/X86/or-with-overflow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+cmov | FileCheck %s --check-prefix=X64
 
 ;
 ; PR48768 - 'or' clears the overflow flag, so we don't need a separate 'test'.
 ;
 
 define i8 @or_i8_ri(i8 zeroext %0, i8 zeroext %1) {
 ; X86-LABEL: or_i8_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orb $-17, %cl
-; X86-NEXT:    je .LBB0_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    orb $-17, %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i8_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    orb $-17, %al
-; X64-NEXT:    movzbl %al, %eax
-; X64-NEXT:    cmovel %edi, %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    retq
   %3 = or i8 %0, -17
   %4 = icmp eq i8 %3, 0
   %5 = select i1 %4, i8 %0, i8 %3
   ret i8 %5
 }
 
; X64-NEXT:    retq
   %4 = icmp eq i8 %3, 0
   %5 = select i1 %4, i8 %0, i8 %3
   ret i8 %5
 }
 
 define i16 @or_i16_ri(i16 zeroext %0, i16 zeroext %1) {
 ; X86-LABEL: or_i16_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $65519, %ecx # imm = 0xFFEF
-; X86-NEXT:    testw %cx, %cx
-; X86-NEXT:    je .LBB2_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB2_2:
+; X86-NEXT:    movl $65519, %eax # imm = 0xFFEF
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i16_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    orl $65519, %eax # imm = 0xFFEF
-; X64-NEXT:    cmovel %edi, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %3 = or i16 %0, -17
   %4 = icmp eq i16 %3, 0
   %5 = select i1 %4, i16 %0, i16 %3
   ret i16 %5
 }
 
; X64-NEXT:    retq
   %5 = select i1 %4, i16 %0, i16 %3
   ret i16 %5
 }
 
 define i32 @or_i32_ri(i32 %0, i32 %1) {
 ; X86-LABEL: or_i32_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    jle .LBB4_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB4_2:
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i32_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-17, %eax
-; X64-NEXT:    cmovlel %edi, %eax
 ; X64-NEXT:    retq
   %3 = or i32 %0, -17
   %4 = icmp slt i32 %3, 1
   %5 = select i1 %4, i32 %0, i32 %3
   ret i32 %5
 }
 
 define i32 @or_i32_rr(i32 %0, i32 %1) {
; X64-NEXT:    retq
   %4 = icmp slt i32 %3, 1
   %5 = select i1 %4, i32 %0, i32 %3
   ret i32 %5
 }
 
 define i64 @or_i64_ri(i64 %0, i64 %1) nounwind {
 ; X86-LABEL: or_i64_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    cmpl $1, %ecx
-; X86-NEXT:    movl $-1, %edx
-; X86-NEXT:    movl $-1, %esi
-; X86-NEXT:    sbbl $0, %esi
-; X86-NEXT:    jl .LBB6_1
-; X86-NEXT:  # %bb.2:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:    popl %esi
-; X86-NEXT:    retl
-; X86-NEXT:  .LBB6_1:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i64_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    orq $-17, %rax
-; X64-NEXT:    cmovleq %rdi, %rax
 ; X64-NEXT:    retq
   %3 = or i64 %0, -17
   %4 = icmp slt i64 %3, 1
   %5 = select i1 %4, i64 %0, i64 %3
   ret i64 %5
 }
 
 define i64 @or_i64_rr(i64 %0, i64 %1) nounwind {

llvm/test/CodeGen/X86/pr16031.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s
 
 define i64 @main(i1 %tobool1) nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    decl %eax
-; CHECK-NEXT:    orl $-12, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    movl %eax, %edx
-; CHECK-NEXT:    addl $-1, %edx
-; CHECK-NEXT:    movl $0, %edx
-; CHECK-NEXT:    adcl $-2, %edx
-; CHECK-NEXT:    cmovsl %ecx, %eax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    retl
 entry:
   %0 = zext i1 %tobool1 to i32
   %. = xor i32 %0, 1
   %.21 = select i1 %tobool1, i32 -12, i32 -1
   %conv = sext i32 %.21 to i64
   %1 = add i64 %conv, -1
   %cmp10 = icmp slt i64 %1, 0
   %sub17 = select i1 %cmp10, i64 0, i64 %conv
   ret i64 %sub17
 }

llvm/test/CodeGen/X86/pr28444.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 < %s | FileCheck %s
 ; https://llvm.org/bugs/show_bug.cgi?id=28444
 
 ; extract_vector_elt is allowed to have a different result type than
 ; the vector scalar type.
 ; This uses both
 ;  i8 = extract_vector_elt v1i1, Constant:i64<0>
 ;  i1 = extract_vector_elt v1i1, Constant:i64<0>
 
 define void @extractelt_mismatch_vector_element_type(i32 %arg, i1 %x) {
 ; CHECK-LABEL: extractelt_mismatch_vector_element_type:
 ; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    movb $-1, %cl
 ; CHECK-NEXT:    movb $1, %al
-; CHECK-NEXT:    movb %al, (%rax)
+; CHECK-NEXT:    andb $1, %cl
+; CHECK-NEXT:    movb %cl, (%rax)
 ; CHECK-NEXT:    movb %al, (%rax)
 ; CHECK-NEXT:    retq
 bb:
   %tmp = icmp ult i32 %arg, 0
   %tmp2 = insertelement <1 x i1> undef, i1 true, i32 0
   %f = insertelement <1 x i1> undef, i1 %x, i32 0
   %tmp3 = select i1 %tmp, <1 x i1> %f, <1 x i1> %tmp2
   %tmp6 = extractelement <1 x i1> %tmp3, i32 0
   br label %bb1
 
 bb1:
   store volatile <1 x i1> %tmp3, ptr undef
   store volatile i1 %tmp6, ptr undef
   ret void
 }
 

llvm/test/CodeGen/X86/select.ll

 ; GENERIC-LABEL: test2:
 ; GENERIC:       ## %bb.0: ## %entry
 ; GENERIC-NEXT:    pushq %rax
 ; GENERIC-NEXT:    callq _return_false
 ; GENERIC-NEXT:    xorl %ecx, %ecx
 ; GENERIC-NEXT:    testb $1, %al
 ; GENERIC-NEXT:    movl $-3840, %eax ## imm = 0xF100
 ; GENERIC-NEXT:    cmovnel %ecx, %eax
-; GENERIC-NEXT:    cmpl $32768, %eax ## imm = 0x8000
+; GENERIC-NEXT:    cmpl $32767, %eax ## imm = 0x7FFF
 ; GENERIC-NEXT:    jge LBB1_1
 ; GENERIC-NEXT:  ## %bb.2: ## %bb91
 ; GENERIC-NEXT:    xorl %eax, %eax
 ; GENERIC-NEXT:    popq %rcx
 ; GENERIC-NEXT:    retq
 ; GENERIC-NEXT:  LBB1_1: ## %bb90
 ; GENERIC-NEXT:    ud2
 ;
 ; ATOM-LABEL: test2:
 ; ATOM:       ## %bb.0: ## %entry
 ; ATOM-NEXT:    pushq %rax
 ; ATOM-NEXT:    callq _return_false
 ; ATOM-NEXT:    xorl %ecx, %ecx
 ; ATOM-NEXT:    movl $-3840, %edx ## imm = 0xF100
 ; ATOM-NEXT:    testb $1, %al
 ; ATOM-NEXT:    cmovnel %ecx, %edx
-; ATOM-NEXT:    cmpl $32768, %edx ## imm = 0x8000
+; ATOM-NEXT:    cmpl $32767, %edx ## imm = 0x7FFF
 ; ATOM-NEXT:    jge LBB1_1
 ; ATOM-NEXT:  ## %bb.2: ## %bb91
 ; ATOM-NEXT:    xorl %eax, %eax
 ; ATOM-NEXT:    popq %rcx
 ; ATOM-NEXT:    retq
 ; ATOM-NEXT:  LBB1_1: ## %bb90
 ; ATOM-NEXT:    ud2
 ;
 ; ATHLON-LABEL: test2:
 ; ATHLON:       ## %bb.0: ## %entry
 ; ATHLON-NEXT:    subl $12, %esp
 ; ATHLON-NEXT:    calll _return_false
 ; ATHLON-NEXT:    xorl %ecx, %ecx
 ; ATHLON-NEXT:    testb $1, %al
 ; ATHLON-NEXT:    movl $-3840, %eax ## imm = 0xF100
 ; ATHLON-NEXT:    cmovnel %ecx, %eax
-; ATHLON-NEXT:    cmpl $32768, %eax ## imm = 0x8000
+; ATHLON-NEXT:    cmpl $32767, %eax ## imm = 0x7FFF
 ; ATHLON-NEXT:    jge LBB1_1
 ; ATHLON-NEXT:  ## %bb.2: ## %bb91
 ; ATHLON-NEXT:    xorl %eax, %eax
 ; ATHLON-NEXT:    addl $12, %esp
 ; ATHLON-NEXT:    retl
 ; ATHLON-NEXT:  LBB1_1: ## %bb90
 ; ATHLON-NEXT:    ud2
 ;
 ; MCU-LABEL: test2:
 ; MCU:       # %bb.0: # %entry
 ; MCU-NEXT:    calll return_false@PLT
 ; MCU-NEXT:    xorl %ecx, %ecx
 ; MCU-NEXT:    testb $1, %al
 ; MCU-NEXT:    jne .LBB1_2
 ; MCU-NEXT:  # %bb.1: # %entry
 ; MCU-NEXT:    movl $-3840, %ecx # imm = 0xF100
 ; MCU-NEXT:  .LBB1_2: # %entry
-; MCU-NEXT:    cmpl $32768, %ecx # imm = 0x8000
+; MCU-NEXT:    cmpl $32767, %ecx # imm = 0x7FFF
 ; MCU-NEXT:    jge .LBB1_3
 ; MCU-NEXT:  # %bb.4: # %bb91
 ; MCU-NEXT:    xorl %eax, %eax
 ; MCU-NEXT:    retl
 ; MCU-NEXT:  .LBB1_3: # %bb90
 entry:
   %tmp73 = tail call i1 @return_false()
   %g.0 = select i1 %tmp73, i16 0, i16 -480

llvm/test/CodeGen/X86/shrink-compare-pgso.ll

 
 if.end:
   ret void
 }
 
 define dso_local void @test2_1(i32 %X) nounwind !prof !14 {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
 entry:
   %and = and i32 %X, 255
   %cmp = icmp eq i32 %and, 256
   br i1 %cmp, label %if.then, label %if.end
 

llvm/test/CodeGen/X86/shrink-compare.ll

 
 if.end:
   ret void
 }
 
 define dso_local void @test2_1(i32 %X) nounwind minsize {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
 entry:
   %and = and i32 %X, 255
   %cmp = icmp eq i32 %and, 256
   br i1 %cmp, label %if.then, label %if.end
 

llvm/test/CodeGen/X86/smul_fix_sat_constants.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64
 
 ; Verify expansion by using constant values. We just want to cover all the paths layed out by ExpandIntRes_MULFIX.
 
 declare  i4  @llvm.smul.fix.sat.i4   (i4,  i4, i32)
 declare  i32 @llvm.smul.fix.sat.i32  (i32, i32, i32)
 declare  i64 @llvm.smul.fix.sat.i64  (i64, i64, i32)
 declare  <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32)
 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)
 
 define i64 @func() nounwind {
 ; X64-LABEL: func:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT:    movl $1, %ecx
-; X64-NEXT:    cmovgeq %rax, %rcx
-; X64-NEXT:    movq $-2, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; X64-NEXT:    cmovgeq %rcx, %rax
+; X64-NEXT:    movl $1, %eax
 ; X64-NEXT:    retq
   %tmp = call i64 @llvm.smul.fix.sat.i64(i64 3, i64 2, i32 2)
   ret i64 %tmp
 }
 
 define i64 @func2() nounwind {
 ; X64-LABEL: func2:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl $3, %eax
 ; X64-NEXT:    imulq $2, %rax, %rcx
 ; X64-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
 ; X64-NEXT:    cmovnoq %rcx, %rax
 ; X64-NEXT:    retq
   %tmp = call i64 @llvm.smul.fix.sat.i64(i64 3, i64 2, i32 0)
   ret i64 %tmp
 }
 
 define i64 @func3() nounwind {
 ; X64-LABEL: func3:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT:    movabsq $4611686018427387903, %rcx # imm = 0x3FFFFFFFFFFFFFFF
-; X64-NEXT:    cmovgeq %rax, %rcx
-; X64-NEXT:    movq $-2, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; X64-NEXT:    cmovgeq %rcx, %rax
+; X64-NEXT:    movabsq $4611686018427387903, %rax # imm = 0x3FFFFFFFFFFFFFFF
 ; X64-NEXT:    retq
   %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 2)
   ret i64 %tmp
 }
 
 define i64 @func4() nounwind {
 ; X64-LABEL: func4:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT:    movl $4294967295, %ecx # imm = 0xFFFFFFFF
-; X64-NEXT:    cmovgq %rax, %rcx
-; X64-NEXT:    movq $-2147483648, %rax # imm = 0x80000000
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; X64-NEXT:    cmovgeq %rcx, %rax
+; X64-NEXT:    movl $4294967295, %eax # imm = 0xFFFFFFFF
 ; X64-NEXT:    retq
   %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 32)
   ret i64 %tmp
 }
 
 define i64 @func5() nounwind {
 ; X64-LABEL: func5:
 ; X64:       # %bb.0:
-; X64-NEXT:    movabsq $4611686018427387903, %rax # imm = 0x3FFFFFFFFFFFFFFF
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT:    movl $1, %ecx
-; X64-NEXT:    cmovgq %rax, %rcx
-; X64-NEXT:    movabsq $-4611686018427387904, %rax # imm = 0xC000000000000000
-; X64-NEXT:    negq %rax
-; X64-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
-; X64-NEXT:    cmovgeq %rcx, %rax
+; X64-NEXT:    movl $1, %eax
 ; X64-NEXT:    retq
   %tmp = call i64 @llvm.smul.fix.sat.i64(i64 9223372036854775807, i64 2, i32 63)
   ret i64 %tmp
 }

llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

 }
 
 
 define <4 x i16> @umulfixsat(<4 x i16> %a) {
 ; CHECK-LABEL: umulfixsat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pextrw $2, %xmm0, %eax
 ; CHECK-NEXT:    leal (%rax,%rax,2), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $16, %ecx
+; CHECK-NEXT:    shldw $1, %ax, %cx
+; CHECK-NEXT:    pextrw $1, %xmm0, %eax
+; CHECK-NEXT:    addl %eax, %eax
 ; CHECK-NEXT:    movl %eax, %edx
 ; CHECK-NEXT:    shrl $16, %edx
-; CHECK-NEXT:    movl %edx, %ecx
-; CHECK-NEXT:    shldw $1, %ax, %cx
-; CHECK-NEXT:    cmpl $32768, %edx # imm = 0x8000
-; CHECK-NEXT:    movl $65535, %eax # imm = 0xFFFF
-; CHECK-NEXT:    cmovael %eax, %ecx
-; CHECK-NEXT:    pextrw $1, %xmm0, %edx
-; CHECK-NEXT:    addl %edx, %edx
-; CHECK-NEXT:    movl %edx, %esi
-; CHECK-NEXT:    shrl $16, %esi
-; CHECK-NEXT:    movl %esi, %edi
-; CHECK-NEXT:    shldw $1, %dx, %di
-; CHECK-NEXT:    cmpl $32768, %esi # imm = 0x8000
-; CHECK-NEXT:    cmovael %eax, %edi
-; CHECK-NEXT:    movd %xmm0, %edx
+; CHECK-NEXT:    shldw $1, %ax, %dx
+; CHECK-NEXT:    movd %xmm0, %eax
 ; CHECK-NEXT:    xorl %esi, %esi
-; CHECK-NEXT:    shldw $1, %dx, %si
-; CHECK-NEXT:    movl $32768, %edx # imm = 0x8000
-; CHECK-NEXT:    negl %edx
-; CHECK-NEXT:    cmovael %eax, %esi
-; CHECK-NEXT:    movzwl %si, %edx
-; CHECK-NEXT:    movd %edx, %xmm1
-; CHECK-NEXT:    pinsrw $1, %edi, %xmm1
+; CHECK-NEXT:    shldw $1, %ax, %si
+; CHECK-NEXT:    movzwl %si, %eax
+; CHECK-NEXT:    movd %eax, %xmm1
+; CHECK-NEXT:    pinsrw $1, %edx, %xmm1
 ; CHECK-NEXT:    pinsrw $2, %ecx, %xmm1
-; CHECK-NEXT:    pextrw $3, %xmm0, %ecx
-; CHECK-NEXT:    shll $2, %ecx
-; CHECK-NEXT:    movl %ecx, %edx
-; CHECK-NEXT:    shrl $16, %edx
-; CHECK-NEXT:    movl %edx, %esi
-; CHECK-NEXT:    shldw $1, %cx, %si
-; CHECK-NEXT:    cmpl $32768, %edx # imm = 0x8000
-; CHECK-NEXT:    cmovael %eax, %esi
-; CHECK-NEXT:    pinsrw $3, %esi, %xmm1
+; CHECK-NEXT:    pextrw $3, %xmm0, %eax
+; CHECK-NEXT:    shll $2, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shrl $16, %ecx
+; CHECK-NEXT:    shldw $1, %ax, %cx
+; CHECK-NEXT:    pinsrw $3, %ecx, %xmm1
 ; CHECK-NEXT:    movdqa %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t = call <4 x i16> @llvm.umul.fix.sat.v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> %a, i32 15)
   ret <4 x i16> %t
 }