This is an archive of the discontinued LLVM Phabricator instance.

Differential D149278

[RISCV] Remove CSR names that are not in Privileged Specification 1.12.
ClosedPublic

Authored by craig.topper on Apr 26 2023, 11:38 AM.

Details

Reviewers
asb
reames
jrtc27
kito-cheng
philipp.tomsich
tangxingxin1008
Commits
rGf0c36dc964a8: [RISCV] Remove CSR names that are not in Privileged Specification 1.12.
Summary

These are from the N extension (User-Level Interrupts) which did
not make it into 1.12 of the Privileged Specification.

D117653 also tried to remove some of these, but it was never reviewed.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 26 2023, 11:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 26 2023, 11:38 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 26 others. · View Herald Transcript
craig.topper requested review of this revision.Apr 26 2023, 11:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 26 2023, 11:38 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
jrtc27 added a comment.Apr 26 2023, 11:39 AM

I can't imagine anyone's actually using N. I would recommend just killing them entirely; the extension has been shelved.

Harbormaster completed remote builds in B228351: Diff 517254.Apr 26 2023, 12:17 PM
craig.topper updated this revision to Diff 517287.Apr 26 2023, 1:19 PM

Remove the CSR names instead

craig.topper retitled this revision from [RISCV] Deprecate CSR names that are not in Privileged Specification 1.12. to [RISCV] Remove CSR names that are not in Privileged Specification 1.12..Apr 26 2023, 1:19 PM
craig.topper edited the summary of this revision. (Show Details)
jrtc27 accepted this revision.Apr 26 2023, 1:24 PM
This revision is now accepted and ready to land.Apr 26 2023, 1:24 PM
This revision was landed with ongoing or failed builds.Apr 26 2023, 1:35 PM
Closed by commit rGf0c36dc964a8: [RISCV] Remove CSR names that are not in Privileged Specification 1.12. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGf0c36dc964a8: [RISCV] Remove CSR names that are not in Privileged Specification 1.12..
Harbormaster completed remote builds in B228370: Diff 517287.Apr 26 2023, 2:08 PM

Revision Contents

PathSize
llvm/
docs/
1 line
lib/
Target/
RISCV/
21 lines
test/
MC/
RISCV/
16 lines
4 lines
4 lines
28 lines
119 lines

Diff 517297

llvm/docs/ReleaseNotes.rst

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
* Changed the ShadowCallStack register from ``x18`` (``s2``) to ``x3`` * Changed the ShadowCallStack register from ``x18`` (``s2``) to ``x3``
(``gp``). Note this breaks the existing non-standard ABI for ShadowCallStack (``gp``). Note this breaks the existing non-standard ABI for ShadowCallStack
on RISC-V, but conforms with the new "platform register" defined in the on RISC-V, but conforms with the new "platform register" defined in the
RISC-V psABI (for more details see the RISC-V psABI (for more details see the
`psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_). `psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_).
* Added support for Zfa extension version 0.2. * Added support for Zfa extension version 0.2.
* Updated support experimental vector crypto extensions to version 0.5.1 of * Updated support experimental vector crypto extensions to version 0.5.1 of
the specification. the specification.
* Removed N extension (User-Level Interrupts) CSR names in the assembler.
Changes to the WebAssembly Backend Changes to the WebAssembly Backend
---------------------------------- ----------------------------------
* ... * ...
Changes to the Windows Target Changes to the Windows Target
----------------------------- -----------------------------
▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSystemOperands.td

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
} }
def lookupSysRegByDeprecatedName : SearchIndex { def lookupSysRegByDeprecatedName : SearchIndex {
let Table = SysRegsList; let Table = SysRegsList;
let Key = [ "DeprecatedName" ]; let Key = [ "DeprecatedName" ];
} }
// The following CSR encodings match those given in Tables 2.2, // The following CSR encodings match those given in Tables 2.2,
// 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual // 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
// Volume II: Privileged Architecture. // Volume II: Privileged Architecture.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// User Trap Setup
//===----------------------------------------------------------------------===//
def : SysReg<"ustatus", 0x000>;
def : SysReg<"uie", 0x004>;
def : SysReg<"utvec", 0x005>;
//===----------------------------------------------------------------------===//
// User Trap Handling
//===----------------------------------------------------------------------===//
def : SysReg<"uscratch", 0x040>;
def : SysReg<"uepc", 0x041>;
def : SysReg<"ucause", 0x042>;
let DeprecatedName = "ubadaddr" in
def : SysReg<"utval", 0x043>;
def : SysReg<"uip", 0x044>;
//===----------------------------------------------------------------------===//
// User Floating-Point CSRs // User Floating-Point CSRs
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def SysRegFFLAGS : SysReg<"fflags", 0x001>; def SysRegFFLAGS : SysReg<"fflags", 0x001>;
def SysRegFRM : SysReg<"frm", 0x002>; def SysRegFRM : SysReg<"frm", 0x002>;
def SysRegFCSR : SysReg<"fcsr", 0x003>; def SysRegFCSR : SysReg<"fcsr", 0x003>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 16 Lines
foreach i = 3...31 in foreach i = 3...31 in
def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>; def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Supervisor Trap Setup // Supervisor Trap Setup
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : SysReg<"sstatus", 0x100>; def : SysReg<"sstatus", 0x100>;
def : SysReg<"sedeleg", 0x102>;
def : SysReg<"sideleg", 0x103>;
def : SysReg<"sie", 0x104>; def : SysReg<"sie", 0x104>;
def : SysReg<"stvec", 0x105>; def : SysReg<"stvec", 0x105>;
def : SysReg<"scounteren", 0x106>; def : SysReg<"scounteren", 0x106>;
def : SysReg<"stimecmp", 0x14D>; def : SysReg<"stimecmp", 0x14D>;
let isRV32Only = 1 in let isRV32Only = 1 in
def : SysReg<"stimecmph", 0x15D>; def : SysReg<"stimecmph", 0x15D>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 248 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/deprecated-csr-names.s

Show All 38 Lines
# CHECK-INST-ALIAS: csrw mtval, zero # CHECK-INST-ALIAS: csrw mtval, zero
# name # name
csrw mbadaddr, zero csrw mbadaddr, zero
# uimm12 # uimm12
csrrw zero, 0x343, zero csrrw zero, 0x343, zero
# CHECK-WARN: warning: 'mbadaddr' is a deprecated alias for 'mtval' # CHECK-WARN: warning: 'mbadaddr' is a deprecated alias for 'mtval'
# ubadaddr
# name
# CHECK-INST: csrrw zero, utval, zero
# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
# CHECK-INST-ALIAS: csrw utval, zero
# uimm12
# CHECK-INST: csrrw zero, utval, zero
# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
# CHECK-INST-ALIAS: csrw utval, zero
# name
csrw ubadaddr, zero
# uimm12
csrrw zero, 0x043, zero
# CHECK-WARN: warning: 'ubadaddr' is a deprecated alias for 'utval'
# sptbr # sptbr
# name # name
# CHECK-INST: csrrw zero, satp, zero # CHECK-INST: csrrw zero, satp, zero
# CHECK-ENC: encoding: [0x73,0x10,0x00,0x18] # CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
# CHECK-INST-ALIAS: csrw satp, zero # CHECK-INST-ALIAS: csrw satp, zero
# uimm12 # uimm12
# CHECK-INST: csrrw zero, satp, zero # CHECK-INST: csrrw zero, satp, zero
# CHECK-ENC: encoding: [0x73,0x10,0x00,0x18] # CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
# CHECK-INST-ALIAS: csrw satp, zero # CHECK-INST-ALIAS: csrw satp, zero
# name # name
csrw sptbr, zero csrw sptbr, zero
# uimm12 # uimm12
csrrw zero, 0x180, zero csrrw zero, 0x180, zero
# CHECK-WARN: warning: 'sptbr' is a deprecated alias for 'satp' # CHECK-WARN: warning: 'sptbr' is a deprecated alias for 'satp'

llvm/test/MC/RISCV/rv32e-valid.s

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
unimp unimp
# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
csrrw t0, 0xfff, t1 csrrw t0, 0xfff, t1
# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
csrrs s0, 0xc00, x0 csrrs s0, 0xc00, x0
# CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
csrrs s0, 0x001, a5 csrrs s0, 0x001, a5
# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra # CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
csrrc sp, 0x000, ra csrrc sp, 0x000, ra
# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 # CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
csrrwi a5, 0x000, 0 csrrwi a5, 0x000, 0
# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
csrrsi t2, 0xfff, 31 csrrsi t2, 0xfff, 31
# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
csrrci t1, 0x140, 5 csrrci t1, 0x140, 5

llvm/test/MC/RISCV/rv32i-valid.s

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00] # CHECK-ASM: encoding: [0x73,0x94,0x14,0x00]
csrrw s0, !0, s1 csrrw s0, !0, s1
# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0] # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
csrrs s0, 0xc00, x0 csrrs s0, 0xc00, x0
# CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
csrrs s3, 0x001, s5 csrrs s3, 0x001, s5
# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra # CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
csrrc sp, 0x000, ra csrrc sp, 0x000, ra
# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 # CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
csrrwi a5, 0x000, 0 csrrwi a5, 0x000, 0
# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] # CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff]
csrrsi t2, 0xfff, 31 csrrsi t2, 0xfff, 31
# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14] # CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14]
csrrci t1, 0x140, 5 csrrci t1, 0x140, 5

llvm/test/MC/RISCV/supervisor-csr-names.s

Show All 22 Lines
# CHECK-INST: csrrs t2, sstatus, zero # CHECK-INST: csrrs t2, sstatus, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x10] # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x10]
# CHECK-INST-ALIAS: csrr t2, sstatus # CHECK-INST-ALIAS: csrr t2, sstatus
# name # name
csrrs t1, sstatus, zero csrrs t1, sstatus, zero
# uimm12 # uimm12
csrrs t2, 0x100, zero csrrs t2, 0x100, zero
# sedeleg
# name
# CHECK-INST: csrrs t1, sedeleg, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x10]
# CHECK-INST-ALIAS: csrr t1, sedeleg
# uimm12
# CHECK-INST: csrrs t2, sedeleg, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x10]
# CHECK-INST-ALIAS: csrr t2, sedeleg
# name
csrrs t1, sedeleg, zero
# uimm12
csrrs t2, 0x102, zero
# sideleg
# name
# CHECK-INST: csrrs t1, sideleg, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x10]
# CHECK-INST-ALIAS: csrr t1, sideleg
# uimm12
# CHECK-INST: csrrs t2, sideleg, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x10]
# CHECK-INST-ALIAS: csrr t2, sideleg
# name
csrrs t1, sideleg, zero
# uimm12
csrrs t2, 0x103, zero
# sie # sie
# name # name
# CHECK-INST: csrrs t1, sie, zero # CHECK-INST: csrrs t1, sie, zero
# CHECK-ENC: [0x73,0x23,0x40,0x10] # CHECK-ENC: [0x73,0x23,0x40,0x10]
# CHECK-INST-ALIAS: csrr t1, sie # CHECK-INST-ALIAS: csrr t1, sie
# uimm12 # uimm12
# CHECK-INST: csrrs t2, sie, zero # CHECK-INST: csrrs t2, sie, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x10] # CHECK-ENC: encoding: [0xf3,0x23,0x40,0x10]
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/user-csr-names.s

# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
# RUN: | llvm-objdump -d - \ # RUN: | llvm-objdump -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
# #
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
# RUN: | llvm-objdump -d - \ # RUN: | llvm-objdump -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
################################## ##################################
# User Trap Setup
##################################
# ustatus
# name
# CHECK-INST: csrrs t1, ustatus, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x00]
# CHECK-INST-ALIAS: csrr t1, ustatus
# uimm12
# CHECK-INST: csrrs t2, ustatus, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x00]
# CHECK-INST-ALIAS: csrr t2, ustatus
csrrs t1, ustatus, zero
# uimm12
csrrs t2, 0x000, zero
# uie
# name
# CHECK-INST: csrrs t1, uie, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x00]
# CHECK-INST-ALIAS: csrr t1, uie
# uimm12
# CHECK-INST: csrrs t2, uie, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x00]
# CHECK-INST-ALIAS: csrr t2, uie
# name
csrrs t1, uie, zero
# uimm12
csrrs t2, 0x004, zero
# utvec
# name
# CHECK-INST: csrrs t1, utvec, zero
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x00]
# CHECK-INST-ALIAS: csrr t1, utvec
# uimm12
# CHECK-INST: csrrs t2, utvec, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x00]
# CHECK-INST-ALIAS: csrr t2, utvec
# name
csrrs t1, utvec, zero
# uimm12
csrrs t2, 0x005, zero
##################################
# User Trap Handling
##################################
# uscratch
# name
# CHECK-INST: csrrs t1, uscratch, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x04]
# CHECK-INST-ALIAS: csrr t1, uscratch
# uimm12
# CHECK-INST: csrrs t2, uscratch, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x04]
# CHECK-INST-ALIAS: csrr t2, uscratch
# name
csrrs t1, uscratch, zero
# uimm12
csrrs t2, 0x040, zero
# uepc
# name
# CHECK-INST: csrrs t1, uepc, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x04]
# CHECK-INST-ALIAS: csrr t1, uepc
# uimm12
# CHECK-INST: csrrs t2, uepc, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x04]
# CHECK-INST-ALIAS: csrr t2, uepc
# name
csrrs t1, uepc, zero
# uimm12
csrrs t2, 0x041, zero
# ucause
# name
# CHECK-INST: csrrs t1, ucause, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x04]
# CHECK-INST-ALIAS: csrr t1, ucause
# uimm12
# CHECK-INST: csrrs t2, ucause, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x04]
# CHECK-INST-ALIAS: csrr t2, ucause
# name
csrrs t1, ucause, zero
# uimm12
csrrs t2, 0x042, zero
# utval
# name
# CHECK-INST: csrrs t1, utval, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x04]
# CHECK-INST-ALIAS: csrr t1, utval
# uimm12
# CHECK-INST: csrrs t2, utval, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x04]
# CHECK-INST-ALIAS: csrr t2, utval
# name
csrrs t1, utval, zero
# uimm12
csrrs t2, 0x043, zero
# uip
# name
# CHECK-INST: csrrs t1, uip, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x04]
# CHECK-INST-ALIAS: csrr t1, uip
# uimm12
# CHECK-INST: csrrs t2, uip, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x04]
# CHECK-INST-ALIAS: csrr t2, uip
#name
csrrs t1, uip, zero
# uimm12
csrrs t2, 0x044, zero
##################################
# User Floating Point CSRs # User Floating Point CSRs
################################## ##################################
# Tests in rvf-user-mode-csr.s # Tests in rvf-user-mode-csr.s
################################## ##################################
# User Counter and Timers # User Counter and Timers
################################## ##################################
▲ Show 20 Lines • Show All 447 Lines • Show Last 20 Lines