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Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines	public:

/// Returns true if the set is empty.		/// Returns true if the set is empty.
bool empty() const { return LiveRegs.empty(); }		bool empty() const { return LiveRegs.empty(); }

/// Adds a physical register and all its sub-registers to the set.		/// Adds a physical register and all its sub-registers to the set.
void addReg(MCPhysReg Reg) {		void addReg(MCPhysReg Reg) {
assert(TRI && "LivePhysRegs is not initialized.");		assert(TRI && "LivePhysRegs is not initialized.");
assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");		assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		LiveRegs.insert(SubReg);
LiveRegs.insert(*SubRegs);
}		}

/// Removes a physical register, all its sub-registers, and all its		/// Removes a physical register, all its sub-registers, and all its
/// super-registers from the set.		/// super-registers from the set.
void removeReg(MCPhysReg Reg) {		void removeReg(MCPhysReg Reg) {
assert(TRI && "LivePhysRegs is not initialized.");		assert(TRI && "LivePhysRegs is not initialized.");
assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");		assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)		for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)
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llvm/include/llvm/MC/MCRegisterInfo.h

Show First 20 Lines • Show All 651 Lines • ▼ Show 20 Lines	MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
if (!IncludeSelf)		if (!IncludeSelf)
++*this;		++*this;
}		}
};		};

// Definition for isSuperRegister. Put it down here since it needs the		// Definition for isSuperRegister. Put it down here since it needs the
// iterator defined above in addition to the MCRegisterInfo class itself.		// iterator defined above in addition to the MCRegisterInfo class itself.
inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{		inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)		for (MCPhysReg I : superregs(RegA))
if (*I == RegB)		if (I == RegB)
return true;		return true;
return false;		return false;
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Register Units		// Register Units
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

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llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Show First 20 Lines • Show All 240 Lines • ▼ Show 20 Lines
void AggressiveAntiDepBreaker::GetPassthruRegs(		void AggressiveAntiDepBreaker::GetPassthruRegs(
MachineInstr &MI, std::set<unsigned> &PassthruRegs) {		MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);		MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;		if (!MO.isReg()) continue;
if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) \|\|		if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) \|\|
IsImplicitDefUse(MI, MO)) {		IsImplicitDefUse(MI, MO)) {
const Register Reg = MO.getReg();		const Register Reg = MO.getReg();
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		PassthruRegs.insert(SubReg);
PassthruRegs.insert(*SubRegs);
}		}
}		}
}		}

/// AntiDepEdges - Return in Edges the anti- and output- dependencies		/// AntiDepEdges - Return in Edges the anti- and output- dependencies
/// in SU that we want to consider for breaking.		/// in SU that we want to consider for breaking.
static void AntiDepEdges(const SUnit SU, std::vector<const SDep > &Edges) {		static void AntiDepEdges(const SUnit SU, std::vector<const SDep > &Edges) {
SmallSet<unsigned, 4> RegSet;		SmallSet<unsigned, 4> RegSet;
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	LLVM_DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI);		dbgs() << header << printReg(Reg, TRI);
header = nullptr;		header = nullptr;
});		});
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);		LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
// Repeat for subregisters. Note that we only do this if the superregister		// Repeat for subregisters. Note that we only do this if the superregister
// was not live because otherwise, regardless whether we have an explicit		// was not live because otherwise, regardless whether we have an explicit
// use of the subregister, the subregister's contents are needed for the		// use of the subregister, the subregister's contents are needed for the
// uses of the superregister.		// uses of the superregister.
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubregReg : TRI->subregs(Reg)) {
unsigned SubregReg = *SubRegs;
if (!State->IsLive(SubregReg)) {		if (!State->IsLive(SubregReg)) {
KillIndices[SubregReg] = KillIdx;		KillIndices[SubregReg] = KillIdx;
DefIndices[SubregReg] = ~0u;		DefIndices[SubregReg] = ~0u;
RegRefs.erase(SubregReg);		RegRefs.erase(SubregReg);
State->LeaveGroup(SubregReg);		State->LeaveGroup(SubregReg);
LLVM_DEBUG(if (header) {		LLVM_DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI);		dbgs() << header << printReg(Reg, TRI);
header = nullptr;		header = nullptr;
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llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines	bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
// If this is a valid register number, emit it.		// If this is a valid register number, emit it.
if (Reg >= 0) {		if (Reg >= 0) {
DwarfRegs.push_back(Register::createRegister(Reg, nullptr));		DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
return true;		return true;
}		}

// Walk up the super-register chain until we find a valid number.		// Walk up the super-register chain until we find a valid number.
// For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.		// For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI.superregs(MachineReg)) {
Reg = TRI.getDwarfRegNum(*SR, false);		Reg = TRI.getDwarfRegNum(SR, false);
if (Reg >= 0) {		if (Reg >= 0) {
unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);		unsigned Idx = TRI.getSubRegIndex(SR, MachineReg);
unsigned Size = TRI.getSubRegIdxSize(Idx);		unsigned Size = TRI.getSubRegIdxSize(Idx);
unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);		unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));		DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
// Use a DW_OP_bit_piece to describe the sub-register.		// Use a DW_OP_bit_piece to describe the sub-register.
setSubRegisterPiece(Size, RegOffset);		setSubRegisterPiece(Size, RegOffset);
return true;		return true;
}		}
}		}

// Otherwise, attempt to find a covering set of sub-register numbers.		// Otherwise, attempt to find a covering set of sub-register numbers.
// For example, Q0 on ARM is a composition of D0+D1.		// For example, Q0 on ARM is a composition of D0+D1.
unsigned CurPos = 0;		unsigned CurPos = 0;
// The size of the register in bits.		// The size of the register in bits.
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);		const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
unsigned RegSize = TRI.getRegSizeInBits(*RC);		unsigned RegSize = TRI.getRegSizeInBits(*RC);
// Keep track of the bits in the register we already emitted, so we		// Keep track of the bits in the register we already emitted, so we
// can avoid emitting redundant aliasing subregs. Because this is		// can avoid emitting redundant aliasing subregs. Because this is
// just doing a greedy scan of all subregisters, it is possible that		// just doing a greedy scan of all subregisters, it is possible that
// this doesn't find a combination of subregisters that fully cover		// this doesn't find a combination of subregisters that fully cover
// the register (even though one may exist).		// the register (even though one may exist).
SmallBitVector Coverage(RegSize, false);		SmallBitVector Coverage(RegSize, false);
for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI.subregs(MachineReg)) {
unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);		unsigned Idx = TRI.getSubRegIndex(MachineReg, SR);
unsigned Size = TRI.getSubRegIdxSize(Idx);		unsigned Size = TRI.getSubRegIdxSize(Idx);
unsigned Offset = TRI.getSubRegIdxOffset(Idx);		unsigned Offset = TRI.getSubRegIdxOffset(Idx);
Reg = TRI.getDwarfRegNum(*SR, false);		Reg = TRI.getDwarfRegNum(SR, false);
if (Reg < 0)		if (Reg < 0)
continue;		continue;

// Used to build the intersection between the bits we already		// Used to build the intersection between the bits we already
// emitted and the bits covered by this subregister.		// emitted and the bits covered by this subregister.
SmallBitVector CurSubReg(RegSize, false);		SmallBitVector CurSubReg(RegSize, false);
CurSubReg.set(Offset, Offset + Size);		CurSubReg.set(Offset, Offset + Size);

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llvm/lib/CodeGen/BranchFolding.cpp

Show First 20 Lines • Show All 1,871 Lines • ▼ Show 20 Lines	for (const MachineOperand &MO : PI->operands()) {
Register Reg = MO.getReg();		Register Reg = MO.getReg();
if (!Reg)		if (!Reg)
continue;		continue;
if (MO.isUse()) {		if (MO.isUse()) {
addRegAndItsAliases(Reg, TRI, Uses);		addRegAndItsAliases(Reg, TRI, Uses);
} else {		} else {
if (Uses.erase(Reg)) {		if (Uses.erase(Reg)) {
if (Reg.isPhysical()) {		if (Reg.isPhysical()) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)		for (MCPhysReg SubReg : TRI->subregs(Reg))
Uses.erase(*SubRegs); // Use sub-registers to be conservative		Uses.erase(SubReg); // Use sub-registers to be conservative
}		}
}		}
addRegAndItsAliases(Reg, TRI, Defs);		addRegAndItsAliases(Reg, TRI, Defs);
}		}
}		}

return PI;		return PI;
}		}
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llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines	for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
}		}

// If we're still willing to consider this register, note the reference.		// If we're still willing to consider this register, note the reference.
if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))		if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
RegRefs.insert(std::make_pair(Reg, &MO));		RegRefs.insert(std::make_pair(Reg, &MO));

if (MO.isUse() && Special) {		if (MO.isUse() && Special) {
if (!KeepRegs.test(Reg)) {		if (!KeepRegs.test(Reg)) {
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		KeepRegs.set(SubReg);
KeepRegs.set(*SubRegs);
}		}
}		}
}		}

for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {		for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI.getOperand(I);		const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;		if (!MO.isReg()) continue;
Register Reg = MO.getReg();		Register Reg = MO.getReg();
if (!Reg.isValid())		if (!Reg.isValid())
continue;		continue;
// If this reg is tied and live (Classes[Reg] is set to -1), we can't change		// If this reg is tied and live (Classes[Reg] is set to -1), we can't change
// it or any of its sub or super regs. We need to use KeepRegs to mark the		// it or any of its sub or super regs. We need to use KeepRegs to mark the
// reg because not all uses of the same reg within an instruction are		// reg because not all uses of the same reg within an instruction are
// necessarily tagged as tied.		// necessarily tagged as tied.
// Example: an x86 "xor %eax, %eax" will have one source operand tied to the		// Example: an x86 "xor %eax, %eax" will have one source operand tied to the
// def register but not the second (see PR20020 for details).		// def register but not the second (see PR20020 for details).
// FIXME: can this check be relaxed to account for undef uses		// FIXME: can this check be relaxed to account for undef uses
// of a register? In the above 'xor' example, the uses of %eax are undef, so		// of a register? In the above 'xor' example, the uses of %eax are undef, so
// earlier instructions could still replace %eax even though the 'xor'		// earlier instructions could still replace %eax even though the 'xor'
// itself can't be changed.		// itself can't be changed.
if (MI.isRegTiedToUseOperand(I) &&		if (MI.isRegTiedToUseOperand(I) &&
Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {		Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
SubRegs.isValid(); ++SubRegs) {		KeepRegs.set(SubReg);
KeepRegs.set(*SubRegs);		}
}		for (MCPhysReg SuperReg : TRI->superregs(Reg)) {
for (MCSuperRegIterator SuperRegs(Reg, TRI);		KeepRegs.set(SuperReg);
SuperRegs.isValid(); ++SuperRegs) {
KeepRegs.set(*SuperRegs);
}		}
}		}
}		}
}		}

void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {		void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
// Update liveness.		// Update liveness.
// Proceeding upwards, registers that are defed but not used in this		// Proceeding upwards, registers that are defed but not used in this
// instruction are now dead.		// instruction are now dead.
assert(!MI.isKill() && "Attempting to scan a kill instruction");		assert(!MI.isKill() && "Attempting to scan a kill instruction");

if (!TII->isPredicated(MI)) {		if (!TII->isPredicated(MI)) {
// Predicated defs are modeled as read + write, i.e. similar to two		// Predicated defs are modeled as read + write, i.e. similar to two
// address updates.		// address updates.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);		MachineOperand &MO = MI.getOperand(i);

if (MO.isRegMask()) {		if (MO.isRegMask()) {
auto ClobbersPhysRegAndSubRegs = [&](unsigned PhysReg) {		auto ClobbersPhysRegAndSubRegs = [&](unsigned PhysReg) {
for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI)		for (MCPhysReg SR : TRI->subregs_inclusive(PhysReg))
if (!MO.clobbersPhysReg(*SRI))		if (!MO.clobbersPhysReg(SR))
return false;		return false;

return true;		return true;
};		};

for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {		for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
if (ClobbersPhysRegAndSubRegs(i)) {		if (ClobbersPhysRegAndSubRegs(i)) {
DefIndices[i] = Count;		DefIndices[i] = Count;
Show All 15 Lines	for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
continue;		continue;

// If we've already marked this reg as unchangeable, don't remove		// If we've already marked this reg as unchangeable, don't remove
// it or any of its subregs from KeepRegs.		// it or any of its subregs from KeepRegs.
bool Keep = KeepRegs.test(Reg);		bool Keep = KeepRegs.test(Reg);

// For the reg itself and all subregs: update the def to current;		// For the reg itself and all subregs: update the def to current;
// reset the kill state, any restrictions, and references.		// reset the kill state, any restrictions, and references.
for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {		for (MCPhysReg SubregReg : TRI->subregs_inclusive(Reg)) {
unsigned SubregReg = *SRI;
DefIndices[SubregReg] = Count;		DefIndices[SubregReg] = Count;
KillIndices[SubregReg] = ~0u;		KillIndices[SubregReg] = ~0u;
Classes[SubregReg] = nullptr;		Classes[SubregReg] = nullptr;
RegRefs.erase(SubregReg);		RegRefs.erase(SubregReg);
if (!Keep)		if (!Keep)
KeepRegs.reset(SubregReg);		KeepRegs.reset(SubregReg);
}		}
// Conservatively mark super-registers as unusable.		// Conservatively mark super-registers as unusable.
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->superregs(Reg))
Classes[SR] = reinterpret_cast<TargetRegisterClass >(-1);		Classes[SR] = reinterpret_cast<TargetRegisterClass *>(-1);
}		}
}		}
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {		for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);		MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;		if (!MO.isReg()) continue;
Register Reg = MO.getReg();		Register Reg = MO.getReg();
if (Reg == 0) continue;		if (Reg == 0) continue;
if (!MO.isUse()) continue;		if (!MO.isUse()) continue;
▲ Show 20 Lines • Show All 386 Lines • Show Last 20 Lines

llvm/lib/CodeGen/IfConversion.cpp

Show First 20 Lines • Show All 1,510 Lines • ▼ Show 20 Lines	if (Op.isRegMask()) {
// the call doesn't return.		// the call doesn't return.
MIB.addReg(Reg, RegState::Implicit \| RegState::Define);		MIB.addReg(Reg, RegState::Implicit \| RegState::Define);
continue;		continue;
}		}
if (LiveBeforeMI.count(Reg))		if (LiveBeforeMI.count(Reg))
MIB.addReg(Reg, RegState::Implicit);		MIB.addReg(Reg, RegState::Implicit);
else {		else {
bool HasLiveSubReg = false;		bool HasLiveSubReg = false;
for (MCSubRegIterator S(Reg, TRI); S.isValid(); ++S) {		for (MCPhysReg S : TRI->subregs(Reg)) {
if (!LiveBeforeMI.count(*S))		if (!LiveBeforeMI.count(S))
continue;		continue;
HasLiveSubReg = true;		HasLiveSubReg = true;
break;		break;
}		}
if (HasLiveSubReg)		if (HasLiveSubReg)
MIB.addReg(Reg, RegState::Implicit);		MIB.addReg(Reg, RegState::Implicit);
}		}
}		}
▲ Show 20 Lines • Show All 424 Lines • ▼ Show 20 Lines	for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
Register Reg = MO.getReg();		Register Reg = MO.getReg();
if (!Reg)		if (!Reg)
continue;		continue;
if (MO.isDef()) {		if (MO.isDef()) {
Defs.push_back(Reg);		Defs.push_back(Reg);
} else if (!RedefsByFalse.count(Reg)) {		} else if (!RedefsByFalse.count(Reg)) {
// These are defined before ctrl flow reach the 'false' instructions.		// These are defined before ctrl flow reach the 'false' instructions.
// They cannot be modified by the 'true' instructions.		// They cannot be modified by the 'true' instructions.
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		ExtUses.insert(SubReg);
ExtUses.insert(*SubRegs);
}		}
}		}

for (MCPhysReg Reg : Defs) {		for (MCPhysReg Reg : Defs) {
if (!ExtUses.count(Reg)) {		if (!ExtUses.count(Reg)) {
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		RedefsByFalse.insert(SubReg);
RedefsByFalse.insert(*SubRegs);
}		}
}		}
}		}
}		}

// Predicate the 'true' block.		// Predicate the 'true' block.
PredicateBlock(BBI1, MBB1.end(), Cond1, &RedefsByFalse);		PredicateBlock(BBI1, MBB1.end(), Cond1, &RedefsByFalse);

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llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

Show First 20 Lines • Show All 1,538 Lines • ▼ Show 20 Lines	if (NewID && !MTracker->isSpill(L)) {
assert(TRC && "Couldn't find target register class?");		assert(TRC && "Couldn't find target register class?");

// If the register we have isn't the right size or in the right place,		// If the register we have isn't the right size or in the right place,
// Try to find a subregister inside it.		// Try to find a subregister inside it.
unsigned MainRegSize = TRI->getRegSizeInBits(*TRC);		unsigned MainRegSize = TRI->getRegSizeInBits(*TRC);
if (Size != MainRegSize \|\| Offset) {		if (Size != MainRegSize \|\| Offset) {
// Enumerate all subregisters, searching.		// Enumerate all subregisters, searching.
Register NewReg = 0;		Register NewReg = 0;
for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {		for (MCPhysReg SR : TRI->subregs(Reg)) {
unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI);		unsigned Subreg = TRI->getSubRegIndex(Reg, SR);
unsigned SubregSize = TRI->getSubRegIdxSize(Subreg);		unsigned SubregSize = TRI->getSubRegIdxSize(Subreg);
unsigned SubregOffset = TRI->getSubRegIdxOffset(Subreg);		unsigned SubregOffset = TRI->getSubRegIdxOffset(Subreg);
if (SubregSize == Size && SubregOffset == Offset) {		if (SubregSize == Size && SubregOffset == Offset) {
NewReg = *SRI;		NewReg = SR;
break;		break;
}		}
}		}

// If we didn't find anything: there's no way to express our value.		// If we didn't find anything: there's no way to express our value.
if (!NewReg) {		if (!NewReg) {
NewID = std::nullopt;		NewID = std::nullopt;
} else {		} else {
▲ Show 20 Lines • Show All 500 Lines • ▼ Show 20 Lines	auto DoTransfer = [&](Register SrcReg, unsigned SpillID) {

if (TTracker) {		if (TTracker) {
LocIdx SrcLoc = MTracker->getRegMLoc(SrcReg);		LocIdx SrcLoc = MTracker->getRegMLoc(SrcReg);
TTracker->transferMlocs(SrcLoc, DstLoc, MI.getIterator());		TTracker->transferMlocs(SrcLoc, DstLoc, MI.getIterator());
}		}
};		};

// Then, transfer subreg bits.		// Then, transfer subreg bits.
for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {		for (MCPhysReg SR : TRI->subregs(Reg)) {
// Ensure this reg is tracked,		// Ensure this reg is tracked,
(void)MTracker->lookupOrTrackRegister(*SRI);		(void)MTracker->lookupOrTrackRegister(SR);
unsigned SubregIdx = TRI->getSubRegIndex(Reg, *SRI);		unsigned SubregIdx = TRI->getSubRegIndex(Reg, SR);
unsigned SpillID = MTracker->getLocID(Loc, SubregIdx);		unsigned SpillID = MTracker->getLocID(Loc, SubregIdx);
DoTransfer(*SRI, SpillID);		DoTransfer(SR, SpillID);
}		}

// Directly lookup size of main source reg, and transfer.		// Directly lookup size of main source reg, and transfer.
unsigned Size = TRI->getRegSizeInBits(Reg, *MRI);		unsigned Size = TRI->getRegSizeInBits(Reg, *MRI);
unsigned SpillID = MTracker->getLocID(Loc, {Size, 0});		unsigned SpillID = MTracker->getLocID(Loc, {Size, 0});
DoTransfer(Reg, SpillID);		DoTransfer(Reg, SpillID);
} else {		} else {
std::optional<SpillLocationNo> Loc = isRestoreInstruction(MI, MF, Reg);		std::optional<SpillLocationNo> Loc = isRestoreInstruction(MI, MF, Reg);
Show All 13 Lines	if (isLocationSpill(MI, MF, Reg)) {
// Now find subregisters within the destination register, and load values		// Now find subregisters within the destination register, and load values
// from stack slot positions.		// from stack slot positions.
auto DoTransfer = [&](Register DestReg, unsigned SpillID) {		auto DoTransfer = [&](Register DestReg, unsigned SpillID) {
LocIdx SrcIdx = MTracker->getSpillMLoc(SpillID);		LocIdx SrcIdx = MTracker->getSpillMLoc(SpillID);
auto ReadValue = MTracker->readMLoc(SrcIdx);		auto ReadValue = MTracker->readMLoc(SrcIdx);
MTracker->setReg(DestReg, ReadValue);		MTracker->setReg(DestReg, ReadValue);
};		};

for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {		for (MCPhysReg SR : TRI->subregs(Reg)) {
unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI);		unsigned Subreg = TRI->getSubRegIndex(Reg, SR);
unsigned SpillID = MTracker->getLocID(*Loc, Subreg);		unsigned SpillID = MTracker->getLocID(*Loc, Subreg);
DoTransfer(*SRI, SpillID);		DoTransfer(SR, SpillID);
}		}

// Directly look up this registers slot idx by size, and transfer.		// Directly look up this registers slot idx by size, and transfer.
unsigned Size = TRI->getRegSizeInBits(Reg, *MRI);		unsigned Size = TRI->getRegSizeInBits(Reg, *MRI);
unsigned SpillID = MTracker->getLocID(*Loc, {Size, 0});		unsigned SpillID = MTracker->getLocID(*Loc, {Size, 0});
DoTransfer(Reg, SpillID);		DoTransfer(Reg, SpillID);
}		}
return true;		return true;
▲ Show 20 Lines • Show All 2,113 Lines • Show Last 20 Lines

llvm/lib/CodeGen/LiveIntervals.cpp

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines	void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
// The physregs aliasing Unit are the roots and their super-registers.		// The physregs aliasing Unit are the roots and their super-registers.
// Create all values as dead defs before extending to uses. Note that roots		// Create all values as dead defs before extending to uses. Note that roots
// may share super-registers. That's OK because createDeadDefs() is		// may share super-registers. That's OK because createDeadDefs() is
// idempotent. It is very rare for a register unit to have multiple roots, so		// idempotent. It is very rare for a register unit to have multiple roots, so
// uniquing super-registers is probably not worthwhile.		// uniquing super-registers is probably not worthwhile.
bool IsReserved = false;		bool IsReserved = false;
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {		for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
bool IsRootReserved = true;		bool IsRootReserved = true;
for (MCSuperRegIterator Super(Root, TRI, /IncludeSelf=*/true);		for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
Super.isValid(); ++Super) {
MCRegister Reg = *Super;
if (!MRI->reg_empty(Reg))		if (!MRI->reg_empty(Reg))
LICalc->createDeadDefs(LR, Reg);		LICalc->createDeadDefs(LR, Reg);
// A register unit is considered reserved if all its roots and all their		// A register unit is considered reserved if all its roots and all their
// super registers are reserved.		// super registers are reserved.
if (!MRI->isReserved(Reg))		if (!MRI->isReserved(Reg))
IsRootReserved = false;		IsRootReserved = false;
}		}
IsReserved \|= IsRootReserved;		IsReserved \|= IsRootReserved;
}		}
assert(IsReserved == MRI->isReservedRegUnit(Unit) &&		assert(IsReserved == MRI->isReservedRegUnit(Unit) &&
"reserved computation mismatch");		"reserved computation mismatch");

// Now extend LR to reach all uses.		// Now extend LR to reach all uses.
// Ignore uses of reserved registers. We only track defs of those.		// Ignore uses of reserved registers. We only track defs of those.
if (!IsReserved) {		if (!IsReserved) {
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {		for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
for (MCSuperRegIterator Super(Root, TRI, /IncludeSelf=*/true);		for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
Super.isValid(); ++Super) {
MCRegister Reg = *Super;
if (!MRI->reg_empty(Reg))		if (!MRI->reg_empty(Reg))
LICalc->extendToUses(LR, Reg);		LICalc->extendToUses(LR, Reg);
}		}
}		}
}		}

// Flush the segment set to the segment vector.		// Flush the segment set to the segment vector.
if (UseSegmentSetForPhysRegs)		if (UseSegmentSetForPhysRegs)
▲ Show 20 Lines • Show All 1,443 Lines • Show Last 20 Lines

llvm/lib/CodeGen/LivePhysRegs.cpp

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Lines	void llvm::addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs) {
const MachineFunction &MF = *MBB.getParent();		const MachineFunction &MF = *MBB.getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();		const MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();		const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
for (MCPhysReg Reg : LiveRegs) {		for (MCPhysReg Reg : LiveRegs) {
if (MRI.isReserved(Reg))		if (MRI.isReserved(Reg))
continue;		continue;
// Skip the register if we are about to add one of its super registers.		// Skip the register if we are about to add one of its super registers.
bool ContainsSuperReg = false;		bool ContainsSuperReg = false;
for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {		for (MCPhysReg SReg : TRI.superregs(Reg)) {
if (LiveRegs.contains(SReg) && !MRI.isReserved(SReg)) {		if (LiveRegs.contains(SReg) && !MRI.isReserved(SReg)) {
ContainsSuperReg = true;		ContainsSuperReg = true;
break;		break;
}		}
}		}
if (ContainsSuperReg)		if (ContainsSuperReg)
continue;		continue;
MBB.addLiveIn(Reg);		MBB.addLiveIn(Reg);
}		}
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/lib/CodeGen/LiveVariables.cpp

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
/// FindLastPartialDef - Return the last partial def of the specified register.		/// FindLastPartialDef - Return the last partial def of the specified register.
/// Also returns the sub-registers that're defined by the instruction.		/// Also returns the sub-registers that're defined by the instruction.
MachineInstr *		MachineInstr *
LiveVariables::FindLastPartialDef(Register Reg,		LiveVariables::FindLastPartialDef(Register Reg,
SmallSet<unsigned, 4> &PartDefRegs) {		SmallSet<unsigned, 4> &PartDefRegs) {
unsigned LastDefReg = 0;		unsigned LastDefReg = 0;
unsigned LastDefDist = 0;		unsigned LastDefDist = 0;
MachineInstr *LastDef = nullptr;		MachineInstr *LastDef = nullptr;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
MachineInstr *Def = PhysRegDef[SubReg];		MachineInstr *Def = PhysRegDef[SubReg];
if (!Def)		if (!Def)
continue;		continue;
unsigned Dist = DistanceMap[Def];		unsigned Dist = DistanceMap[Def];
if (Dist > LastDefDist) {		if (Dist > LastDefDist) {
LastDefReg = SubReg;		LastDefReg = SubReg;
LastDef = Def;		LastDef = Def;
LastDefDist = Dist;		LastDefDist = Dist;
}		}
}		}

if (!LastDef)		if (!LastDef)
return nullptr;		return nullptr;

PartDefRegs.insert(LastDefReg);		PartDefRegs.insert(LastDefReg);
for (MachineOperand &MO : LastDef->operands()) {		for (MachineOperand &MO : LastDef->operands()) {
if (!MO.isReg() \|\| !MO.isDef() \|\| MO.getReg() == 0)		if (!MO.isReg() \|\| !MO.isDef() \|\| MO.getReg() == 0)
continue;		continue;
Register DefReg = MO.getReg();		Register DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) {		if (TRI->isSubRegister(Reg, DefReg)) {
for (MCSubRegIterator SubRegs(DefReg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
SubRegs.isValid(); ++SubRegs)		PartDefRegs.insert(SubReg);
PartDefRegs.insert(*SubRegs);
}		}
}		}
return LastDef;		return LastDef;
}		}

/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add		/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
/// implicit defs to a machine instruction if there was an earlier def of its		/// implicit defs to a machine instruction if there was an earlier def of its
/// super-register.		/// super-register.
Show All 12 Lines	if (!LastDef && !PhysRegUse[Reg]) {
SmallSet<unsigned, 4> PartDefRegs;		SmallSet<unsigned, 4> PartDefRegs;
MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);		MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
// If LastPartialDef is NULL, it must be using a livein register.		// If LastPartialDef is NULL, it must be using a livein register.
if (LastPartialDef) {		if (LastPartialDef) {
LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/IsDef/,		LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/IsDef/,
true/IsImp/));		true/IsImp/));
PhysRegDef[Reg] = LastPartialDef;		PhysRegDef[Reg] = LastPartialDef;
SmallSet<unsigned, 8> Processed;		SmallSet<unsigned, 8> Processed;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
if (Processed.count(SubReg))		if (Processed.count(SubReg))
continue;		continue;
if (PartDefRegs.count(SubReg))		if (PartDefRegs.count(SubReg))
continue;		continue;
// This part of Reg was defined before the last partial def. It's killed		// This part of Reg was defined before the last partial def. It's killed
// here.		// here.
LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,		LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
false/IsDef/,		false/IsDef/,
true/IsImp/));		true/IsImp/));
PhysRegDef[SubReg] = LastPartialDef;		PhysRegDef[SubReg] = LastPartialDef;
for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)		for (MCPhysReg SS : TRI->subregs(SubReg))
Processed.insert(*SS);		Processed.insert(SS);
}		}
}		}
} else if (LastDef && !PhysRegUse[Reg] &&		} else if (LastDef && !PhysRegUse[Reg] &&
!LastDef->findRegisterDefOperand(Reg))		!LastDef->findRegisterDefOperand(Reg))
// Last def defines the super register, add an implicit def of reg.		// Last def defines the super register, add an implicit def of reg.
LastDef->addOperand(MachineOperand::CreateReg(Reg, true/IsDef/,		LastDef->addOperand(MachineOperand::CreateReg(Reg, true/IsDef/,
true/IsImp/));		true/IsImp/));

// Remember this use.		// Remember this use.
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		PhysRegUse[SubReg] = &MI;
PhysRegUse[*SubRegs] = &MI;
}		}

/// FindLastRefOrPartRef - Return the last reference or partial reference of		/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.		/// the specified register.
MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {		MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
MachineInstr *LastDef = PhysRegDef[Reg];		MachineInstr *LastDef = PhysRegDef[Reg];
MachineInstr *LastUse = PhysRegUse[Reg];		MachineInstr *LastUse = PhysRegUse[Reg];
if (!LastDef && !LastUse)		if (!LastDef && !LastUse)
return nullptr;		return nullptr;

MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;		MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];		unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
unsigned LastPartDefDist = 0;		unsigned LastPartDefDist = 0;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
MachineInstr *Def = PhysRegDef[SubReg];		MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) {		if (Def && Def != LastDef) {
// There was a def of this sub-register in between. This is a partial		// There was a def of this sub-register in between. This is a partial
// def, keep track of the last one.		// def, keep track of the last one.
unsigned Dist = DistanceMap[Def];		unsigned Dist = DistanceMap[Def];
if (Dist > LastPartDefDist)		if (Dist > LastPartDefDist)
LastPartDefDist = Dist;		LastPartDefDist = Dist;
} else if (MachineInstr *Use = PhysRegUse[SubReg]) {		} else if (MachineInstr *Use = PhysRegUse[SubReg]) {
Show All 31 Lines	bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
//		//
// Or whole register is defined, but only partly used.		// Or whole register is defined, but only partly used.
// dead AX = implicit-def AL		// dead AX = implicit-def AL
// = killed AL		// = killed AL
// AX =		// AX =
MachineInstr *LastPartDef = nullptr;		MachineInstr *LastPartDef = nullptr;
unsigned LastPartDefDist = 0;		unsigned LastPartDefDist = 0;
SmallSet<unsigned, 8> PartUses;		SmallSet<unsigned, 8> PartUses;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
MachineInstr *Def = PhysRegDef[SubReg];		MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) {		if (Def && Def != LastDef) {
// There was a def of this sub-register in between. This is a partial		// There was a def of this sub-register in between. This is a partial
// def, keep track of the last one.		// def, keep track of the last one.
unsigned Dist = DistanceMap[Def];		unsigned Dist = DistanceMap[Def];
if (Dist > LastPartDefDist) {		if (Dist > LastPartDefDist) {
LastPartDefDist = Dist;		LastPartDefDist = Dist;
LastPartDef = Def;		LastPartDef = Def;
}		}
continue;		continue;
}		}
if (MachineInstr *Use = PhysRegUse[SubReg]) {		if (MachineInstr *Use = PhysRegUse[SubReg]) {
for (MCSubRegIterator SS(SubReg, TRI, /IncludeSelf=/true); SS.isValid();		for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
++SS)		PartUses.insert(SS);
PartUses.insert(*SS);
unsigned Dist = DistanceMap[Use];		unsigned Dist = DistanceMap[Use];
if (Dist > LastRefOrPartRefDist) {		if (Dist > LastRefOrPartRefDist) {
LastRefOrPartRefDist = Dist;		LastRefOrPartRefDist = Dist;
LastRefOrPartRef = Use;		LastRefOrPartRef = Use;
}		}
}		}
}		}

if (!PhysRegUse[Reg]) {		if (!PhysRegUse[Reg]) {
// Partial uses. Mark register def dead and add implicit def of		// Partial uses. Mark register def dead and add implicit def of
// sub-registers which are used.		// sub-registers which are used.
// dead EAX = op implicit-def AL		// dead EAX = op implicit-def AL
// That is, EAX def is dead but AL def extends pass it.		// That is, EAX def is dead but AL def extends pass it.
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);		PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
if (!PartUses.count(SubReg))		if (!PartUses.count(SubReg))
continue;		continue;
bool NeedDef = true;		bool NeedDef = true;
if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {		if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);		MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
if (MO) {		if (MO) {
NeedDef = false;		NeedDef = false;
assert(!MO->isDead());		assert(!MO->isDead());
}		}
}		}
if (NeedDef)		if (NeedDef)
PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,		PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
true/IsDef/, true/IsImp/));		true/IsDef/, true/IsImp/));
MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);		MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
if (LastSubRef)		if (LastSubRef)
LastSubRef->addRegisterKilled(SubReg, TRI, true);		LastSubRef->addRegisterKilled(SubReg, TRI, true);
else {		else {
LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);		LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
for (MCSubRegIterator SS(SubReg, TRI, /IncludeSelf=/true);		for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
SS.isValid(); ++SS)		PhysRegUse[SS] = LastRefOrPartRef;
PhysRegUse[*SS] = LastRefOrPartRef;
}		}
for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)		for (MCPhysReg SS : TRI->subregs(SubReg))
PartUses.erase(*SS);		PartUses.erase(SS);
}		}
} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {		} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
if (LastPartDef)		if (LastPartDef)
// The last partial def kills the register.		// The last partial def kills the register.
LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/IsDef/,		LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/IsDef/,
true/IsImp/, true/IsKill/));		true/IsImp/, true/IsKill/));
else {		else {
MachineOperand *MO =		MachineOperand *MO =
Show All 24 Lines	for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
if (!PhysRegDef[Reg] && !PhysRegUse[Reg])		if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
continue;		continue;
// Skip mask-preserved regs.		// Skip mask-preserved regs.
if (!MO.clobbersPhysReg(Reg))		if (!MO.clobbersPhysReg(Reg))
continue;		continue;
// Kill the largest clobbered super-register.		// Kill the largest clobbered super-register.
// This avoids needless implicit operands.		// This avoids needless implicit operands.
unsigned Super = Reg;		unsigned Super = Reg;
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->superregs(Reg))
if ((PhysRegDef[SR] \|\| PhysRegUse[SR]) && MO.clobbersPhysReg(*SR))		if ((PhysRegDef[SR] \|\| PhysRegUse[SR]) && MO.clobbersPhysReg(SR))
Super = *SR;		Super = SR;
HandlePhysRegKill(Super, nullptr);		HandlePhysRegKill(Super, nullptr);
}		}
}		}

void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,		void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,
SmallVectorImpl<unsigned> &Defs) {		SmallVectorImpl<unsigned> &Defs) {
// What parts of the register are previously defined?		// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;		SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] \|\| PhysRegUse[Reg]) {		if (PhysRegDef[Reg] \|\| PhysRegUse[Reg]) {
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
SubRegs.isValid(); ++SubRegs)		Live.insert(SubReg);
Live.insert(*SubRegs);
} else {		} else {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
// If a register isn't itself defined, but all parts that make up of it		// If a register isn't itself defined, but all parts that make up of it
// are defined, then consider it also defined.		// are defined, then consider it also defined.
// e.g.		// e.g.
// AL =		// AL =
// AH =		// AH =
// = AX		// = AX
if (Live.count(SubReg))		if (Live.count(SubReg))
continue;		continue;
if (PhysRegDef[SubReg] \|\| PhysRegUse[SubReg]) {		if (PhysRegDef[SubReg] \|\| PhysRegUse[SubReg]) {
for (MCSubRegIterator SS(SubReg, TRI, /IncludeSelf=/true);		for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
SS.isValid(); ++SS)		Live.insert(SS);
Live.insert(*SS);
}		}
}		}
}		}

// Start from the largest piece, find the last time any part of the register		// Start from the largest piece, find the last time any part of the register
// is referenced.		// is referenced.
HandlePhysRegKill(Reg, MI);		HandlePhysRegKill(Reg, MI);
// Only some of the sub-registers are used.		// Only some of the sub-registers are used.
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
if (!Live.count(SubReg))		if (!Live.count(SubReg))
// Skip if this sub-register isn't defined.		// Skip if this sub-register isn't defined.
continue;		continue;
HandlePhysRegKill(SubReg, MI);		HandlePhysRegKill(SubReg, MI);
}		}

if (MI)		if (MI)
Defs.push_back(Reg); // Remember this def.		Defs.push_back(Reg); // Remember this def.
}		}

void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,		void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
SmallVectorImpl<unsigned> &Defs) {		SmallVectorImpl<unsigned> &Defs) {
while (!Defs.empty()) {		while (!Defs.empty()) {
Register Reg = Defs.pop_back_val();		Register Reg = Defs.pop_back_val();
for (MCSubRegIterator SubRegs(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
SubRegs.isValid(); ++SubRegs) {
unsigned SubReg = *SubRegs;
PhysRegDef[SubReg] = &MI;		PhysRegDef[SubReg] = &MI;
PhysRegUse[SubReg] = nullptr;		PhysRegUse[SubReg] = nullptr;
}		}
}		}
}		}

void LiveVariables::runOnInstr(MachineInstr &MI,		void LiveVariables::runOnInstr(MachineInstr &MI,
SmallVectorImpl<unsigned> &Defs) {		SmallVectorImpl<unsigned> &Defs) {
▲ Show 20 Lines • Show All 407 Lines • Show Last 20 Lines

llvm/lib/CodeGen/MachineFrameInfo.cpp

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines	BitVector MachineFrameInfo::getPristineRegs(const MachineFunction &MF) const {

const MachineRegisterInfo &MRI = MF.getRegInfo();		const MachineRegisterInfo &MRI = MF.getRegInfo();
for (const MCPhysReg CSR = MRI.getCalleeSavedRegs(); CSR && CSR;		for (const MCPhysReg CSR = MRI.getCalleeSavedRegs(); CSR && CSR;
++CSR)		++CSR)
BV.set(*CSR);		BV.set(*CSR);

// Saved CSRs are not pristine.		// Saved CSRs are not pristine.
for (const auto &I : getCalleeSavedInfo())		for (const auto &I : getCalleeSavedInfo())
for (MCSubRegIterator S(I.getReg(), TRI, true); S.isValid(); ++S)		for (MCPhysReg S : TRI->subregs_inclusive(I.getReg()))
BV.reset(*S);		BV.reset(S);

return BV;		return BV;
}		}

uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {		uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();		const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();		const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
Align MaxAlign = getMaxAlign();		Align MaxAlign = getMaxAlign();
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

llvm/lib/CodeGen/MachineInstrBundle.cpp

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines	for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
// Re-defined inside the bundle, it's no longer killed.		// Re-defined inside the bundle, it's no longer killed.
KilledDefSet.erase(Reg);		KilledDefSet.erase(Reg);
if (!MO.isDead())		if (!MO.isDead())
// Previously defined but dead.		// Previously defined but dead.
DeadDefSet.erase(Reg);		DeadDefSet.erase(Reg);
}		}

if (!MO.isDead() && Reg.isPhysical()) {		if (!MO.isDead() && Reg.isPhysical()) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI->subregs(Reg)) {
unsigned SubReg = *SubRegs;
if (LocalDefSet.insert(SubReg).second)		if (LocalDefSet.insert(SubReg).second)
LocalDefs.push_back(SubReg);		LocalDefs.push_back(SubReg);
}		}
}		}
}		}

Defs.clear();		Defs.clear();
}		}
▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines

llvm/lib/CodeGen/MachineRegisterInfo.cpp

Show First 20 Lines • Show All 639 Lines • ▼ Show 20 Lines	void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
UpdatedCSRs.push_back(0);		UpdatedCSRs.push_back(0);
IsUpdatedCSRsInitialized = true;		IsUpdatedCSRsInitialized = true;
}		}

bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {		bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
const TargetRegisterInfo *TRI = getTargetRegisterInfo();		const TargetRegisterInfo *TRI = getTargetRegisterInfo();
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {		for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
bool IsRootReserved = true;		bool IsRootReserved = true;
for (MCSuperRegIterator Super(Root, TRI, /IncludeSelf=*/true);		for (MCPhysReg Super : TRI->superregs_inclusive(*Root)) {
Super.isValid(); ++Super) {		MCRegister Reg = Super;
MCRegister Reg = *Super;
if (!isReserved(Reg)) {		if (!isReserved(Reg)) {
IsRootReserved = false;		IsRootReserved = false;
break;		break;
}		}
}		}
if (IsRootReserved)		if (IsRootReserved)
return true;		return true;
}		}
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llvm/lib/CodeGen/MachineSink.cpp

	Show First 20 Lines • Show All 1,694 Lines • ▼ Show 20 Lines
	}			}

	static void updateLiveIn(MachineInstr MI, MachineBasicBlock SuccBB,			static void updateLiveIn(MachineInstr MI, MachineBasicBlock SuccBB,
	SmallVectorImpl<unsigned> &UsedOpsInCopy,			SmallVectorImpl<unsigned> &UsedOpsInCopy,
	SmallVectorImpl<unsigned> &DefedRegsInCopy) {			SmallVectorImpl<unsigned> &DefedRegsInCopy) {
	MachineFunction &MF = *SuccBB->getParent();			MachineFunction &MF = *SuccBB->getParent();
	const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();			const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
	for (unsigned DefReg : DefedRegsInCopy)			for (unsigned DefReg : DefedRegsInCopy)
	for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)			for (MCPhysReg S : TRI->subregs_inclusive(DefReg))
	SuccBB->removeLiveIn(*S);			SuccBB->removeLiveIn(S);
	for (auto U : UsedOpsInCopy) {			for (auto U : UsedOpsInCopy) {
	Register SrcReg = MI->getOperand(U).getReg();			Register SrcReg = MI->getOperand(U).getReg();
	LaneBitmask Mask;			LaneBitmask Mask;
	for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {			for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {
	Mask \|= (*S).second;			Mask \|= (*S).second;
	}			}
	SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());			SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
	}			}
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llvm/lib/CodeGen/RDFLiveness.cpp

Show First 20 Lines • Show All 937 Lines • ▼ Show 20 Lines	for (auto &Op : MI.operands()) {
// live range of it, since an implicit use could be used to keep parts		// live range of it, since an implicit use could be used to keep parts
// of it live. Instead of analyzing the implicit operands, ignore		// of it live. Instead of analyzing the implicit operands, ignore
// implicit defs.		// implicit defs.
if (!Op.isReg() \|\| !Op.isDef() \|\| Op.isImplicit())		if (!Op.isReg() \|\| !Op.isDef() \|\| Op.isImplicit())
continue;		continue;
Register R = Op.getReg();		Register R = Op.getReg();
if (!R.isPhysical())		if (!R.isPhysical())
continue;		continue;
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI.subregs_inclusive(R))
Live.reset(*SR);		Live.reset(SR);
}		}
for (auto &Op : MI.operands()) {		for (auto &Op : MI.operands()) {
if (!Op.isReg() \|\| !Op.isUse() \|\| Op.isUndef())		if (!Op.isReg() \|\| !Op.isUse() \|\| Op.isUndef())
continue;		continue;
Register R = Op.getReg();		Register R = Op.getReg();
if (!R.isPhysical())		if (!R.isPhysical())
continue;		continue;
bool IsLive = false;		bool IsLive = false;
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {		for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
if (!Live[*AR])		if (!Live[*AR])
continue;		continue;
IsLive = true;		IsLive = true;
break;		break;
}		}
if (!IsLive)		if (!IsLive)
Op.setIsKill(true);		Op.setIsKill(true);
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI.subregs_inclusive(R))
Live.set(*SR);		Live.set(SR);
}		}
}		}
}		}

// Helper function to obtain the basic block containing the reaching def		// Helper function to obtain the basic block containing the reaching def
// of the given use.		// of the given use.
MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {		MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
auto F = NBMap.find(RN);		auto F = NBMap.find(RN);
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llvm/lib/CodeGen/RDFRegisters.cpp

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines	for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
}		}
MaskInfos[M].Units = PU.flip();		MaskInfos[M].Units = PU.flip();
}		}

AliasInfos.resize(TRI.getNumRegUnits());		AliasInfos.resize(TRI.getNumRegUnits());
for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {		for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
BitVector AS(TRI.getNumRegs());		BitVector AS(TRI.getNumRegs());
for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)		for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)
for (MCSuperRegIterator S(*R, &TRI, true); S.isValid(); ++S)		for (MCPhysReg S : TRI.superregs_inclusive(*R))
AS.set(*S);		AS.set(S);
AliasInfos[U].Regs = AS;		AliasInfos[U].Regs = AS;
}		}
}		}

std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {		std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
// Do not include RR in the alias set.		// Do not include RR in the alias set.
std::set<RegisterId> AS;		std::set<RegisterId> AS;
assert(isRegMaskId(Reg) \|\| Register::isPhysicalRegister(Reg));		assert(isRegMaskId(Reg) \|\| Register::isPhysicalRegister(Reg));
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llvm/lib/CodeGen/RegUsageInfoCollector.cpp

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines	if (SavedRegs.none())
return;		return;

// Insert subregs.		// Insert subregs.
const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);		const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
for (unsigned i = 0; CSRegs[i]; ++i) {		for (unsigned i = 0; CSRegs[i]; ++i) {
MCPhysReg Reg = CSRegs[i];		MCPhysReg Reg = CSRegs[i];
if (SavedRegs.test(Reg)) {		if (SavedRegs.test(Reg)) {
// Save subregisters		// Save subregisters
for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI.subregs(Reg))
SavedRegs.set(*SR);		SavedRegs.set(SR);
}		}
}		}
}		}

llvm/lib/CodeGen/RegisterScavenging.cpp

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines	if (MO.isUse()) {
// insert_subreg around causes both correctness and performance issues.		// insert_subreg around causes both correctness and performance issues.
bool SubUsed = false;		bool SubUsed = false;
for (const MCPhysReg &SubReg : TRI->subregs(Reg))		for (const MCPhysReg &SubReg : TRI->subregs(Reg))
if (isRegUsed(SubReg)) {		if (isRegUsed(SubReg)) {
SubUsed = true;		SubUsed = true;
break;		break;
}		}
bool SuperUsed = false;		bool SuperUsed = false;
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI->superregs(Reg)) {
if (isRegUsed(*SR)) {		if (isRegUsed(SR)) {
SuperUsed = true;		SuperUsed = true;
break;		break;
}		}
}		}
if (!SubUsed && !SuperUsed) {		if (!SubUsed && !SuperUsed) {
MBB->getParent()->verify(nullptr, "In Register Scavenger");		MBB->getParent()->verify(nullptr, "In Register Scavenger");
llvm_unreachable("Using an undefined register!");		llvm_unreachable("Using an undefined register!");
}		}
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llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

Show First 20 Lines • Show All 328 Lines • ▼ Show 20 Lines	if (!MO.isDef()) {
// Push this SUnit on the use list.		// Push this SUnit on the use list.
Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));		Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
if (RemoveKillFlags)		if (RemoveKillFlags)
MO.setIsKill(false);		MO.setIsKill(false);
} else {		} else {
addPhysRegDataDeps(SU, OperIdx);		addPhysRegDataDeps(SU, OperIdx);

// Clear previous uses and defs of this register and its subergisters.		// Clear previous uses and defs of this register and its subergisters.
for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {		for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
if (Uses.contains(*SubReg))		if (Uses.contains(SubReg))
Uses.eraseAll(*SubReg);		Uses.eraseAll(SubReg);
if (!MO.isDead())		if (!MO.isDead())
Defs.eraseAll(*SubReg);		Defs.eraseAll(SubReg);
}		}
if (MO.isDead() && SU->isCall) {		if (MO.isDead() && SU->isCall) {
// Calls will not be reordered because of chain dependencies (see		// Calls will not be reordered because of chain dependencies (see
// below). Since call operands are dead, calls may continue to be added		// below). Since call operands are dead, calls may continue to be added
// to the DefList making dependence checking quadratic in the size of		// to the DefList making dependence checking quadratic in the size of
// the block. Instead, we leave only one call at the back of the		// the block. Instead, we leave only one call at the back of the
// DefList.		// DefList.
Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);		Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
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llvm/lib/CodeGen/StackMaps.cpp

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines	unsigned StackMaps::getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx) {
++CurIdx;		++CurIdx;
assert(CurIdx < MI->getNumOperands() && "points past operand list");		assert(CurIdx < MI->getNumOperands() && "points past operand list");
return CurIdx;		return CurIdx;
}		}

/// Go up the super-register chain until we hit a valid dwarf register number.		/// Go up the super-register chain until we hit a valid dwarf register number.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {		static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
int RegNum = TRI->getDwarfRegNum(Reg, false);		int RegNum = TRI->getDwarfRegNum(Reg, false);
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)		for (MCPhysReg SR : TRI->superregs(Reg)) {
RegNum = TRI->getDwarfRegNum(*SR, false);		if (RegNum >= 0)
		break;
		RegNum = TRI->getDwarfRegNum(SR, false);
		}

assert(RegNum >= 0 && "Invalid Dwarf register number.");		assert(RegNum >= 0 && "Invalid Dwarf register number.");
return (unsigned)RegNum;		return (unsigned)RegNum;
}		}

MachineInstr::const_mop_iterator		MachineInstr::const_mop_iterator
StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,		StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
MachineInstr::const_mop_iterator MOE, LocationVec &Locs,		MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
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llvm/lib/CodeGen/TargetRegisterInfo.cpp

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
if (MI && TII->isTriviallyReMaterializable(*MI) &&		if (MI && TII->isTriviallyReMaterializable(*MI) &&
VirtReg.size() > HugeSizeForSplit)		VirtReg.size() > HugeSizeForSplit)
return false;		return false;
return true;		return true;
}		}

void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,		void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
MCRegister Reg) const {		MCRegister Reg) const {
for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)		for (MCPhysReg SR : superregs_inclusive(Reg))
RegisterSet.set(*AI);		RegisterSet.set(SR);
}		}

bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,		bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
ArrayRef<MCPhysReg> Exceptions) const {		ArrayRef<MCPhysReg> Exceptions) const {
// Check that all super registers of reserved regs are reserved as well.		// Check that all super registers of reserved regs are reserved as well.
BitVector Checked(getNumRegs());		BitVector Checked(getNumRegs());
for (unsigned Reg : RegisterSet.set_bits()) {		for (unsigned Reg : RegisterSet.set_bits()) {
if (Checked[Reg])		if (Checked[Reg])
continue;		continue;
for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {		for (MCPhysReg SR : superregs(Reg)) {
if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {		if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) {
dbgs() << "Error: Super register " << printReg(*SR, this)		dbgs() << "Error: Super register " << printReg(SR, this)
<< " of reserved register " << printReg(Reg, this)		<< " of reserved register " << printReg(Reg, this)
<< " is not reserved.\n";		<< " is not reserved.\n";
return false;		return false;
}		}

// We transitively check superregs. So we can remember this for later		// We transitively check superregs. So we can remember this for later
// to avoid compiletime explosion in deep register hierarchies.		// to avoid compiletime explosion in deep register hierarchies.
Checked.set(*SR);		Checked.set(SR);
}		}
}		}
return true;		return true;
}		}

namespace llvm {		namespace llvm {

Printable printReg(Register Reg, const TargetRegisterInfo *TRI,		Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
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llvm/lib/MC/MCRegisterInfo.cpp

	Show All 17 Lines
	#include <cassert>			#include <cassert>
	#include <cstdint>			#include <cstdint>

	using namespace llvm;			using namespace llvm;

	MCRegister			MCRegister
	MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,			MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
	const MCRegisterClass *RC) const {			const MCRegisterClass *RC) const {
	for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)			for (MCPhysReg Super : superregs(Reg))
	if (RC->contains(Supers) && Reg == getSubReg(Supers, SubIdx))			if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx))
	return *Supers;			return Super;
	return 0;			return 0;
	}			}

	MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {			MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
	assert(Idx && Idx < getNumSubRegIndices() &&			assert(Idx && Idx < getNumSubRegIndices() &&
	"This is not a subregister index");			"This is not a subregister index");
	// Get a pointer to the corresponding SubRegIndices list. This list has the			// Get a pointer to the corresponding SubRegIndices list. This list has the
	// name of each sub-register in the same order as MCSubRegIterator.			// name of each sub-register in the same order as MCSubRegIterator.
	const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;			const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
	for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)			for (MCPhysReg Sub : subregs(Reg)) {
	if (*SRI == Idx)			if (*SRI == Idx)
	return *Subs;			return Sub;
				++SRI;
				}
	return 0;			return 0;
	}			}

	unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,			unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
	MCRegister SubReg) const {			MCRegister SubReg) const {
	assert(SubReg && SubReg < getNumRegs() && "This is not a register");			assert(SubReg && SubReg < getNumRegs() && "This is not a register");
	// Get a pointer to the corresponding SubRegIndices list. This list has the			// Get a pointer to the corresponding SubRegIndices list. This list has the
	// name of each sub-register in the same order as MCSubRegIterator.			// name of each sub-register in the same order as MCSubRegIterator.
	const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;			const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
	for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)			for (MCPhysReg Sub : subregs(Reg)) {
	if (*Subs == SubReg)			if (Sub == SubReg)
	return *SRI;			return *SRI;
				++SRI;
				}
	return 0;			return 0;
	}			}

	unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {			unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
	assert(Idx && Idx < getNumSubRegIndices() &&			assert(Idx && Idx < getNumSubRegIndices() &&
	"This is not a subregister index");			"This is not a subregister index");
	return SubRegIdxRanges[Idx].Size;			return SubRegIdxRanges[Idx].Size;
	}			}
	▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Lines	for (WriteState &WS : IS->getDefs()) {
MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs;		MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs;
if (RenameAs && RenameAs != RegID)		if (RenameAs && RenameAs != RegID)
RegID = RenameAs;		RegID = RenameAs;

WriteRef &WR = RegisterMappings[RegID].first;		WriteRef &WR = RegisterMappings[RegID].first;
if (WR.getWriteState() == &WS)		if (WR.getWriteState() == &WS)
WR.notifyExecuted(CurrentCycle);		WR.notifyExecuted(CurrentCycle);

for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.subregs(RegID)) {
WriteRef &OtherWR = RegisterMappings[*I].first;		WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)		if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle);		OtherWR.notifyExecuted(CurrentCycle);
}		}

if (!WS.clearsSuperRegisters())		if (!WS.clearsSuperRegisters())
continue;		continue;

for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.superregs(RegID)) {
WriteRef &OtherWR = RegisterMappings[*I].first;		WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)		if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle);		OtherWR.notifyExecuted(CurrentCycle);
}		}
}		}
}		}

void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF,		void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF,
ArrayRef<MCRegisterCostEntry> Entries) {		ArrayRef<MCRegisterCostEntry> Entries) {
Show All 28 Lines	for (const MCPhysReg Reg : RC) {
errs() << "warning: register " << MRI.getName(Reg)		errs() << "warning: register " << MRI.getName(Reg)
<< " defined in multiple register files.";		<< " defined in multiple register files.";
}		}
IPC = std::make_pair(RegisterFileIndex, RCE.Cost);		IPC = std::make_pair(RegisterFileIndex, RCE.Cost);
Entry.RenameAs = Reg;		Entry.RenameAs = Reg;
Entry.AllowMoveElimination = RCE.AllowMoveElimination;		Entry.AllowMoveElimination = RCE.AllowMoveElimination;

// Assume the same cost for each sub-register.		// Assume the same cost for each sub-register.
for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.subregs(Reg)) {
RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second;		RegisterRenamingInfo &OtherEntry = RegisterMappings[I].second;
if (!OtherEntry.IndexPlusCost.first &&		if (!OtherEntry.IndexPlusCost.first &&
(!OtherEntry.RenameAs \|\|		(!OtherEntry.RenameAs \|\|
MRI.isSuperRegister(*I, OtherEntry.RenameAs))) {		MRI.isSuperRegister(I, OtherEntry.RenameAs))) {
OtherEntry.IndexPlusCost = IPC;		OtherEntry.IndexPlusCost = IPC;
OtherEntry.RenameAs = Reg;		OtherEntry.RenameAs = Reg;
}		}
}		}
}		}
}		}
}		}

▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines	if (!WS.clearsSuperRegisters()) {
}		}
}		}
}		}

// Update zero registers.		// Update zero registers.
MCPhysReg ZeroRegisterID =		MCPhysReg ZeroRegisterID =
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();		WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);		ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I)		for (MCPhysReg I : MRI.subregs(ZeroRegisterID))
ZeroRegisters.setBitVal(*I, IsWriteZero);		ZeroRegisters.setBitVal(I, IsWriteZero);

// If this move has been eliminated, then method tryEliminateMoveOrSwap should		// If this move has been eliminated, then method tryEliminateMoveOrSwap should
// have already updated all the register mappings.		// have already updated all the register mappings.
if (!IsEliminated) {		if (!IsEliminated) {
// Check if this is one of multiple writes performed by this		// Check if this is one of multiple writes performed by this
// instruction to register RegID.		// instruction to register RegID.
const WriteRef &OtherWrite = RegisterMappings[RegID].first;		const WriteRef &OtherWrite = RegisterMappings[RegID].first;
const WriteState *OtherWS = OtherWrite.getWriteState();		const WriteState *OtherWS = OtherWrite.getWriteState();
if (OtherWS && OtherWrite.getSourceIndex() == Write.getSourceIndex()) {		if (OtherWS && OtherWrite.getSourceIndex() == Write.getSourceIndex()) {
if (OtherWS->getLatency() > WS.getLatency()) {		if (OtherWS->getLatency() > WS.getLatency()) {
// Conservatively keep the slowest write on RegID.		// Conservatively keep the slowest write on RegID.
if (ShouldAllocatePhysRegs)		if (ShouldAllocatePhysRegs)
allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);		allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);
return;		return;
}		}
}		}

// Update the mapping for register RegID including its sub-registers.		// Update the mapping for register RegID including its sub-registers.
RegisterMappings[RegID].first = Write;		RegisterMappings[RegID].first = Write;
RegisterMappings[RegID].second.AliasRegID = 0U;		RegisterMappings[RegID].second.AliasRegID = 0U;
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.subregs(RegID)) {
RegisterMappings[*I].first = Write;		RegisterMappings[I].first = Write;
RegisterMappings[*I].second.AliasRegID = 0U;		RegisterMappings[I].second.AliasRegID = 0U;
}		}

// No physical registers are allocated for instructions that are optimized		// No physical registers are allocated for instructions that are optimized
// in hardware. For example, zero-latency data-dependency breaking		// in hardware. For example, zero-latency data-dependency breaking
// instructions don't consume physical registers.		// instructions don't consume physical registers.
if (ShouldAllocatePhysRegs)		if (ShouldAllocatePhysRegs)
allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);		allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);
}		}

if (!WS.clearsSuperRegisters())		if (!WS.clearsSuperRegisters())
return;		return;

for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.superregs(RegID)) {
if (!IsEliminated) {		if (!IsEliminated) {
RegisterMappings[*I].first = Write;		RegisterMappings[I].first = Write;
RegisterMappings[*I].second.AliasRegID = 0U;		RegisterMappings[I].second.AliasRegID = 0U;
}		}

ZeroRegisters.setBitVal(*I, IsWriteZero);		ZeroRegisters.setBitVal(I, IsWriteZero);
}		}
}		}

void RegisterFile::removeRegisterWrite(		void RegisterFile::removeRegisterWrite(
const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) {		const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) {
// Early exit if this write was eliminated. A write eliminated at register		// Early exit if this write was eliminated. A write eliminated at register
// renaming stage generates an alias, and it is not added to the PRF.		// renaming stage generates an alias, and it is not added to the PRF.
if (WS.isEliminated())		if (WS.isEliminated())
Show All 23 Lines	void RegisterFile::removeRegisterWrite(

if (ShouldFreePhysRegs)		if (ShouldFreePhysRegs)
freePhysRegs(RegisterMappings[RegID].second, FreedPhysRegs);		freePhysRegs(RegisterMappings[RegID].second, FreedPhysRegs);

WriteRef &WR = RegisterMappings[RegID].first;		WriteRef &WR = RegisterMappings[RegID].first;
if (WR.getWriteState() == &WS)		if (WR.getWriteState() == &WS)
WR.commit();		WR.commit();

for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.subregs(RegID)) {
WriteRef &OtherWR = RegisterMappings[*I].first;		WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)		if (OtherWR.getWriteState() == &WS)
OtherWR.commit();		OtherWR.commit();
}		}

if (!WS.clearsSuperRegisters())		if (!WS.clearsSuperRegisters())
return;		return;

for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.superregs(RegID)) {
WriteRef &OtherWR = RegisterMappings[*I].first;		WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)		if (OtherWR.getWriteState() == &WS)
OtherWR.commit();		OtherWR.commit();
}		}
}		}

bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS,		bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS,
unsigned RegisterFileIndex) const {		unsigned RegisterFileIndex) const {
const RegisterMapping &RMFrom = RegisterMappings[RS.getRegisterID()];		const RegisterMapping &RMFrom = RegisterMappings[RS.getRegisterID()];
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines	MCPhysReg AliasedReg =
RRIFrom.RenameAs ? RRIFrom.RenameAs : RS.getRegisterID();		RRIFrom.RenameAs ? RRIFrom.RenameAs : RS.getRegisterID();
MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID();		MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID();

const RegisterRenamingInfo &RMAlias = RegisterMappings[AliasedReg].second;		const RegisterRenamingInfo &RMAlias = RegisterMappings[AliasedReg].second;
if (RMAlias.AliasRegID)		if (RMAlias.AliasRegID)
AliasedReg = RMAlias.AliasRegID;		AliasedReg = RMAlias.AliasRegID;

RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;		RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
for (MCSubRegIterator I(AliasReg, &MRI); I.isValid(); ++I)		for (MCPhysReg I : MRI.subregs(AliasReg))
RegisterMappings[*I].second.AliasRegID = AliasedReg;		RegisterMappings[I].second.AliasRegID = AliasedReg;

if (ZeroRegisters[RS.getRegisterID()]) {		if (ZeroRegisters[RS.getRegisterID()]) {
WS.setWriteZero();		WS.setWriteZero();
RS.setReadZero();		RS.setReadZero();
}		}

WS.setEliminated();		WS.setEliminated();
RMT.NumMoveEliminated++;		RMT.NumMoveEliminated++;
Show All 40 Lines	if (WR.getWriteState()) {
if (ReadAdvance < 0) {		if (ReadAdvance < 0) {
unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);		unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
if (Elapsed < static_cast<unsigned>(-ReadAdvance))		if (Elapsed < static_cast<unsigned>(-ReadAdvance))
CommittedWrites.push_back(WR);		CommittedWrites.push_back(WR);
}		}
}		}

// Handle potential partial register updates.		// Handle potential partial register updates.
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {		for (MCPhysReg I : MRI.subregs(RegID)) {
const WriteRef &WR = RegisterMappings[*I].first;		const WriteRef &WR = RegisterMappings[I].first;
if (WR.getWriteState()) {		if (WR.getWriteState()) {
Writes.push_back(WR);		Writes.push_back(WR);
} else if (WR.hasKnownWriteBackCycle()) {		} else if (WR.hasKnownWriteBackCycle()) {
unsigned WriteResID = WR.getWriteResourceID();		unsigned WriteResID = WR.getWriteResourceID();
int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);		int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
if (ReadAdvance < 0) {		if (ReadAdvance < 0) {
unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);		unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
if (Elapsed < static_cast<unsigned>(-ReadAdvance))		if (Elapsed < static_cast<unsigned>(-ReadAdvance))
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Show First 20 Lines • Show All 303 Lines • ▼ Show 20 Lines
void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF,		void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF,
const uint32_t **Mask) const {		const uint32_t **Mask) const {
uint32_t *UpdatedMask = MF.allocateRegMask();		uint32_t *UpdatedMask = MF.allocateRegMask();
unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());		unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
memcpy(UpdatedMask, Mask, sizeof(UpdatedMask[0]) RegMaskSize);		memcpy(UpdatedMask, Mask, sizeof(UpdatedMask[0]) RegMaskSize);

for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {		for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {		if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),		for (MCPhysReg SubReg :
this, true);		subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
SubReg.isValid(); ++SubReg) {
// See TargetRegisterInfo::getCallPreservedMask for how to interpret the		// See TargetRegisterInfo::getCallPreservedMask for how to interpret the
// register mask.		// register mask.
UpdatedMask[SubReg / 32] \|= 1u << (SubReg % 32);		UpdatedMask[SubReg / 32] \|= 1u << (SubReg % 32);
}		}
}		}
}		}
*Mask = UpdatedMask;		*Mask = UpdatedMask;
}		}

const uint32_t *AArch64RegisterInfo::getSMStartStopCallPreservedMask() const {		const uint32_t *AArch64RegisterInfo::getSMStartStopCallPreservedMask() const {
return CSR_AArch64_SMStartStop_RegMask;		return CSR_AArch64_SMStartStop_RegMask;
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines	if (hasBasePointer(MF))
markSuperRegs(Reserved, AArch64::W19);		markSuperRegs(Reserved, AArch64::W19);

// SLH uses register W16/X16 as the taint register.		// SLH uses register W16/X16 as the taint register.
if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))		if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
markSuperRegs(Reserved, AArch64::W16);		markSuperRegs(Reserved, AArch64::W16);

// SME tiles are not allocatable.		// SME tiles are not allocatable.
if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {		if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
for (MCSubRegIterator SubReg(AArch64::ZA, this, /self=/true);		for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA))
SubReg.isValid(); ++SubReg)		Reserved.set(SubReg);
Reserved.set(*SubReg);
}		}

markSuperRegs(Reserved, AArch64::FPCR);		markSuperRegs(Reserved, AArch64::FPCR);

assert(checkAllSuperRegsMarked(Reserved));		assert(checkAllSuperRegsMarked(Reserved));
return Reserved;		return Reserved;
}		}

▲ Show 20 Lines • Show All 550 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Show First 20 Lines • Show All 280 Lines • ▼ Show 20 Lines	case 'q': // Print a NEON quad precision register.
printOperand(MI, OpNum, O);		printOperand(MI, OpNum, O);
return false;		return false;
case 'y': // Print a VFP single precision register as indexed double.		case 'y': // Print a VFP single precision register as indexed double.
if (MI->getOperand(OpNum).isReg()) {		if (MI->getOperand(OpNum).isReg()) {
MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();		MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();		const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
// Find the 'd' register that has this 's' register as a sub-register,		// Find the 'd' register that has this 's' register as a sub-register,
// and determine the lane number.		// and determine the lane number.
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI->superregs(Reg)) {
if (!ARM::DPRRegClass.contains(*SR))		if (!ARM::DPRRegClass.contains(SR))
continue;		continue;
bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;		bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg;
O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");		O << ARMInstPrinter::getRegisterName(SR) << (Lane0 ? "[0]" : "[1]");
return false;		return false;
}		}
}		}
return true;		return true;
case 'B': // Bitwise inverse of integer or symbol without a preceding #.		case 'B': // Bitwise inverse of integer or symbol without a preceding #.
if (!MI->getOperand(OpNum).isImm())		if (!MI->getOperand(OpNum).isImm())
return true;		return true;
O << ~(MI->getOperand(OpNum).getImm());		O << ~(MI->getOperand(OpNum).getImm());
▲ Show 20 Lines • Show All 2,036 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines	getReservedRegs(const MachineFunction &MF) const {
// Reserve D16-D31 if the subtarget doesn't support them.		// Reserve D16-D31 if the subtarget doesn't support them.
if (!STI.hasD32()) {		if (!STI.hasD32()) {
static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");		static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
for (unsigned R = 0; R < 16; ++R)		for (unsigned R = 0; R < 16; ++R)
markSuperRegs(Reserved, ARM::D16 + R);		markSuperRegs(Reserved, ARM::D16 + R);
}		}
const TargetRegisterClass &RC = ARM::GPRPairRegClass;		const TargetRegisterClass &RC = ARM::GPRPairRegClass;
for (unsigned Reg : RC)		for (unsigned Reg : RC)
for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)		for (MCPhysReg S : subregs(Reg))
if (Reserved.test(*SI))		if (Reserved.test(S))
markSuperRegs(Reserved, Reg);		markSuperRegs(Reserved, Reg);
// For v8.1m architecture		// For v8.1m architecture
markSuperRegs(Reserved, ARM::ZR);		markSuperRegs(Reserved, ARM::ZR);

assert(checkAllSuperRegsMarked(Reserved));		assert(checkAllSuperRegsMarked(Reserved));
return Reserved;		return Reserved;
}		}

▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines	ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case ARM::DPRRegClassID:		case ARM::DPRRegClassID:
return 32 - 10;		return 32 - 10;
}		}
}		}

// Get the other register in a GPRPair.		// Get the other register in a GPRPair.
static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,		static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
const MCRegisterInfo *RI) {		const MCRegisterInfo *RI) {
for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)		for (MCPhysReg Super : RI->superregs(Reg))
if (ARM::GPRPairRegClass.contains(*Supers))		if (ARM::GPRPairRegClass.contains(Super))
return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);		return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
return 0;		return 0;
}		}

// Resolve the RegPairEven / RegPairOdd register allocator hints.		// Resolve the RegPairEven / RegPairOdd register allocator hints.
bool ARMBaseRegisterInfo::getRegAllocationHints(		bool ARMBaseRegisterInfo::getRegAllocationHints(
Register VirtReg, ArrayRef<MCPhysReg> Order,		Register VirtReg, ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,		SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
const VirtRegMap VRM, const LiveRegMatrix Matrix) const {		const VirtRegMap VRM, const LiveRegMatrix Matrix) const {
▲ Show 20 Lines • Show All 609 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines	for (auto &MO : MI->operands()) {
if (MO.isUse())		if (MO.isUse())
LocalUses.push_back(Reg);		LocalUses.push_back(Reg);
else		else
LocalDefs.push_back(Reg);		LocalDefs.push_back(Reg);
}		}

auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {		auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
for (unsigned Reg : Regs)		for (unsigned Reg : Regs)
for (MCSubRegIterator Subreg(Reg, TRI, /IncludeSelf=/true);		for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg))
Subreg.isValid(); ++Subreg)		UsesDefs.insert(Subreg);
UsesDefs.insert(*Subreg);
};		};

InsertUsesDefs(LocalDefs, Defs);		InsertUsesDefs(LocalDefs, Defs);
InsertUsesDefs(LocalUses, Uses);		InsertUsesDefs(LocalUses, Uses);
}		}

/// Clear kill flags for any uses in the given set. This will likely		/// Clear kill flags for any uses in the given set. This will likely
/// conservatively remove more kill flags than are necessary, but removing them		/// conservatively remove more kill flags than are necessary, but removing them
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/lib/Target/BPF/BPFMIChecking.cpp

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines	static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) {

// No GPR64 dead Def, so all those GPR32 live Def can't have alias, therefore		// No GPR64 dead Def, so all those GPR32 live Def can't have alias, therefore
// must be truely live, safe to return true.		// must be truely live, safe to return true.
if (GPR64DeadDefs.empty())		if (GPR64DeadDefs.empty())
return true;		return true;

// Otherwise, return true if any aliased SuperReg of GPR32 is not dead.		// Otherwise, return true if any aliased SuperReg of GPR32 is not dead.
for (auto I : GPR32LiveDefs)		for (auto I : GPR32LiveDefs)
for (MCSuperRegIterator SR(I, TRI); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->superregs(I))
if (!llvm::is_contained(GPR64DeadDefs, *SR))		if (!llvm::is_contained(GPR64DeadDefs, SR))
return true;		return true;

return false;		return false;
}		}

bool BPFMIPreEmitChecking::processAtomicInsts() {		bool BPFMIPreEmitChecking::processAtomicInsts() {
for (MachineBasicBlock &MBB : *MF) {		for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {		for (MachineInstr &MI : MBB) {
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

	Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
	} // end namespace llvm			} // end namespace llvm

	#define DEBUG_TYPE "asm-printer"			#define DEBUG_TYPE "asm-printer"

	// Given a scalar register return its pair.			// Given a scalar register return its pair.
	inline static unsigned getHexagonRegisterPair(unsigned Reg,			inline static unsigned getHexagonRegisterPair(unsigned Reg,
	const MCRegisterInfo *RI) {			const MCRegisterInfo *RI) {
	assert(Hexagon::IntRegsRegClass.contains(Reg));			assert(Hexagon::IntRegsRegClass.contains(Reg));
	MCSuperRegIterator SR(Reg, RI, false);			unsigned Pair = *RI->superregs(Reg).begin();
	unsigned Pair = *SR;
	assert(Hexagon::DoubleRegsRegClass.contains(Pair));			assert(Hexagon::DoubleRegsRegClass.contains(Pair));
	return Pair;			return Pair;
	}			}

	void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,			void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
	raw_ostream &O) {			raw_ostream &O) {
	const MachineOperand &MO = MI->getOperand(OpNo);			const MachineOperand &MO = MI->getOperand(OpNo);

	▲ Show 20 Lines • Show All 764 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines	HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs(
RegisterSet SRs;		RegisterSet SRs;

if (R.Sub != 0) {		if (R.Sub != 0) {
SRs.insert(R);		SRs.insert(R);
return SRs;		return SRs;
}		}

if (R.Reg.isPhysical()) {		if (R.Reg.isPhysical()) {
MCSubRegIterator I(R.Reg, &TRI);		if (TRI.subregs(R.Reg).empty())
if (!I.isValid())
SRs.insert({R.Reg, 0});		SRs.insert({R.Reg, 0});
for (; I.isValid(); ++I)		for (MCPhysReg I : TRI.subregs(R.Reg))
SRs.insert({*I, 0});		SRs.insert({I, 0});
		arsenmUnsubmitted Not Done Reply Inline Actions This is a bit ugly arsenm: This is a bit ugly
} else {		} else {
assert(R.Reg.isVirtual());		assert(R.Reg.isVirtual());
auto &RC = *MRI.getRegClass(R.Reg);		auto &RC = *MRI.getRegClass(R.Reg);
unsigned PReg = *RC.begin();		unsigned PReg = *RC.begin();
MCSubRegIndexIterator I(PReg, &TRI);		MCSubRegIndexIterator I(PReg, &TRI);
if (!I.isValid())		if (!I.isValid())
SRs.insert({R.Reg, 0});		SRs.insert({R.Reg, 0});
for (; I.isValid(); ++I)		for (; I.isValid(); ++I)
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	for (auto &In : B) {
for (auto &Op : In.operands()) {		for (auto &Op : In.operands()) {
if (!Op.isRegMask())		if (!Op.isRegMask())
continue;		continue;
const uint32_t *BM = Op.getRegMask();		const uint32_t *BM = Op.getRegMask();
for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) {		for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) {
// Skip registers that have subregisters. A register is preserved		// Skip registers that have subregisters. A register is preserved
// iff its bit is set in the regmask, so if R1:0 was preserved, both		// iff its bit is set in the regmask, so if R1:0 was preserved, both
// R1 and R0 would also be present.		// R1 and R0 would also be present.
if (MCSubRegIterator(PR, &TRI, false).isValid())		if (!TRI.subregs(PR).empty())
continue;		continue;
if (Reserved[PR])		if (Reserved[PR])
continue;		continue;
if (BM[PR/32] & (1u << (PR%32)))		if (BM[PR/32] & (1u << (PR%32)))
continue;		continue;
RegisterRef R = { PR, 0 };		RegisterRef R = { PR, 0 };
if (!Defs.count(R))		if (!Defs.count(R))
Clobbers.insert(R);		Clobbers.insert(R);
}		}
}		}
// Defs and clobbers can overlap, e.g.		// Defs and clobbers can overlap, e.g.
// dead %d0 = COPY %5, implicit-def %r0, implicit-def %r1		// dead %d0 = COPY %5, implicit-def %r0, implicit-def %r1
for (RegisterRef R : Defs)		for (RegisterRef R : Defs)
Clobbers.erase(R);		Clobbers.erase(R);

// Update maps for defs.		// Update maps for defs.
for (RegisterRef S : Defs) {		for (RegisterRef S : Defs) {
// Defs should already be expanded into subregs.		// Defs should already be expanded into subregs.
assert(!S.Reg.isPhysical() \|\|		assert(!S.Reg.isPhysical() \|\| TRI.subregs(S.Reg).empty());
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None \|\| LastUse[S] != IndexType::None)		if (LastDef[S] != IndexType::None \|\| LastUse[S] != IndexType::None)
closeRange(S);		closeRange(S);
LastDef[S] = Index;		LastDef[S] = Index;
}		}
// Update maps for clobbers.		// Update maps for clobbers.
for (RegisterRef S : Clobbers) {		for (RegisterRef S : Clobbers) {
// Clobbers should already be expanded into subregs.		// Clobbers should already be expanded into subregs.
assert(!S.Reg.isPhysical() \|\|		assert(!S.Reg.isPhysical() \|\| TRI.subregs(S.Reg).empty());
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None \|\| LastUse[S] != IndexType::None)		if (LastDef[S] != IndexType::None \|\| LastUse[S] != IndexType::None)
closeRange(S);		closeRange(S);
// Create a single-instruction range.		// Create a single-instruction range.
LastDef[S] = LastUse[S] = Index;		LastDef[S] = LastUse[S] = Index;
closeRange(S);		closeRange(S);
}		}
}		}

▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines	for (MachineInstr &MI : BB) {
// Put instructions that last defined integer or double registers into the		// Put instructions that last defined integer or double registers into the
// map.		// map.
for (MachineOperand &Op : MI.operands()) {		for (MachineOperand &Op : MI.operands()) {
if (Op.isReg()) {		if (Op.isReg()) {
if (!Op.isDef() \|\| !Op.getReg())		if (!Op.isDef() \|\| !Op.getReg())
continue;		continue;
Register Reg = Op.getReg();		Register Reg = Op.getReg();
if (Hexagon::DoubleRegsRegClass.contains(Reg)) {		if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)		for (MCPhysReg SubReg : TRI->subregs(Reg))
LastDef[*SubRegs] = &MI;		LastDef[SubReg] = &MI;
} else if (Hexagon::IntRegsRegClass.contains(Reg))		} else if (Hexagon::IntRegsRegClass.contains(Reg))
LastDef[Reg] = &MI;		LastDef[Reg] = &MI;
} else if (Op.isRegMask()) {		} else if (Op.isRegMask()) {
for (unsigned Reg : Hexagon::IntRegsRegClass)		for (unsigned Reg : Hexagon::IntRegsRegClass)
if (Op.clobbersPhysReg(Reg))		if (Op.clobbersPhysReg(Reg))
LastDef[Reg] = &MI;		LastDef[Reg] = &MI;
}		}
}		}
▲ Show 20 Lines • Show All 431 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Lines
/// i.e. D3 (aka R7:6) will be mapped to R7, etc.		/// i.e. D3 (aka R7:6) will be mapped to R7, etc.
static Register getMax32BitSubRegister(Register Reg,		static Register getMax32BitSubRegister(Register Reg,
const TargetRegisterInfo &TRI,		const TargetRegisterInfo &TRI,
bool hireg = true) {		bool hireg = true) {
if (Reg < Hexagon::D0 \|\| Reg > Hexagon::D15)		if (Reg < Hexagon::D0 \|\| Reg > Hexagon::D15)
return Reg;		return Reg;

Register RegNo = 0;		Register RegNo = 0;
for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {		for (MCPhysReg SubReg : TRI.subregs(Reg)) {
if (hireg) {		if (hireg) {
if (*SubRegs > RegNo)		if (SubReg > RegNo)
RegNo = *SubRegs;		RegNo = SubReg;
} else {		} else {
if (!RegNo \|\| *SubRegs < RegNo)		if (!RegNo \|\| SubReg < RegNo)
RegNo = *SubRegs;		RegNo = SubReg;
}		}
}		}
return RegNo;		return RegNo;
}		}

/// Returns the callee saved register with the largest id in the vector.		/// Returns the callee saved register with the largest id in the vector.
static Register getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,		static Register getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,
const TargetRegisterInfo &TRI) {		const TargetRegisterInfo &TRI) {
Show All 36 Lines	for (const MachineInstr &MI : MBB) {
if (MO.isFI())		if (MO.isFI())
return true;		return true;
if (MO.isReg()) {		if (MO.isReg()) {
Register R = MO.getReg();		Register R = MO.getReg();
// Virtual registers will need scavenging, which then may require		// Virtual registers will need scavenging, which then may require
// a stack slot.		// a stack slot.
if (R.isVirtual())		if (R.isVirtual())
return true;		return true;
for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)		for (MCPhysReg S : HRI.subregs_inclusive(R))
if (CSR[*S])		if (CSR[S])
return true;		return true;
continue;		continue;
}		}
if (MO.isRegMask()) {		if (MO.isRegMask()) {
// A regmask would normally have all callee-saved registers marked		// A regmask would normally have all callee-saved registers marked
// as preserved, so this check would not be needed, but in case of		// as preserved, so this check would not be needed, but in case of
// ever having other regmasks (for other calling conventions),		// ever having other regmasks (for other calling conventions),
// make sure they would be processed correctly.		// make sure they would be processed correctly.
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines	for (MachineBasicBlock *Succ : I.successors())
return;		return;
}		}

// Collect the set of blocks that need a stack frame to execute. Scan		// Collect the set of blocks that need a stack frame to execute. Scan
// each block for uses/defs of callee-saved registers, calls, etc.		// each block for uses/defs of callee-saved registers, calls, etc.
SmallVector<MachineBasicBlock*,16> SFBlocks;		SmallVector<MachineBasicBlock*,16> SFBlocks;
BitVector CSR(Hexagon::NUM_TARGET_REGS);		BitVector CSR(Hexagon::NUM_TARGET_REGS);
for (const MCPhysReg P = HRI.getCalleeSavedRegs(&MF); P; ++P)		for (const MCPhysReg P = HRI.getCalleeSavedRegs(&MF); P; ++P)
for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)		for (MCPhysReg S : HRI.subregs_inclusive(*P))
CSR[*S] = true;		CSR[S] = true;

for (auto &I : MF)		for (auto &I : MF)
if (needsStackFrame(I, CSR, HRI))		if (needsStackFrame(I, CSR, HRI))
SFBlocks.push_back(&I);		SFBlocks.push_back(&I);

LLVM_DEBUG({		LLVM_DEBUG({
dbgs() << "Blocks needing SF: {";		dbgs() << "Blocks needing SF: {";
for (auto &B : SFBlocks)		for (auto &B : SFBlocks)
▲ Show 20 Lines • Show All 1,112 Lines • ▼ Show 20 Lines	bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
// i.e. for each R in SRegs, no proper super-register of R is also in SRegs.		// i.e. for each R in SRegs, no proper super-register of R is also in SRegs.

// (1) For each callee-saved register, add that register and all of its		// (1) For each callee-saved register, add that register and all of its
// sub-registers to SRegs.		// sub-registers to SRegs.
LLVM_DEBUG(dbgs() << "Initial CS registers: {");		LLVM_DEBUG(dbgs() << "Initial CS registers: {");
for (const CalleeSavedInfo &I : CSI) {		for (const CalleeSavedInfo &I : CSI) {
Register R = I.getReg();		Register R = I.getReg();
LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));		LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->subregs_inclusive(R))
SRegs[*SR] = true;		SRegs[SR] = true;
}		}
LLVM_DEBUG(dbgs() << " }\n");		LLVM_DEBUG(dbgs() << " }\n");
LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);		LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
dbgs() << "\n");		dbgs() << "\n");

// (2) For each reserved register, remove that register and all of its		// (2) For each reserved register, remove that register and all of its
// sub- and super-registers from SRegs.		// sub- and super-registers from SRegs.
BitVector Reserved = TRI->getReservedRegs(MF);		BitVector Reserved = TRI->getReservedRegs(MF);
// Unreserve the stack align register: it is reserved for this function		// Unreserve the stack align register: it is reserved for this function
// only, it still needs to be saved/restored.		// only, it still needs to be saved/restored.
Register AP =		Register AP =
MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();		MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();
if (AP.isValid()) {		if (AP.isValid()) {
Reserved[AP] = false;		Reserved[AP] = false;
// Unreserve super-regs if no other subregisters are reserved.		// Unreserve super-regs if no other subregisters are reserved.
for (MCSuperRegIterator SP(AP, TRI, false); SP.isValid(); ++SP) {		for (MCPhysReg SP : TRI->superregs(AP)) {
bool HasResSub = false;		bool HasResSub = false;
for (MCSubRegIterator SB(*SP, TRI, false); SB.isValid(); ++SB) {		for (MCPhysReg SB : TRI->subregs(SP)) {
if (!Reserved[*SB])		if (!Reserved[SB])
continue;		continue;
HasResSub = true;		HasResSub = true;
break;		break;
}		}
if (!HasResSub)		if (!HasResSub)
Reserved[*SP] = false;		Reserved[SP] = false;
}		}
}		}

for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {		for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
Register R = x;		Register R = x;
for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->superregs_inclusive(R))
SRegs[*SR] = false;		SRegs[SR] = false;
}		}
LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);		LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
dbgs() << "\n");		dbgs() << "\n");
LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);		LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
dbgs() << "\n");		dbgs() << "\n");

// (3) Collect all registers that have at least one sub-register in SRegs,		// (3) Collect all registers that have at least one sub-register in SRegs,
// and also have no sub-registers that are reserved. These will be the can-		// and also have no sub-registers that are reserved. These will be the can-
// didates for saving as a whole instead of their individual sub-registers.		// didates for saving as a whole instead of their individual sub-registers.
// (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)		// (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
BitVector TmpSup(Hexagon::NUM_TARGET_REGS);		BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {		for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
Register R = x;		Register R = x;
for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)		for (MCPhysReg SR : TRI->superregs(R))
TmpSup[*SR] = true;		TmpSup[SR] = true;
}		}
for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {		for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
Register R = x;		Register R = x;
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI->subregs_inclusive(R)) {
if (!Reserved[*SR])		if (!Reserved[SR])
continue;		continue;
TmpSup[R] = false;		TmpSup[R] = false;
break;		break;
}		}
}		}
LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);		LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
dbgs() << "\n");		dbgs() << "\n");

// (4) Include all super-registers found in (3) into SRegs.		// (4) Include all super-registers found in (3) into SRegs.
SRegs \|= TmpSup;		SRegs \|= TmpSup;
LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);		LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
dbgs() << "\n");		dbgs() << "\n");

// (5) For each register R in SRegs, if any super-register of R is in SRegs,		// (5) For each register R in SRegs, if any super-register of R is in SRegs,
// remove R from SRegs.		// remove R from SRegs.
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {		for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
Register R = x;		Register R = x;
for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : TRI->superregs(R)) {
if (!SRegs[*SR])		if (!SRegs[SR])
continue;		continue;
SRegs[R] = false;		SRegs[R] = false;
break;		break;
}		}
}		}
LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);		LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
dbgs() << "\n");		dbgs() << "\n");

▲ Show 20 Lines • Show All 1,035 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
} // end anonymous namespace		} // end anonymous namespace

char HexagonGenMux::ID = 0;		char HexagonGenMux::ID = 0;

INITIALIZE_PASS(HexagonGenMux, "hexagon-gen-mux",		INITIALIZE_PASS(HexagonGenMux, "hexagon-gen-mux",
"Hexagon generate mux instructions", false, false)		"Hexagon generate mux instructions", false, false)

void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {		void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)		for (MCPhysReg I : HRI->subregs(Reg))
SRs[*I] = true;		SRs[I] = true;
}		}

void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const {		void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const {
if (isRegPair(Reg))		if (isRegPair(Reg))
getSubRegs(Reg, Set);		getSubRegs(Reg, Set);
else		else
Set[Reg] = true;		Set[Reg] = true;
}		}
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines	for (MuxInfo &MX : ML) {
B.remove(MX.Def2);		B.remove(MX.Def2);
Changed = true;		Changed = true;
}		}

// Fix up kill flags.		// Fix up kill flags.

LivePhysRegs LPR(*HRI);		LivePhysRegs LPR(*HRI);
LPR.addLiveOuts(B);		LPR.addLiveOuts(B);
auto IsLive = [&LPR,this] (unsigned Reg) -> bool {		auto IsLive = [&LPR, this](unsigned Reg) -> bool {
for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S)		for (MCPhysReg S : HRI->subregs_inclusive(Reg))
if (LPR.contains(*S))		if (LPR.contains(S))
return true;		return true;
return false;		return false;
};		};
for (MachineInstr &I : llvm::reverse(B)) {		for (MachineInstr &I : llvm::reverse(B)) {
if (I.isDebugInstr())		if (I.isDebugInstr())
continue;		continue;
// This isn't 100% accurate, but it's safe.		// This isn't 100% accurate, but it's safe.
// It won't detect (as a kill) a case like this		// It won't detect (as a kill) a case like this
Show All 29 Lines

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Show First 20 Lines • Show All 2,214 Lines • ▼ Show 20 Lines	bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,

for (auto &RegA : DefsA)		for (auto &RegA : DefsA)
for (auto &RegB : UsesB) {		for (auto &RegB : UsesB) {
// True data dependency.		// True data dependency.
if (RegA == RegB)		if (RegA == RegB)
return true;		return true;

if (RegA.isPhysical())		if (RegA.isPhysical())
for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)		for (MCPhysReg SubReg : HRI.subregs(RegA))
if (RegB == *SubRegs)		if (RegB == SubReg)
return true;		return true;

if (RegB.isPhysical())		if (RegB.isPhysical())
for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)		for (MCPhysReg SubReg : HRI.subregs(RegB))
if (RegA == *SubRegs)		if (RegA == SubReg)
return true;		return true;
}		}

return false;		return false;
}		}

// Returns true if the instruction is alread a .cur.		// Returns true if the instruction is alread a .cur.
bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {		bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
▲ Show 20 Lines • Show All 2,061 Lines • ▼ Show 20 Lines	int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
unsigned UseIdx) const {		unsigned UseIdx) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();		const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();

// Get DefIdx and UseIdx for super registers.		// Get DefIdx and UseIdx for super registers.
const MachineOperand &DefMO = DefMI.getOperand(DefIdx);		const MachineOperand &DefMO = DefMI.getOperand(DefIdx);

if (DefMO.isReg() && DefMO.getReg().isPhysical()) {		if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
if (DefMO.isImplicit()) {		if (DefMO.isImplicit()) {
for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);		int Idx = DefMI.findRegisterDefOperandIdx(SR, false, false, &HRI);
if (Idx != -1) {		if (Idx != -1) {
DefIdx = Idx;		DefIdx = Idx;
break;		break;
}		}
}		}
}		}

const MachineOperand &UseMO = UseMI.getOperand(UseIdx);		const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
if (UseMO.isImplicit()) {		if (UseMO.isImplicit()) {
for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {		for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) {
int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);		int Idx = UseMI.findRegisterUseOperandIdx(SR, false, &HRI);
if (Idx != -1) {		if (Idx != -1) {
UseIdx = Idx;		UseIdx = Idx;
break;		break;
}		}
}		}
}		}
}		}

▲ Show 20 Lines • Show All 419 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);		isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);

// Note use of new predicate register.		// Note use of new predicate register.
if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))		if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
NewPreds.insert(PredReg);		NewPreds.insert(PredReg);
} else		} else
// Note register use. Super-registers are not tracked directly,		// Note register use. Super-registers are not tracked directly,
// but their components.		// but their components.
for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());		for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid();
SRI.isValid(); ++SRI)		++SRI)
if (!MCSubRegIterator(*SRI, &RI).isValid())		if (RI.subregs(*SRI).empty())
// Skip super-registers used indirectly.		// Skip super-registers used indirectly.
Uses.insert(*SRI);		Uses.insert(*SRI);

if (HexagonMCInstrInfo::IsReverseVecRegPair(R))		if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
ReversePairs.insert(R);		ReversePairs.insert(R);
}		}

void HexagonMCChecker::init(MCInst const &MCI) {		void HexagonMCChecker::init(MCInst const &MCI) {
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines	for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
if (R == Hexagon::C8)		if (R == Hexagon::C8)
R = Hexagon::USR;		R = Hexagon::USR;

if (HexagonMCInstrInfo::IsReverseVecRegPair(R))		if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
ReversePairs.insert(R);		ReversePairs.insert(R);

// Note register definitions, direct ones as well as indirect side-effects.		// Note register definitions, direct ones as well as indirect side-effects.
// Super-registers are not tracked directly, but their components.		// Super-registers are not tracked directly, but their components.
for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());		for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid();
SRI.isValid(); ++SRI) {		++SRI) {
if (MCSubRegIterator(*SRI, &RI).isValid())		if (!RI.subregs(*SRI).empty())
// Skip super-registers defined indirectly.		// Skip super-registers defined indirectly.
continue;		continue;

if (R == *SRI) {		if (R == *SRI) {
if (S == R)		if (S == R)
// Avoid scoring the defined register multiple times.		// Avoid scoring the defined register multiple times.
continue;		continue;
else		else
▲ Show 20 Lines • Show All 673 Lines • Show Last 20 Lines

llvm/lib/Target/M68k/M68kRegisterInfo.cpp

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
const TargetRegisterClass *		const TargetRegisterClass *
M68kRegisterInfo::getRegsForTailCall(const MachineFunction &MF) const {		M68kRegisterInfo::getRegsForTailCall(const MachineFunction &MF) const {
return &M68k::XR32_TCRegClass;		return &M68k::XR32_TCRegClass;
}		}

unsigned		unsigned
M68kRegisterInfo::getMatchingMegaReg(unsigned Reg,		M68kRegisterInfo::getMatchingMegaReg(unsigned Reg,
const TargetRegisterClass *RC) const {		const TargetRegisterClass *RC) const {
for (MCSuperRegIterator Super(Reg, this); Super.isValid(); ++Super)		for (MCPhysReg Super : superregs(Reg))
if (RC->contains(*Super))		if (RC->contains(*Super))
return *Super;		return *Super;
return 0;		return 0;
}		}

const TargetRegisterClass *		const TargetRegisterClass *
M68kRegisterInfo::getMaximalPhysRegClass(unsigned reg, MVT VT) const {		M68kRegisterInfo::getMaximalPhysRegClass(unsigned reg, MVT VT) const {
assert(Register::isPhysicalRegister(reg) &&		assert(Register::isPhysicalRegister(reg) &&
Show All 37 Lines	BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

BitVector Reserved(getNumRegs());		BitVector Reserved(getNumRegs());

// Set a register's and its sub-registers and aliases as reserved.		// Set a register's and its sub-registers and aliases as reserved.
auto setBitVector = [&Reserved, this](unsigned Reg) {		auto setBitVector = [&Reserved, this](unsigned Reg) {
for (MCRegAliasIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {		for (MCRegAliasIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {
Reserved.set(*I);		Reserved.set(*I);
}		}
for (MCSubRegIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {		for (MCPhysReg I : subregs_inclusive(Reg)) {
Reserved.set(*I);		Reserved.set(*I);
}		}
};		};

// Registers reserved by users		// Registers reserved by users
for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {		for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {
if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))		if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))
setBitVector(Reg);		setBitVector(Reg);
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

Show First 20 Lines • Show All 424 Lines • ▼ Show 20 Lines	bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,

// Check if coalescing seems safe by finding the set of clobbered physreg		// Check if coalescing seems safe by finding the set of clobbered physreg
// pairs in the region.		// pairs in the region.
BitVector PhysClobbered(getNumRegs());		BitVector PhysClobbered(getNumRegs());
MEE++;		MEE++;
for (; MII != MEE; ++MII) {		for (; MII != MEE; ++MII) {
for (const MachineOperand &MO : MII->operands())		for (const MachineOperand &MO : MII->operands())
if (MO.isReg() && MO.getReg().isPhysical()) {		if (MO.isReg() && MO.getReg().isPhysical()) {
for (MCSuperRegIterator SI(MO.getReg(), this, true/IncludeSelf/);		for (MCPhysReg SI : superregs_inclusive(MO.getReg()))
SI.isValid(); ++SI)		if (NewRC->contains(SI)) {
if (NewRC->contains(*SI)) {		PhysClobbered.set(SI);
PhysClobbered.set(*SI);
break;		break;
}		}
}		}
}		}

// Demand an arbitrary margin of free regs.		// Demand an arbitrary margin of free regs.
unsigned const DemandedFreeGR128 = 3;		unsigned const DemandedFreeGR128 = 3;
if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))		if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
Show All 22 Lines

llvm/lib/Target/X86/X86ISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 3,572 Lines • ▼ Show 20 Lines	SDValue X86TargetLowering::LowerCallResult(
for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;		for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
++I, ++InsIndex) {		++I, ++InsIndex) {
CCValAssign &VA = RVLocs[I];		CCValAssign &VA = RVLocs[I];
EVT CopyVT = VA.getLocVT();		EVT CopyVT = VA.getLocVT();

// In some calling conventions we need to remove the used registers		// In some calling conventions we need to remove the used registers
// from the register mask.		// from the register mask.
if (RegMask) {		if (RegMask) {
for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(VA.getLocReg()))
SubRegs.isValid(); ++SubRegs)		RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
RegMask[SubRegs / 32] &= ~(1u << (SubRegs % 32));
}		}

// Report an error if there was an attempt to return FP values via XMM		// Report an error if there was an attempt to return FP values via XMM
// registers.		// registers.
if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {		if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) {
errorUnsupported(DAG, dl, "SSE register return with SSE disabled");		errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
if (VA.getLocReg() == X86::XMM1)		if (VA.getLocReg() == X86::XMM1)
VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.		VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts.
▲ Show 20 Lines • Show All 1,344 Lines • ▼ Show 20 Lines	if (ShouldDisableArgRegs \|\| shouldDisableRetRegFromCSR(CallConv)) {
RegMask = MF.allocateRegMask();		RegMask = MF.allocateRegMask();
unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());		unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);		memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize);

// Make sure all sub registers of the argument registers are reset		// Make sure all sub registers of the argument registers are reset
// in the RegMask.		// in the RegMask.
if (ShouldDisableArgRegs) {		if (ShouldDisableArgRegs) {
for (auto const &RegPair : RegsToPass)		for (auto const &RegPair : RegsToPass)
for (MCSubRegIterator SubRegs(RegPair.first, TRI, /IncludeSelf=/true);		for (MCPhysReg SubReg : TRI->subregs_inclusive(RegPair.first))
SubRegs.isValid(); ++SubRegs)		RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
RegMask[SubRegs / 32] &= ~(1u << (SubRegs % 32));
}		}

// Create the RegMask Operand according to our updated mask.		// Create the RegMask Operand according to our updated mask.
Ops.push_back(DAG.getRegisterMask(RegMask));		Ops.push_back(DAG.getRegisterMask(RegMask));
} else {		} else {
// Create the RegMask Operand according to the static mask.		// Create the RegMask Operand according to the static mask.
Ops.push_back(DAG.getRegisterMask(Mask));		Ops.push_back(DAG.getRegisterMask(Mask));
}		}
▲ Show 20 Lines • Show All 54,002 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.ClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 514617

llvm/include/llvm/CodeGen/LivePhysRegs.h

llvm/include/llvm/MC/MCRegisterInfo.h

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp

llvm/lib/CodeGen/BranchFolding.cpp

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

llvm/lib/CodeGen/IfConversion.cpp

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

llvm/lib/CodeGen/LiveIntervals.cpp

llvm/lib/CodeGen/LivePhysRegs.cpp

llvm/lib/CodeGen/LiveVariables.cpp

llvm/lib/CodeGen/MachineFrameInfo.cpp

llvm/lib/CodeGen/MachineInstrBundle.cpp

llvm/lib/CodeGen/MachineRegisterInfo.cpp

llvm/lib/CodeGen/MachineSink.cpp

llvm/lib/CodeGen/RDFLiveness.cpp

llvm/lib/CodeGen/RDFRegisters.cpp

llvm/lib/CodeGen/RegUsageInfoCollector.cpp

llvm/lib/CodeGen/RegisterScavenging.cpp

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

llvm/lib/CodeGen/StackMaps.cpp

llvm/lib/CodeGen/TargetRegisterInfo.cpp

llvm/lib/MC/MCRegisterInfo.cpp

llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm/lib/Target/BPF/BPFMIChecking.cpp

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp

llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

llvm/lib/Target/M68k/M68kRegisterInfo.cpp

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

llvm/lib/Target/X86/X86ISelLowering.cpp

[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.
ClosedPublic