This is an archive of the discontinued LLVM Phabricator instance.

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	Changes to Interprocedural Optimizations			Changes to Interprocedural Optimizations
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	Changes to the AArch64 Backend			Changes to the AArch64 Backend
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	Changes to the AMDGPU Backend			Changes to the AMDGPU Backend
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				* More fine-grained synchronization around barriers for newer architectures
				(gfx90a+, gfx10+). The AMDGPU backend now omits previously automatically
				generated waitcnt instructions before barriers, allowing for more precise
				control. Users must now use memory fences to implement fine-grained
				synchronization strategies around barriers. Refer to `AMDGPU memory model
				<AMDGPUUsage.html#memory-model>`__.

	Changes to the ARM Backend			Changes to the ARM Backend
	--------------------------			--------------------------

	- The hard-float ABI is now available in Armv8.1-M configurations that			- The hard-float ABI is now available in Armv8.1-M configurations that
	have integer MVE instructions (and therefore have FP registers) but			have integer MVE instructions (and therefore have FP registers) but
	no scalar or vector floating point computation.			no scalar or vector floating point computation.

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[AMDGPU] Add release note for ommited barrier waitcntClosedPublic