Introduce `llvm-min-tblgen` to build public header files

[chapuni]

Summary

llvm-min-tblgen is capable of building llvm/include/llvm;

• -gen-attrs
• -gen-directive-*
• -gen-intrinsics-*
• -gen-riscv-target-def
• -gen-vt

llvm-min-tblgen is built and used only when llvm-tblgen is built in-tree.
This is not installed.

llvm-tblgen is built with complete set and may be installed.
check-llvm uses not llvm-min-tblgen but llvm-tblgen.

LLVM_TABLEGEN_PROJECT overrides the definition of tablegen(project).
LLVM_HEADERS is used as the overridden prefix for LLVM header generators.

If EXPORT is not specified in add_tablegen, its tablegen is treated as internal.

Let llvm-tblgen depend on intrinsics_gen

Depends on D149072

[chapuni]

Changes in test files can be committed separately in advance.

I have just confirmed building. Let me know if there would be issues around installation and customization.

I am planning to move llvm-cg-tblgen to other place, possibly llvm/lib/CodeGen/TableGen.
See also D144351 and https://discourse.llvm.org/t/issues-in-llvm-tblgen-high-parallelized-build/68037/30

[mstorsjo]

llvm/utils/TableGen/CMakeLists.txt

68

I think there's a bit of conflict here, when you're calling add_tablegen twice with project set to LLVM.

This parameter is used for setting up the ${project}_TABLEGEN variable, which allows the user to specify a path to an existing such binary when e.g. cross compiling, instead of building a new one - see e.g. https://github.com/llvm/llvm-project/blob/llvmorg-16.0.0/llvm/cmake/modules/TableGen.cmake#L156-L169.

Currently, this can be set via LLVM_TABLEGEN, CLANG_TABLEGEN etc. I'm not sure if we should rename the project parameter there - I think it might work by passing LLVM_CG for that parameter for the new executable, making LLVM_CG_TABLEGEN.

For easier use, one can implicitly set LLVM_NATIVE_TOOL_DIR=<directory> these days, pointing at a directory containing all these *-tblgen binaries. But despite this, the individual setting variables kinda need to work too (and I'm afraid this current form, with clashing options, might cause trouble in build configs where that variable is used, e.g. when cross compiling LLVM).

[chapuni]

@mstorsjo How about it?

• llvm-minimal-tblgen -- Build only in the tree.
• llvm-tblgen includes codegen emitters. It may be exported. It may be used to check-llvm (my patches to test/TableGen would be unneeded)

[mstorsjo]

In D146352#4205131, @chapuni wrote:

@mstorsjo How about it?

• llvm-minimal-tblgen -- Build only in the tree.
• llvm-tblgen includes codegen emitters. It may be exported. It may be used to check-llvm (my patches to test/TableGen would be unneeded)

Hmm, unsure... It would hide the fact that there's two separate tools more, making it mostly a concern of the llvm build itself internally, but I wonder how much more complex it would make the cmake logic; it makes more reasoning about the tblgen executables less straightforward...

[chapuni]

• Adopt D144351. Changes to TableGen.cpp is not needed.

[chapuni]

• Use llvm-min-tblgen for llvm/include/llvm

[chapuni]

@mstorsjo I have introduced llvm-min-tblgen as the special tablegen for headers.
How about it? I think less intrusive.

[chapuni]

• Bazel

[chapuni]

I have confirmed this works fine for the simple bootstrap.
I expect this wouldn't prevent external llvm-tblgen.

[chapuni]

I knew this won't work with build_native_tool.
I supposed I could avoid building host's llvm-min-tblgen.

I will introduce like subproject in add_tablegen.

[chapuni]

• Revise

[chapuni]

• Restore LLVM_LINK_COMPONENTS

[chapuni]

• Use llvm-min-tblgen for SupportTests

[chapuni]

• bazel: s/LLVMTableGenGlobalISel/TableGenGlobalISel/

[chapuni]

• Rebase

[chapuni]

• Introduce D149072
• Use llvm-min-tblgen for SupportTests

[chapuni]

• Update comment line

[mstorsjo]

I think this looks quite neat overall, good stuff!

I measured the benefit from this patch in another build case; where I just want to build a small set of executables (for testing compiller-rt) in a new build tree; building tools like FileCheck is quite quick in general, but llvm-config has got surprisingly large numbers of dependencies. With this patch, the number of build steps to build llvm-config drops from 248 to 188, and the total cpu time for compiling it drops from ~11 minutes to ~5 minutes.

llvm/cmake/modules/TableGen.cmake

185 ↗

(On Diff #516432)

I guess these two lines could be consider a standalone NFC refactoring/cleanup on top of the current code as well?

[chapuni]

• Rebase
• Let llvm-tblgen depend on intrinsics_gen
• Cleanup llvm/modmap

[chapuni]

• [Bazel] Let llvm-tblgen depend on :intrinsic_enums_gen

[chapuni]

In D146352#4296422, @mstorsjo wrote:

I measured the benefit from this patch in another build case; where I just want to build a small set of executables (for testing compiller-rt) in a new build tree; building tools like FileCheck is quite quick in general, but llvm-config has got surprisingly large numbers of dependencies. With this patch, the number of build steps to build llvm-config drops from 248 to 188, and the total cpu time for compiling it drops from ~11 minutes to ~5 minutes.

I don't guess your background. Does it come from the bottleneck in the full version of llvm-tblgen?

llvm/cmake/modules/TableGen.cmake

185 ↗

(On Diff #516432)

It is leftover in my attempts.
Would it be better to rewind it? I prefer this.

[mstorsjo]

In D146352#4299284, @chapuni wrote:

In D146352#4296422, @mstorsjo wrote:

I measured the benefit from this patch in another build case; where I just want to build a small set of executables (for testing compiller-rt) in a new build tree; building tools like FileCheck is quite quick in general, but llvm-config has got surprisingly large numbers of dependencies. With this patch, the number of build steps to build llvm-config drops from 248 to 188, and the total cpu time for compiling it drops from ~11 minutes to ~5 minutes.

I don't guess your background. Does it come from the bottleneck in the full version of llvm-tblgen?

Yes; building llvm-config seems to require building some files that currently require the full llvm-tblgen, but after this patch can make do with llvm-min-tblgen.

llvm/cmake/modules/TableGen.cmake

185 ↗

(On Diff #516432)

I think the refactoring is good, but I think you could split it out from this patch and apply it directly (or send a separate patch which should be quick and easy to review+approve), and rebase this on top of it.

[chapuni]

• Restore ${project}-tablegen-host

[chapuni]

llvm/cmake/modules/TableGen.cmake

185 ↗

(On Diff #516432)

Okay, I've split it to D149343.

[chapuni]

• Add comment lines

[chapuni]

This is the last diff for the series of D148770.

@dblaikie Could you please take a look as a view of layering?

[dblaikie]

Don't know that I'm a great reviewer for this - I'm really bad at all the build file stuff (but thanks a bunch for having a go at updating the bazel build files - much appreciated). But, at a very rough glance it looks OK to me.

[mehdi_amini]

I just see this popping up in the recent hours:

[ 20%] Building RISCVTargetParserDef.inc...
llvm-min-tblgen: Unknown command line argument '-gen-riscv-target-def'.  Try: '../../../bin/llvm-min-tblgen --help'
llvm-min-tblgen: Did you mean '--help-list-hidden'?
make[3]: *** [include/llvm/TargetParser/CMakeFiles/RISCVTargetParserTableGen.dir/build.make:118: include/llvm/TargetParser/RISCVTargetParserDef.inc] Error 1
make[2]: *** [CMakeFiles/Makefile2:17904: include/llvm/TargetParser/CMakeFiles/RISCVTargetParserTableGen.dir/all] Error 2
make[2]: *** Waiting for unfinished jobs....
[ 20%] Linking CXX static library ../../../../../lib/libMLIRTblgenLib.a

Seems related?

[chapuni]

In D146352#4311572, @mehdi_amini wrote:

I just see this popping up in the recent hours:

It was an issue in Makefile generator. Resolved in rG73fbe9c9291a.
Sorry for inconvenience.

Besides, I see a few still failing builders, for example
https://lab.llvm.org/buildbot/#/builders/77/builds/26531

I will revert this later if I didn't find any solutions.

[chapuni]

I have fixed external LLVM_TABLEGEN in rG95d4506dda79 as a quick fix. I will rewrite it later.

llvm/lib/Target/CMakeLists.txt

 list(APPEND LLVM_COMMON_DEPENDS intrinsics_gen)
 
 list(APPEND LLVM_TABLEGEN_FLAGS -I ${LLVM_MAIN_SRC_DIR}/lib/Target)
 
+set(LLVM_TABLEGEN_EXE llvm-cg-tblgen)
+
 add_llvm_component_library(LLVMTarget
   Target.cpp
   TargetIntrinsicInfo.cpp
   TargetLoweringObjectFile.cpp
   TargetMachine.cpp
   TargetMachineC.cpp
 
   ADDITIONAL_HEADER_DIRS

llvm/test/CMakeLists.txt

set(LLVM_TEST_DEPENDS
           llvm-addr2line
           llvm-ar
           llvm-as
           llvm-bcanalyzer
           llvm-bitcode-strip
           llvm-c-test
           llvm-cat
           llvm-cfi-verify
+          llvm-cg-tblgen
           llvm-config
           llvm-cov
           llvm-cvtres
           llvm-cxxdump
           llvm-cxxfilt
           llvm-cxxmap
           llvm-debuginfo-analyzer
           llvm-debuginfod

llvm/test/TableGen/AliasAsmString.td

-// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {
   let InstructionSet = ArchInstrInfo;
 }

llvm/test/TableGen/AllowDuplicateRegisterNames.td

-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
 
 // Check that MatchRegisterName and MatchRegisterAltName are generated
 // correctly when multiple registers are defined with the same name and
 // AllowDuplicateRegisterNames is set.
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo;

llvm/test/TableGen/AsmPredicateCombining.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | \
 // RUN:     FileCheck --check-prefix=DISASS %s
-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | \
 // RUN:     FileCheck --check-prefix=MATCHER %s
-// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \
+// RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | \
 // RUN:     FileCheck --check-prefix=WRITER %s
 
 // Check that combining conditions in AssemblerPredicate generates the correct
 // output when using both the (all_of) AND operator, and the (any_of) OR
 // operator.
 
 include "llvm/Target/Target.td"
 

llvm/test/TableGen/AsmPredicateCombiningRISCV.td

-// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
+// RUN: %llvm-cg-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
 // RUN:     FileCheck --check-prefix=COMPRESS %s
 
 // Check that combining conditions in AssemblerPredicate generates the correct
 // output when using both the (all_of) AND operator, and the (any_of) OR
 // operator in the RISC-V specific instruction compressor.
 
 include "llvm/Target/Target.td"
 

llvm/test/TableGen/AsmPredicateCondsEmission.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 // Check that we don't generate invalid code of the form "( && Cond2)" when
 // emitting AssemblerPredicate conditions. In the example below, the invalid
 // code would be: "return ( && (Bits & arch::AssemblerCondition2));".
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }

llvm/test/TableGen/AsmVariant.td

-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
 
 // Check that specifying AsmVariant works correctly
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def FooAsmParserVariant : AsmParserVariant {

llvm/test/TableGen/AsmWriterPCRelOp.td

-// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {
   let InstructionSet = ArchInstrInfo;
 }

llvm/test/TableGen/BigEncoder.td

-// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
     let InstructionSet = archInstrInfo;
 }

llvm/test/TableGen/BitOffsetDecoder.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
     let InstructionSet = archInstrInfo;
 }

llvm/test/TableGen/CodeGenSchedule-duplicate-instrw.td

-// RUN: not llvm-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s
+// RUN: not %llvm-cg-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def FakeTarget : Target { }
 
 def FakeModel : SchedMachineModel { }
 
 def WriteA : SchedWrite;
 def WriteB : SchedWrite;
 
 let SchedModel = NoSchedModel in {
   def : InstRW<[WriteA], (instrs COPY)>;
 
   def : InstRW<[WriteB], (instrs COPY)>;
 // CHECK: [[@LINE-1]]:3: error: Overlapping InstRW definition for "COPY" also matches previous "(instrs COPY)".
 // CHECK-NEXT: def : InstRW<[WriteB], (instrs COPY)>;
 
 // CHECK: [[@LINE-6]]:3: note: Previous match was here.
 // CHECK-NEXT: def : InstRW<[WriteA], (instrs COPY)>;
 }
 No newline at end of file

llvm/test/TableGen/CompressWriteLatencyEntry.td

-// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
 
 // Make sure that ReadAdvance entries are correctly processed.
 // Not all ProcReadAdvance definitions implicitly inherit from SchedRead.
 // Some ProcReadAdvances are subclasses of ReadAdvance.
 
 include "llvm/Target/Target.td"
 
 def MyTarget : Target;

llvm/test/TableGen/ConcatenatedSubregs.td

-// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
 // Checks that tablegen correctly and completely infers subregister relations.
 include "llvm/Target/Target.td"
 
 class MyReg<string n, list<Register> subregs = []>
   : Register<n> {
   let Namespace = "Test";
   let SubRegs = subregs;
   let CoveredBySubRegs = 1;

llvm/test/TableGen/ConstraintChecking1.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Unrecognized constraint '$dest1 ~ $src2' in 'Foo'
 def Foo : TestInstructionWithConstraints<"$dest1 ~ $src2">;

llvm/test/TableGen/ConstraintChecking2.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for @earlyclobber constraint in 'Foo'
 def Foo : TestInstructionWithConstraints<"@earlyclobber ">;

llvm/test/TableGen/ConstraintChecking3.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // (This is illegal because the '=' has to be surrounded by whitespace)
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Illegal format for tied-to constraint in 'Foo'
 def Foo : TestInstructionWithConstraints<"$dest1=$dest2">;

llvm/test/TableGen/ConstraintChecking4.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Output operands '$dest1' and '$dest2' of 'Foo' cannot be tied!
 def Foo : TestInstructionWithConstraints<"$dest1 = $dest2">;

llvm/test/TableGen/ConstraintChecking5.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Input operands '$src1' and '$src2' of 'Foo' cannot be tied!
 def Foo : TestInstructionWithConstraints<"$src1 = $src2">;

llvm/test/TableGen/ConstraintChecking6.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$dest1' of 'Foo' cannot have multiple operands tied to it!
 def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest1 = $src2">;

llvm/test/TableGen/ConstraintChecking7.td

-// RUN: not llvm-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-asm-writer -I %p -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "ConstraintChecking.inc"
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: Operand '$src1' of 'Foo' cannot have multiple constraints!
 def Foo : TestInstructionWithConstraints<"$dest1 = $src1, $dest2 = $src1">;

llvm/test/TableGen/ContextlessPredicates.td

-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/context-optimized.cpp
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/context-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
 
 
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val),

llvm/test/TableGen/DAGDefaultOps.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s -o %t
 // RUN: FileCheck --check-prefix=ADD %s < %t
 // RUN: FileCheck --check-prefix=ADDINT %s < %t
 // RUN: FileCheck --check-prefix=SUB %s < %t
 // RUN: FileCheck --check-prefix=MULINT %s < %t
 
 include "llvm/Target/Target.td"
 
 def TestInstrInfo : InstrInfo;

llvm/test/TableGen/DefaultOpsGlobalISel.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 
 def SelectClamp  : ComplexPattern<untyped, 2, "SelectClamp">;
 def SelectOMod  : ComplexPattern<untyped, 2, "SelectOMod">;
 def SelectClampOMod  : ComplexPattern<untyped, 3, "SelectClampOMod">;

llvm/test/TableGen/DuplicateFieldValues.td

-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
 
 // CHECK: ABCForm_A
 // CHECK-NOT: ABCForm_A
 
 //
 // include Target.td for InstrMapping class and define minimally required objects
 //
 

llvm/test/TableGen/FastISelEmitter.td

-// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 //===- Define the necessary boilerplate for our test target. --------------===//
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
 

llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
     let InstructionSet = archInstrInfo;
 }

llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td

-// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {
   let InstructionSet = ArchInstrInfo;
 }

llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
 // RUN: FileCheck %s < %t
 
 include "llvm/Target/Target.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
 
 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }

llvm/test/TableGen/GICombinerEmitter/defs-invalid.td

-// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
+// RUN: not %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombiner %s 2>&1 | \
 // RUN:     FileCheck -implicit-check-not=error: %s
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }

llvm/test/TableGen/GICombinerEmitter/match-invalid.td

-// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
+// RUN: not %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombiner %s 2>&1 | \
 // RUN:     FileCheck -implicit-check-not=error: %s
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }

llvm/test/TableGen/GICombinerEmitter/match-tree.td

-// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
+// RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombinerHelper -gicombiner-stop-after-build %s \
 // RUN:     -o %t.inc | FileCheck %s
 //
-// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
+// RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombinerHelper %s | \
 // RUN: FileCheck --check-prefix=CODE %s
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }

llvm/test/TableGen/GICombinerEmitter/parse-match-pattern.td

-// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
+// RUN: %llvm-cg-tblgen -I %p/../../../include -gen-global-isel-combiner \
 // RUN:     -combiners=MyCombiner -gicombiner-stop-after-parse %s \
 // RUN:     -o /dev/null -debug 2>&1 | FileCheck %s
 // REQUIRES: asserts
 
 include "llvm/Target/Target.td"
 include "llvm/Target/GlobalISel/Combine.td"
 
 def MyTargetISA : InstrInfo;

llvm/test/TableGen/GlobalISelEmitter-PR39045.td

-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common  %s -o %t
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common  %s -o %t
 // RUN: FileCheck %s < %t
 
 // Both predicates should be tested
 // CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_b,
 // CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"

llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def shiftl_1 : SDNodeXForm<timm, [{
   return CurDAG->getTargetConstant(N->getZExtValue() << 1, SDLoc(N), MVT::i32);
 }]>;
 

llvm/test/TableGen/GlobalISelEmitter-atomic_store.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>;
 
 // Check that the pattern for atomic_store inverts the operands to
 // match the order of G_STORE.

llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // GISEL-OPT: GIM_SwitchOpcode
 // GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/
 // GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/
 // GISEL-OPT-NEXT: // Label

llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 
 def G_TGT_CAT : MyTargetGenericInstruction {
   let OutOperandList = (outs type0:$dst);

llvm/test/TableGen/GlobalISelEmitter-input-discard.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def int_tgt_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
 
 // Test that using srcvalue works for discarded pattern inputs.
 def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;

llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Verify that patterns will add temp registers if NumDstDef > NumSrcDef when NumSrcDef >= 1
 // and that these temp registers are marked as dead
 // Note: This is an extension of the test GlobalISelEmitter-output-discard.td
 

llvm/test/TableGen/GlobalISelEmitter-multiple-output.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Test the generation of patterns with multiple output operands and makes sure that
 // we are able to create a new instruction if necessary, or just simply change the
 // opcode if the input and output operands of the generic instruction are the same
 // as the target-specific instruction

llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 let Namespace = "MyTarget" in {
 
 def lo8  : SubRegIndex<8>;
 def hi8  : SubRegIndex<8, 8>;

llvm/test/TableGen/GlobalISelEmitter-output-discard.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Test that extra explicit results are treated as dead defs.
 def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
                (ins GPR32Op:$src0, GPR32Op:$src1), []>;
 

llvm/test/TableGen/GlobalISelEmitter-setcc.td

-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
 // RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // GISEL: GIM_Try
 // GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP,

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf
 def : Pat<(zext (i16 (trunc i32:$src))),
           (i32 $src)>;

llvm/test/TableGen/GlobalISelEmitter-zero-reg.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def P0 : Register<"p0"> { let Namespace = "MyTarget"; }
 def PR32 : RegisterClass<"MyTarget", [i32], 32, (add P0)>;
 def PR32Op : RegisterOperand<PR32>;
 

llvm/test/TableGen/GlobalISelEmitter.td

-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/optimized.cpp
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
 
 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
 
 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21N -input-file=%T/non-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21O -input-file=%T/optimized.cpp
 
 // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20N -input-file=%T/non-optimized.cpp

llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 // Verify that all MI predicates are enumerated.
 //
 // CHECK: // PatFrag predicates.
 // CHECK-NEXT: enum {
 // CHECK-NEXT:   GIPFP_MI_Predicate_and_or_pat = GIPFP_MI_Invalid + 1,
 // CHECK-NEXT:   GIPFP_MI_Predicate_or_oneuse,
 // CHECK-NEXT:   GIPFP_MI_Predicate_patfrags_test_pat,

llvm/test/TableGen/GlobalISelEmitterFlags.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
 
 class SrlPF<bit IC>: PatFrag<
   (ops node:$PATFRAG_Src0, node:$src1),

 // CHECK:   // (srl:{ *:[i32] } (shl:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0)
 // CHECK:   GIR_Done
 // CHECK: GIM_Try
 // CHECK:   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
 // CHECK:   GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL
 // CHECK:   GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1
 // CHECK:   // (sub:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)  =>  (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src1)
 // CHECK:   GIR_Done
 No newline at end of file

llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Two LOADs with same output size but different input size, hence their
 // GIM_CheckPointerToAny should *not* be merged
 def LOAD8 : I<(outs GPR8:$dst), (ins GPR8:$src), []>;
 def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>;

llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
 
 // CHECK:         GIM_Try, /*On fail goto*//*Label 0*/ 219,

llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
 
 // Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group

llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td

-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
 
 // Boilerplate code.
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 let TargetPrefix = "mytarget" in {
     def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
 }

llvm/test/TableGen/GlobalISelEmitterRegSequence.td

-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Boilerplate code for setting up some registers with subregs.
 class MyReg<string n, list<Register> subregs = []>
   : Register<n> {
   let SubRegs = subregs;

llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td

-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 //===- Boiler plate target code -===//
 
 def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
   let MIOperandInfo = (ops i32imm, i32imm);
 }

llvm/test/TableGen/GlobalISelEmitterSubreg.td

-// RUN: llvm-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
+// RUN: %llvm-cg-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
 // RUN: cat %t.skipped | FileCheck %s --check-prefix=SKIPPED
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Boilerplate code for setting up some registers with subregs.
 class MyReg<string n, list<Register> subregs = []>
   : Register<n> {

llvm/test/TableGen/GlobalISelEmitterVariadic.td

-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
 
 def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
 def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;

llvm/test/TableGen/HasNoUse.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Test the HasNoUse predicate
 
 def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
 

llvm/test/TableGen/HwModeEncodeDecode.td

-// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s --check-prefix=ENCODER
-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=DECODER
+// RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s --check-prefix=ENCODER
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=DECODER
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
     let InstructionSet = archInstrInfo;
 }

llvm/test/TableGen/HwModeSelect.td

-// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: not --crash %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
 
 // The HwModeSelect class is intended to serve as a base class for other
 // classes that are then used to select a value based on the HW mode.
 // It contains a list of HW modes, and a derived class should provide a
 // list of corresponding values.
 // These two lists must have the same size. Make sure that a violation of
 // this requirement is diagnosed.
 

llvm/test/TableGen/InvalidMCSchedClassDesc.td

-// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
 // Check if it is valid MCSchedClassDesc if didn't have the resources. 
 
 include "llvm/Target/Target.td"
 
 def MyTarget : Target;
 
 let OutOperandList = (outs), InOperandList = (ins) in {
   def Inst_A : Instruction; 

llvm/test/TableGen/MissingOperandField.td

-// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not %llvm-cg-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
 
 // Check that we emit reasonable diagnostics when fields do not have
 // corresponding operands.
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 

llvm/test/TableGen/MixedCasedMnemonic.td

-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=MATCHER
-// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s --check-prefix=WRITER
-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=ALIAS
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=MATCHER
+// RUN: %llvm-cg-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s --check-prefix=WRITER
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s --check-prefix=ALIAS
 
 // Check that an instruction that uses mixed upper/lower case in its mnemonic
 // is printed as-is, and is parsed in its "canonicalized" lowercase form.
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 

llvm/test/TableGen/MnemonicAlias.td

-// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {
   let InstructionSet = ArchInstrInfo;
 }

llvm/test/TableGen/RegisterBankEmitter.td

-// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def MyTarget : Target;
 def R0 : Register<"r0">;
 let Size = 32 in {
   def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
   def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
 }
 
 // CHECK: GPRRegBankCoverageData
 // CHECK: MyTarget::ClassARegClassID
 // CHECK: MyTarget::ClassBRegClassID
 def GPRRegBank : RegisterBank<"GPR", [ClassA]>;

llvm/test/TableGen/RegisterClass.td

-// RUN: not llvm-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: not %llvm-cg-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def MyTarget : Target;
 def R0 : Register<"r0">;
 def ClassA : RegisterClass<"MyTarget", [], 32, (add R0)>; // CHECK: [[@LINE]]:5: error: RegTypes list must not be empty!

llvm/test/TableGen/RegisterEncoder.td

-// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
 
 // Check that EncoderMethod for RegisterOperand is working correctly
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {

llvm/test/TableGen/RegisterInfoEmitter-BaseClassOrder.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 let Namespace = "MyTarget" in {
   def R0 : Register<"r0">; // base class BaseA
   def R1 : Register<"r1">; // base class BaseA
   def R2 : Register<"r2">; // base class BaseC
   def R3 : Register<"r3">; // base class BaseC

llvm/test/TableGen/RegisterInfoEmitter-regcost-list.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 // Checks two CostPerUse values for the registers.
 include "llvm/Target/Target.td"
 
 let Namespace = "MyTarget" in {
   foreach Index = 0-3 in {
     // Adding two cost values per register.
     let CostPerUse = [1, Index] in {

llvm/test/TableGen/RegisterInfoEmitter-regcost-tuple.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 // Checks the cost values for the register tuple.
 include "llvm/Target/Target.td"
 
 class MyClass<int size, list<ValueType> types, dag registers>
   : RegisterClass<"MyTarget", types, size, registers> {
   let Size = size;
 }

llvm/test/TableGen/RegisterInfoEmitter-regcost.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 // Checks the CostPerUse value for the registers.
 include "llvm/Target/Target.td"
 
 let Namespace = "MyTarget" in {
 
   foreach Index = 0-3 in {
     // Adds register cost value 1.

llvm/test/TableGen/RegisterInfoEmitter-tsflags.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 // Configure and test TSFlags for a target.
 include "llvm/Target/Target.td"
 
 let Namespace = "MyTarget" in {
   def R : Register<"r">;
   def D : Register<"d">;
   def S : Register<"s">;

llvm/test/TableGen/RelTest.td

-// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: not %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
 
 // This test verifies that TableGen is displaying an error when mapped instruction
 // does not contain a field listed under RowFields.
 
 include "llvm/Target/Target.td"
 
 class SimpleReg<string n> : Register<n> {
   let Namespace = "Simple";

llvm/test/TableGen/SchedModelError.td

-// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not %llvm-cg-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
 
 include "llvm/Target/Target.td"
 
 def TestTarget : Target;
 
 // CHECK: [[FILE]]:[[@LINE+1]]:5: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
 def TestInst : Instruction {
   let OutOperandList = (outs);

llvm/test/TableGen/VarLenDecoder.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {
   let InstructionSet = ArchInstrInfo;
 }

llvm/test/TableGen/VarLenEncoder.td

-// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
 
 // Check if VarLenCodeEmitterGen works correctly.
 
 include "llvm/Target/Target.td"
 
 def ArchInstrInfo : InstrInfo { }
 
 def Arch : Target {

llvm/test/TableGen/address-space-patfrags.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;

llvm/test/TableGen/ambiguous-composition.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s
 //
 // CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Test::subreg_hh32 or Test::subreg_h32
 // CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::subreg_ll32 or Test::subreg_l32
 
 include "llvm/Target/Target.td"
 
 def TestInstrInfo : InstrInfo {
 }

llvm/test/TableGen/bare-minimum-psets.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 // Test to check the bare minimum pressure sets.
 // At least one register pressure set is required for the target.
 // Allowed the pset only for D_32 regclass and ignored it for all
 // other classes including the tuples.
 include "llvm/Target/Target.td"
 
 class MyClass<int size, list<ValueType> types, dag registers>

llvm/test/TableGen/dag-isel-complexpattern.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;
 }

llvm/test/TableGen/dag-isel-regclass-emit-enum.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;
 }

llvm/test/TableGen/dag-isel-res-order.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;
 }

llvm/test/TableGen/dag-isel-subregs.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
 
 include "reg-with-subregs-common.td"
 
 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
 // CHECK: OPC_CheckChild1Integer, 0,
 // CHECK: OPC_EmitStringInteger, MVT::i32, sub0_sub1,
 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
           (EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
 
 // CHECK: OPC_CheckChild1Integer, 30,
 // CHECK: OPC_EmitInteger, MVT::i32, 10|128,2/*266*/,
 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
           (EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;

llvm/test/TableGen/empty-psets.td

-// RUN: not llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s 2>&1 | FileCheck %s
+// RUN: not %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s 2>&1 | FileCheck %s
 
 // Negative test to check empty Psets for a target.
 
 include "llvm/Target/Target.td"
 
 def R : Register<"r">;
 
 def R_32 : RegisterClass<"MyTarget", [i32], 32, (add R)> {
   let GeneratePressureSet = 0;
 }
 
 def MyTarget : Target;
 
 // CHECK: error: RegUnitSets cannot be empty!

llvm/test/TableGen/generic-tables-instruction.td

-// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
 // XFAIL: vg_leak
 
 include "llvm/TableGen/SearchableTable.td"
 
 // CHECK-LABEL: GET_InstrTable_IMPL
 // CHECK: constexpr MyInstr InstrTable[] = {
 // CHECK:   { B, 0xA },
 // CHECK:   { C, 0x0 },

llvm/test/TableGen/generic-tables.td

-// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
-// RUN: not llvm-tblgen -gen-searchable-tables -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
+// RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
+// RUN: not %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
 // XFAIL: vg_leak
 
 include "llvm/TableGen/SearchableTable.td"
 
 // CHECK-LABEL: GET_BValues_DECL
 // CHECK: enum BValues {
 // CHECK:   BAlice = 172,
 // CHECK:   BBob = 20,

llvm/test/TableGen/get-operand-type-no-expand.td

def InstA : Instruction {
   let Size = 1;
   let OutOperandList = (outs i512complex:$a);
   let InOperandList = (ins i8complex:$b, i32imm:$c);
   field bits<8> Inst;
   field bits<8> SoftFail = 0;
   let Namespace = "MyNamespace";
 }
 
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
+// RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s \
 // RUN:   -instr-info-expand-mi-operand-info=1 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-EXPAND
 // CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK-EXPAND: OpcodeOperandTypes[] = {
 // CHECK-EXPAND:        /* InstA */
 // CHECK-EXPAND-NEXT:   i8imm, i32imm, i8imm, i32imm, i32imm,
 // CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
 
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
+// RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s \
 // RUN:   -instr-info-expand-mi-operand-info=0 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-NOEXPAND
 // CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK-NOEXPAND: OpcodeOperandTypes[] = {
 // CHECK-NOEXPAND:        /* InstA */
 // CHECK-NOEXPAND-NEXT:   i512complex, i8complex, i32imm,
 // CHECK-NOEXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE

llvm/test/TableGen/get-operand-type.td

-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
 
 // Check that getOperandType has the expected info in it
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {

llvm/test/TableGen/gisel-physreg-input.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;
 }

llvm/test/TableGen/immarg-predicated.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 let TargetPrefix = "mytarget" in {
 def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 }
 

llvm/test/TableGen/immarg.td

-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 let TargetPrefix = "mytarget" in {
 def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 }

llvm/test/TableGen/inhibit-pset.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 include "reg-with-subregs-common.td"
 
 // CHECK-DAG: GPR32_AND_XR32RegClassID =
 // CHECK-DAG: XR32RegClassID =
 
 def X0 : Register <"x0">;
 

llvm/test/TableGen/predicate-patfags.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=GISEL %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=SDAG %s
+// RUN: %llvm-cg-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Test that a predicate works when there are multiple pattern trees
 // in a PatFrags.
 
 def int_tgt_mul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty]>;

llvm/test/TableGen/pset-enum.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s
 
 include "reg-with-subregs-common.td"
 
 // CHECK-LABEL:    // Register pressure sets enum.
 // NAMESPACE-NEXT: namespace TestNamespace {
 // CHECK-NEXT:     enum RegisterPressureSets {
 // CHECK-NEXT:       GPR32 = 0,
 // CHECK-NEXT:     };
 // NAMESPACE-NEXT: } // end namespace TestNamespace

llvm/test/TableGen/pseudo-inst-expansion.td

-// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def TestTargetInstrInfo : InstrInfo;
 
 def TestTarget : Target {
   let InstructionSet = TestTargetInstrInfo;
 }

llvm/test/TableGen/rc-weight-override.td

-// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
 
 include "reg-with-subregs-common.td"
 
 // CHECK-LABEL: static const RegClassWeight RCWeightTable[] = {
 // CHECK: {1, 256}, // GPR32
 // CHECK: {2, 256}, // GPR_64
 
 // CHECK: {0, 256}, // GPR_64_W0

llvm/test/TableGen/searchabletables-intrinsic.td

-// RUN: llvm-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-searchable-tables -I %p/../../include %s | FileCheck %s
 // XFAIL: vg_leak
 
 include "llvm/TableGen/SearchableTable.td"
 
 class IntrinsicProperty<bit is_default = 0> {
   bit IsDefault = is_default;
 }
 

llvm/test/TableGen/simplify-patfrag.td

-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 // Minimal Target definition
 def DemoInstrInfo : InstrInfo;
 def Demo : Target {
   let InstructionSet = DemoInstrInfo;
 }

llvm/test/TableGen/trydecode-emission.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 // Check that if decoding of an instruction fails and the instruction does not
 // have a complete decoder method that can determine if the bitpattern is valid
 // or not then the decoder tries to find a more general instruction that
 // matches the bitpattern too.
 
 include "llvm/Target/Target.td"
 

llvm/test/TableGen/trydecode-emission2.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
   let InstructionSet = archInstrInfo;
 }

llvm/test/TableGen/trydecode-emission3.td

-// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+// RUN: %llvm-cg-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
 
 include "llvm/Target/Target.td"
 
 def archInstrInfo : InstrInfo { }
 
 def arch : Target {
   let InstructionSet = archInstrInfo;
 }

llvm/test/lit.cfg.py

tools = [
     ToolSubst('%llvm', FindTool('llvm'), unresolved='ignore'),
     ToolSubst('%lli', FindTool('lli'), post='.', extra_args=lli_args),
     ToolSubst('%llc_dwarf', FindTool('llc'), extra_args=llc_args),
     ToolSubst('%gold', config.gold_executable, unresolved='ignore'),
     ToolSubst('%ld64', ld64_cmd, unresolved='ignore'),
     ToolSubst('%ocamlc', ocamlc_command, unresolved='ignore'),
     ToolSubst('%ocamlopt', ocamlopt_command, unresolved='ignore'),
     ToolSubst('%opt-viewer', opt_viewer_cmd),
+    ToolSubst('%llvm-cg-tblgen', FindTool('llvm-cg-tblgen')),
     ToolSubst('%llvm-objcopy', FindTool('llvm-objcopy')),
     ToolSubst('%llvm-strip', FindTool('llvm-strip')),
     ToolSubst('%llvm-install-name-tool', FindTool('llvm-install-name-tool')),
     ToolSubst('%llvm-bitcode-strip', FindTool('llvm-bitcode-strip')),
     ToolSubst('%split-file', FindTool('split-file')),
 ]
 
 # FIXME: Why do we have both `lli` and `%lli` that do slightly different things?

llvm/unittests/TableGen/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   TableGen
   Support
   )
 
 set(LLVM_TARGET_DEFINITIONS Automata.td)
 
+set(LLVM_TABLEGEN_EXE llvm-cg-tblgen)
+
 tablegen(LLVM AutomataTables.inc -gen-searchable-tables)
 tablegen(LLVM AutomataAutomata.inc -gen-automata)
 add_public_tablegen_target(AutomataTestTableGen)
 
 add_llvm_unittest(TableGenTests DISABLE_LLVM_LINK_LLVM_DYLIB
   AutomataTest.cpp
   CodeExpanderTest.cpp
   ParserEntryPointTest.cpp
   )
 
 target_link_libraries(TableGenTests PRIVATE LLVMTableGenGlobalISel LLVMTableGen)

llvm/utils/TableGen/CGTableGen.cpp

-//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
+//===- CGTableGen.cpp - Top-Level TableGen implementation for LLVM --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the main function for LLVM's TableGen.
enum ActionType {
   GenDisassembler,
   GenPseudoLowering,
   GenCompressInst,
   GenCallingConv,
   GenDAGISel,
   GenDFAPacketizer,
   GenFastISel,
   GenSubtarget,
-  GenIntrinsicEnums,
-  GenIntrinsicImpl,
   PrintEnums,
   PrintSets,
-  GenOptParserDefs,
-  GenOptRST,
-  GenCTags,
-  GenAttributes,
   GenSearchableTables,
   GenGlobalISel,
   GenGICombiner,
   GenX86EVEX2VEXTables,
   GenX86FoldTables,
   GenX86MnemonicTables,
   GenRegisterBank,
   GenExegesis,
   GenAutomata,
-  GenDirectivesEnumDecl,
-  GenDirectivesEnumImpl,
   GenDXILOperation,
-  GenRISCVTargetDef,
 };
 
 namespace llvm {
 cl::opt<bool> EmitLongStrLiterals(
     "long-string-literals",
     cl::desc("when emitting large string tables, prefer string literals over "
              "comma-separated char literals. This can be a readability and "
              "compile-time performance win, but upsets some compilers"),
cl::values(
         clEnumValN(GenDAGISel, "gen-dag-isel",
                    "Generate a DAG instruction selector"),
         clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
                    "Generate DFA Packetizer for VLIW targets"),
         clEnumValN(GenFastISel, "gen-fast-isel",
                    "Generate a \"fast\" instruction selector"),
         clEnumValN(GenSubtarget, "gen-subtarget",
                    "Generate subtarget enumerations"),
-        clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
-                   "Generate intrinsic enums"),
-        clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
-                   "Generate intrinsic information"),
-        clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"),
-        clEnumValN(PrintSets, "print-sets",
-                   "Print expanded sets for testing DAG exprs"),
-        clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
-                   "Generate option definitions"),
-        clEnumValN(GenOptRST, "gen-opt-rst", "Generate option RST"),
-        clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"),
-        clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"),
         clEnumValN(GenSearchableTables, "gen-searchable-tables",
                    "Generate generic binary-searchable table"),
         clEnumValN(GenGlobalISel, "gen-global-isel",
                    "Generate GlobalISel selector"),
         clEnumValN(GenGICombiner, "gen-global-isel-combiner",
                    "Generate GlobalISel combiner"),
         clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
                    "Generate X86 EVEX to VEX compress tables"),
         clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
                    "Generate X86 fold tables"),
         clEnumValN(GenX86MnemonicTables, "gen-x86-mnemonic-tables",
                    "Generate X86 mnemonic tables"),
         clEnumValN(GenRegisterBank, "gen-register-bank",
                    "Generate registers bank descriptions"),
         clEnumValN(GenExegesis, "gen-exegesis",
                    "Generate llvm-exegesis tables"),
         clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
-        clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
-                   "Generate directive related declaration code (header file)"),
-        clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
-                   "Generate directive related implementation code"),
+
+
+
         clEnumValN(GenDXILOperation, "gen-dxil-operation",
-                   "Generate DXIL operation information"),
-        clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
-                   "Generate the list of CPU for RISCV")));
+                   "Generate DXIL operation information")));
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
case GenDFAPacketizer:
     EmitDFAPacketizer(Records, OS);
     break;
   case GenFastISel:
     EmitFastISel(Records, OS);
     break;
   case GenSubtarget:
     EmitSubtarget(Records, OS);
     break;
-  case GenIntrinsicEnums:
-    EmitIntrinsicEnums(Records, OS);
-    break;
-  case GenIntrinsicImpl:
-    EmitIntrinsicImpl(Records, OS);
-    break;
-  case GenOptParserDefs:
-    EmitOptParser(Records, OS);
-    break;
-  case GenOptRST:
-    EmitOptRST(Records, OS);
-    break;
   case PrintEnums: {
     for (Record *Rec : Records.getAllDerivedDefinitions(Class))
       OS << Rec->getName() << ", ";
     OS << "\n";
     break;
   }
   case PrintSets:
   {
     SetTheory Sets;
     Sets.addFieldExpander("Set", "Elements");
     for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
       OS << Rec->getName() << " = [";
       const std::vector<Record*> *Elts = Sets.expand(Rec);
       assert(Elts && "Couldn't expand Set instance");
       for (Record *Elt : *Elts)
         OS << ' ' << Elt->getName();
       OS << " ]\n";
     }
     break;
   }
-  case GenCTags:
-    EmitCTags(Records, OS);
-    break;
-  case GenAttributes:
-    EmitAttributes(Records, OS);
-    break;
   case GenSearchableTables:
     EmitSearchableTables(Records, OS);
     break;
   case GenGlobalISel:
     EmitGlobalISel(Records, OS);
     break;
   case GenGICombiner:
     EmitGICombiner(Records, OS);
case GenX86FoldTables:
     EmitX86FoldTables(Records, OS);
     break;
   case GenExegesis:
     EmitExegesis(Records, OS);
     break;
   case GenAutomata:
     EmitAutomata(Records, OS);
     break;
-  case GenDirectivesEnumDecl:
-    EmitDirectivesDecl(Records, OS);
-    break;
-  case GenDirectivesEnumImpl:
-    EmitDirectivesImpl(Records, OS);
-    break;
   case GenDXILOperation:
     EmitDXILOperation(Records, OS);
     break;
-  case GenRISCVTargetDef:
-    EmitRISCVTargetDef(Records, OS);
-    break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {
   InitLLVM X(argc, argv);

llvm/utils/TableGen/CMakeLists.txt

 add_subdirectory(GlobalISel)
 
 set(LLVM_LINK_COMPONENTS Support)
 
-add_tablegen(llvm-tblgen LLVM
+add_llvm_library(TableGenCommon EXCLUDE_FROM_ALL
+  CodeGenIntrinsics.cpp
+  SDNodeProperties.cpp
+  PARTIAL_SOURCES_INTENDED
+  )
+
+add_tablegen(llvm-cg-tblgen LLVM
   DESTINATION "${LLVM_TOOLS_INSTALL_DIR}"
   EXPORT LLVM
   AsmMatcherEmitter.cpp
   AsmWriterEmitter.cpp
   AsmWriterInst.cpp
-  Attributes.cpp
   CallingConvEmitter.cpp
   CodeEmitterGen.cpp
   CodeGenDAGPatterns.cpp
   CodeGenHwModes.cpp
   CodeGenInstAlias.cpp
   CodeGenInstruction.cpp
-  CodeGenIntrinsics.cpp
   CodeGenMapTable.cpp
   CodeGenRegisters.cpp
   CodeGenSchedule.cpp
   CodeGenTarget.cpp
   DAGISelEmitter.cpp
   DAGISelMatcherEmitter.cpp
   DAGISelMatcherGen.cpp
   DAGISelMatcherOpt.cpp
   DAGISelMatcher.cpp
   DecoderEmitter.cpp
   DFAEmitter.cpp
   DFAPacketizerEmitter.cpp
-  DirectiveEmitter.cpp
   DisassemblerEmitter.cpp
   DXILEmitter.cpp
   ExegesisEmitter.cpp
   FastISelEmitter.cpp
   GICombinerEmitter.cpp
   GlobalISelEmitter.cpp
   InfoByHwMode.cpp
   InstrInfoEmitter.cpp
   InstrDocsEmitter.cpp
-  IntrinsicEmitter.cpp
-  OptEmitter.cpp
-  OptParserEmitter.cpp
-  OptRSTEmitter.cpp
   PredicateExpander.cpp
   PseudoLoweringEmitter.cpp
   CompressInstEmitter.cpp
   RegisterBankEmitter.cpp
   RegisterInfoEmitter.cpp
-  RISCVTargetDefEmitter.cpp
-  SDNodeProperties.cpp
   SearchableTableEmitter.cpp
   SubtargetEmitter.cpp
   SubtargetFeatureInfo.cpp
-  TableGen.cpp
   Types.cpp
   VarLenCodeEmitterGen.cpp
   X86DisassemblerTables.cpp
   X86EVEX2VEXTablesEmitter.cpp
   X86FoldTablesEmitter.cpp
   X86MnemonicTables.cpp
   X86ModRMFilters.cpp
   X86RecognizableInstr.cpp
   WebAssemblyDisassemblerEmitter.cpp
+  CGTableGen.cpp
+  PARTIAL_SOURCES_INTENDED
+  $<TARGET_OBJECTS:TableGenCommon>
+  )
+target_link_libraries(llvm-cg-tblgen PRIVATE LLVMTableGenGlobalISel)
+set_target_properties(llvm-cg-tblgen PROPERTIES FOLDER "Tablegenning")
+
+add_tablegen(llvm-tblgen LLVM
+  DESTINATION "${LLVM_TOOLS_INSTALL_DIR}"
+  EXPORT LLVM
+  Attributes.cpp
   CTagsEmitter.cpp
+  DirectiveEmitter.cpp
+  IntrinsicEmitter.cpp
+  OptEmitter.cpp
+  OptParserEmitter.cpp
+  OptRSTEmitter.cpp
+  RISCVTargetDefEmitter.cpp
+  TableGen.cpp
+  $<TARGET_OBJECTS:TableGenCommon>
   )
-target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
 set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")

llvm/utils/TableGen/TableGen.cpp

 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 using namespace llvm;
 
 enum ActionType {
   PrintRecords,
   PrintDetailedRecords,
   NullBackend,
   DumpJSON,
-  GenEmitter,
-  GenRegisterInfo,
-  GenInstrInfo,
-  GenInstrDocs,
-  GenAsmWriter,
-  GenAsmMatcher,
-  GenDisassembler,
-  GenPseudoLowering,
-  GenCompressInst,
-  GenCallingConv,
-  GenDAGISel,
-  GenDFAPacketizer,
-  GenFastISel,
-  GenSubtarget,
   GenIntrinsicEnums,
   GenIntrinsicImpl,
   PrintEnums,
   PrintSets,
   GenOptParserDefs,
   GenOptRST,
   GenCTags,
   GenAttributes,
-  GenSearchableTables,
-  GenGlobalISel,
-  GenGICombiner,
-  GenX86EVEX2VEXTables,
-  GenX86FoldTables,
-  GenX86MnemonicTables,
-  GenRegisterBank,
-  GenExegesis,
-  GenAutomata,
   GenDirectivesEnumDecl,
   GenDirectivesEnumImpl,
-  GenDXILOperation,
   GenRISCVTargetDef,
 };
 
-namespace llvm {
-cl::opt<bool> EmitLongStrLiterals(
-    "long-string-literals",
-    cl::desc("when emitting large string tables, prefer string literals over "
-             "comma-separated char literals. This can be a readability and "
-             "compile-time performance win, but upsets some compilers"),
-    cl::Hidden, cl::init(true));
-} // end namespace llvm
-
 namespace {
 cl::opt<ActionType> Action(
     cl::desc("Action to perform:"),
     cl::values(
         clEnumValN(PrintRecords, "print-records",
                    "Print all records to stdout (default)"),
         clEnumValN(PrintDetailedRecords, "print-detailed-records",
                    "Print full details of all records to stdout"),
         clEnumValN(NullBackend, "null-backend",
                    "Do nothing after parsing (useful for timing)"),
         clEnumValN(DumpJSON, "dump-json",
                    "Dump all records as machine-readable JSON"),
-        clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
-        clEnumValN(GenRegisterInfo, "gen-register-info",
-                   "Generate registers and register classes info"),
-        clEnumValN(GenInstrInfo, "gen-instr-info",
-                   "Generate instruction descriptions"),
-        clEnumValN(GenInstrDocs, "gen-instr-docs",
-                   "Generate instruction documentation"),
-        clEnumValN(GenCallingConv, "gen-callingconv",
-                   "Generate calling convention descriptions"),
-        clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"),
-        clEnumValN(GenDisassembler, "gen-disassembler",
-                   "Generate disassembler"),
-        clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
-                   "Generate pseudo instruction lowering"),
-        clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
-                   "Generate RISCV compressed instructions."),
-        clEnumValN(GenAsmMatcher, "gen-asm-matcher",
-                   "Generate assembly instruction matcher"),
-        clEnumValN(GenDAGISel, "gen-dag-isel",
-                   "Generate a DAG instruction selector"),
-        clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
-                   "Generate DFA Packetizer for VLIW targets"),
-        clEnumValN(GenFastISel, "gen-fast-isel",
-                   "Generate a \"fast\" instruction selector"),
-        clEnumValN(GenSubtarget, "gen-subtarget",
-                   "Generate subtarget enumerations"),
         clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
                    "Generate intrinsic enums"),
         clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
                    "Generate intrinsic information"),
         clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"),
         clEnumValN(PrintSets, "print-sets",
                    "Print expanded sets for testing DAG exprs"),
         clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
                    "Generate option definitions"),
         clEnumValN(GenOptRST, "gen-opt-rst", "Generate option RST"),
         clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"),
         clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"),
-        clEnumValN(GenSearchableTables, "gen-searchable-tables",
-                   "Generate generic binary-searchable table"),
-        clEnumValN(GenGlobalISel, "gen-global-isel",
-                   "Generate GlobalISel selector"),
-        clEnumValN(GenGICombiner, "gen-global-isel-combiner",
-                   "Generate GlobalISel combiner"),
-        clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
-                   "Generate X86 EVEX to VEX compress tables"),
-        clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
-                   "Generate X86 fold tables"),
-        clEnumValN(GenX86MnemonicTables, "gen-x86-mnemonic-tables",
-                   "Generate X86 mnemonic tables"),
-        clEnumValN(GenRegisterBank, "gen-register-bank",
-                   "Generate registers bank descriptions"),
-        clEnumValN(GenExegesis, "gen-exegesis",
-                   "Generate llvm-exegesis tables"),
-        clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
         clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
                    "Generate directive related declaration code (header file)"),
         clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
                    "Generate directive related implementation code"),
-        clEnumValN(GenDXILOperation, "gen-dxil-operation",
-                   "Generate DXIL operation information"),
         clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
                    "Generate the list of CPU for RISCV")));
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
     OS << Records;              // No argument, dump all contents
     break;
   case PrintDetailedRecords:
     EmitDetailedRecords(Records, OS);
     break;
   case NullBackend:             // No backend at all.
     break;
   case DumpJSON:
     EmitJSON(Records, OS);
     break;
-  case GenEmitter:
-    EmitCodeEmitter(Records, OS);
-    break;
-  case GenRegisterInfo:
-    EmitRegisterInfo(Records, OS);
-    break;
-  case GenInstrInfo:
-    EmitInstrInfo(Records, OS);
-    break;
-  case GenInstrDocs:
-    EmitInstrDocs(Records, OS);
-    break;
-  case GenCallingConv:
-    EmitCallingConv(Records, OS);
-    break;
-  case GenAsmWriter:
-    EmitAsmWriter(Records, OS);
-    break;
-  case GenAsmMatcher:
-    EmitAsmMatcher(Records, OS);
-    break;
-  case GenDisassembler:
-    EmitDisassembler(Records, OS);
-    break;
-  case GenPseudoLowering:
-    EmitPseudoLowering(Records, OS);
-    break;
-  case GenCompressInst:
-    EmitCompressInst(Records, OS);
-    break;
-  case GenDAGISel:
-    EmitDAGISel(Records, OS);
-    break;
-  case GenDFAPacketizer:
-    EmitDFAPacketizer(Records, OS);
-    break;
-  case GenFastISel:
-    EmitFastISel(Records, OS);
-    break;
-  case GenSubtarget:
-    EmitSubtarget(Records, OS);
-    break;
   case GenIntrinsicEnums:
     EmitIntrinsicEnums(Records, OS);
     break;
   case GenIntrinsicImpl:
     EmitIntrinsicImpl(Records, OS);
     break;
   case GenOptParserDefs:
     EmitOptParser(Records, OS);
case PrintSets:
     break;
   }
   case GenCTags:
     EmitCTags(Records, OS);
     break;
   case GenAttributes:
     EmitAttributes(Records, OS);
     break;
-  case GenSearchableTables:
-    EmitSearchableTables(Records, OS);
-    break;
-  case GenGlobalISel:
-    EmitGlobalISel(Records, OS);
-    break;
-  case GenGICombiner:
-    EmitGICombiner(Records, OS);
-    break;
-  case GenRegisterBank:
-    EmitRegisterBank(Records, OS);
-    break;
-  case GenX86EVEX2VEXTables:
-    EmitX86EVEX2VEXTables(Records, OS);
-    break;
-  case GenX86MnemonicTables:
-    EmitX86MnemonicTables(Records, OS);
-    break;
-  case GenX86FoldTables:
-    EmitX86FoldTables(Records, OS);
-    break;
-  case GenExegesis:
-    EmitExegesis(Records, OS);
-    break;
-  case GenAutomata:
-    EmitAutomata(Records, OS);
-    break;
   case GenDirectivesEnumDecl:
     EmitDirectivesDecl(Records, OS);
     break;
   case GenDirectivesEnumImpl:
     EmitDirectivesImpl(Records, OS);
     break;
-  case GenDXILOperation:
-    EmitDXILOperation(Records, OS);
-    break;
   case GenRISCVTargetDef:
     EmitRISCVTargetDef(Records, OS);
     break;
   }
 
   return false;
 }
 }