[RISCV] Add an empty block after outlined MBB

[• pcwang-thead]

Summary

So that MCP won't delete any copy instructions where a register is
set that is intended to be live-out, since MCP assumes that all the
defs are live-out conservatively.

This is a fix for D146037.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

RISCVInstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI,
 
   return outliner::InstrType::Legal;
 }
 
 void RISCVInstrInfo::buildOutlinedFrame(
     MachineBasicBlock &MBB, MachineFunction &MF,
     const outliner::OutlinedFunction &OF) const {
 
+  // FIXME: Add an empty successor so that MCP won't delete any copy
+  // instructions where a register is set that is intended to be live-out, since
+  // MCP assumes that all the defs are live-out conservatively.
+  MachineBasicBlock &EmptyMBB = *MF.CreateMachineBasicBlock();
+  MF.insert(MF.end(), &EmptyMBB);
+  MBB.addSuccessorWithoutProb(&EmptyMBB);
+
   // Strip out any CFI instructions
   bool Changed = true;
   while (Changed) {
     Changed = false;
     auto I = MBB.begin();
     auto E = MBB.end();
     for (; I != E; ++I) {
       if (I->isCFIInstruction()) {

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

bool RISCVPassConfig::addGlobalInstructionSelect() {
   return false;
 }
 
 void RISCVPassConfig::addPreSched2() {}
 
 void RISCVPassConfig::addPreEmitPass() {
   addPass(&BranchRelaxationPassID);
   addPass(createRISCVMakeCompressibleOptPass());
-
-  // TODO: It would potentially be better to schedule copy propagation after
-  // expanding pseudos (in addPreEmitPass2). However, performing copy
-  // propagation after the machine outliner (which runs after addPreEmitPass)
-  // currently leads to incorrect code-gen, where copies to registers within
-  // outlined functions are removed erroneously.
-  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
-    addPass(createMachineCopyPropagationPass(true));
 }
 
 void RISCVPassConfig::addPreEmitPass2() {
   addPass(createRISCVExpandPseudoPass());
 
+  // Do the copy propagation after expanding pseudos because we may produce some
+  // MVs when expanding.
+  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
+    addPass(createMachineCopyPropagationPass(true));
+
   // Schedule the expansion of AMOs at the last possible moment, avoiding the
   // possibility for other passes to break the requirements for forward
   // progress in the LR/SC block.
   addPass(createRISCVExpandAtomicPseudoPass());
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();

llvm/test/CodeGen/RISCV/O3-pipeline.ll

 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement
 ; CHECK-NEXT:       Insert fentry calls
 ; CHECK-NEXT:       Insert XRay ops
 ; CHECK-NEXT:       Implement the 'patchable-function' attribute
 ; CHECK-NEXT:       Branch relaxation pass
 ; CHECK-NEXT:       RISCV Make Compressible
-; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       Contiguously Lay Out Funclets
 ; CHECK-NEXT:       StackMap Liveness Analysis
 ; CHECK-NEXT:       Live DEBUG_VALUE analysis
 ; CHECK-NEXT:       Machine Sanitizer Binary Metadata
 ; CHECK-NEXT:     Machine Outliner
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       Stack Frame Layout Analysis
 ; CHECK-NEXT:       RISCV pseudo instruction expansion pass
+; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       RISCV atomic pseudo instruction expansion pass
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       RISCV Assembly Printer
 ; CHECK-NEXT:       Free MachineFunction

llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll

 ;
 ; RV64I-LABEL: OUTLINED_FUNCTION_0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui s0, 524288
 ; RV64I-NEXT:    addiw s0, s0, -1
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    jr t0
+; RV64I-NEXT:  # %bb.1: