[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).

[fpetrogalli]

Summary

This is done for consistency with other Predicate/SubtargetFeature pairs, where the second parameter of the SubtargetFeature correspond to the NAME of the def of the Predicate associated to the SubtargetFeature.

[asb]

Thanks for making this suggestion.

The suggested renaming would be consistent with those other predicates, but RV{32,64}{I,E} are different base ISAs while the other predicates refer to instruction set extensions. Because of this logical distinction IsRV32/IsRV64 make more sense to me at least.

It's a bit less clear for RVE given the way me model it within LLVM is somewhat like as if it was an instruction set extension. Though I still think I personally prefer IsRVE for that case.

[fpetrogalli]

In D146129#4196146, @asb wrote:

Thanks for making this suggestion.

The suggested renaming would be consistent with those other predicates, but RV{32,64}{I,E} are different base ISAs while the other predicates refer to instruction set extensions. Because of this logical distinction IsRV32/IsRV64 make more sense to me at least.

It's a bit less clear for RVE given the way me model it within LLVM is somewhat like as if it was an instruction set extension. Though I still think I personally prefer IsRVE for that case.

Oh I see - thank you for explaining.

Would it be OK if I change the SubtargetFeature param from "HasRV32" to "IsRV32" then? (same for the 64 bit one) So that we can associate SubtargetFeature and Predicate.

[fpetrogalli]

I have updated the patch modifying the SubtargetFeature definition instead of the Predicate NAME.

[asb]

LGTM - thanks!

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
-    : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
+    : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
 def Feature64Bit
-    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
+    : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                                          "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                                           "RV32I Base Instruction Set">;
 
 defvar RV32 = DefaultMode;

llvm/lib/Target/RISCV/RISCVSubtarget.h

 
 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
   bool GETTER() const { return ATTRIBUTE; }
 #include "RISCVGenSubtargetInfo.inc"
 
   bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
-  bool is64Bit() const { return HasRV64; }
+  bool is64Bit() const { return IsRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   unsigned getFLen() const {
     if (HasStdExtD)
       return 64;
 
     if (HasStdExtF)
       return 32;