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Differential D146008

[RISCV][NFC] Combine identical switch cases in TTI
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Authored by benshi001 on Mar 13 2023, 9:02 PM.

Details

Reviewers
craig.topper
reames
asb
jrtc27
fhahn
Commits
rGcb45be2b4f62: [RISCV][NFC] Combine identical switch cases in TTI

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Event Timeline

benshi001 created this revision.Mar 13 2023, 9:02 PM
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benshi001 requested review of this revision.Mar 13 2023, 9:02 PM
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Harbormaster completed remote builds in B219237: Diff 504928.Mar 13 2023, 9:46 PM
craig.topper accepted this revision.Mar 14 2023, 8:45 AM

LGTM

This revision is now accepted and ready to land.Mar 14 2023, 8:45 AM
asb accepted this revision.Mar 14 2023, 10:53 AM
Closed by commit rGcb45be2b4f62: [RISCV][NFC] Combine identical switch cases in TTI (authored by benshi001). · Explain WhyMar 14 2023, 5:28 PM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGcb45be2b4f62: [RISCV][NFC] Combine identical switch cases in TTI.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
11 lines

Diff 505335

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show First 20 Lines • Show All 870 Lines • ▼ Show 20 Lines case Intrinsic::smax: {
if ((ST->hasVInstructions() && LT.second.isVector()) || if ((ST->hasVInstructions() && LT.second.isVector()) ||
(LT.second.isScalarInteger() && ST->hasStdExtZbb())) (LT.second.isScalarInteger() && ST->hasStdExtZbb()))
return LT.first; return LT.first;
break; break;
} }
case Intrinsic::sadd_sat: case Intrinsic::sadd_sat:
case Intrinsic::ssub_sat: case Intrinsic::ssub_sat:
case Intrinsic::uadd_sat: case Intrinsic::uadd_sat:
case Intrinsic::usub_sat: { case Intrinsic::usub_sat:
case Intrinsic::fabs:
case Intrinsic::sqrt: {
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector()) if (ST->hasVInstructions() && LT.second.isVector())
return LT.first; return LT.first;
break; break;
} }
case Intrinsic::abs: { case Intrinsic::abs: {
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector()) { if (ST->hasVInstructions() && LT.second.isVector()) {
// vrsub.vi v10, v8, 0 // vrsub.vi v10, v8, 0
// vmax.vv v8, v8, v10 // vmax.vv v8, v8, v10
return LT.first * 2; return LT.first * 2;
} }
break; break;
} }
case Intrinsic::fabs:
case Intrinsic::sqrt: {
auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector())
return LT.first;
break;
}
// TODO: add more intrinsic // TODO: add more intrinsic
case Intrinsic::experimental_stepvector: { case Intrinsic::experimental_stepvector: {
unsigned Cost = 1; // vid unsigned Cost = 1; // vid
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
return Cost + (LT.first - 1); return Cost + (LT.first - 1);
} }
case Intrinsic::vp_rint: { case Intrinsic::vp_rint: {
// RISC-V target uses at least 5 instructions to lower rounding intrinsics. // RISC-V target uses at least 5 instructions to lower rounding intrinsics.
▲ Show 20 Lines • Show All 622 Lines • Show Last 20 Lines