Replace `IntrinsicEmitter::ComputeFixedEncoding()` and cleanup

[chapuni]

Summary

Depends on D146915

[chapuni]

• Update (w/ some fixups)

[arsenm]

llvm/include/llvm/CodeGen/ValueTypes.td

29

Does this mean it's now possible to define codegen patterns that accept different types? e.g. a single store pattern that accepts i32 and f32 inputs?

[chapuni]

Rebase on D143844

[chapuni]

Restore the last cleanup

[chapuni]

llvm/include/llvm/CodeGen/ValueTypes.td

29

I suppose this is just a convention for coming MVTEmitter to emit MVT::isOverloaded(). I have no idea if we could enhance semantics.

[chapuni]

• Update for recent changes

[chapuni]

• Update

[chapuni]

• Merge D146147

[chapuni]

• Reflect D145872

[chapuni]

• Split out preceding changes

[chapuni]

• Rebase

[chapuni]

• Rebase

[chapuni]

• Rebase

llvm/docs/TableGen/ProgRef.rst

 Note that all of the values have rules for converting them from one type to
 another. For example, these rules allow you to assign a value like ``7``
 to an entity of type ``bits<4>``.
 
 .. productionlist::
    Value: `SimpleValue` `ValueSuffix`*
         :| `Value` "#" [`Value`]
    ValueSuffix: "{" `RangeList` "}"
-              :| "[" `RangeList` "]"
+              :| "[" `SliceElements` "]"
               :| "." `TokIdentifier`
    RangeList: `RangePiece` ("," `RangePiece`)*
    RangePiece: `TokInteger`
              :| `TokInteger` "..." `TokInteger`
              :| `TokInteger` "-" `TokInteger`
              :| `TokInteger` `TokInteger`
+   SliceElements: (`SliceElement` ",")* `SliceElement` ","?
+   SliceElement: `Value`
+               :| `Value` "..." `Value`
+               :| `Value` "-" `Value`
+               :| `Value` `TokInteger`(negative)
 
 .. warning::
   The peculiar last form of :token:`RangePiece` is due to the fact that the
   "``-``" is included in the :token:`TokInteger`, hence ``1-5`` gets lexed as
   two consecutive tokens, with values ``1`` and ``-5``, instead of "1", "-",
   and "5". The use of hyphen as the range punctuation is deprecated.
 
 Simple values

 
 *value*\ ``{17}``
     The final value is bit 17 of the integer *value* (note the braces).
 
 *value*\ ``{8...15}``
     The final value is bits 8--15 of the integer *value*. The order of the
     bits can be reversed by specifying ``{15...8}``.
 
-*value*\ ``[4]``
-    The final value is element 4 of the list *value* (note the brackets).
+*value*\ ``[i]``
+    The final value is element `i` of the list *value* (note the brackets).
     In other words, the brackets act as a subscripting operator on the list.
     This is the case only when a single element is specified.
 
+*value*\ ``[i,]``
+    The final value is a list that contains a single element `i` of the list.
+    In short, a list slice with a single element.
+
 *value*\ ``[4...7,17,2...3,4]``
     The final value is a new list that is a slice of the list *value*.
     The new list contains elements 4, 5, 6, 7, 17, 2, 3, and 4.
     Elements may be included multiple times and in any order. This is the result
     only when more than one element is specified.
 
+    *value*\ ``[i,m...n,j,ls]``
+        Each element may be an expression (variables, bang operators).
+        The type of `m` and `n` should be `int`.
+        The tyep of `i`, `j`, and `ls` should be either `int` or `list<int>`.
+
 *value*\ ``.``\ *field*
     The final value is the value of the specified *field* in the specified
     record *value*.
 
 The paste operator
 ------------------
 
 The paste operator (``#``) is the only infix operator available in TableGen
``!not(``\ *a*\ ``)``
     an integer. The argument 0 results in 1 (true); any other
     argument results in 0 (false).
 
 ``!or(``\ *a*\ ``,`` *b*\ ``, ...)``
     This operator does a bitwise OR on *a*, *b*, etc., and produces the
     result. A logical OR can be performed if all the arguments are either
     0 or 1.
 
+``!range([``\ *a*\ ``,``] *b*\ ``)``
+    This operator produces half-open range sequence ``[a : b)`` as ``list<int>``.
+    *a* is ``0`` by default. ``!range(4)`` is equivalent to ``!range(0, 4)``.
+    Its result is `[0, 1, 2, 3]`.
+    The result is `[]<list<int>>` if *a* ``>=`` *b*.
+
+``!range([``\ *list*\ ``)``
+    Equivalent to ``!range(0, !size(list))``.
+
 ``!setdagop(``\ *dag*\ ``,`` *op*\ ``)``
     This operator produces a DAG node with the same arguments as *dag*, but with its
     operator replaced with *op*.
 
     Example: ``!setdagop((foo 1, 2), bar)`` results in ``(bar 1, 2)``.
 
 ``!shl(``\ *a*\ ``,`` *count*\ ``)``
     This operator shifts *a* left logically by *count* bits and produces the resulting

llvm/include/llvm/CodeGen/ValueTypes.td

 // there as well!
 //
 //===----------------------------------------------------------------------===//
 
 class ValueType<int size, int value> {
   string Namespace = "MVT";
   int Size = size;
   int Value = value;
+  int nElem = 1;
+  ValueType ElementType = ?;
+  int isOverloaded = false;
+  int isInteger = false;
+  int isFP = false;
+  int isVector = false;
+  int isScalable = false;
 }
 
+class VTAny<int value> : ValueType<0, value> {
+  let isOverloaded = true;
+}
+
+class VTInt<int size, int value>
+    : ValueType<size, value> {
+  let isInteger = true;
+}
+
+class VTFP<int size, int value>
+    : ValueType<size, value> {
+  let isFP = true;
+}
+
+class VTVec<int nelem, ValueType elt, int value>
+    : ValueType<!mul(nelem, elt.Size), value> {
+  let nElem = nelem;
+  let ElementType = elt;
+  let isInteger = elt.isInteger;
+  let isFP = elt.isFP;
+  let isVector = true;
+}
+
+class VTScalableVec<int nelem, ValueType elt, int value>
+    : VTVec<nelem, elt, value> {
+  let isScalable = true;
+}
+
+defset list<ValueType> ValueTypes = {
+
 def OtherVT : ValueType<0,   1>;  // "Other" value
-def i1      : ValueType<1,   2>;  // One bit boolean value
-def i2      : ValueType<2,   3>;  // 2-bit integer value
-def i4      : ValueType<4,   4>;  // 4-bit integer value
-def i8      : ValueType<8,   5>;  // 8-bit integer value
-def i16     : ValueType<16,  6>;  // 16-bit integer value
-def i32     : ValueType<32,  7>;  // 32-bit integer value
-def i64     : ValueType<64,  8>;  // 64-bit integer value
-def i128    : ValueType<128, 9>;  // 128-bit integer value
-
-def bf16    : ValueType<16,  10>;  // 16-bit brain floating point value
-def f16     : ValueType<16,  11>;  // 16-bit floating point value
-def f32     : ValueType<32,  12>;  // 32-bit floating point value
-def f64     : ValueType<64,  13>;  // 64-bit floating point value
-def f80     : ValueType<80,  14>;  // 80-bit floating point value
-def f128    : ValueType<128, 15>;  // 128-bit floating point value
-def ppcf128 : ValueType<128, 16>;  // PPC 128-bit floating point value
-
-def v1i1    : ValueType<1,    17>;  //    1 x i1 vector value
-def v2i1    : ValueType<2,    18>;  //    2 x i1 vector value
-def v4i1    : ValueType<4,    19>;  //    4 x i1 vector value
-def v8i1    : ValueType<8,    20>;  //    8 x i1 vector value
-def v16i1   : ValueType<16,   21>;  //   16 x i1 vector value
-def v32i1   : ValueType<32,   22>;  //   32 x i1 vector value
-def v64i1   : ValueType<64,   23>;  //   64 x i1 vector value
-def v128i1  : ValueType<128,  24>;  //  128 x i1 vector value
-def v256i1  : ValueType<256,  25>;  //  256 x i1 vector value
-def v512i1  : ValueType<512,  26>;  //  512 x i1 vector value
-def v1024i1 : ValueType<1024, 27>;  // 1024 x i1 vector value
-def v2048i1 : ValueType<2048, 28>;  // 2048 x i1 vector value
-
-def v128i2  : ValueType<256,  29>;   //  128 x i2 vector value
-def v256i2  : ValueType<512,  30>;   //  256 x i2 vector value
-
-def v64i4   : ValueType<256,  31>;   //   64 x i4 vector value
-def v128i4  : ValueType<512,  32>;   //  128 x i4 vector value
-
-def v1i8    : ValueType<8,    33>;  //    1 x i8 vector value
-def v2i8    : ValueType<16,   34>;  //    2 x i8 vector value
-def v4i8    : ValueType<32,   35>;  //    4 x i8 vector value
-def v8i8    : ValueType<64,   36>;  //    8 x i8 vector value
-def v16i8   : ValueType<128,  37>;  //   16 x i8 vector value
-def v32i8   : ValueType<256,  38>;  //   32 x i8 vector value
-def v64i8   : ValueType<512,  39>;  //   64 x i8 vector value
-def v128i8  : ValueType<1024, 40>;  //  128 x i8 vector value
-def v256i8  : ValueType<2048, 41>;  //  256 x i8 vector value
-def v512i8  : ValueType<4096, 42>;  //  512 x i8 vector value
-def v1024i8 : ValueType<8192, 43>;  // 1024 x i8 vector value
-
-def v1i16   : ValueType<16,   44>;  //   1 x i16 vector value
-def v2i16   : ValueType<32,   45>;  //   2 x i16 vector value
-def v3i16   : ValueType<48,   46>;  //   3 x i16 vector value
-def v4i16   : ValueType<64,   47>;  //   4 x i16 vector value
-def v8i16   : ValueType<128,  48>;  //   8 x i16 vector value
-def v16i16  : ValueType<256,  49>;  //  16 x i16 vector value
-def v32i16  : ValueType<512,  50>;  //  32 x i16 vector value
-def v64i16  : ValueType<1024, 51>;  //  64 x i16 vector value
-def v128i16 : ValueType<2048, 52>;  // 128 x i16 vector value
-def v256i16 : ValueType<4096, 53>;  // 256 x i16 vector value
-def v512i16 : ValueType<8192, 54>;  // 512 x i16 vector value
-
-def v1i32    : ValueType<32,    55>;  //    1 x i32 vector value
-def v2i32    : ValueType<64,    56>;  //    2 x i32 vector value
-def v3i32    : ValueType<96,    57>;  //    3 x i32 vector value
-def v4i32    : ValueType<128,   58>;  //    4 x i32 vector value
-def v5i32    : ValueType<160,   59>;  //    5 x i32 vector value
-def v6i32    : ValueType<192,   60>;  //    6 x f32 vector value
-def v7i32    : ValueType<224,   61>;  //    7 x f32 vector value
-def v8i32    : ValueType<256,   62>;  //    8 x i32 vector value
-def v9i32    : ValueType<288,   63>;  //    9 x i32 vector value
-def v10i32   : ValueType<320,   64>;  //   10 x i32 vector value
-def v11i32   : ValueType<352,   65>;  //   11 x i32 vector value
-def v12i32   : ValueType<384,   66>;  //   12 x i32 vector value
-def v16i32   : ValueType<512,   67>;  //   16 x i32 vector value
-def v32i32   : ValueType<1024,  68>;  //   32 x i32 vector value
-def v64i32   : ValueType<2048,  69>;  //   64 x i32 vector value
-def v128i32  : ValueType<4096,  70>;  //  128 x i32 vector value
-def v256i32  : ValueType<8192,  71>;  //  256 x i32 vector value
-def v512i32  : ValueType<16384, 72>;  //  512 x i32 vector value
-def v1024i32 : ValueType<32768, 73>;  // 1024 x i32 vector value
-def v2048i32 : ValueType<65536, 74>;  // 2048 x i32 vector value
-
-def v1i64   : ValueType<64,    75>;  //   1 x i64 vector value
-def v2i64   : ValueType<128,   76>;  //   2 x i64 vector value
-def v3i64   : ValueType<192,   77>;  //   3 x i64 vector value
-def v4i64   : ValueType<256,   78>;  //   4 x i64 vector value
-def v8i64   : ValueType<512,   79>;  //   8 x i64 vector value
-def v16i64  : ValueType<1024,  80>;  //  16 x i64 vector value
-def v32i64  : ValueType<2048,  81>;  //  32 x i64 vector value
-def v64i64  : ValueType<4096,  82>;  //  64 x i64 vector value
-def v128i64 : ValueType<8192,  83>;  // 128 x i64 vector value
-def v256i64 : ValueType<16384, 84>;  // 256 x i64 vector value
-
-def v1i128 : ValueType<128, 85>;  //  1 x i128 vector value
-
-def v1f16    : ValueType<16,     86>;  //    1 x f16 vector value
-def v2f16    : ValueType<32,     87>;  //    2 x f16 vector value
-def v3f16    : ValueType<48,     88>;  //    3 x f16 vector value
-def v4f16    : ValueType<64,     89>;  //    4 x f16 vector value
-def v8f16    : ValueType<128,    90>;  //    8 x f16 vector value
-def v16f16   : ValueType<256,    91>;  //   16 x f16 vector value
-def v32f16   : ValueType<512,    92>;  //   32 x f16 vector value
-def v64f16   : ValueType<1024,   93>;  //   64 x f16 vector value
-def v128f16  : ValueType<2048,   94>;  //  128 x f16 vector value
-def v256f16  : ValueType<4096,   95>;  //  256 x f16 vector value
-def v512f16  : ValueType<8192,   96>;  //  512 x f16 vector value
-
-def v2bf16   : ValueType<32,     97>;  //    2 x bf16 vector value
-def v3bf16   : ValueType<48,     98>;  //    3 x bf16 vector value
-def v4bf16   : ValueType<64,     99>;  //    4 x bf16 vector value
-def v8bf16   : ValueType<128,   100>;  //    8 x bf16 vector value
-def v16bf16  : ValueType<256,   101>;  //   16 x bf16 vector value
-def v32bf16  : ValueType<512,   102>;  //   32 x bf16 vector value
-def v64bf16  : ValueType<1024,  103>;  //   64 x bf16 vector value
-def v128bf16 : ValueType<2048,  104>;  //  128 x bf16 vector value
-
-def v1f32    : ValueType<32,    105>;  //    1 x f32 vector value
-def v2f32    : ValueType<64,    106>;  //    2 x f32 vector value
-def v3f32    : ValueType<96,    107>;  //    3 x f32 vector value
-def v4f32    : ValueType<128,   108>;  //    4 x f32 vector value
-def v5f32    : ValueType<160,   109>;  //    5 x f32 vector value
-def v6f32    : ValueType<192,   110>;  //    6 x f32 vector value
-def v7f32    : ValueType<224,   111>;  //    7 x f32 vector value
-def v8f32    : ValueType<256,   112>;  //    8 x f32 vector value
-def v9f32    : ValueType<288,   113>;  //    9 x f32 vector value
-def v10f32   : ValueType<320,   114>;  //   10 x f32 vector value
-def v11f32   : ValueType<352,   115>;  //   11 x f32 vector value
-def v12f32   : ValueType<384,   116>;  //   12 x f32 vector value
-def v16f32   : ValueType<512,   117>;  //   16 x f32 vector value
-def v32f32   : ValueType<1024,  118>;  //   32 x f32 vector value
-def v64f32   : ValueType<2048,  119>;  //   64 x f32 vector value
-def v128f32  : ValueType<4096,  120>;  //  128 x f32 vector value
-def v256f32  : ValueType<8192,  121>;  //  256 x f32 vector value
-def v512f32  : ValueType<16384, 122>;  //  512 x f32 vector value
-def v1024f32 : ValueType<32768, 123>;  // 1024 x f32 vector value
-def v2048f32 : ValueType<65536, 124>;  // 2048 x f32 vector value
-
-def v1f64    : ValueType<64,    125>;  //    1 x f64 vector value
-def v2f64    : ValueType<128,   126>;  //    2 x f64 vector value
-def v3f64    : ValueType<192,   127>;  //    3 x f64 vector value
-def v4f64    : ValueType<256,   128>;  //    4 x f64 vector value
-def v8f64    : ValueType<512,   129>;  //    8 x f64 vector value
-def v16f64   : ValueType<1024,  130>;  //   16 x f64 vector value
-def v32f64   : ValueType<2048,  131>;  //   32 x f64 vector value
-def v64f64   : ValueType<4096,  132>;  //   64 x f64 vector value
-def v128f64  : ValueType<8192,  133>;  //  128 x f64 vector value
-def v256f64  : ValueType<16384, 134>;  //  256 x f64 vector value
-
-def nxv1i1  : ValueType<1,  135>;  // n x  1 x i1  vector value
-def nxv2i1  : ValueType<2,  136>;  // n x  2 x i1  vector value
-def nxv4i1  : ValueType<4,  137>;  // n x  4 x i1  vector value
-def nxv8i1  : ValueType<8,  138>;  // n x  8 x i1  vector value
-def nxv16i1 : ValueType<16, 139>;  // n x 16 x i1  vector value
-def nxv32i1 : ValueType<32, 140>;  // n x 32 x i1  vector value
-def nxv64i1 : ValueType<64, 141>;  // n x 64 x i1  vector value
-
-def nxv1i8  : ValueType<8,   142>;  // n x  1 x i8  vector value
-def nxv2i8  : ValueType<16,  143>;  // n x  2 x i8  vector value
-def nxv4i8  : ValueType<32,  144>;  // n x  4 x i8  vector value
-def nxv8i8  : ValueType<64,  145>;  // n x  8 x i8  vector value
-def nxv16i8 : ValueType<128, 146>;  // n x 16 x i8  vector value
-def nxv32i8 : ValueType<256, 147>;  // n x 32 x i8  vector value
-def nxv64i8 : ValueType<512, 148>;  // n x 64 x i8  vector value
-
-def nxv1i16  : ValueType<16,  149>;  // n x  1 x i16 vector value
-def nxv2i16  : ValueType<32,  150>;  // n x  2 x i16 vector value
-def nxv4i16  : ValueType<64,  151>;  // n x  4 x i16 vector value
-def nxv8i16  : ValueType<128, 152>;  // n x  8 x i16 vector value
-def nxv16i16 : ValueType<256, 153>;  // n x 16 x i16 vector value
-def nxv32i16 : ValueType<512, 154>;  // n x 32 x i16 vector value
-
-def nxv1i32  : ValueType<32,   155>;  // n x  1 x i32 vector value
-def nxv2i32  : ValueType<64,   156>;  // n x  2 x i32 vector value
-def nxv4i32  : ValueType<128,  157>;  // n x  4 x i32 vector value
-def nxv8i32  : ValueType<256,  158>;  // n x  8 x i32 vector value
-def nxv16i32 : ValueType<512,  159>;  // n x 16 x i32 vector value
-def nxv32i32 : ValueType<1024, 160>;  // n x 32 x i32 vector value
-
-def nxv1i64  : ValueType<64,   161>;  // n x  1 x i64 vector value
-def nxv2i64  : ValueType<128,  162>;  // n x  2 x i64 vector value
-def nxv4i64  : ValueType<256,  163>;  // n x  4 x i64 vector value
-def nxv8i64  : ValueType<512,  164>;  // n x  8 x i64 vector value
-def nxv16i64 : ValueType<1024, 165>;  // n x 16 x i64 vector value
-def nxv32i64 : ValueType<2048, 166>;  // n x 32 x i64 vector value
-
-def nxv1f16  : ValueType<16,  167>;  // n x  1 x  f16 vector value
-def nxv2f16  : ValueType<32,  168>;  // n x  2 x  f16 vector value
-def nxv4f16  : ValueType<64,  169>;  // n x  4 x  f16 vector value
-def nxv8f16  : ValueType<128, 170>;  // n x  8 x  f16 vector value
-def nxv16f16 : ValueType<256, 171>;  // n x 16 x  f16 vector value
-def nxv32f16 : ValueType<512, 172>;  // n x 32 x  f16 vector value
-
-def nxv1bf16 : ValueType<16,  173>;  // n x  1 x bf16 vector value
-def nxv2bf16 : ValueType<32,  174>;  // n x  2 x bf16 vector value
-def nxv4bf16 : ValueType<64,  175>;  // n x  4 x bf16 vector value
-def nxv8bf16 : ValueType<128, 176>;  // n x  8 x bf16 vector value
-def nxv16bf16 : ValueType<256, 177>;  // n x 16 x bf16 vector value
-def nxv32bf16 : ValueType<512, 178>;  // n x 32 x bf16 vector value
-
-def nxv1f32  : ValueType<32,  179>;  // n x  1 x  f32 vector value
-def nxv2f32  : ValueType<64,  180>;  // n x  2 x  f32 vector value
-def nxv4f32  : ValueType<128, 181>;  // n x  4 x  f32 vector value
-def nxv8f32  : ValueType<256, 182>;  // n x  8 x  f32 vector value
-def nxv16f32 : ValueType<512, 183>;  // n x 16 x  f32 vector value
-
-def nxv1f64  : ValueType<64,  184>;  // n x  1 x  f64 vector value
-def nxv2f64  : ValueType<128, 185>;  // n x  2 x  f64 vector value
-def nxv4f64  : ValueType<256, 186>;  // n x  4 x  f64 vector value
-def nxv8f64  : ValueType<512, 187>;  // n x  8 x  f64 vector value
+
+def i1      : VTInt<1,   2>;  // One bit boolean value
+def i2      : VTInt<2,   3>;  // 2-bit integer value
+def i4      : VTInt<4,   4>;  // 4-bit integer value
+def i8      : VTInt<8,   5>;  // 8-bit integer value
+def i16     : VTInt<16,  6>;  // 16-bit integer value
+def i32     : VTInt<32,  7>;  // 32-bit integer value
+def i64     : VTInt<64,  8>;  // 64-bit integer value
+def i128    : VTInt<128, 9>;  // 128-bit integer value
+
+def bf16    : VTFP<16,  10>;  // 16-bit brain floating point value
+def f16     : VTFP<16,  11>;  // 16-bit floating point value
+def f32     : VTFP<32,  12>;  // 32-bit floating point value
+def f64     : VTFP<64,  13>;  // 64-bit floating point value
+def f80     : VTFP<80,  14>;  // 80-bit floating point value
+def f128    : VTFP<128, 15>;  // 128-bit floating point value
+def ppcf128 : VTFP<128, 16>;  // PPC 128-bit floating point value
+
+def v1i1    : VTVec<1,    i1, 17>;  //    1 x i1 vector value
+def v2i1    : VTVec<2,    i1, 18>;  //    2 x i1 vector value
+def v4i1    : VTVec<4,    i1, 19>;  //    4 x i1 vector value
+def v8i1    : VTVec<8,    i1, 20>;  //    8 x i1 vector value
+def v16i1   : VTVec<16,   i1, 21>;  //   16 x i1 vector value
+def v32i1   : VTVec<32,   i1, 22>;  //   32 x i1 vector value
+def v64i1   : VTVec<64,   i1, 23>;  //   64 x i1 vector value
+def v128i1  : VTVec<128,  i1, 24>;  //  128 x i1 vector value
+def v256i1  : VTVec<256,  i1, 25>;  //  256 x i1 vector value
+def v512i1  : VTVec<512,  i1, 26>;  //  512 x i1 vector value
+def v1024i1 : VTVec<1024, i1, 27>;  // 1024 x i1 vector value
+def v2048i1 : VTVec<2048, i1, 28>;  // 2048 x i1 vector value
+
+def v128i2  : VTVec<128,  i2, 29>;   //  128 x i2 vector value
+def v256i2  : VTVec<256,  i2, 30>;   //  256 x i2 vector value
+
+def v64i4   : VTVec<64,   i4, 31>;   //   64 x i4 vector value
+def v128i4  : VTVec<128,  i4, 32>;   //  128 x i4 vector value
+
+def v1i8    : VTVec<1,    i8, 33>;  //    1 x i8 vector value
+def v2i8    : VTVec<2,    i8, 34>;  //    2 x i8 vector value
+def v4i8    : VTVec<4,    i8, 35>;  //    4 x i8 vector value
+def v8i8    : VTVec<8,    i8, 36>;  //    8 x i8 vector value
+def v16i8   : VTVec<16,   i8, 37>;  //   16 x i8 vector value
+def v32i8   : VTVec<32,   i8, 38>;  //   32 x i8 vector value
+def v64i8   : VTVec<64,   i8, 39>;  //   64 x i8 vector value
+def v128i8  : VTVec<128,  i8, 40>;  //  128 x i8 vector value
+def v256i8  : VTVec<256,  i8, 41>;  //  256 x i8 vector value
+def v512i8  : VTVec<512,  i8, 42>;  //  512 x i8 vector value
+def v1024i8 : VTVec<1024, i8, 43>;  // 1024 x i8 vector value
+
+def v1i16   : VTVec<1,   i16, 44>;  //   1 x i16 vector value
+def v2i16   : VTVec<2,   i16, 45>;  //   2 x i16 vector value
+def v3i16   : VTVec<3,   i16, 46>;  //   3 x i16 vector value
+def v4i16   : VTVec<4,   i16, 47>;  //   4 x i16 vector value
+def v8i16   : VTVec<8,   i16, 48>;  //   8 x i16 vector value
+def v16i16  : VTVec<16,  i16, 49>;  //  16 x i16 vector value
+def v32i16  : VTVec<32,  i16, 50>;  //  32 x i16 vector value
+def v64i16  : VTVec<64,  i16, 51>;  //  64 x i16 vector value
+def v128i16 : VTVec<128, i16, 52>;  // 128 x i16 vector value
+def v256i16 : VTVec<256, i16, 53>;  // 256 x i16 vector value
+def v512i16 : VTVec<512, i16, 54>;  // 512 x i16 vector value
+
+def v1i32    : VTVec<1,    i32, 55>;  //    1 x i32 vector value
+def v2i32    : VTVec<2,    i32, 56>;  //    2 x i32 vector value
+def v3i32    : VTVec<3,    i32, 57>;  //    3 x i32 vector value
+def v4i32    : VTVec<4,    i32, 58>;  //    4 x i32 vector value
+def v5i32    : VTVec<5,    i32, 59>;  //    5 x i32 vector value
+def v6i32    : VTVec<6,    i32, 60>;  //    6 x f32 vector value
+def v7i32    : VTVec<7,    i32, 61>;  //    7 x f32 vector value
+def v8i32    : VTVec<8,    i32, 62>;  //    8 x i32 vector value
+def v9i32    : VTVec<9,    i32, 63>;  //    9 x i32 vector value
+def v10i32   : VTVec<10,   i32, 64>;  //   10 x i32 vector value
+def v11i32   : VTVec<11,   i32, 65>;  //   11 x i32 vector value
+def v12i32   : VTVec<12,   i32, 66>;  //   12 x i32 vector value
+def v16i32   : VTVec<16,   i32, 67>;  //   16 x i32 vector value
+def v32i32   : VTVec<32,   i32, 68>;  //   32 x i32 vector value
+def v64i32   : VTVec<64,   i32, 69>;  //   64 x i32 vector value
+def v128i32  : VTVec<128,  i32, 70>;  //  128 x i32 vector value
+def v256i32  : VTVec<256,  i32, 71>;  //  256 x i32 vector value
+def v512i32  : VTVec<512,  i32, 72>;  //  512 x i32 vector value
+def v1024i32 : VTVec<1024, i32, 73>;  // 1024 x i32 vector value
+def v2048i32 : VTVec<2048, i32, 74>;  // 2048 x i32 vector value
+
+def v1i64   : VTVec<1,   i64, 75>;  //   1 x i64 vector value
+def v2i64   : VTVec<2,   i64, 76>;  //   2 x i64 vector value
+def v3i64   : VTVec<3,   i64, 77>;  //   3 x i64 vector value
+def v4i64   : VTVec<4,   i64, 78>;  //   4 x i64 vector value
+def v8i64   : VTVec<8,   i64, 79>;  //   8 x i64 vector value
+def v16i64  : VTVec<16,  i64, 80>;  //  16 x i64 vector value
+def v32i64  : VTVec<32,  i64, 81>;  //  32 x i64 vector value
+def v64i64  : VTVec<64,  i64, 82>;  //  64 x i64 vector value
+def v128i64 : VTVec<128, i64, 83>;  // 128 x i64 vector value
+def v256i64 : VTVec<256, i64, 84>;  // 256 x i64 vector value
+
+def v1i128  : VTVec<1,  i128, 85>;  //  1 x i128 vector value
+
+def v1f16    : VTVec<1,    f16,  86>;  //    1 x f16 vector value
+def v2f16    : VTVec<2,    f16,  87>;  //    2 x f16 vector value
+def v3f16    : VTVec<3,    f16,  88>;  //    3 x f16 vector value
+def v4f16    : VTVec<4,    f16,  89>;  //    4 x f16 vector value
+def v8f16    : VTVec<8,    f16,  90>;  //    8 x f16 vector value
+def v16f16   : VTVec<16,   f16,  91>;  //   16 x f16 vector value
+def v32f16   : VTVec<32,   f16,  92>;  //   32 x f16 vector value
+def v64f16   : VTVec<64,   f16,  93>;  //   64 x f16 vector value
+def v128f16  : VTVec<128,  f16,  94>;  //  128 x f16 vector value
+def v256f16  : VTVec<256,  f16,  95>;  //  256 x f16 vector value
+def v512f16  : VTVec<512,  f16,  96>;  //  512 x f16 vector value
+
+def v2bf16   : VTVec<2,   bf16,  97>;  //    2 x bf16 vector value
+def v3bf16   : VTVec<3,   bf16,  98>;  //    3 x bf16 vector value
+def v4bf16   : VTVec<4,   bf16,  99>;  //    4 x bf16 vector value
+def v8bf16   : VTVec<8,   bf16, 100>;  //    8 x bf16 vector value
+def v16bf16  : VTVec<16,  bf16, 101>;  //   16 x bf16 vector value
+def v32bf16  : VTVec<32,  bf16, 102>;  //   32 x bf16 vector value
+def v64bf16  : VTVec<64,  bf16, 103>;  //   64 x bf16 vector value
+def v128bf16 : VTVec<128, bf16, 104>;  //  128 x bf16 vector value
+
+def v1f32    : VTVec<1,    f32, 105>;  //    1 x f32 vector value
+def v2f32    : VTVec<2,    f32, 106>;  //    2 x f32 vector value
+def v3f32    : VTVec<3,    f32, 107>;  //    3 x f32 vector value
+def v4f32    : VTVec<4,    f32, 108>;  //    4 x f32 vector value
+def v5f32    : VTVec<5,    f32, 109>;  //    5 x f32 vector value
+def v6f32    : VTVec<6,    f32, 110>;  //    6 x f32 vector value
+def v7f32    : VTVec<7,    f32, 111>;  //    7 x f32 vector value
+def v8f32    : VTVec<8,    f32, 112>;  //    8 x f32 vector value
+def v9f32    : VTVec<9,    f32, 113>;  //    9 x f32 vector value
+def v10f32   : VTVec<10,   f32, 114>;  //   10 x f32 vector value
+def v11f32   : VTVec<11,   f32, 115>;  //   11 x f32 vector value
+def v12f32   : VTVec<12,   f32, 116>;  //   12 x f32 vector value
+def v16f32   : VTVec<16,   f32, 117>;  //   16 x f32 vector value
+def v32f32   : VTVec<32,   f32, 118>;  //   32 x f32 vector value
+def v64f32   : VTVec<64,   f32, 119>;  //   64 x f32 vector value
+def v128f32  : VTVec<128,  f32, 120>;  //  128 x f32 vector value
+def v256f32  : VTVec<256,  f32, 121>;  //  256 x f32 vector value
+def v512f32  : VTVec<512,  f32, 122>;  //  512 x f32 vector value
+def v1024f32 : VTVec<1024, f32, 123>;  // 1024 x f32 vector value
+def v2048f32 : VTVec<2048, f32, 124>;  // 2048 x f32 vector value
+
+def v1f64    : VTVec<1,    f64, 125>;  //    1 x f64 vector value
+def v2f64    : VTVec<2,    f64, 126>;  //    2 x f64 vector value
+def v3f64    : VTVec<3,    f64, 127>;  //    3 x f64 vector value
+def v4f64    : VTVec<4,    f64, 128>;  //    4 x f64 vector value
+def v8f64    : VTVec<8,    f64, 129>;  //    8 x f64 vector value
+def v16f64   : VTVec<16,   f64, 130>;  //   16 x f64 vector value
+def v32f64   : VTVec<32,   f64, 131>;  //   32 x f64 vector value
+def v64f64   : VTVec<64,   f64, 132>;  //   64 x f64 vector value
+def v128f64  : VTVec<128,  f64, 133>;  //  128 x f64 vector value
+def v256f64  : VTVec<256,  f64, 134>;  //  256 x f64 vector value
+
+def nxv1i1  : VTScalableVec<1,  i1, 135>;  // n x  1 x i1  vector value
+def nxv2i1  : VTScalableVec<2,  i1, 136>;  // n x  2 x i1  vector value
+def nxv4i1  : VTScalableVec<4,  i1, 137>;  // n x  4 x i1  vector value
+def nxv8i1  : VTScalableVec<8,  i1, 138>;  // n x  8 x i1  vector value
+def nxv16i1 : VTScalableVec<16, i1, 139>;  // n x 16 x i1  vector value
+def nxv32i1 : VTScalableVec<32, i1, 140>;  // n x 32 x i1  vector value
+def nxv64i1 : VTScalableVec<64, i1, 141>;  // n x 64 x i1  vector value
+
+def nxv1i8  : VTScalableVec<1,  i8, 142>;  // n x  1 x i8  vector value
+def nxv2i8  : VTScalableVec<2,  i8, 143>;  // n x  2 x i8  vector value
+def nxv4i8  : VTScalableVec<4,  i8, 144>;  // n x  4 x i8  vector value
+def nxv8i8  : VTScalableVec<8,  i8, 145>;  // n x  8 x i8  vector value
+def nxv16i8 : VTScalableVec<16, i8, 146>;  // n x 16 x i8  vector value
+def nxv32i8 : VTScalableVec<32, i8, 147>;  // n x 32 x i8  vector value
+def nxv64i8 : VTScalableVec<64, i8, 148>;  // n x 64 x i8  vector value
+
+def nxv1i16  : VTScalableVec<1,  i16, 149>;  // n x  1 x i16 vector value
+def nxv2i16  : VTScalableVec<2,  i16, 150>;  // n x  2 x i16 vector value
+def nxv4i16  : VTScalableVec<4,  i16, 151>;  // n x  4 x i16 vector value
+def nxv8i16  : VTScalableVec<8,  i16, 152>;  // n x  8 x i16 vector value
+def nxv16i16 : VTScalableVec<16, i16, 153>;  // n x 16 x i16 vector value
+def nxv32i16 : VTScalableVec<32, i16, 154>;  // n x 32 x i16 vector value
+
+def nxv1i32  : VTScalableVec<1,  i32, 155>;  // n x  1 x i32 vector value
+def nxv2i32  : VTScalableVec<2,  i32, 156>;  // n x  2 x i32 vector value
+def nxv4i32  : VTScalableVec<4,  i32, 157>;  // n x  4 x i32 vector value
+def nxv8i32  : VTScalableVec<8,  i32, 158>;  // n x  8 x i32 vector value
+def nxv16i32 : VTScalableVec<16, i32, 159>;  // n x 16 x i32 vector value
+def nxv32i32 : VTScalableVec<32, i32, 160>;  // n x 32 x i32 vector value
+
+def nxv1i64  : VTScalableVec<1,  i64, 161>;  // n x  1 x i64 vector value
+def nxv2i64  : VTScalableVec<2,  i64, 162>;  // n x  2 x i64 vector value
+def nxv4i64  : VTScalableVec<4,  i64, 163>;  // n x  4 x i64 vector value
+def nxv8i64  : VTScalableVec<8,  i64, 164>;  // n x  8 x i64 vector value
+def nxv16i64 : VTScalableVec<16, i64, 165>;  // n x 16 x i64 vector value
+def nxv32i64 : VTScalableVec<32, i64, 166>;  // n x 32 x i64 vector value
+
+def nxv1f16  : VTScalableVec<1,  f16, 167>;  // n x  1 x  f16 vector value
+def nxv2f16  : VTScalableVec<2,  f16, 168>;  // n x  2 x  f16 vector value
+def nxv4f16  : VTScalableVec<4,  f16, 169>;  // n x  4 x  f16 vector value
+def nxv8f16  : VTScalableVec<8,  f16, 170>;  // n x  8 x  f16 vector value
+def nxv16f16 : VTScalableVec<16, f16, 171>;  // n x 16 x  f16 vector value
+def nxv32f16 : VTScalableVec<32, f16, 172>;  // n x 32 x  f16 vector value
+
+def nxv1bf16  : VTScalableVec<1,  bf16, 173>;  // n x  1 x bf16 vector value
+def nxv2bf16  : VTScalableVec<2,  bf16, 174>;  // n x  2 x bf16 vector value
+def nxv4bf16  : VTScalableVec<4,  bf16, 175>;  // n x  4 x bf16 vector value
+def nxv8bf16  : VTScalableVec<8,  bf16, 176>;  // n x  8 x bf16 vector value
+def nxv16bf16 : VTScalableVec<16, bf16, 177>;  // n x 16 x bf16 vector value
+def nxv32bf16 : VTScalableVec<32, bf16, 178>;  // n x 32 x bf16 vector value
+
+def nxv1f32  : VTScalableVec<1,  f32, 179>;  // n x  1 x  f32 vector value
+def nxv2f32  : VTScalableVec<2,  f32, 180>;  // n x  2 x  f32 vector value
+def nxv4f32  : VTScalableVec<4,  f32, 181>;  // n x  4 x  f32 vector value
+def nxv8f32  : VTScalableVec<8,  f32, 182>;  // n x  8 x  f32 vector value
+def nxv16f32 : VTScalableVec<16, f32, 183>;  // n x 16 x  f32 vector value
+
+def nxv1f64  : VTScalableVec<1,  f64, 184>;  // n x  1 x  f64 vector value
+def nxv2f64  : VTScalableVec<2,  f64, 185>;  // n x  2 x  f64 vector value
+def nxv4f64  : VTScalableVec<4,  f64, 186>;  // n x  4 x  f64 vector value
+def nxv8f64  : VTScalableVec<8,  f64, 187>;  // n x  8 x  f64 vector value
 
 def x86mmx    : ValueType<64,   188>;  // X86 MMX value
 def FlagVT    : ValueType<0,    189>;  // Pre-RA sched glue
 def isVoid    : ValueType<0,    190>;  // Produces no value
 def untyped   : ValueType<8,    191>;  // Produces an untyped value
 def funcref   : ValueType<0,    192>;  // WebAssembly's funcref type
 def externref : ValueType<0,    193>;  // WebAssembly's externref type
 def x86amx    : ValueType<8192, 194>;  // X86 AMX value
 def i64x8     : ValueType<512,  195>;  // 8 Consecutive GPRs (AArch64)
 def aarch64svcount
               : ValueType<16,   196>;  // AArch64 predicate-as-counter
 
 def token      : ValueType<0, 248>;  // TokenTy
 def MetadataVT : ValueType<0, 249>;  // Metadata
 
 // Pseudo valuetype mapped to the current pointer size to any address space.
 // Should only be used in TableGen.
-def iPTRAny    : ValueType<0, 250>;
+def iPTRAny    : VTAny<250>;
 
 // Pseudo valuetype to represent "vector of any size"
-def vAny       : ValueType<0, 251>;
+def vAny       : VTAny<251>;
 
 // Pseudo valuetype to represent "float of any format"
-def fAny       : ValueType<0, 252>;
+def fAny       : VTAny<252>;
 
 // Pseudo valuetype to represent "integer of any bit width"
-def iAny       : ValueType<0, 253>;
+def iAny       : VTAny<253>;
 
 // Pseudo valuetype mapped to the current pointer size.
 def iPTR       : ValueType<0, 254>;
 
 // Pseudo valuetype to represent "any type of any size".
-def Any        : ValueType<0, 255>;
+def Any        : VTAny<255>;
+
+} // end defset ValueTypes
 
 /// This class is for targets that want to use pointer types in patterns
 /// with the GlobalISelEmitter.  Targets must define their own pointer
 /// derived from this class.  The scalar argument should be an
 /// integer type with the same bit size as the pointer.
 /// e.g. def p0 : PtrValueType <i64, 0>;
 
 class PtrValueType <ValueType scalar, int addrspace> :
     ValueType<scalar.Size, scalar.Value> {
   int AddrSpace = addrspace;
 }

llvm/include/llvm/IR/Intrinsics.h

 //===- Intrinsics.h - LLVM Intrinsic Function Handling ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
union {
       unsigned Integer_Width;
       unsigned Float_Width;
       unsigned Pointer_AddressSpace;
       unsigned Struct_NumElements;
       unsigned Argument_Info;
       ElementCount Vector_Width;
     };
 
+    // AK_% : Defined in Intrinsics.td
     enum ArgKind {
-      AK_Any,
-      AK_AnyInteger,
-      AK_AnyFloat,
-      AK_AnyVector,
-      AK_AnyPointer,
-      AK_MatchType = 7
+#define GET_INTRINSIC_ARGKIND
+#include "llvm/IR/IntrinsicEnums.inc"
+#undef GET_INTRINSIC_ARGKIND
     };
 
     unsigned getArgumentNumber() const {
       assert(Kind == Argument || Kind == ExtendArgument ||
              Kind == TruncArgument || Kind == HalfVecArgument ||
              Kind == SameVecWidthArgument || Kind == PtrToArgument ||
              Kind == PtrToElt || Kind == VecElementArgument ||
              Kind == Subdivide2Argument || Kind == Subdivide4Argument ||

llvm/include/llvm/IR/Intrinsics.td

 // intrinsic properties.  By default, intrinsics are assumed to have side
 // effects, so this property is only necessary if you have defined one of
 // the memory properties listed above.
 // For this property, 'side effects' has the same meaning as 'side effects'
 // defined by the hasSideEffects property of the TableGen Instruction class.
 def IntrHasSideEffects : IntrinsicProperty;
 
 //===----------------------------------------------------------------------===//
+// IIT constants and utils
+//===----------------------------------------------------------------------===//
+
+// llvm::Intrinsic::IITDescriptor::ArgKind::AK_%
+def ArgKind {
+  int Any        = 0;
+  int AnyInteger = 1;
+  int AnyFloat   = 2;
+  int AnyVector  = 3;
+  int AnyPointer = 4;
+
+  int MatchType  = 7;
+}
+
+// (Idx << 3) | ArgCode
+class EncAnyType<int ArgCode=0> {
+  int ret = !or(0x100, ArgCode);
+}
+
+// (Mapping[Num] << 3) | MatchType
+class EncMatchType<int Num=0> {
+  int ret = !or(0x200, Num);
+}
+
+// (Mapping[Num] << 3) | ArgCodes[Mapping[Num]]
+class EncSameWidth<int Num=0> {
+  int ret = !or(0x300, Num);
+}
+
+// ArgNo
+class EncNextArgA<int dummy=0> {
+  int ret = !or(0x400, dummy);
+}
+
+// Mapping[Num]
+class EncNextArgN<int Num=0> {
+  int ret = !or(0x500, Num);
+}
+
+class DecArgCode<
+  list<int> Mapping,
+  list<int> ArgCodes,
+  int ACIdx,
+  int ax
+> {
+  int ah = !and(ax, 0xFF00);
+  int al = !and(ax, 0x00FF);
+  int num = Mapping[al];
+  int ret = !cond(
+    !eq(ah, EncAnyType<>.ret)   : !or(!shl(ACIdx, 3), al),
+    !eq(ah, EncMatchType<>.ret) : !or(!shl(num, 3), ArgKind.MatchType),
+    !eq(ah, EncSameWidth<>.ret) : !or(!shl(num, 3), ArgCodes[num]),
+    !eq(ah, EncNextArgA<>.ret)  : ACIdx,
+    !eq(ah, EncNextArgN<>.ret)  : num,
+    true : al);
+}
+
+//===----------------------------------------------------------------------===//
+// IIT_Info
+//===----------------------------------------------------------------------===//
+
+class IIT_Base<int num> {
+  int Number = num;
+  list<ValueType> VTs = ?;
+}
+
+class IIT_VT<ValueType vt, int num> : IIT_Base<num> {
+  let VTs = [vt];
+}
+
+class IIT_Int<int size, int num> : IIT_Base<num> {
+  let VTs = !filter(vti, ValueTypes,
+    !and(vti.isInteger, !eq(vti.Size, size)));
+}
+
+class IIT_Vec<int nelem, int num> : IIT_Base<num> {
+  let VTs = !filter(vti, ValueTypes,
+    !and(vti.isVector, !eq(vti.nElem, nelem)));
+}
+
+defset list<IIT_Base> IIT_all = {
+def IIT_Done : IIT_Base<    0>;
+def IIT_I1   : IIT_Int<1,   1>;
+def IIT_I8   : IIT_Int<8,   2>;
+def IIT_I16  : IIT_Int<16,  3>;
+def IIT_I32  : IIT_Int<32,  4>;
+def IIT_I64  : IIT_Int<64,  5>;
+def IIT_F16  : IIT_VT<f16,  6>;
+def IIT_F32  : IIT_VT<f32,  7>;
+def IIT_F64  : IIT_VT<f64,  8>;
+def IIT_V2   : IIT_Vec<2,   9>;
+def IIT_V4   : IIT_Vec<4,  10>;
+def IIT_V8   : IIT_Vec<8,  11>;
+def IIT_V16  : IIT_Vec<16, 12>;
+def IIT_V32  : IIT_Vec<32, 13>;
+def IIT_PTR  : IIT_Base<   14>;
+def IIT_ARG  : IIT_Base<   15>;
+
+def IIT_V64 : IIT_Vec<64, 16>;
+def IIT_MMX : IIT_VT<x86mmx, 17>;
+def IIT_TOKEN : IIT_VT<token, 18>;
+def IIT_METADATA : IIT_VT<MetadataVT, 19>;
+def IIT_EMPTYSTRUCT : IIT_VT<OtherVT, 20>;
+def IIT_STRUCT2 : IIT_Base<21>;
+def IIT_STRUCT3 : IIT_Base<22>;
+def IIT_STRUCT4 : IIT_Base<23>;
+def IIT_STRUCT5 : IIT_Base<24>;
+def IIT_EXTEND_ARG : IIT_Base<25>;
+def IIT_TRUNC_ARG : IIT_Base<26>;
+def IIT_ANYPTR : IIT_Base<27>;
+def IIT_V1 : IIT_Vec<1, 28>;
+def IIT_VARARG : IIT_VT<isVoid, 29>;
+def IIT_HALF_VEC_ARG : IIT_Base<30>;
+def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
+def IIT_PTR_TO_ARG : IIT_Base<32>;
+def IIT_PTR_TO_ELT : IIT_Base<33>;
+def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
+def IIT_I128 : IIT_Int<128, 35>;
+def IIT_V512 : IIT_Vec<512, 36>;
+def IIT_V1024 : IIT_Vec<1024, 37>;
+def IIT_STRUCT6 : IIT_Base<38>;
+def IIT_STRUCT7 : IIT_Base<39>;
+def IIT_STRUCT8 : IIT_Base<40>;
+def IIT_F128 : IIT_VT<f128, 41>;
+def IIT_VEC_ELEMENT : IIT_Base<42>;
+def IIT_SCALABLE_VEC : IIT_Base<43>;
+def IIT_SUBDIVIDE2_ARG : IIT_Base<44>;
+def IIT_SUBDIVIDE4_ARG : IIT_Base<45>;
+def IIT_VEC_OF_BITCASTS_TO_INT : IIT_Base<46>;
+def IIT_V128 : IIT_Vec<128, 47>;
+def IIT_BF16 : IIT_VT<bf16, 48>;
+def IIT_STRUCT9 : IIT_Base<49>;
+def IIT_V256 : IIT_Vec<256, 50>;
+def IIT_AMX : IIT_VT<x86amx, 51>;
+def IIT_PPCF128 : IIT_VT<ppcf128, 52>;
+def IIT_V3 : IIT_Vec<3, 53>;
+def IIT_EXTERNREF : IIT_VT<externref, 54>;
+def IIT_FUNCREF : IIT_VT<funcref, 55>;
+def IIT_ANYPTR_TO_ELT : IIT_Base<56>;
+def IIT_I2 : IIT_Int<2, 57>;
+def IIT_I4 : IIT_Int<4, 58>;
+}
+
+defvar IIT_all_FixedTypes = !filter(iit, IIT_all,
+  !or(!isa<IIT_VT>(iit), !isa<IIT_Int>(iit)));
+
+defvar IIT_all_VectorTypes = !filter(iit, IIT_all,
+  !isa<IIT_Vec>(iit));
+
+defvar IIT_RetNumbers = [
+  [IIT_Done.Number],
+  []<int>,
+  [IIT_STRUCT2.Number],
+  [IIT_STRUCT3.Number],
+  [IIT_STRUCT4.Number],
+  [IIT_STRUCT5.Number],
+  [IIT_STRUCT6.Number],
+  [IIT_STRUCT7.Number],
+  [IIT_STRUCT8.Number],
+  [IIT_STRUCT9.Number],
+];
+
+//===----------------------------------------------------------------------===//
 // Types used by intrinsics.
 //===----------------------------------------------------------------------===//
 
 class LLVMType<ValueType vt> {
   ValueType VT = vt;
-  int isAny = false;
+  int isAny = vt.isOverloaded;
+
+  int ArgCode = ?;
+  int Number = ?;
+
+  list<IIT_Base> IITs = !filter(iit, IIT_all_FixedTypes,
+    !not(!empty(!filter(iit_vt, iit.VTs,
+      !eq(iit_vt, !if(vt.isVector, vt.ElementType, vt))))));
+  assert !le(!size(IITs), 1), "Duplicate type";
+
+  list<IIT_Base> IIT_Vecs = !if(vt.isVector,
+    !filter(iit, IIT_all_VectorTypes,
+      !not(!empty(!filter(iit_vt, iit.VTs, !and(
+        !eq(iit_vt.ElementType, vt.ElementType),
+        !eq(iit_vt.nElem, vt.nElem)))))),
+    []);
+  assert !le(!size(IIT_Vecs), 1), "Duplicate type";
+
+  list<int> Sig = !listconcat(
+    !if(vt.isScalable, [IIT_SCALABLE_VEC.Number], []),
+    !foreach(iit, IIT_Vecs, iit.Number),
+    !foreach(iit, IITs,     iit.Number));
+}
+
+class LLVMAnyType<ValueType vt> : LLVMType<vt> {
+  let ArgCode = !cond(
+    !eq(vt, Any)     : ArgKind.Any,
+    !eq(vt, iAny)    : ArgKind.AnyInteger,
+    !eq(vt, fAny)    : ArgKind.AnyFloat,
+    !eq(vt, vAny)    : ArgKind.AnyVector,
+    !eq(vt, iPTRAny) : ArgKind.AnyPointer,
+  );
+  let Sig = [
+    IIT_ARG.Number,
+    EncAnyType<ArgCode>.ret,
+  ];
+
+  assert isAny, "LLVMAnyType.VT should have isOverloaded";
 }
 
 class LLVMQualPointerType<LLVMType elty, int addrspace>
   : LLVMType<iPTR>{
   LLVMType ElTy = elty;
-  int AddrSpace = addrspace;
+  assert !and(!le(0, addrspace), !le(addrspace, 255)),
+    "Address space exceeds 255";
+
+  // D63507: LLVMPointerType<llvm_any_ty>
+  let isAny = elty.isAny;
+
+  let Sig = !listconcat(
+    !if(addrspace, [
+      IIT_ANYPTR.Number,
+      addrspace,
+    ], [
+      IIT_PTR.Number,
+    ]),
+    ElTy.Sig);
 }
 
 class LLVMPointerType<LLVMType elty>
   : LLVMQualPointerType<elty, 0>;
 
 class LLVMAnyPointerType<LLVMType elty>
-  : LLVMType<iPTRAny>{
+  : LLVMAnyType<iPTRAny> {
   LLVMType ElTy = elty;
 
-  let isAny = true;
+  assert isAny, "iPTRAny should have isOverloaded";
 }
 
 // Match the type of another intrinsic parameter.  Number is an index into the
 // list of overloaded types for the intrinsic, excluding all the fixed types.
 // The Number value must refer to a previously listed type.  For example:
 //   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyfloat_ty, LLVMMatchType<0>]>
 // has two overloaded types, the 2nd and 3rd arguments.  LLVMMatchType<0>
 // refers to the first overloaded type, which is the 2nd argument.
-class LLVMMatchType<int num>
+class LLVMMatchType<int num, IIT_Base IIT_Info = IIT_ARG>
   : LLVMType<OtherVT>{
-  int Number = num;
+  let Number = num;
+  let Sig = [
+    IIT_Info.Number,
+    EncMatchType<num>.ret,
+  ];
+}
+
+class LLVMMatchTypeNextArg<int num, IIT_Base IIT_Info>
+  : LLVMMatchType<num, IIT_Info> {
+  let Sig = [
+    IIT_Info.Number,
+    EncNextArgA<>.ret,
+    EncNextArgN<num>.ret,
+  ];
 }
 
 // Match the type of another intrinsic parameter that is expected to be based on
 // an integral type (i.e. either iN or <N x iM>), but change the scalar size to
 // be twice as wide or half as wide as the other type.  This is only useful when
 // the intrinsic is overloaded, so the matched type should be declared as iAny.
-class LLVMExtendedType<int num> : LLVMMatchType<num>;
-class LLVMTruncatedType<int num> : LLVMMatchType<num>;
+class LLVMExtendedType<int num> : LLVMMatchType<num, IIT_EXTEND_ARG>;
+class LLVMTruncatedType<int num> : LLVMMatchType<num, IIT_TRUNC_ARG>;
 
 // Match the scalar/vector of another intrinsic parameter but with a different
 // element type. Either both are scalars or both are vectors with the same
 // number of elements.
 class LLVMScalarOrSameVectorWidth<int idx, LLVMType elty>
-  : LLVMMatchType<idx> {
-  ValueType ElTy = elty.VT;
+  : LLVMMatchType<idx, IIT_SAME_VEC_WIDTH_ARG> {
+  let Sig = !listconcat([
+    IIT_SAME_VEC_WIDTH_ARG.Number,
+    EncSameWidth<idx>.ret,
+  ], elty.Sig);
 }
 
-class LLVMPointerTo<int num> : LLVMMatchType<num>;
-class LLVMPointerToElt<int num> : LLVMMatchType<num>;
-class LLVMAnyPointerToElt<int num> : LLVMMatchType<num>;
-class LLVMVectorOfAnyPointersToElt<int num> : LLVMMatchType<num>;
-class LLVMVectorElementType<int num> : LLVMMatchType<num>;
+class LLVMPointerTo<int num> : LLVMMatchType<num, IIT_PTR_TO_ARG>;
+class LLVMPointerToElt<int num> : LLVMMatchType<num, IIT_PTR_TO_ELT>;
+class LLVMAnyPointerToElt<int num>
+  : LLVMMatchTypeNextArg<num, IIT_ANYPTR_TO_ELT>;
+class LLVMVectorOfAnyPointersToElt<int num>
+  : LLVMMatchTypeNextArg<num, IIT_VEC_OF_ANYPTRS_TO_ELT>;
+class LLVMVectorElementType<int num> : LLVMMatchType<num, IIT_VEC_ELEMENT>;
 
 // Match the type of another intrinsic parameter that is expected to be a
 // vector type, but change the element count to be half as many.
-class LLVMHalfElementsVectorType<int num> : LLVMMatchType<num>;
+class LLVMHalfElementsVectorType<int num>
+  : LLVMMatchType<num, IIT_HALF_VEC_ARG>;
 
 // Match the type of another intrinsic parameter that is expected to be a
 // vector type (i.e. <N x iM>) but with each element subdivided to
 // form a vector with more elements that are smaller than the original.
-class LLVMSubdivide2VectorType<int num> : LLVMMatchType<num>;
-class LLVMSubdivide4VectorType<int num> : LLVMMatchType<num>;
+class LLVMSubdivide2VectorType<int num>
+  : LLVMMatchType<num, IIT_SUBDIVIDE2_ARG>;
+class LLVMSubdivide4VectorType<int num>
+  : LLVMMatchType<num, IIT_SUBDIVIDE4_ARG>;
 
 // Match the element count and bit width of another intrinsic parameter, but
 // change the element type to an integer.
-class LLVMVectorOfBitcastsToInt<int num> : LLVMMatchType<num>;
+class LLVMVectorOfBitcastsToInt<int num>
+  : LLVMMatchType<num, IIT_VEC_OF_BITCASTS_TO_INT>;
 
 def llvm_void_ty       : LLVMType<isVoid>;
-let isAny = true in {
-  def llvm_any_ty        : LLVMType<Any>;
-  def llvm_anyint_ty     : LLVMType<iAny>;
-  def llvm_anyfloat_ty   : LLVMType<fAny>;
-  def llvm_anyvector_ty  : LLVMType<vAny>;
-}
+
+def llvm_any_ty        : LLVMAnyType<Any>;
+def llvm_anyint_ty     : LLVMAnyType<iAny>;
+def llvm_anyfloat_ty   : LLVMAnyType<fAny>;
+def llvm_anyvector_ty  : LLVMAnyType<vAny>;
+
 def llvm_i1_ty         : LLVMType<i1>;
 def llvm_i8_ty         : LLVMType<i8>;
 def llvm_i16_ty        : LLVMType<i16>;
 def llvm_i32_ty        : LLVMType<i32>;
 def llvm_i64_ty        : LLVMType<i64>;
 def llvm_i128_ty       : LLVMType<i128>;
 def llvm_half_ty       : LLVMType<f16>;
 def llvm_bfloat_ty     : LLVMType<bf16>;

 def llvm_v16f64_ty     : LLVMType<v16f64>;   // 16 x double
 
 def llvm_vararg_ty     : LLVMType<isVoid>;   // this means vararg here
 
 def llvm_externref_ty  : LLVMType<externref>;
 def llvm_funcref_ty    : LLVMType<funcref>;
 
 //===----------------------------------------------------------------------===//
+
+class MakeIdx<list<int> Set> {
+  list<int> IdxsR = !foreach(i, !range(Set),
+    !if(Set[i],
+      !foldl(0, !range(0, i), m, j, !add(m, Set[j])),
+      -1));
+
+  list<int> RIdxsR = !foreach(i, !range(Set),
+    !foldl(-1, !range(Set), m, j,
+      !if(!and(Set[j], !eq(IdxsR[j], i)), j, m)));
+
+  list<int> Idxs  = !foreach(a, IdxsR,  !if(!ge(a, 0), a, ?));
+  list<int> RIdxs = !foreach(a, RIdxsR, !if(!ge(a, 0), a, ?));
+}
+
+class TypeInfoGen<
+  list<LLVMType> RetTypes,
+  list<LLVMType> ParamTypes
+> {
+  list<LLVMType> AllTypes = !listconcat(RetTypes, ParamTypes);
+
+  // ArgCodes for NextArg -- isAny or MatchTypeNextArg
+  list<int> ACIdxs = MakeIdx<
+    !foreach(ty, AllTypes,
+      !or(ty.isAny, !isa<LLVMMatchTypeNextArg>(ty)))>.Idxs;
+
+  // ArgCodes (only for isAny or MatchTypeNextArg)
+  list<LLVMType> ACTys = !filter(ty, AllTypes,
+    !or(ty.isAny, !isa<LLVMMatchTypeNextArg>(ty)));
+
+  list<int> ArgCodes = !foreach(ty, ACTys, ty.ArgCode);
+
+  // Mappings MatchTypeIdx to ACTys
+  list<int> MappingRIdxs = MakeIdx<
+    !foreach(ty, ACTys, ty.isAny)>.RIdxs;
+
+  list<LLVMType> Types = !foreach(ty, AllTypes,
+    !if(!isa<LLVMMatchType>(ty), ACTys[MappingRIdxs[ty.Number]], ty));
+
+  list<list<int>> TypeSig = !listconcat(
+    [IIT_RetNumbers[!size(RetTypes)]],
+    !foreach(i, !range(AllTypes),
+      !foreach(a, AllTypes[i].Sig,
+        DecArgCode<
+          MappingRIdxs,
+          ArgCodes,
+          ACIdxs[i],
+          a>.ret)));
+}
+
+//===----------------------------------------------------------------------===//
 // Intrinsic Definitions.
 //===----------------------------------------------------------------------===//
 
 // Intrinsic class - This is used to define one LLVM intrinsic.  The name of the
 // intrinsic definition should start with "int_", then match the LLVM intrinsic
 // name with the "llvm." prefix removed, and all "."s turned into "_"s.  For
 // example, llvm.bswap.i16 -> int_bswap_i16.
 //
class Intrinsic<list<LLVMType> ret_types,
   list<IntrinsicProperty> IntrProperties = intr_properties;
   let Properties = sd_properties;
 
   // Disable applying IntrinsicProperties that are marked default with
   // IntrinsicProperty<1>
   bit DisableDefaultAttributes = disable_default_attributes;
 
   bit isTarget = false;
+
+  TypeInfoGen TypeInfo = TypeInfoGen<RetTypes, ParamTypes>;
+  bit isOverloaded = !gt(!size(TypeInfo.MappingRIdxs), 0);
+  list<LLVMType> Types = TypeInfo.Types;
+  list<list<int>> TypeSig = TypeInfo.TypeSig;
 }
 
 // Intrinsic with default attributes (disable_default_attributes = false).
 class DefaultAttrsIntrinsic<list<LLVMType> ret_types,
                 list<LLVMType> param_types = [],
                 list<IntrinsicProperty> intr_properties = [],
                 string name = "",
                 list<SDNodeProperty> sd_properties = []>

llvm/include/llvm/TableGen/Record.h

 //===- llvm/TableGen/Record.h - Classes for Table Records -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
enum InitKind : uint8_t {
     IK_LastOpInit,
     IK_CondOpInit,
     IK_FoldOpInit,
     IK_IsAOpInit,
     IK_ExistsOpInit,
     IK_AnonymousNameInit,
     IK_StringInit,
     IK_VarInit,
-    IK_VarListElementInit,
     IK_VarBitInit,
     IK_VarDefInit,
     IK_LastTypedInit,
     IK_UnsetInit
   };
 
 private:
   const InitKind Kind;
public:
   /// This function is used to implement the bit range
   /// selection operator. Given a value, it selects the specified bits,
   /// returning them as a new \p Init of type \p bits. If it is not legal
   /// to use the bit selection operator on this value, null is returned.
   virtual Init *convertInitializerBitRange(ArrayRef<unsigned> Bits) const {
     return nullptr;
   }
 
-  /// This function is used to implement the list slice
-  /// selection operator.  Given a value, it selects the specified list
-  /// elements, returning them as a new \p Init of type \p list. If it
-  /// is not legal to use the slice operator, null is returned.
-  virtual Init *convertInitListSlice(ArrayRef<unsigned> Elements) const {
-    return nullptr;
-  }
-
   /// This function is used to implement the FieldInit class.
   /// Implementors of this method should return the type of the named
   /// field if they are of type record.
   virtual RecTy *getFieldType(StringInit *FieldName) const {
     return nullptr;
   }
 
   /// This function is used by classes that refer to other
public:
 
   /// Get the record keeper that initialized this Init.
   RecordKeeper &getRecordKeeper() const { return ValueTy->getRecordKeeper(); }
 
   Init *getCastTo(RecTy *Ty) const override;
   Init *convertInitializerTo(RecTy *Ty) const override;
 
   Init *convertInitializerBitRange(ArrayRef<unsigned> Bits) const override;
-  Init *convertInitListSlice(ArrayRef<unsigned> Elements) const override;
 
   /// This method is used to implement the FieldInit class.
   /// Implementors of this method should return the type of the named field if
   /// they are of type record.
   RecTy *getFieldType(StringInit *FieldName) const override;
 };
 
 /// '?' - Represents an uninitialized value.
Init *getElement(unsigned i) const {
     return getTrailingObjects<Init *>()[i];
   }
   RecTy *getElementType() const {
     return cast<ListRecTy>(getType())->getElementType();
   }
 
   Record *getElementAsRecord(unsigned i) const;
 
-  Init *convertInitListSlice(ArrayRef<unsigned> Elements) const override;
-
   Init *convertInitializerTo(RecTy *Ty) const override;
 
   /// This method is used by classes that refer to other
   /// variables which may not be defined at the time they expression is formed.
   /// If a value is set for the variable later, this method will be called on
   /// users of the value to allow the value to propagate out.
   ///
   Init *resolveReferences(Resolver &R) const override;
enum BinaryOp : uint8_t {
     OR,
     XOR,
     SHL,
     SRA,
     SRL,
     LISTCONCAT,
     LISTSPLAT,
     LISTREMOVE,
+    LISTELEM,
+    LISTSLICE,
+    RANGE,
+    RANGEC,
     STRCONCAT,
     INTERLEAVE,
     CONCAT,
     EQ,
     NE,
     LE,
     LT,
     GE,
public:
   Init *resolveReferences(Resolver &R) const override;
 
   Init *getBit(unsigned B) const override {
     assert(B < 1 && "Bit index out of range!");
     return const_cast<VarBitInit*>(this);
   }
 };
 
-/// List[4] - Represent access to one element of a var or
-/// field.
-class VarListElementInit : public TypedInit {
-  TypedInit *TI;
-  unsigned Element;
-
-  VarListElementInit(TypedInit *T, unsigned E)
-      : TypedInit(IK_VarListElementInit,
-                  cast<ListRecTy>(T->getType())->getElementType()),
-        TI(T), Element(E) {
-    assert(T->getType() && isa<ListRecTy>(T->getType()) &&
-           "Illegal VarBitInit expression!");
-  }
-
-public:
-  VarListElementInit(const VarListElementInit &) = delete;
-  VarListElementInit &operator=(const VarListElementInit &) = delete;
-
-  static bool classof(const Init *I) {
-    return I->getKind() == IK_VarListElementInit;
-  }
-
-  static VarListElementInit *get(TypedInit *T, unsigned E);
-
-  TypedInit *getVariable() const { return TI; }
-  unsigned getElementNum() const { return Element; }
-
-  std::string getAsString() const override;
-  Init *resolveReferences(Resolver &R) const override;
-
-  Init *getBit(unsigned Bit) const override;
-};
-
 /// AL - Represent a reference to a 'def' in the description
 class DefInit : public TypedInit {
   friend class Record;
 
   Record *Def;
 
   explicit DefInit(Record *D);
 

llvm/lib/IR/Function.cpp

 //===- Function.cpp - Implement the Global object classes -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 std::string Intrinsic::getNameNoUnnamedTypes(ID Id, ArrayRef<Type *> Tys) {
   return getIntrinsicNameImpl(Id, Tys, nullptr, nullptr, false);
 }
 
 /// IIT_Info - These are enumerators that describe the entries returned by the
 /// getIntrinsicInfoTableEntries function.
 ///
-/// NOTE: This must be kept in synch with the copy in TblGen/IntrinsicEmitter!
+/// Defined in Intrinsics.td.
 enum IIT_Info {
-  // Common values should be encoded with 0-15.
-  IIT_Done = 0,
-  IIT_I1 = 1,
-  IIT_I8 = 2,
-  IIT_I16 = 3,
-  IIT_I32 = 4,
-  IIT_I64 = 5,
-  IIT_F16 = 6,
-  IIT_F32 = 7,
-  IIT_F64 = 8,
-  IIT_V2 = 9,
-  IIT_V4 = 10,
-  IIT_V8 = 11,
-  IIT_V16 = 12,
-  IIT_V32 = 13,
-  IIT_PTR = 14,
-  IIT_ARG = 15,
-
-  // Values from 16+ are only encodable with the inefficient encoding.
-  IIT_V64 = 16,
-  IIT_MMX = 17,
-  IIT_TOKEN = 18,
-  IIT_METADATA = 19,
-  IIT_EMPTYSTRUCT = 20,
-  IIT_STRUCT2 = 21,
-  IIT_STRUCT3 = 22,
-  IIT_STRUCT4 = 23,
-  IIT_STRUCT5 = 24,
-  IIT_EXTEND_ARG = 25,
-  IIT_TRUNC_ARG = 26,
-  IIT_ANYPTR = 27,
-  IIT_V1 = 28,
-  IIT_VARARG = 29,
-  IIT_HALF_VEC_ARG = 30,
-  IIT_SAME_VEC_WIDTH_ARG = 31,
-  IIT_PTR_TO_ARG = 32,
-  IIT_PTR_TO_ELT = 33,
-  IIT_VEC_OF_ANYPTRS_TO_ELT = 34,
-  IIT_I128 = 35,
-  IIT_V512 = 36,
-  IIT_V1024 = 37,
-  IIT_STRUCT6 = 38,
-  IIT_STRUCT7 = 39,
-  IIT_STRUCT8 = 40,
-  IIT_F128 = 41,
-  IIT_VEC_ELEMENT = 42,
-  IIT_SCALABLE_VEC = 43,
-  IIT_SUBDIVIDE2_ARG = 44,
-  IIT_SUBDIVIDE4_ARG = 45,
-  IIT_VEC_OF_BITCASTS_TO_INT = 46,
-  IIT_V128 = 47,
-  IIT_BF16 = 48,
-  IIT_STRUCT9 = 49,
-  IIT_V256 = 50,
-  IIT_AMX = 51,
-  IIT_PPCF128 = 52,
-  IIT_V3 = 53,
-  IIT_EXTERNREF = 54,
-  IIT_FUNCREF = 55,
-  IIT_ANYPTR_TO_ELT = 56,
-  IIT_I2 = 57,
-  IIT_I4 = 58,
+#define GET_INTRINSIC_IITINFO
+#include "llvm/IR/IntrinsicImpl.inc"
+#undef GET_INTRINSIC_IITINFO
 };
 
 static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
                       IIT_Info LastInfo,
                       SmallVectorImpl<Intrinsic::IITDescriptor> &OutputTable) {
   using namespace Intrinsic;
 
   bool IsScalableVector = (LastInfo == IIT_SCALABLE_VEC);

llvm/lib/TableGen/Record.cpp

 //===- Record.cpp - Record implementation ---------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
struct RecordKeeperImpl {
   FoldingSet<UnOpInit> TheUnOpInitPool;
   FoldingSet<BinOpInit> TheBinOpInitPool;
   FoldingSet<TernOpInit> TheTernOpInitPool;
   FoldingSet<FoldOpInit> TheFoldOpInitPool;
   FoldingSet<IsAOpInit> TheIsAOpInitPool;
   FoldingSet<ExistsOpInit> TheExistsOpInitPool;
   DenseMap<std::pair<RecTy *, Init *>, VarInit *> TheVarInitPool;
   DenseMap<std::pair<TypedInit *, unsigned>, VarBitInit *> TheVarBitInitPool;
-  DenseMap<std::pair<TypedInit *, unsigned>, VarListElementInit *>
-      TheVarListElementInitPool;
   FoldingSet<VarDefInit> TheVarDefInitPool;
   DenseMap<std::pair<Init *, StringInit *>, FieldInit *> TheFieldInitPool;
   FoldingSet<CondOpInit> TheCondOpInitPool;
   FoldingSet<DagInit> TheDagInitPool;
   FoldingSet<RecordRecTy> RecordTypePool;
 
   unsigned AnonCounter;
   unsigned LastRecordID;
if (auto *LRT = dyn_cast<ListRecTy>(Ty)) {
     if (!Changed)
       return const_cast<ListInit*>(this);
     return ListInit::get(Elements, ElementType);
   }
 
   return nullptr;
 }
 
-Init *ListInit::convertInitListSlice(ArrayRef<unsigned> Elements) const {
-  if (Elements.size() == 1) {
-    if (Elements[0] >= size())
-      return nullptr;
-    return getElement(Elements[0]);
-  }
-
-  SmallVector<Init*, 8> Vals;
-  Vals.reserve(Elements.size());
-  for (unsigned Element : Elements) {
-    if (Element >= size())
-      return nullptr;
-    Vals.push_back(getElement(Element));
-  }
-  return ListInit::get(Vals, getElementType());
-}
-
 Record *ListInit::getElementAsRecord(unsigned i) const {
   assert(i < NumValues && "List element index out of range!");
   DefInit *DI = dyn_cast<DefInit>(getElement(i));
   if (!DI)
     PrintFatalError("Expected record in list!");
   return DI->getDef();
 }
 
if (LHSs && RHSs) {
         }
         if (!Found)
           Args.push_back(EltLHS);
       }
       return ListInit::get(Args, LHSs->getElementType());
     }
     break;
   }
+  case LISTELEM: {
+    auto *TheList = dyn_cast<ListInit>(LHS);
+    auto *Idx = dyn_cast<IntInit>(RHS);
+    if (TheList && Idx) {
+      auto i = Idx->getValue();
+      if (0 <= i && i < (ssize_t)TheList->size())
+        return TheList->getElement(i);
+    }
+    break;
+  }
+  case LISTSLICE: {
+    auto *TheList = dyn_cast<ListInit>(LHS);
+    auto *SliceIdxs = dyn_cast<ListInit>(RHS);
+    if (TheList && SliceIdxs) {
+      SmallVector<Init *, 8> Args;
+      Args.reserve(SliceIdxs->size());
+      for (auto *I : *SliceIdxs) {
+        auto *II = dyn_cast<IntInit>(I);
+        if (!II)
+          goto listslice_fail;
+        auto i = II->getValue();
+        if (!(0 <= i && i < (ssize_t)TheList->size()))
+          goto listslice_fail;
+        Args.push_back(TheList->getElement(i));
+      }
+      return ListInit::get(Args, TheList->getElementType());
+    }
+  listslice_fail:
+    break;
+  }
+  case RANGE:
+  case RANGEC: {
+    auto *LHSi = dyn_cast<IntInit>(LHS);
+    auto *RHSi = dyn_cast<IntInit>(RHS);
+    if (LHSi && RHSi) {
+      auto Start = LHSi->getValue();
+      auto End = RHSi->getValue();
+      SmallVector<Init *, 8> Args;
+      if (getOpcode() == RANGEC) {
+        // Closed interval
+        if (Start <= End) {
+          // Ascending order
+          Args.reserve(End - Start + 1);
+          for (auto i = Start; i <= End; ++i)
+            Args.push_back(IntInit::get(getRecordKeeper(), i));
+        } else {
+          // Descending order
+          Args.reserve(Start - End + 1);
+          for (auto i = Start; i >= End; --i)
+            Args.push_back(IntInit::get(getRecordKeeper(), i));
+        }
+      } else if (Start < End) {
+        // Half-open interval (excludes `End`)
+        Args.reserve(End - Start);
+        for (auto i = Start; i < End; ++i)
+          Args.push_back(IntInit::get(getRecordKeeper(), i));
+      } else {
+        // Empty set
+      }
+      return ListInit::get(Args, LHSi->getType());
+    }
+    break;
+  }
   case STRCONCAT: {
     StringInit *LHSs = dyn_cast<StringInit>(LHS);
     StringInit *RHSs = dyn_cast<StringInit>(RHS);
     if (LHSs && RHSs)
       return ConcatStringInits(LHSs, RHSs);
     break;
   }
   case INTERLEAVE: {
if (LHS != lhs || RHS != rhs)
     return (BinOpInit::get(getOpcode(), lhs, rhs, getType()))
         ->Fold(R.getCurrentRecord());
   return const_cast<BinOpInit *>(this);
 }
 
 std::string BinOpInit::getAsString() const {
   std::string Result;
   switch (getOpcode()) {
+  case LISTELEM:
+  case LISTSLICE:
+    return LHS->getAsString() + "[" + RHS->getAsString() + "]";
+  case RANGEC:
+    return LHS->getAsString() + "..." + RHS->getAsString();
   case CONCAT: Result = "!con"; break;
   case ADD: Result = "!add"; break;
   case SUB: Result = "!sub"; break;
   case MUL: Result = "!mul"; break;
   case DIV: Result = "!div"; break;
   case AND: Result = "!and"; break;
   case OR: Result = "!or"; break;
   case XOR: Result = "!xor"; break;
   case SHL: Result = "!shl"; break;
   case SRA: Result = "!sra"; break;
   case SRL: Result = "!srl"; break;
   case EQ: Result = "!eq"; break;
   case NE: Result = "!ne"; break;
   case LE: Result = "!le"; break;
   case LT: Result = "!lt"; break;
   case GE: Result = "!ge"; break;
   case GT: Result = "!gt"; break;
   case LISTCONCAT: Result = "!listconcat"; break;
   case LISTSPLAT: Result = "!listsplat"; break;
   case LISTREMOVE: Result = "!listremove"; break;
+  case RANGE: Result = "!range"; break;
   case STRCONCAT: Result = "!strconcat"; break;
   case INTERLEAVE: Result = "!interleave"; break;
   case SETDAGOP: Result = "!setdagop"; break;
   }
   return Result + "(" + LHS->getAsString() + ", " + RHS->getAsString() + ")";
 }
 
 static void
Init *TypedInit::getCastTo(RecTy *Ty) const {
 
   if (!getType()->typeIsConvertibleTo(Ty))
     return nullptr;
 
   return UnOpInit::get(UnOpInit::CAST, const_cast<TypedInit *>(this), Ty)
       ->Fold(nullptr);
 }
 
-Init *TypedInit::convertInitListSlice(ArrayRef<unsigned> Elements) const {
-  ListRecTy *T = dyn_cast<ListRecTy>(getType());
-  if (!T) return nullptr;  // Cannot subscript a non-list variable.
-
-  if (Elements.size() == 1)
-    return VarListElementInit::get(const_cast<TypedInit *>(this), Elements[0]);
-
-  SmallVector<Init*, 8> ListInits;
-  ListInits.reserve(Elements.size());
-  for (unsigned Element : Elements)
-    ListInits.push_back(VarListElementInit::get(const_cast<TypedInit *>(this),
-                                                Element));
-  return ListInit::get(ListInits, T->getElementType());
-}
-
-
 VarInit *VarInit::get(StringRef VN, RecTy *T) {
   Init *Value = StringInit::get(T->getRecordKeeper(), VN);
   return VarInit::get(Value, T);
 }
 
 VarInit *VarInit::get(Init *VN, RecTy *T) {
   detail::RecordKeeperImpl &RK = T->getRecordKeeper().getImpl();
   VarInit *&I = RK.TheVarInitPool[std::make_pair(T, VN)];

 Init *VarBitInit::resolveReferences(Resolver &R) const {
   Init *I = TI->resolveReferences(R);
   if (TI != I)
     return I->getBit(getBitNum());
 
   return const_cast<VarBitInit*>(this);
 }
 
-VarListElementInit *VarListElementInit::get(TypedInit *T, unsigned E) {
-  detail::RecordKeeperImpl &RK = T->getRecordKeeper().getImpl();
-  VarListElementInit *&I = RK.TheVarListElementInitPool[std::make_pair(T, E)];
-  if (!I)
-    I = new (RK.Allocator) VarListElementInit(T, E);
-  return I;
-}
-
-std::string VarListElementInit::getAsString() const {
-  return TI->getAsString() + "[" + utostr(Element) + "]";
-}
-
-Init *VarListElementInit::resolveReferences(Resolver &R) const {
-  Init *NewTI = TI->resolveReferences(R);
-  if (ListInit *List = dyn_cast<ListInit>(NewTI)) {
-    // Leave out-of-bounds array references as-is. This can happen without
-    // being an error, e.g. in the untaken "branch" of an !if expression.
-    if (getElementNum() < List->size())
-      return List->getElement(getElementNum());
-  }
-  if (NewTI != TI && isa<TypedInit>(NewTI))
-    return VarListElementInit::get(cast<TypedInit>(NewTI), getElementNum());
-  return const_cast<VarListElementInit *>(this);
-}
-
-Init *VarListElementInit::getBit(unsigned Bit) const {
-  if (getType() == BitRecTy::get(getRecordKeeper()))
-    return const_cast<VarListElementInit*>(this);
-  return VarBitInit::get(const_cast<VarListElementInit*>(this), Bit);
-}
-
 DefInit::DefInit(Record *D)
     : TypedInit(IK_DefInit, D->getType()), Def(D) {}
 
 DefInit *DefInit::get(Record *R) {
   return R->getDefInit();
 }
 
 Init *DefInit::convertInitializerTo(RecTy *Ty) const {
std::vector<Record *> RecordKeeper::getAllDerivedDefinitions(
 
   for (const auto &OneDef : getDefs()) {
     if (all_of(ClassRecs, [&OneDef](const Record *Class) {
                             return OneDef.second->isSubClassOf(Class);
                           }))
       Defs.push_back(OneDef.second.get());
   }
 
+  llvm::sort(Defs, [](Record *LHS, Record *RHS) {
+    return LHS->getName().compare_numeric(RHS->getName()) < 0;
+  });
+
   return Defs;
 }
 
 std::vector<Record *>
 RecordKeeper::getAllDerivedDefinitionsIfDefined(StringRef ClassName) const {
   return getClass(ClassName) ? getAllDerivedDefinitions(ClassName)
                              : std::vector<Record *>();
 }

llvm/lib/TableGen/TGLexer.h

 //===- TGLexer.h - Lexer for TableGen Files ---------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
// existing 'Else' that means the preprocessor #else.)
     FalseKW, Field, Foreach, If, In, Include, Int, Let, List, MultiClass,
     String, Then, TrueKW,
 
   // Bang operators.
     XConcat, XADD, XSUB, XMUL, XDIV, XNOT, XLOG2, XAND, XOR, XXOR, XSRA, XSRL,
     XSHL, XListConcat, XListSplat, XStrConcat, XInterleave, XSubstr, XFind,
     XCast, XSubst, XForEach, XFilter, XFoldl, XHead, XTail, XSize, XEmpty, XIf,
     XCond, XEq, XIsA, XDag, XNe, XLe, XLt, XGe, XGt, XSetDagOp, XGetDagOp,
-    XExists, XListRemove,  XToLower, XToUpper,
+    XExists, XListRemove, XToLower, XToUpper, XRange,
 
   // Boolean literals.
     TrueVal, FalseVal,
 
   // Integer value.
   IntVal,
 
   // Binary constant.  Note that these are sized according to the number of

llvm/lib/TableGen/TGLexer.cpp

 //===- TGLexer.cpp - Lexer for TableGen -----------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
tgtok::TokKind Kind =
           .Case("empty", tgtok::XEmpty)
           .Case("subst", tgtok::XSubst)
           .Case("foldl", tgtok::XFoldl)
           .Case("foreach", tgtok::XForEach)
           .Case("filter", tgtok::XFilter)
           .Case("listconcat", tgtok::XListConcat)
           .Case("listsplat", tgtok::XListSplat)
           .Case("listremove", tgtok::XListRemove)
+          .Case("range", tgtok::XRange)
           .Case("strconcat", tgtok::XStrConcat)
           .Case("interleave", tgtok::XInterleave)
           .Case("substr", tgtok::XSubstr)
           .Case("find", tgtok::XFind)
           .Cases("setdagop", "setop", tgtok::XSetDagOp) // !setop is deprecated.
           .Cases("getdagop", "getop", tgtok::XGetDagOp) // !getop is deprecated.
           .Case("exists", tgtok::XExists)
           .Case("tolower", tgtok::XToLower)

llvm/lib/TableGen/TGParser.h

 //===- TGParser.h - Parser for TableGen Files -------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void ParseValueList(SmallVectorImpl<llvm::Init*> &Result,
                       Record *CurRec, RecTy *ItemType = nullptr);
   bool ParseTemplateArgValueList(SmallVectorImpl<llvm::Init *> &Result,
                                  Record *CurRec, Record *ArgsRec);
   void ParseDagArgList(
       SmallVectorImpl<std::pair<llvm::Init*, StringInit*>> &Result,
       Record *CurRec);
   bool ParseOptionalRangeList(SmallVectorImpl<unsigned> &Ranges);
   bool ParseOptionalBitList(SmallVectorImpl<unsigned> &Ranges);
+  TypedInit *ParseSliceElements(Record *CurRec, bool Single = false);
   void ParseRangeList(SmallVectorImpl<unsigned> &Result);
   bool ParseRangePiece(SmallVectorImpl<unsigned> &Ranges,
                        TypedInit *FirstItem = nullptr);
   RecTy *ParseType();
   Init *ParseOperation(Record *CurRec, RecTy *ItemType);
   Init *ParseOperationSubstr(Record *CurRec, RecTy *ItemType);
   Init *ParseOperationFind(Record *CurRec, RecTy *ItemType);
   Init *ParseOperationForEachFilter(Record *CurRec, RecTy *ItemType);

llvm/lib/TableGen/TGParser.cpp

 //===- TGParser.cpp - Parser for TableGen Files ---------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (ParseTemplateArgValueList(Result.TemplateArgs, &CurMC->Rec,
     return Result;
   }
 
   Result.RefRange.End = Lex.getLoc();
 
   return Result;
 }
 
+/// ParseSliceElements - Parse subscripts in square brackets.
+///
+///  SliceElements ::= ( SliceElement ',' )* SliceElement ','?
+///  SliceElement  ::= Value<list<int>>
+///  SliceElement  ::= Value<int>
+///  SliceElement  ::= Value<int> '...' Value<int>
+///  SliceElement  ::= Value<int> '-' Value<int> (deprecated)
+///  SliceElement  ::= Value<int> INTVAL(Negative; deprecated)
+///
+/// Returns ListRecTy by defaut.
+/// Returns IntRecTy if;
+///  - Single=true
+///  - SliceElements is Value<int> w/o trailing comma
+///
+TypedInit *TGParser::ParseSliceElements(Record *CurRec, bool Single) {
+  TypedInit *CurVal = nullptr;
+  SmallVector<Init *, 2> LoV;      // int
+  SmallVector<TypedInit *, 2> LoL; // list<int>
+  auto *IntTy = IntRecTy::get(Records);
+
+  auto FlushLoV = [&] {
+    if (!LoV.empty()) {
+      LoL.push_back(ListInit::get(LoV, IntTy));
+      LoV.clear();
+    }
+    Single = false;
+  };
+
+  do {
+    if (CurVal)
+      LoV.push_back(CurVal);
+
+    auto LHSLoc = Lex.getLoc();
+    auto *LHS = ParseValue(CurRec);
+    if (!LHS)
+      return nullptr;
+    CurVal = cast<TypedInit>(LHS);
+
+    TypedInit *RHS = nullptr;
+    switch (Lex.getCode()) {
+    case tgtok::dotdotdot:
+    case tgtok::minus: { // Deprecated
+      Lex.Lex();         // eat
+      auto RHSLoc = Lex.getLoc();
+      RHS = cast<TypedInit>(ParseValue(CurRec));
+      if (!isa<IntRecTy>(RHS->getType())) {
+        Error(RHSLoc, "expected int...int, got " +
+                          Twine(RHS->getType()->getAsString()));
+        return nullptr;
+      }
+      break;
+    }
+    case tgtok::IntVal: { // Deprecated "-num"
+      auto *RHSi = IntInit::get(Records, -Lex.getCurIntVal());
+      if (RHSi->getValue() < 0) {
+        TokError("invalid range, cannot be negative");
+        return nullptr;
+      }
+      RHS = RHSi;
+      Lex.Lex(); // eat IntVal
+      break;
+    }
+    default:
+      break;
+    }
+
+    if (RHS) {
+      // Closed-interval range <CurVal:IntRecTy>...<RHS:IntRecTy>
+      if (!isa<IntRecTy>(CurVal->getType())) {
+        Error(LHSLoc, "expected int...int, got " +
+                          Twine(CurVal->getType()->getAsString()));
+        return nullptr;
+      }
+
+      FlushLoV();
+      LoL.push_back(cast<TypedInit>(
+          BinOpInit::get(BinOpInit::RANGEC, CurVal, RHS, IntTy->getListTy())
+              ->Fold(CurRec)));
+      CurVal = nullptr;
+    } else {
+      // Single value (not a range)
+      if (auto *LHSTy = dyn_cast<ListRecTy>(CurVal->getType())) {
+        // list<int>
+        if (!isa<IntRecTy>(LHSTy->getElementType())) {
+          Error(LHSLoc,
+                "expected list<int>, got " + Twine(LHSTy->getAsString()));
+          return nullptr;
+        }
+        FlushLoV();
+        LoL.push_back(CurVal);
+        CurVal = nullptr;
+      } else if (isa<IntRecTy>(CurVal->getType())) {
+        // int -- `CurVal` will be added lazily.
+      } else {
+        Error(LHSLoc, "unhandled type in range");
+        return nullptr;
+      }
+    }
+
+    if (Lex.getCode() != tgtok::comma)
+      break;
+
+    Lex.Lex(); // eat comma
+    Single = false;
+  } while (Lex.getCode() != tgtok::r_square);
+
+  if (CurVal) {
+    if (Single)
+      return CurVal;
+
+    LoV.push_back(CurVal);
+  }
+
+  FlushLoV();
+
+  TypedInit *Result = nullptr;
+  for (auto *LE : LoL) {
+    Result =
+        (Result ? cast<TypedInit>(BinOpInit::getListConcat(Result, LE)) : LE);
+  }
+
+  return Result;
+}
+
 /// ParseRangePiece - Parse a bit/value range.
 ///   RangePiece ::= INTVAL
 ///   RangePiece ::= INTVAL '...' INTVAL
 ///   RangePiece ::= INTVAL '-' INTVAL
 ///   RangePiece ::= INTVAL INTVAL 
 // The last two forms are deprecated.
 bool TGParser::ParseRangePiece(SmallVectorImpl<unsigned> &Ranges,
                                TypedInit *FirstItem) {
Init *TGParser::ParseOperation(Record *CurRec, RecTy *ItemType) {
   case tgtok::XNe:
   case tgtok::XLe:
   case tgtok::XLt:
   case tgtok::XGe:
   case tgtok::XGt:
   case tgtok::XListConcat:
   case tgtok::XListSplat:
   case tgtok::XListRemove:
+  case tgtok::XRange:
   case tgtok::XStrConcat:
   case tgtok::XInterleave:
   case tgtok::XSetDagOp: { // Value ::= !binop '(' Value ',' Value ')'
     tgtok::TokKind OpTok = Lex.getCode();
     SMLoc OpLoc = Lex.getLoc();
     Lex.Lex();  // eat the operation
 
     BinOpInit::BinaryOp Code;
case tgtok::XSetDagOp: { // Value ::= !binop '(' Value ',' Value ')'
     case tgtok::XNe:     Code = BinOpInit::NE; break;
     case tgtok::XLe:     Code = BinOpInit::LE; break;
     case tgtok::XLt:     Code = BinOpInit::LT; break;
     case tgtok::XGe:     Code = BinOpInit::GE; break;
     case tgtok::XGt:     Code = BinOpInit::GT; break;
     case tgtok::XListConcat: Code = BinOpInit::LISTCONCAT; break;
     case tgtok::XListSplat:  Code = BinOpInit::LISTSPLAT; break;
     case tgtok::XListRemove: Code = BinOpInit::LISTREMOVE; break;
+    case tgtok::XRange:      Code = BinOpInit::RANGE; break;
     case tgtok::XStrConcat:  Code = BinOpInit::STRCONCAT; break;
     case tgtok::XInterleave: Code = BinOpInit::INTERLEAVE; break;
     case tgtok::XSetDagOp:   Code = BinOpInit::SETDAGOP; break;
     }
 
     RecTy *Type = nullptr;
     RecTy *ArgType = nullptr;
     switch (OpTok) {
case tgtok::XListConcat:
       break;
     case tgtok::XListSplat:
       // Can't do any typechecking until we parse the first argument.
       break;
     case tgtok::XListRemove:
       // We don't know the list type until we parse the first argument.
       ArgType = ItemType;
       break;
+    case tgtok::XRange:
+      Type = IntRecTy::get(Records)->getListTy();
+      // ArgType may be either Int or List.
+      break;
     case tgtok::XStrConcat:
       Type = StringRecTy::get(Records);
       ArgType = StringRecTy::get(Records);
       break;
     case tgtok::XInterleave:
       Type = StringRecTy::get(Records);
       // The first argument type is not yet known.
     }
for (;;) {
           break;
         case BinOpInit::LISTREMOVE:
           if (!isa<ListRecTy>(ArgType)) {
             Error(InitLoc, Twine("expected a list, got value of type '") +
                                ArgType->getAsString() + "'");
             return nullptr;
           }
           break;
+        case BinOpInit::RANGE:
+          if (InitList.size() == 1) {
+            if (isa<ListRecTy>(ArgType)) {
+              ArgType = nullptr; // Detect error if 2nd arg were present.
+            } else if (isa<IntRecTy>(ArgType)) {
+              // Assume 2nd arg should be IntRecTy
+            } else {
+              Error(InitLoc,
+                    Twine("expected list or int, got value of type '") +
+                        ArgType->getAsString() + "'");
+              return nullptr;
+            }
+          } else {
+            // Don't come here unless 1st arg is ListRecTy.
+            assert(isa<ListRecTy>(cast<TypedInit>(InitList[0])->getType()));
+            Error(InitLoc,
+                  Twine("expected one list, got extra value of type '") +
+                      ArgType->getAsString() + "'");
+            return nullptr;
+          }
+          break;
         case BinOpInit::EQ:
         case BinOpInit::NE:
           if (!ArgType->typeIsConvertibleTo(IntRecTy::get(Records)) &&
               !ArgType->typeIsConvertibleTo(StringRecTy::get(Records)) &&
               !ArgType->typeIsConvertibleTo(RecordRecTy::get(Records, {}))) {
             Error(InitLoc, Twine("expected bit, bits, int, string, or record; "
                                  "got value of type '") + ArgType->getAsString() + 
                                  "'");
if (Code == BinOpInit::LISTCONCAT)
       Type = ArgType;
     // listsplat returns a list of type of the *first* argument.
     if (Code == BinOpInit::LISTSPLAT)
       Type = cast<TypedInit>(InitList.front())->getType()->getListTy();
     // listremove returns a list with type of the argument.
     if (Code == BinOpInit::LISTREMOVE)
       Type = ArgType;
 
+    if (Code == BinOpInit::RANGE) {
+      Init *LHS, *RHS;
+      auto ArgCount = InitList.size();
+      assert(ArgCount >= 1);
+      auto *Arg0 = cast<TypedInit>(InitList[0]);
+      auto *Arg0Ty = Arg0->getType();
+      if (ArgCount == 1) {
+        if (isa<ListRecTy>(Arg0Ty)) {
+          // (0, !size(arg))
+          LHS = IntInit::get(Records, 0);
+          RHS = UnOpInit::get(UnOpInit::SIZE, Arg0, IntRecTy::get(Records))
+                    ->Fold(CurRec);
+        } else {
+          assert(isa<IntRecTy>(Arg0Ty));
+          // (0, arg)
+          LHS = IntInit::get(Records, 0);
+          RHS = Arg0;
+        }
+      } else if (ArgCount == 2) {
+        assert(isa<IntRecTy>(Arg0Ty));
+        assert(isa<IntRecTy>(cast<TypedInit>(InitList[1])->getType()));
+        LHS = Arg0;
+        RHS = InitList[1];
+      } else {
+        Error(OpLoc, "expected at most two values of integer");
+        return nullptr;
+      }
+      return BinOpInit::get(Code, LHS, RHS, Type)->Fold(CurRec);
+    }
+
     // We allow multiple operands to associative operators like !strconcat as
     // shorthand for nesting them.
     if (Code == BinOpInit::STRCONCAT || Code == BinOpInit::LISTCONCAT ||
         Code == BinOpInit::CONCAT || Code == BinOpInit::ADD ||
         Code == BinOpInit::AND || Code == BinOpInit::OR ||
         Code == BinOpInit::XOR || Code == BinOpInit::MUL) {
       while (InitList.size() > 2) {
         Init *RHS = InitList.pop_back_val();

 ///   SimpleValue ::= DIVTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SUBTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SHLTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SRATOK '(' Value ',' Value ')'
 ///   SimpleValue ::= SRLTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= LISTCONCATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= LISTSPLATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= LISTREMOVETOK '(' Value ',' Value ')'
+///   SimpleValue ::= RANGE '(' Value ')'
+///   SimpleValue ::= RANGE '(' Value ',' Value ')'
 ///   SimpleValue ::= STRCONCATTOK '(' Value ',' Value ')'
 ///   SimpleValue ::= COND '(' [Value ':' Value,]+ ')'
 ///
 Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
                                  IDParseMode Mode) {
   Init *R = nullptr;
   switch (Lex.getCode()) {
   default: TokError("Unknown or reserved token when parsing a value"); break;
Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
   case tgtok::XNe:
   case tgtok::XLe:
   case tgtok::XLt:
   case tgtok::XGe:
   case tgtok::XGt:
   case tgtok::XListConcat:
   case tgtok::XListSplat:
   case tgtok::XListRemove:
+  case tgtok::XRange:
   case tgtok::XStrConcat:
   case tgtok::XInterleave:
   case tgtok::XSetDagOp: // Value ::= !binop '(' Value ',' Value ')'
   case tgtok::XIf:
   case tgtok::XCond:
   case tgtok::XFoldl:
   case tgtok::XForEach:
   case tgtok::XFilter:
   case tgtok::XSubst:
   case tgtok::XSubstr:
   case tgtok::XFind: { // Value ::= !ternop '(' Value ',' Value ',' Value ')'
     return ParseOperation(CurRec, ItemType);
   }
   }
 
   return R;
 }
 
 /// ParseValue - Parse a TableGen value. This returns null on error.
 ///
 ///   Value       ::= SimpleValue ValueSuffix*
 ///   ValueSuffix ::= '{' BitList '}'
-///   ValueSuffix ::= '[' BitList ']'
+///   ValueSuffix ::= '[' SliceElements ']'
 ///   ValueSuffix ::= '.' ID
 ///
 Init *TGParser::ParseValue(Record *CurRec, RecTy *ItemType, IDParseMode Mode) {
   Init *Result = ParseSimpleValue(CurRec, ItemType, Mode);
   if (!Result) return nullptr;
 
   // Parse the suffixes now if present.
   while (true) {
case tgtok::l_brace: {
       if (!consume(tgtok::r_brace)) {
         TokError("expected '}' at end of bit range list");
         return nullptr;
       }
       break;
     }
     case tgtok::l_square: {
       SMLoc SquareLoc = Lex.getLoc();
+
+      auto *LHS = dyn_cast<TypedInit>(Result);
+      assert(LHS);
+      auto *LHSTy = dyn_cast<ListRecTy>(LHS->getType());
+      if (!LHSTy) {
+        Error(SquareLoc, "Type '" + Twine(LHS->getType()->getAsString()) +
+                             "' is invalid for list subscript");
+        return nullptr;
+      }
+
       Lex.Lex(); // eat the '['
-      SmallVector<unsigned, 16> Ranges;
-      ParseRangeList(Ranges);
-      if (Ranges.empty()) return nullptr;
+      TypedInit *RHS = ParseSliceElements(CurRec, /*Single=*/true);
+      if (!RHS)
+        return nullptr;
+
+      if (isa<ListRecTy>(RHS->getType())) {
+        Result =
+            BinOpInit::get(BinOpInit::LISTSLICE, LHS, RHS, LHSTy)->Fold(CurRec);
+      } else {
+        Result = BinOpInit::get(BinOpInit::LISTELEM, LHS, RHS,
+                                LHSTy->getElementType())
+                     ->Fold(CurRec);
+      }
 
-      Result = Result->convertInitListSlice(Ranges);
       if (!Result) {
         Error(SquareLoc, "Invalid range for list slice");
         return nullptr;
       }
 
       // Eat the ']'.
       if (!consume(tgtok::r_square)) {
         TokError("expected ']' at end of list slice");

llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir

body:             |
   ; CHECK-NEXT:   $sgpr13 = COPY killed renamable $sgpr33
   ; CHECK-NEXT:   dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr68_sgpr69, 0, csr_amdgpu, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit killed $sgpr12, implicit killed $sgpr13, implicit $sgpr0_sgpr1_sgpr2_sgpr3
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
   ; CHECK-NEXT:   renamable $sgpr4_sgpr5 = COPY $exec, implicit-def $exec
   ; CHECK-NEXT:   dead renamable $sgpr6_sgpr7 = IMPLICIT_DEF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
-  ; CHECK-NEXT:   liveins: $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF, $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F
+  ; CHECK-NEXT:   liveins: $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F, $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $sgpr6_sgpr7 = COPY $exec, implicit-def $exec
   ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.4, implicit $exec
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
-  ; CHECK-NEXT:   liveins: $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF, $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F
+  ; CHECK-NEXT:   liveins: $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F, $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vreg_1024 = COPY renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75
   ; CHECK-NEXT:   renamable $sgpr6 = S_LSHL_B32 renamable $sgpr67, 1, implicit-def dead $scc
   ; CHECK-NEXT:   dead [[COPY]]:vreg_1024 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V32 [[COPY]], 0, killed $sgpr6, 3, implicit-def $m0, implicit $m0, implicit $exec
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
   ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.1(0x40000000)
-  ; CHECK-NEXT:   liveins: $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF, $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F
+  ; CHECK-NEXT:   liveins: $sgpr4_sgpr5, $sgpr66_sgpr67:0x000000000000000F, $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK-NEXT:   renamable $sgpr68 = COPY renamable $sgpr44
   ; CHECK-NEXT:   renamable $sgpr69 = COPY renamable $sgpr44
   ; CHECK-NEXT:   renamable $sgpr70 = COPY renamable $sgpr44
   ; CHECK-NEXT:   renamable $sgpr71 = COPY renamable $sgpr44
   ; CHECK-NEXT:   renamable $sgpr72 = COPY renamable $sgpr44
   ; CHECK-NEXT:   renamable $sgpr73 = COPY renamable $sgpr44
body:             |
   ; CHECK-NEXT:   renamable $sgpr89 = COPY renamable $sgpr44
   ; CHECK-NEXT:   dead %18:vreg_1024 = COPY renamable $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99, implicit $exec
   ; CHECK-NEXT:   $exec = S_XOR_B64_term $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
   ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.5, implicit $exec
   ; CHECK-NEXT:   S_BRANCH %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.4:
   ; CHECK-NEXT:   successors: %bb.5(0x80000000)
-  ; CHECK-NEXT:   liveins: $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF, $sgpr6_sgpr7, $sgpr66_sgpr67:0x0000000000000003
+  ; CHECK-NEXT:   liveins: $sgpr6_sgpr7, $sgpr66_sgpr67:0x0000000000000003, $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75:0x000003FFFFFFFFFF
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
   ; CHECK-NEXT:   dead renamable $sgpr4 = S_LSHL_B32 killed renamable $sgpr66, 1, implicit-def dead $scc
   ; CHECK-NEXT:   dead %16:vreg_1024 = COPY renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.5:
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15

llvm/test/CodeGen/AMDGPU/ipra-regmask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
 ; Make sure the expected regmask is generated for sub/superregisters.
 
-; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr0_vgpr1 $vgpr0_vgpr1_vgpr2 {{$}}
+; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1 $vgpr0_vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 {{$}}
 define void @csr() #0 {
   call void asm sideeffect "", "~{v0},~{v44},~{v45}"() #0
   ret void
 }
 
-; CHECK-DAG: subregs_for_super Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}}
+; CHECK-DAG: subregs_for_super Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 {{$}}
 define void @subregs_for_super() #0 {
   call void asm sideeffect "", "~{v0},~{v1}"() #0
   ret void
 }
 
-; CHECK-DAG: clobbered_reg_with_sub Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}}
+; CHECK-DAG: clobbered_reg_with_sub Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 {{$}}
 define void @clobbered_reg_with_sub() #0 {
   call void asm sideeffect "", "~{v[0:1]}"() #0
   ret void
 }
 
 ; CHECK-DAG: nothing Clobbered Registers: {{$}}
 define void @nothing() #0 {
   ret void

llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+enable-flat-scratch -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name: partial_spill_v128_1_of_4
 tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, size: 16, alignment: 4 }
 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr24_agpr25_agpr26_agpr27, $agpr28_agpr29, $agpr30
 
     ; GCN-LABEL: name: partial_spill_v128_1_of_4
-    ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr28_agpr29, $vgpr0_vgpr1_vgpr2_vgpr3
+    ; GCN: liveins: $agpr30, $agpr31, $agpr28_agpr29, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s96) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28_agpr29, implicit $agpr30
     SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
     $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)
     S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28_agpr29, implicit $agpr30
 ...
 
 ---
 name: partial_spill_v128_2_of_4
 tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, size: 16, alignment: 4 }
 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr24_agpr25_agpr26_agpr27, $agpr28_agpr29
 
     ; GCN-LABEL: name: partial_spill_v128_2_of_4
-    ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr28_agpr29, $vgpr0_vgpr1_vgpr2_vgpr3
+    ; GCN: liveins: $agpr30, $agpr31, $agpr28_agpr29, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr30, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s64) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28_agpr29

 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr52_vgpr53, $vgpr54
 
     ; GCN-LABEL: name: partial_spill_a128_1_of_4
-    ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr52_vgpr53
+    ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr52_vgpr53, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s96) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3 :: (load (s96) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52_vgpr53, implicit $vgpr54
     SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
     $agpr0_agpr1_agpr2_agpr3 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)
     S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52_vgpr53, implicit $vgpr54
 ...
 
 ---
 name: partial_spill_a128_2_of_4
 tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, size: 16, alignment: 4 }
 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr52_vgpr53
 
     ; GCN-LABEL: name: partial_spill_a128_2_of_4
-    ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr52_vgpr53
+    ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr52_vgpr53, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s64) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3
     ; GCN-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3 :: (load (s64) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52_vgpr53

llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir

body:             |
   ; VR-NEXT:   renamable $sgpr37 = S_MOV_B32 -1
   ; VR-NEXT:   renamable $sgpr36 = S_MOV_B32 -1
   ; VR-NEXT:   renamable $sgpr68 = S_MOV_B32 0
   ; VR-NEXT:   renamable $sgpr30_sgpr31 = IMPLICIT_DEF
   ; VR-NEXT:   renamable $sgpr34_sgpr35 = IMPLICIT_DEF
   ; VR-NEXT: {{  $}}
   ; VR-NEXT: bb.1:
   ; VR-NEXT:   successors: %bb.2(0x80000000)
-  ; VR-NEXT:   liveins: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x000000000000000F, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x0000000000000003, $sgpr30_sgpr31, $sgpr34_sgpr35
+  ; VR-NEXT:   liveins: $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x000000000000000F, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x0000000000000003
   ; VR-NEXT: {{  $}}
   ; VR-NEXT:   renamable $sgpr38 = COPY renamable $sgpr36
   ; VR-NEXT:   renamable $sgpr39 = COPY renamable $sgpr37
   ; VR-NEXT:   renamable $sgpr40 = COPY renamable $sgpr36
   ; VR-NEXT:   renamable $sgpr41 = COPY renamable $sgpr37
   ; VR-NEXT:   renamable $sgpr42 = COPY renamable $sgpr36
   ; VR-NEXT:   renamable $sgpr43 = COPY renamable $sgpr37
   ; VR-NEXT:   renamable $sgpr44 = COPY renamable $sgpr36
body:             |
   ; VR-NEXT:   renamable $sgpr95 = COPY renamable $sgpr68
   ; VR-NEXT:   renamable $sgpr96 = COPY renamable $sgpr68
   ; VR-NEXT:   renamable $sgpr97 = COPY renamable $sgpr68
   ; VR-NEXT:   renamable $sgpr98 = COPY renamable $sgpr68
   ; VR-NEXT:   renamable $sgpr99 = COPY renamable $sgpr68
   ; VR-NEXT: {{  $}}
   ; VR-NEXT: bb.2:
   ; VR-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; VR-NEXT:   liveins: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x000000000000000F, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x0000000000000003, $sgpr30_sgpr31, $sgpr34_sgpr35
+  ; VR-NEXT:   liveins: $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67:0x000000000000000F, $sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95_sgpr96_sgpr97_sgpr98_sgpr99:0x0000000000000003
   ; VR-NEXT: {{  $}}
   ; VR-NEXT:   S_NOP 0, csr_amdgpu, implicit renamable $sgpr30_sgpr31, implicit renamable $sgpr34_sgpr35
   ; VR-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
   ; VR-NEXT:   S_BRANCH %bb.2
   bb.0:
     %0:sreg_64 = IMPLICIT_DEF
     %1:sreg_64 = IMPLICIT_DEF
     undef %2.sub1:sgpr_1024 = S_MOV_B32 -1

llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir

 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $agpr31, $vgpr0_vgpr1_vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr24_agpr25
 
     ; GCN-LABEL: name: partial_spill_v128_restore_to_a128_1_of_4
-    ; GCN: liveins: $agpr30, $agpr31, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr24_agpr25, $vgpr0_vgpr1_vgpr2_vgpr3
+    ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $agpr29 = COPY $agpr30, implicit-def $agpr26_agpr27_agpr28_agpr29
     ; GCN-NEXT: $agpr26_agpr27_agpr28 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29 :: (load (s96) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25
     SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
     $agpr26_agpr27_agpr28_agpr29 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5)
     S_ENDPGM 0, implicit $agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25
 ...
 
 ---
 name: partial_spill_v128_restore_to_a128_2_of_4
 tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, size: 16, alignment: 4 }
 machineFunctionInfo:
   hasSpilledVGPRs: true
   stackPtrOffsetReg: '$sgpr32'
 body:             |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr24_agpr25
 
     ; GCN-LABEL: name: partial_spill_v128_restore_to_a128_2_of_4
-    ; GCN: liveins: $agpr30, $agpr31, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr24_agpr25, $vgpr0_vgpr1_vgpr2_vgpr3
+    ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3
     ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: $agpr29 = COPY $agpr30, implicit-def $agpr26_agpr27_agpr28_agpr29
     ; GCN-NEXT: $agpr28 = COPY $agpr31, implicit $agpr26_agpr27_agpr28_agpr29
     ; GCN-NEXT: $agpr26_agpr27 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29 :: (load (s64) from %stack.0, align 4, addrspace 5)
     ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25

llvm/test/TableGen/ListSlices-fail.td

+// Each RUN line is scattered.
+
+defvar list_int = [0, 1, 2, 3, 4, 5];
+defvar list_str = ["foo", "bar"];
+defvar str = "hoge";
+
+#ifdef ERR0
+// RUN: not llvm-tblgen %s -DERR0 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR0
+// ERR0: [[FILE]]:[[@LINE+1]]:24: error: Unknown or reserved token when parsing a value
+defvar errs = list_str[];
+#endif
+
+#ifdef ERR1
+// RUN: not llvm-tblgen %s -DERR1 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR1
+// ERR1: [[FILE]]:[[@LINE+1]]:24: error: Unknown or reserved token when parsing a value
+defvar errs = list_str[,];
+#endif
+
+#ifdef ERR2
+// RUN: not llvm-tblgen %s -DERR2 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR2
+// ERR2: [[FILE]]:[[@LINE+1]]:24: error: expected list<int>, got list<string>
+defvar errs = list_str[list_str];
+#endif
+
+#ifdef ERR3
+// RUN: not llvm-tblgen %s -DERR3 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR3
+// ERR3: [[FILE]]:[[@LINE+1]]:24: error: expected int...int, got list<string>
+defvar errs = list_str[list_str...42];
+#endif
+
+#ifdef ERR4
+// RUN: not llvm-tblgen %s -DERR4 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR4
+// ERR4: [[FILE]]:[[@LINE+1]]:28: error: expected int...int, got list<string>
+defvar errs = list_str[0...list_str];
+#endif
+
+#ifdef ERR5
+// RUN: not llvm-tblgen %s -DERR5 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR5
+// ERR5: [[FILE]]:[[@LINE+1]]:24: error: unhandled type in range
+defvar errs = list_str[str];
+#endif
+
+#ifdef ERR6
+// RUN: not llvm-tblgen %s -DERR6 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR6
+// ERR6: [[FILE]]:[[@LINE+1]]:26: error: invalid range, cannot be negative
+defvar errs = list_str[5 1];
+#endif
+
+#ifdef ERR7
+// RUN: not llvm-tblgen %s -DERR7 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR7
+// ERR7: [[FILE]]:[[@LINE+1]]:18: error: Type 'string' is invalid for list subscript
+defvar errs = str[0];
+#endif

llvm/test/TableGen/ListSlices.td

 // CHECK-NEXT:   list<int> TwoFive = [2, 3, ?, 5];
 
 def Rec09 : Class1<[?, ?, 2, 3, ?, 5, ?]>;
 
 def Rec10 {
   int Zero = Class1<[?, ?, 2, 3, ?, 5, ?]>.Zero;
   list<int> TwoFive = Class1<[?, ?, 2, 3, ?, 5, ?]>.TwoFive;
 }
+
+// Test list[list] and list[int]
+// CHECK: def Rec11
+def Rec11 {
+  list<int> s5 = Var1[0...4];
+
+  // list[expr]
+  // CHECK:   list<int> rev = [4, 3, 2, 1, 0];
+  list<int> rev = !foreach(i, s5, Var1[!sub(4, i)]);
+
+  // Slice by list[foreach]
+  // CHECK:   list<int> revf = [4, 3, 2, 1, 0];
+  list<int> revf = Var1[!foreach(i, s5, !sub(4, i))];
+
+  // Simple slice
+  // CHECK:   list<int> rr = [0, 1, 2, 3, 4];
+  list<int> rr  = rev[rev];
+
+  // Trailing comma is acceptable
+  // CHECK:   list<int> rr_ = [0, 1, 2, 3, 4];
+  list<int> rr_ = rev[rev,];
+
+  // Concatenation in slice
+  // CHECK:   list<int> rrr = [1, 2, 4, 3, 2, 1, 0, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 8];
+  list<int> empty = [];
+  list<int> rrr = Var1[1, 2, rev, 3...6, 7, empty, rr, 8];
+
+  // Recognized as slice by the trailing comma
+  // CHECK:   list<list<int>> rl1 = {{\[}}[0], [1], [2], [3], [4]];
+  list<list<int>> rl1 = !foreach(i, rev, rev[i,]);
+
+  // Slice by pair<int,int>
+  // CHECK:   list<list<int>> rll = {{\[}}[0, 4], [1, 3], [2, 2], [3, 1], [4, 0]];
+  list<list<int>> rll = !foreach(i, rev, rev[i, !sub(4, i)]);
+
+  // Slice by dynamic range
+  // CHECK:   list<list<int>> rlr = {{\[}}[4, 3, 2, 1, 0], [3, 2, 1], [2], [1, 2, 3], [0, 1, 2, 3, 4]];
+  list<list<int>> rlr = !foreach(i, s5, rev[i...!sub(4, i)]);
+}

llvm/test/TableGen/RegisterInfoEmitter-regcost-tuple.td

 
 def GPR_64 : MyClass<64, [v2i32], (add GPR64)>;
 def GPR_128 : MyClass<128, [v4i32], (add GPR128)>;
 
 
 def MyTarget : Target;
 
 // CHECK: static const uint8_t CostPerUseTable[] = {
-// CHECK-NEXT:  0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, };
+// CHECK-NEXT:  0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 0, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, };
 
 // CHECK:  static const TargetRegisterInfoDesc MyTargetRegInfoDesc = { // Extra Descriptors
 // CHECK-NEXT:  CostPerUseTable, 2, InAllocatableClassTable};
 
 // CHECK:  TargetRegisterInfo(&MyTargetRegInfoDesc, RegisterClasses, RegisterClasses+3,

llvm/test/TableGen/range-op-fail.td

+// Each RUN line is scattered.
+
+defvar list_int = !range(4);
+
+#ifdef ERR0
+// RUN: not llvm-tblgen %s -DERR0 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR0
+// ERR0: [[FILE]]:[[@LINE+1]]:32: error: expected one list, got extra value of type 'int'
+defvar errs = !range(list_int, 42);
+#endif
+
+#ifdef ERR1
+// RUN: not llvm-tblgen %s -DERR1 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR1
+// ERR1: [[FILE]]:[[@LINE+1]]:25: error: expected value of type 'int', got 'list<int>'
+defvar errs = !range(0, list_int);
+#endif
+
+#ifdef ERR2
+// RUN: not llvm-tblgen %s -DERR2 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR2
+// ERR2: [[FILE]]:[[@LINE+1]]:15: error: expected at most two values of integer
+defvar errs = !range(0, 42, 255);
+#endif
+
+#ifdef ERR3
+// RUN: not llvm-tblgen %s -DERR3 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR3
+// ERR3: [[FILE]]:[[@LINE+1]]:22: error: expected list or int, got value of type 'string'
+defvar errs = !range("hoge", "fuga");
+#endif
+
+#ifdef ERR4
+// RUN: not llvm-tblgen %s -DERR4 2>&1 | FileCheck -DFILE=%s %s --check-prefix=ERR4
+// ERR4: [[FILE]]:[[@LINE+1]]:22: error: Unknown or reserved token when parsing a value
+defvar errs = !range();
+#endif

llvm/test/TableGen/range-op.td

+// RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+// CHECK: def range_op_ranges {
+def range_op_ranges {
+  // !range(n) generates half-open interval "[0,n)"
+  // CHECK: list<int> idxs8 = [0, 1, 2, 3, 4, 5, 6, 7];
+  list<int> idxs8 = !range(8);
+
+  // !range(m, n) generates half-open interval "[m,n)"
+  // CHECK: list<int> idxs4 = [4, 5, 6, 7];
+  list<int> idxs4 = !range(4, 8);
+
+  // !range(m, n) generates empty set if m >= n
+  // CHECK: list<int> idxs84 = [];
+  list<int> idxs84 = !range(8, 4);
+
+  // !range(list) generates index values for the list. (Not a copy of the list)
+  // CHECK: list<int> idxsl = [0, 1, 2, 3];
+  list<int> idxsl = !range(idxs4);
+
+  // !range(emptylist) generates empty set
+  // CHECK: list<int> idxs0 = [];
+  list<int> idxs0 = !range(idxs84);
+
+  // Example: Dynamic !range(n)
+  // CHECK: list<list<int>> rn = {{\[}}[0, 1, 2, 3], [0, 1, 2, 3, 4], [0, 1, 2, 3, 4, 5], [0, 1, 2, 3, 4, 5, 6]];
+  list<list<int>> rn = !foreach(i, idxs4, !range(i));
+
+  // Example: Dynamic !range(m, n)
+  // CHECK: list<list<int>> rm = {{\[}}[0, 1, 2, 3, 4, 5, 6], [1, 2, 3, 4, 5], [2, 3, 4], [3], [], [], [], []];
+  list<list<int>> rm = !foreach(i, idxs8, !range(i, !sub(7, i)));
+
+  // Example: Dynamic !range(list)
+  // CHECK: list<list<int>> rl = {{\[}}[0, 1, 2, 3, 4, 5, 6], [0, 1, 2, 3, 4], [0, 1, 2], [0], [], [], [], []];
+  list<list<int>> rl = !foreach(r, rm, !range(r));
+}

llvm/utils/TableGen/CodeGenDAGPatterns.cpp

 //===- CodeGenDAGPatterns.cpp - Read DAG patterns from .td file -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 //
 
 static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
   if (Operator->getName() == "set" ||
       Operator->getName() == "implicit")
     return 0;  // All return nothing.
 
   if (Operator->isSubClassOf("Intrinsic"))
-    return CDP.getIntrinsic(Operator).IS.RetVTs.size();
+    return CDP.getIntrinsic(Operator).IS.RetTys.size();
 
   if (Operator->isSubClassOf("SDNode"))
     return CDP.getSDNodeInfo(Operator).getNumResults();
 
   if (Operator->isSubClassOf("PatFrags")) {
     // If we've already parsed this pattern fragment, get it.  Otherwise, handle
     // the forward reference case where one pattern fragment references another
     // before it is processed.
if (isLeaf()) {
 
     return false;
   }
 
   if (const CodeGenIntrinsic *Int = getIntrinsicInfo(CDP)) {
     bool MadeChange = false;
 
     // Apply the result type to the node.
-    unsigned NumRetVTs = Int->IS.RetVTs.size();
-    unsigned NumParamVTs = Int->IS.ParamVTs.size();
+    unsigned NumRetVTs = Int->IS.RetTys.size();
+    unsigned NumParamVTs = Int->IS.ParamTys.size();
 
     for (unsigned i = 0, e = NumRetVTs; i != e; ++i)
-      MadeChange |= UpdateNodeType(i, Int->IS.RetVTs[i], TP);
+      MadeChange |= UpdateNodeType(
+          i, getValueType(Int->IS.RetTys[i]->getValueAsDef("VT")), TP);
 
     if (getNumChildren() != NumParamVTs + 1) {
       TP.error("Intrinsic '" + Int->Name + "' expects " + Twine(NumParamVTs) +
                " operands, not " + Twine(getNumChildren() - 1) + " operands!");
       return false;
     }
 
     // Apply type info to the intrinsic ID.
     MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP);
 
     for (unsigned i = 0, e = getNumChildren()-1; i != e; ++i) {
       MadeChange |= getChild(i+1)->ApplyTypeConstraints(TP, NotRegisters);
 
-      MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i];
-      assert(getChild(i+1)->getNumTypes() == 1 && "Unhandled case");
-      MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP);
+      MVT::SimpleValueType OpVT =
+          getValueType(Int->IS.ParamTys[i]->getValueAsDef("VT"));
+      assert(getChild(i + 1)->getNumTypes() == 1 && "Unhandled case");
+      MadeChange |= getChild(i + 1)->UpdateNodeType(0, OpVT, TP);
     }
     return MadeChange;
   }
 
   if (getOperator()->isSubClassOf("SDNode")) {
     const SDNodeInfo &NI = CDP.getSDNodeInfo(getOperator());
 
     // Check that the number of operands is sane.  Negative operands -> varargs.
TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
   // (intrinsic_* <number>, ..children..).  Pick the right intrinsic node, and
   // convert the intrinsic name to a number.
   if (Operator->isSubClassOf("Intrinsic")) {
     const CodeGenIntrinsic &Int = getDAGPatterns().getIntrinsic(Operator);
     unsigned IID = getDAGPatterns().getIntrinsicID(Operator)+1;
 
     // If this intrinsic returns void, it must have side-effects and thus a
     // chain.
-    if (Int.IS.RetVTs.empty())
+    if (Int.IS.RetTys.empty())
       Operator = getDAGPatterns().get_intrinsic_void_sdnode();
     else if (!Int.ME.doesNotAccessMemory() || Int.hasSideEffects)
       // Has side-effects, requires chain.
       Operator = getDAGPatterns().get_intrinsic_w_chain_sdnode();
     else // Otherwise, no chain.
       Operator = getDAGPatterns().get_intrinsic_wo_chain_sdnode();
 
     Children.insert(Children.begin(), std::make_shared<TreePatternNode>(

llvm/utils/TableGen/CodeGenIntrinsics.h

 //===- CodeGenIntrinsics.h - Intrinsic Class Wrapper -----------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a wrapper class for the 'Intrinsic' TableGen class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_UTILS_TABLEGEN_CODEGENINTRINSICS_H
 #define LLVM_UTILS_TABLEGEN_CODEGENINTRINSICS_H
 
 #include "SDNodeProperties.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/ModRef.h"
 #include <string>
 #include <tuple>
 #include <vector>
 
 namespace llvm {
 class Record;
 class RecordKeeper;
 
-// FIXME: Sweep this in the near future.
-namespace tmp {
-/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
-/// record corresponds to.
-MVT::SimpleValueType getValueType(Record *Rec);
-} // namespace tmp
-
 struct CodeGenIntrinsic {
   Record *TheDef;             // The actual record defining this intrinsic.
   std::string Name;           // The name of the LLVM function "llvm.bswap.i32"
   std::string EnumName;       // The name of the enum "bswap_i32"
   std::string ClangBuiltinName; // Name of the corresponding GCC builtin, or "".
   std::string MSBuiltinName;  // Name of the corresponding MS builtin, or "".
   std::string TargetPrefix;   // Target prefix, e.g. "ppc" for t-s intrinsics.
 
   /// This structure holds the return values and parameter values of an
   /// intrinsic. If the number of return values is > 1, then the intrinsic
   /// implicitly returns a first-class aggregate. The numbering of the types
   /// starts at 0 with the first return value and continues from there through
   /// the parameter list. This is useful for "matching" types.
   struct IntrinsicSignature {
     /// The MVT::SimpleValueType for each return type. Note that this list is
     /// only populated when in the context of a target .td file. When building
     /// Intrinsics.td, this isn't available, because we don't know the target
     /// pointer size.
-    std::vector<MVT::SimpleValueType> RetVTs;
-
-    /// The records for each return type.
-    std::vector<Record *> RetTypeDefs;
+    std::vector<Record *> RetTys;
 
     /// The MVT::SimpleValueType for each parameter type. Note that this list is
     /// only populated when in the context of a target .td file.  When building
     /// Intrinsics.td, this isn't available, because we don't know the target
     /// pointer size.
-    std::vector<MVT::SimpleValueType> ParamVTs;
-
-    /// The records for each parameter type.
-    std::vector<Record *> ParamTypeDefs;
+    std::vector<Record *> ParamTys;
   };
 
   IntrinsicSignature IS;
 
   /// Memory effects of the intrinsic.
   MemoryEffects ME = MemoryEffects::unknown();
 
   /// SDPatternOperator Properties applied to the intrinsic.

llvm/utils/TableGen/CodeGenIntrinsics.cpp

 //===- CodeGenIntrinsics.cpp - Intrinsic Class Wrapper --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a wrapper class for the 'Intrinsic' TableGen class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenIntrinsics.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include <algorithm>
 #include <cassert>
 using namespace llvm;
-using namespace llvm::tmp;
-
-/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
-/// record corresponds to.
-MVT::SimpleValueType llvm::tmp::getValueType(Record *Rec) {
-  return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
-}
 
 //===----------------------------------------------------------------------===//
 // CodeGenIntrinsic Implementation
 //===----------------------------------------------------------------------===//
 
 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
   std::vector<Record *> IntrProperties =
       RC.getAllDerivedDefinitions("IntrinsicProperty");
CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
   if (!TargetPrefix.empty()) {
     if (Name.size() < 6 + TargetPrefix.size() ||
         Name.substr(5, 1 + TargetPrefix.size()) != (TargetPrefix + "."))
       PrintFatalError(DefLoc, "Intrinsic '" + DefName +
                                   "' does not start with 'llvm." +
                                   TargetPrefix + ".'!");
   }
 
-  ListInit *RetTypes = R->getValueAsListInit("RetTypes");
-  ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
-
-  // First collate a list of overloaded types.
-  std::vector<MVT::SimpleValueType> OverloadedVTs;
-  for (ListInit *TypeList : {RetTypes, ParamTypes}) {
-    for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
-      Record *TyEl = TypeList->getElementAsRecord(i);
-      assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
-
-      if (TyEl->isSubClassOf("LLVMMatchType"))
-        continue;
-
-      MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
-      if (MVT(VT).isOverloaded()) {
-        OverloadedVTs.push_back(VT);
-        isOverloaded = true;
-      }
-    }
-  }
-
-  // Parse the list of return types.
-  ListInit *TypeList = RetTypes;
-  for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
-    Record *TyEl = TypeList->getElementAsRecord(i);
-    assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
-    MVT::SimpleValueType VT;
-    if (TyEl->isSubClassOf("LLVMMatchType")) {
-      unsigned MatchTy = TyEl->getValueAsInt("Number");
-      assert(MatchTy < OverloadedVTs.size() && "Invalid matching number!");
-      VT = OverloadedVTs[MatchTy];
-      // It only makes sense to use the extended and truncated vector element
-      // variants with iAny types; otherwise, if the intrinsic is not
-      // overloaded, all the types can be specified directly.
-      assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
-               !TyEl->isSubClassOf("LLVMTruncatedType")) ||
-              VT == MVT::iAny || VT == MVT::vAny) &&
-             "Expected iAny or vAny type");
-    } else {
-      VT = getValueType(TyEl->getValueAsDef("VT"));
-    }
-
-    // Reject invalid types.
-    if (VT == MVT::isVoid)
-      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
-                                  " has void in result type list!");
-
-    IS.RetVTs.push_back(VT);
-    IS.RetTypeDefs.push_back(TyEl);
-  }
-
-  // Parse the list of parameter types.
-  TypeList = ParamTypes;
-  for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
-    Record *TyEl = TypeList->getElementAsRecord(i);
-    assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
-    MVT::SimpleValueType VT;
-    if (TyEl->isSubClassOf("LLVMMatchType")) {
-      unsigned MatchTy = TyEl->getValueAsInt("Number");
-      if (MatchTy >= OverloadedVTs.size()) {
-        PrintError(R->getLoc(), "Parameter #" + Twine(i) +
-                                    " has out of bounds matching "
-                                    "number " +
-                                    Twine(MatchTy));
-        PrintFatalError(DefLoc,
-                        Twine("ParamTypes is ") + TypeList->getAsString());
-      }
-      VT = OverloadedVTs[MatchTy];
-      // It only makes sense to use the extended and truncated vector element
-      // variants with iAny types; otherwise, if the intrinsic is not
-      // overloaded, all the types can be specified directly.
-      assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
-               !TyEl->isSubClassOf("LLVMTruncatedType")) ||
-              VT == MVT::iAny || VT == MVT::vAny) &&
-             "Expected iAny or vAny type");
-    } else
-      VT = getValueType(TyEl->getValueAsDef("VT"));
-
-    // Reject invalid types.
-    if (VT == MVT::isVoid && i != e - 1 /*void at end means varargs*/)
-      PrintFatalError(DefLoc, "Intrinsic '" + DefName +
-                                  " has void in result type list!");
+  if (auto *Types = R->getValue("Types")) {
+    auto *TypeList = dyn_cast<ListInit>(Types->getValue());
+    isOverloaded = R->getValueAsBit("isOverloaded");
+
+    unsigned I = 0;
+    for (unsigned E = R->getValueAsListInit("RetTypes")->size(); I < E; ++I)
+      IS.RetTys.push_back(TypeList->getElementAsRecord(I));
 
-    IS.ParamVTs.push_back(VT);
-    IS.ParamTypeDefs.push_back(TyEl);
+    for (unsigned E = TypeList->size(); I < E; ++I)
+      IS.ParamTys.push_back(TypeList->getElementAsRecord(I));
   }
 
   // Parse the intrinsic properties.
   ListInit *PropList = R->getValueAsListInit("IntrProperties");
   for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
     Record *Property = PropList->getElementAsRecord(i);
     assert(Property->isSubClassOf("IntrinsicProperty") &&
            "Expected a property!");
else if (R->isSubClassOf("NoCapture")) {
     unsigned ArgNo = R->getValueAsInt("ArgNo");
     uint64_t Align = R->getValueAsInt("Align");
     addArgAttribute(ArgNo, Alignment, Align);
   } else
     llvm_unreachable("Unknown property!");
 }
 
 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
-  if (ParamIdx >= IS.ParamVTs.size())
+  if (ParamIdx >= IS.ParamTys.size())
     return false;
-  MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
-  return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
+  return (IS.ParamTys[ParamIdx]->isSubClassOf("LLVMQualPointerType") ||
+          IS.ParamTys[ParamIdx]->isSubClassOf("LLVMAnyPointerType"));
 }
 
 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
   // Convert argument index to attribute index starting from `FirstArgIndex`.
   ++ParamIdx;
   if (ParamIdx >= ArgumentAttributes.size())
     return false;
   ArgAttribute Val{ImmArg, 0};

llvm/utils/TableGen/IntrinsicEmitter.cpp

 //===- IntrinsicEmitter.cpp - Generate intrinsic information --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend emits information about intrinsic functions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenIntrinsics.h"
 #include "SequenceToOffsetTable.h"
 #include "TableGenBackends.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/ModRef.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/StringToOffsetTable.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
 #include <cassert>
 #include <map>
 #include <optional>
 #include <string>
 #include <utility>
 #include <vector>
 using namespace llvm;
-using namespace llvm::tmp;
 
 cl::OptionCategory GenIntrinsicCat("Options for -gen-intrinsic-enums");
 cl::opt<std::string>
     IntrinsicPrefix("intrinsic-prefix",
                     cl::desc("Generate intrinsics with this target prefix"),
                     cl::value_desc("target prefix"), cl::cat(GenIntrinsicCat));
 
 namespace {
 class IntrinsicEmitter {
   RecordKeeper &Records;
 
 public:
   IntrinsicEmitter(RecordKeeper &R) : Records(R) {}
 
   void run(raw_ostream &OS, bool Enums);
 
   void EmitEnumInfo(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
+  void EmitArgKind(raw_ostream &OS);
+  void EmitIITInfo(raw_ostream &OS);
   void EmitTargetInfo(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
   void EmitIntrinsicToNameTable(const CodeGenIntrinsicTable &Ints,
                                 raw_ostream &OS);
   void EmitIntrinsicToOverloadTable(const CodeGenIntrinsicTable &Ints,
                                     raw_ostream &OS);
   void EmitGenerator(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
   void EmitAttributes(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
   void EmitIntrinsicToBuiltinMap(const CodeGenIntrinsicTable &Ints, bool IsClang,
                                  raw_ostream &OS);
 };
 } // End anonymous namespace
 
 //===----------------------------------------------------------------------===//
 // IntrinsicEmitter Implementation
 //===----------------------------------------------------------------------===//
 
 void IntrinsicEmitter::run(raw_ostream &OS, bool Enums) {
   emitSourceFileHeader("Intrinsic Function Source Fragment", OS);
 
   CodeGenIntrinsicTable Ints(Records);
 
   if (Enums) {
     // Emit the enum information.
     EmitEnumInfo(Ints, OS);
+
+    // Emit ArgKind for Intrinsics.h.
+    EmitArgKind(OS);
   } else {
+    // Emit IIT_Info constants.
+    EmitIITInfo(OS);
+
     // Emit the target metadata.
     EmitTargetInfo(Ints, OS);
 
     // Emit the intrinsic ID -> name table.
     EmitIntrinsicToNameTable(Ints, OS);
 
     // Emit the intrinsic ID -> overload table.
     EmitIntrinsicToOverloadTable(Ints, OS);
for (const auto &Target : Ints.Targets)
       if (!Target.Name.empty())
         KnownTargets.push_back(Target.Name);
     PrintFatalError("tried to generate intrinsics for unknown target " +
                     IntrinsicPrefix +
                     "\nKnown targets are: " + join(KnownTargets, ", ") + "\n");
   }
 
   // Generate a complete header for target specific intrinsics.
-  if (!IntrinsicPrefix.empty()) {
+  if (IntrinsicPrefix.empty()) {
+    OS << "#ifdef GET_INTRINSIC_ENUM_VALUES\n";
+  } else {
     std::string UpperPrefix = StringRef(IntrinsicPrefix).upper();
     OS << "#ifndef LLVM_IR_INTRINSIC_" << UpperPrefix << "_ENUMS_H\n";
     OS << "#define LLVM_IR_INTRINSIC_" << UpperPrefix << "_ENUMS_H\n\n";
     OS << "namespace llvm {\n";
     OS << "namespace Intrinsic {\n";
     OS << "enum " << UpperPrefix << "Intrinsics : unsigned {\n";
   }
 
for (unsigned i = Set->Offset, e = Set->Offset + Set->Count; i != e; ++i) {
     if (Ints[i].EnumName.size() < 40)
       OS.indent(40 - Ints[i].EnumName.size());
     OS << " // " << Ints[i].Name << "\n";
   }
 
   // Emit num_intrinsics into the target neutral enum.
   if (IntrinsicPrefix.empty()) {
     OS << "    num_intrinsics = " << (Ints.size() + 1) << "\n";
+    OS << "#endif\n\n";
   } else {
     OS << "}; // enum\n";
     OS << "} // namespace Intrinsic\n";
     OS << "} // namespace llvm\n\n";
     OS << "#endif\n";
   }
 }
 
+void IntrinsicEmitter::EmitArgKind(raw_ostream &OS) {
+  if (!IntrinsicPrefix.empty())
+    return;
+  OS << "// llvm::Intrinsic::IITDescriptor::ArgKind\n";
+  OS << "#ifdef GET_INTRINSIC_ARGKIND\n";
+  if (auto RecArgKind = Records.getDef("ArgKind")) {
+    for (auto &RV : RecArgKind->getValues())
+      OS << "    AK_" << RV.getName() << " = " << *RV.getValue() << ",\n";
+  } else {
+    OS << "#error \"ArgKind is not defined\"\n";
+  }
+  OS << "#endif\n\n";
+}
+
+void IntrinsicEmitter::EmitIITInfo(raw_ostream &OS) {
+  OS << "#ifdef GET_INTRINSIC_IITINFO\n";
+  std::vector<StringRef> RecsByNumber(256);
+  auto IIT_Base = Records.getAllDerivedDefinitionsIfDefined("IIT_Base");
+  for (auto Rec : IIT_Base) {
+    auto Number = Rec->getValueAsInt("Number");
+    assert(0 <= Number && Number < 256 && "IIT_Info.Number should be uint8_t");
+    assert(RecsByNumber[Number].empty() && "Duplicate IIT_Info.Number");
+    RecsByNumber[Number] = Rec->getName();
+  }
+  if (IIT_Base.size() > 0) {
+    for (unsigned I = 0, E = RecsByNumber.size(); I < E; ++I)
+      if (!RecsByNumber[I].empty())
+        OS << "  " << RecsByNumber[I] << " = " << I << ",\n";
+  } else {
+    OS << "#error \"class IIT_Base is not defined\"\n";
+  }
+  OS << "#endif\n\n";
+}
+
 void IntrinsicEmitter::EmitTargetInfo(const CodeGenIntrinsicTable &Ints,
                                     raw_ostream &OS) {
   OS << "// Target mapping\n";
   OS << "#ifdef GET_INTRINSIC_TARGET_DATA\n";
   OS << "struct IntrinsicTargetInfo {\n"
      << "  llvm::StringLiteral Name;\n"
      << "  size_t Offset;\n"
      << "  size_t Count;\n"
if (Ints[i].isOverloaded)
       OS << " | (1<<" << (i+1)%8 << ')';
   }
   OS << "\n};\n\n";
   // OTable contains a true bit at the position if the intrinsic is overloaded.
   OS << "return (OTable[id/8] & (1 << (id%8))) != 0;\n";
   OS << "#endif\n\n";
 }
 
-
-// NOTE: This must be kept in synch with the copy in lib/IR/Function.cpp!
-enum IIT_Info {
-  // Common values should be encoded with 0-15.
-  IIT_Done = 0,
-  IIT_I1 = 1,
-  IIT_I8 = 2,
-  IIT_I16 = 3,
-  IIT_I32 = 4,
-  IIT_I64 = 5,
-  IIT_F16 = 6,
-  IIT_F32 = 7,
-  IIT_F64 = 8,
-  IIT_V2 = 9,
-  IIT_V4 = 10,
-  IIT_V8 = 11,
-  IIT_V16 = 12,
-  IIT_V32 = 13,
-  IIT_PTR = 14,
-  IIT_ARG = 15,
-
-  // Values from 16+ are only encodable with the inefficient encoding.
-  IIT_V64 = 16,
-  IIT_MMX = 17,
-  IIT_TOKEN = 18,
-  IIT_METADATA = 19,
-  IIT_EMPTYSTRUCT = 20,
-  IIT_STRUCT2 = 21,
-  IIT_STRUCT3 = 22,
-  IIT_STRUCT4 = 23,
-  IIT_STRUCT5 = 24,
-  IIT_EXTEND_ARG = 25,
-  IIT_TRUNC_ARG = 26,
-  IIT_ANYPTR = 27,
-  IIT_V1 = 28,
-  IIT_VARARG = 29,
-  IIT_HALF_VEC_ARG = 30,
-  IIT_SAME_VEC_WIDTH_ARG = 31,
-  IIT_PTR_TO_ARG = 32,
-  IIT_PTR_TO_ELT = 33,
-  IIT_VEC_OF_ANYPTRS_TO_ELT = 34,
-  IIT_I128 = 35,
-  IIT_V512 = 36,
-  IIT_V1024 = 37,
-  IIT_STRUCT6 = 38,
-  IIT_STRUCT7 = 39,
-  IIT_STRUCT8 = 40,
-  IIT_F128 = 41,
-  IIT_VEC_ELEMENT = 42,
-  IIT_SCALABLE_VEC = 43,
-  IIT_SUBDIVIDE2_ARG = 44,
-  IIT_SUBDIVIDE4_ARG = 45,
-  IIT_VEC_OF_BITCASTS_TO_INT = 46,
-  IIT_V128 = 47,
-  IIT_BF16 = 48,
-  IIT_STRUCT9 = 49,
-  IIT_V256 = 50,
-  IIT_AMX = 51,
-  IIT_PPCF128 = 52,
-  IIT_V3 = 53,
-  IIT_EXTERNREF = 54,
-  IIT_FUNCREF = 55,
-  IIT_ANYPTR_TO_ELT = 56,
-  IIT_I2 = 57,
-  IIT_I4 = 58,
-};
-
-static void EncodeFixedValueType(MVT::SimpleValueType VT,
-                                 std::vector<unsigned char> &Sig) {
-  // clang-format off
-  if (MVT(VT).isInteger()) {
-    unsigned BitWidth = MVT(VT).getFixedSizeInBits();
-    switch (BitWidth) {
-    default: PrintFatalError("unhandled integer type width in intrinsic!");
-    case 1: return Sig.push_back(IIT_I1);
-    case 2: return Sig.push_back(IIT_I2);
-    case 4: return Sig.push_back(IIT_I4);
-    case 8: return Sig.push_back(IIT_I8);
-    case 16: return Sig.push_back(IIT_I16);
-    case 32: return Sig.push_back(IIT_I32);
-    case 64: return Sig.push_back(IIT_I64);
-    case 128: return Sig.push_back(IIT_I128);
-    }
-  }
-
-  switch (VT) {
-  default: PrintFatalError("unhandled MVT in intrinsic!");
-  case MVT::f16: return Sig.push_back(IIT_F16);
-  case MVT::bf16: return Sig.push_back(IIT_BF16);
-  case MVT::f32: return Sig.push_back(IIT_F32);
-  case MVT::f64: return Sig.push_back(IIT_F64);
-  case MVT::f128: return Sig.push_back(IIT_F128);
-  case MVT::ppcf128: return Sig.push_back(IIT_PPCF128);
-  case MVT::token: return Sig.push_back(IIT_TOKEN);
-  case MVT::Metadata: return Sig.push_back(IIT_METADATA);
-  case MVT::x86mmx: return Sig.push_back(IIT_MMX);
-  case MVT::x86amx: return Sig.push_back(IIT_AMX);
-  // MVT::OtherVT is used to mean the empty struct type here.
-  case MVT::Other: return Sig.push_back(IIT_EMPTYSTRUCT);
-  // MVT::isVoid is used to represent varargs here.
-  case MVT::isVoid: return Sig.push_back(IIT_VARARG);
-  case MVT::externref:
-    return Sig.push_back(IIT_EXTERNREF);
-  case MVT::funcref:
-    return Sig.push_back(IIT_FUNCREF);
-  }
-  // clang-format on
-}
-
-#if defined(_MSC_VER) && !defined(__clang__)
-#pragma optimize("",off) // MSVC 2015 optimizer can't deal with this function.
-#endif
-
-static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
-                            unsigned &NextArgCode,
-                            std::vector<unsigned char> &Sig,
-                            ArrayRef<unsigned char> Mapping) {
-
-  if (R->isSubClassOf("LLVMMatchType")) {
-    unsigned Number = Mapping[R->getValueAsInt("Number")];
-    assert(Number < ArgCodes.size() && "Invalid matching number!");
-    if (R->isSubClassOf("LLVMExtendedType"))
-      Sig.push_back(IIT_EXTEND_ARG);
-    else if (R->isSubClassOf("LLVMTruncatedType"))
-      Sig.push_back(IIT_TRUNC_ARG);
-    else if (R->isSubClassOf("LLVMHalfElementsVectorType"))
-      Sig.push_back(IIT_HALF_VEC_ARG);
-    else if (R->isSubClassOf("LLVMScalarOrSameVectorWidth")) {
-      Sig.push_back(IIT_SAME_VEC_WIDTH_ARG);
-      Sig.push_back((Number << 3) | ArgCodes[Number]);
-      MVT::SimpleValueType VT = getValueType(R->getValueAsDef("ElTy"));
-      EncodeFixedValueType(VT, Sig);
-      return;
-    }
-    else if (R->isSubClassOf("LLVMPointerTo"))
-      Sig.push_back(IIT_PTR_TO_ARG);
-    else if (R->isSubClassOf("LLVMVectorOfAnyPointersToElt")) {
-      Sig.push_back(IIT_VEC_OF_ANYPTRS_TO_ELT);
-      // Encode overloaded ArgNo
-      Sig.push_back(NextArgCode++);
-      // Encode LLVMMatchType<Number> ArgNo
-      Sig.push_back(Number);
-      return;
-    } else if (R->isSubClassOf("LLVMAnyPointerToElt")) {
-      Sig.push_back(IIT_ANYPTR_TO_ELT);
-      // Encode overloaded ArgNo
-      Sig.push_back(NextArgCode++);
-      // Encode LLVMMatchType<Number> ArgNo
-      Sig.push_back(Number);
-      return;
-    } else if (R->isSubClassOf("LLVMPointerToElt"))
-      Sig.push_back(IIT_PTR_TO_ELT);
-    else if (R->isSubClassOf("LLVMVectorElementType"))
-      Sig.push_back(IIT_VEC_ELEMENT);
-    else if (R->isSubClassOf("LLVMSubdivide2VectorType"))
-      Sig.push_back(IIT_SUBDIVIDE2_ARG);
-    else if (R->isSubClassOf("LLVMSubdivide4VectorType"))
-      Sig.push_back(IIT_SUBDIVIDE4_ARG);
-    else if (R->isSubClassOf("LLVMVectorOfBitcastsToInt"))
-      Sig.push_back(IIT_VEC_OF_BITCASTS_TO_INT);
-    else
-      Sig.push_back(IIT_ARG);
-    return Sig.push_back((Number << 3) | 7 /*IITDescriptor::AK_MatchType*/);
-  }
-
-  MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT"));
-
-  unsigned Tmp = 0;
-  switch (VT) {
-  default: break;
-  case MVT::iPTRAny: ++Tmp; [[fallthrough]];
-  case MVT::vAny: ++Tmp;    [[fallthrough]];
-  case MVT::fAny: ++Tmp;    [[fallthrough]];
-  case MVT::iAny: ++Tmp;    [[fallthrough]];
-  case MVT::Any: {
-    // If this is an "any" valuetype, then the type is the type of the next
-    // type in the list specified to getIntrinsic().
-    Sig.push_back(IIT_ARG);
-
-    // Figure out what arg # this is consuming, and remember what kind it was.
-    assert(NextArgCode < ArgCodes.size() && ArgCodes[NextArgCode] == Tmp &&
-           "Invalid or no ArgCode associated with overloaded VT!");
-    unsigned ArgNo = NextArgCode++;
-
-    // Encode what sort of argument it must be in the low 3 bits of the ArgNo.
-    return Sig.push_back((ArgNo << 3) | Tmp);
-  }
-
-  case MVT::iPTR: {
-    unsigned AddrSpace = 0;
-    if (R->isSubClassOf("LLVMQualPointerType")) {
-      AddrSpace = R->getValueAsInt("AddrSpace");
-      assert(AddrSpace < 256 && "Address space exceeds 255");
-    }
-    if (AddrSpace) {
-      Sig.push_back(IIT_ANYPTR);
-      Sig.push_back(AddrSpace);
-    } else {
-      Sig.push_back(IIT_PTR);
-    }
-    return EncodeFixedType(R->getValueAsDef("ElTy"), ArgCodes, NextArgCode, Sig,
-                           Mapping);
-  }
-  }
-
-  if (MVT(VT).isVector()) {
-    MVT VVT = VT;
-    if (VVT.isScalableVector())
-      Sig.push_back(IIT_SCALABLE_VEC);
-    switch (VVT.getVectorMinNumElements()) {
-    default: PrintFatalError("unhandled vector type width in intrinsic!");
-    case 1: Sig.push_back(IIT_V1); break;
-    case 2: Sig.push_back(IIT_V2); break;
-    case 3: Sig.push_back(IIT_V3); break;
-    case 4: Sig.push_back(IIT_V4); break;
-    case 8: Sig.push_back(IIT_V8); break;
-    case 16: Sig.push_back(IIT_V16); break;
-    case 32: Sig.push_back(IIT_V32); break;
-    case 64: Sig.push_back(IIT_V64); break;
-    case 128: Sig.push_back(IIT_V128); break;
-    case 256: Sig.push_back(IIT_V256); break;
-    case 512: Sig.push_back(IIT_V512); break;
-    case 1024: Sig.push_back(IIT_V1024); break;
-    }
-
-    return EncodeFixedValueType(VVT.getVectorElementType().SimpleTy, Sig);
-  }
-
-  EncodeFixedValueType(VT, Sig);
-}
-
-static void UpdateArgCodes(Record *R, std::vector<unsigned char> &ArgCodes,
-                           unsigned int &NumInserted,
-                           SmallVectorImpl<unsigned char> &Mapping) {
-  if (R->isSubClassOf("LLVMMatchType")) {
-    if (R->isSubClassOf("LLVMVectorOfAnyPointersToElt")) {
-      ArgCodes.push_back(3 /*vAny*/);
-      ++NumInserted;
-    } else if (R->isSubClassOf("LLVMAnyPointerToElt")) {
-      ArgCodes.push_back(4 /*iPTRAny*/);
-      ++NumInserted;
-    }
-    return;
-  }
-
-  unsigned Tmp = 0;
-  switch (getValueType(R->getValueAsDef("VT"))) {
-  default: break;
-  case MVT::iPTR:
-    UpdateArgCodes(R->getValueAsDef("ElTy"), ArgCodes, NumInserted, Mapping);
-    break;
-  case MVT::iPTRAny:
-    ++Tmp;
-    [[fallthrough]];
-  case MVT::vAny:
-    ++Tmp;
-    [[fallthrough]];
-  case MVT::fAny:
-    ++Tmp;
-    [[fallthrough]];
-  case MVT::iAny:
-    ++Tmp;
-    [[fallthrough]];
-  case MVT::Any:
-    unsigned OriginalIdx = ArgCodes.size() - NumInserted;
-    assert(OriginalIdx >= Mapping.size());
-    Mapping.resize(OriginalIdx+1);
-    Mapping[OriginalIdx] = ArgCodes.size();
-    ArgCodes.push_back(Tmp);
-    break;
-  }
-}
-
-#if defined(_MSC_VER) && !defined(__clang__)
-#pragma optimize("",on)
-#endif
-
 /// ComputeFixedEncoding - If we can encode the type signature for this
 /// intrinsic into 32 bits, return it.  If not, return ~0U.
 static void ComputeFixedEncoding(const CodeGenIntrinsic &Int,
                                  std::vector<unsigned char> &TypeSig) {
-  std::vector<unsigned char> ArgCodes;
-
-  // Add codes for any overloaded result VTs.
-  unsigned int NumInserted = 0;
-  SmallVector<unsigned char, 8> ArgMapping;
-  for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i)
-    UpdateArgCodes(Int.IS.RetTypeDefs[i], ArgCodes, NumInserted, ArgMapping);
-
-  // Add codes for any overloaded operand VTs.
-  for (unsigned i = 0, e = Int.IS.ParamTypeDefs.size(); i != e; ++i)
-    UpdateArgCodes(Int.IS.ParamTypeDefs[i], ArgCodes, NumInserted, ArgMapping);
-
-  unsigned NextArgCode = 0;
-  if (Int.IS.RetVTs.empty())
-    TypeSig.push_back(IIT_Done);
-  else if (Int.IS.RetVTs.size() == 1 &&
-           Int.IS.RetVTs[0] == MVT::isVoid)
-    TypeSig.push_back(IIT_Done);
-  else {
-    switch (Int.IS.RetVTs.size()) {
-      case 1: break;
-      case 2: TypeSig.push_back(IIT_STRUCT2); break;
-      case 3: TypeSig.push_back(IIT_STRUCT3); break;
-      case 4: TypeSig.push_back(IIT_STRUCT4); break;
-      case 5: TypeSig.push_back(IIT_STRUCT5); break;
-      case 6: TypeSig.push_back(IIT_STRUCT6); break;
-      case 7: TypeSig.push_back(IIT_STRUCT7); break;
-      case 8: TypeSig.push_back(IIT_STRUCT8); break;
-      case 9: TypeSig.push_back(IIT_STRUCT9); break;
-      default: llvm_unreachable("Unhandled case in struct");
-    }
-
-    for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i)
-      EncodeFixedType(Int.IS.RetTypeDefs[i], ArgCodes, NextArgCode, TypeSig,
-                      ArgMapping);
-  }
-
-  for (unsigned i = 0, e = Int.IS.ParamTypeDefs.size(); i != e; ++i)
-    EncodeFixedType(Int.IS.ParamTypeDefs[i], ArgCodes, NextArgCode, TypeSig,
-                    ArgMapping);
+  if (auto *R = Int.TheDef->getValue("TypeSig")) {
+    for (auto &a : dyn_cast<ListInit>(R->getValue())->getValues()) {
+      for (auto &b : dyn_cast<ListInit>(a)->getValues())
+        TypeSig.push_back(dyn_cast<IntInit>(b)->getValue());
+    }
+  }
 }
 
 static void printIITEntry(raw_ostream &OS, unsigned char X) {
   OS << (unsigned)X;
 }
 
 void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
                                      raw_ostream &OS) {