[X86][FP16] Optimize FMAXNUM/FMINNUM into SMAX/SMIN for FP16 emulation under fast math

[pengfei]

Summary

We don't need to promote it to f32 FMAXNUM/FMINNUM if we can make sure
no NaN in inputs.

Fixes #61271

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

53168–53184

We might need to improve soft float test coverage?

llvm/test/CodeGen/X86/half.ll

1368

It seems a shame to scalarize this when we're already on the FPU, and we have pminsw/pmaxsw since SSE2

[pengfei]

Address review commnets.

llvm/lib/Target/X86/X86ISelLowering.cpp

53168–53184

Good catch! I didn't intend to support soft float. And IIRC, we have problems in supporting soft float. So bail it out.

llvm/test/CodeGen/X86/half.ll

1368

Good point! We can vectorize it first, though we still need to improve the f16 extract.

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

53178

I forget the encoding of exponent. Is the result same for min(vXf16) and min(i16)?

[pengfei]

The negative comparison is not correct.

llvm/lib/Target/X86/X86ISelLowering.cpp

53178

Thanks for the reminding. Review it again, I found it is only correct to positive value. The reason is FP is represented in Sign-Magnitude while integer is 2’s Complement Code. Let me try to think out some way to solve it.

llvm/lib/Target/X86/X86ISelLowering.cpp

   }
 
   return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
                      N->getOperand(0), N->getOperand(1));
 }
 
 static SDValue combineFMinNumFMaxNum(SDNode *N, SelectionDAG &DAG,
                                      const X86Subtarget &Subtarget) {
+  if (Subtarget.useSoftFloat())
+    return SDValue();
+
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  SDLoc DL(N);
+
   EVT VT = N->getValueType(0);
-  if (Subtarget.useSoftFloat() || isSoftFP16(VT, Subtarget))
+  if (isSoftFP16(VT, Subtarget)) {
+    if (DAG.getTarget().Options.NoNaNsFPMath || N->getFlags().hasNoNaNs()) {
+      auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? ISD::SMAX : ISD::SMIN;
+      EVT NVT = MVT::v8i16;
+      if (VT.isVector()) {
+        NVT = VT.changeVectorElementTypeToInteger();
+      } else {
+        Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v8f16, Op0);
+        Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v8f16, Op1);
+      }
+      SDValue Res = DAG.getNode(MinMaxOp, DL, NVT, DAG.getBitcast(NVT, Op0),
+                                DAG.getBitcast(NVT, Op1));
+      if (!VT.isVector())
+        Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i16, Res,
+                          DAG.getIntPtrConstant(0, DL));
+      return DAG.getBitcast(VT, Res);
+    }
     return SDValue();
+  }
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
   if (!((Subtarget.hasSSE1() && VT == MVT::f32) ||
         (Subtarget.hasSSE2() && VT == MVT::f64) ||
         (Subtarget.hasFP16() && VT == MVT::f16) ||
         (VT.isVector() && TLI.isTypeLegal(VT))))
     return SDValue();
 
-  SDValue Op0 = N->getOperand(0);
-  SDValue Op1 = N->getOperand(1);
-  SDLoc DL(N);
   auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN;
 
   // If we don't have to respect NaN inputs, this is a direct translation to x86
   // min/max instructions.
   if (DAG.getTarget().Options.NoNaNsFPMath || N->getFlags().hasNoNaNs())
     return DAG.getNode(MinMaxOp, DL, VT, Op0, Op1, N->getFlags());
 
   // If one of the operands is known non-NaN use the native min/max instructions

llvm/test/CodeGen/X86/half.ll

 ; CHECK-I686-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,4,4]
 ; CHECK-I686-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,2,2,2]
 ; CHECK-I686-NEXT:    retl
   %1 = load <8 x half>, ptr %p, align 8
   %2 = shufflevector <8 x half> %1, <8 x half> poison, <8 x i32> <i32 4, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <8 x half> %2
 }
 
+declare half @llvm.minnum.f16(half, half)
+
+define half @pr61271(half %0, half %1) #0 {
+; CHECK-LIBCALL-LABEL: pr61271:
+; CHECK-LIBCALL:       # %bb.0:
+; CHECK-LIBCALL-NEXT:    pminsw %xmm1, %xmm0
+; CHECK-LIBCALL-NEXT:    movd %xmm0, %eax
+; CHECK-LIBCALL-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK-LIBCALL-NEXT:    retq
+;
+; BWON-F16C-LABEL: pr61271:
+; BWON-F16C:       # %bb.0:
+; BWON-F16C-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
+; BWON-F16C-NEXT:    vmovd %xmm0, %eax
+; BWON-F16C-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; BWON-F16C-NEXT:    retq
+;
+; CHECK-I686-LABEL: pr61271:
+; CHECK-I686:       # %bb.0:
+; CHECK-I686-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm0
+; CHECK-I686-NEXT:    pinsrw $0, {{[0-9]+}}(%esp), %xmm1
+; CHECK-I686-NEXT:    pminsw %xmm0, %xmm1
+; CHECK-I686-NEXT:    movd %xmm1, %eax
+; CHECK-I686-NEXT:    pinsrw $0, %eax, %xmm0
+; CHECK-I686-NEXT:    retl
+  %3 = call fast half @llvm.minnum.f16(half %0, half %1)
+  ret half %3
+}
+
+declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>)
+
+define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 {
+; CHECK-LIBCALL-LABEL: maxnum_v8f16:
+; CHECK-LIBCALL:       # %bb.0:
+; CHECK-LIBCALL-NEXT:    pmaxsw %xmm1, %xmm0
+; CHECK-LIBCALL-NEXT:    retq
+;
+; BWON-F16C-LABEL: maxnum_v8f16:
+; BWON-F16C:       # %bb.0:
+; BWON-F16C-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
+; BWON-F16C-NEXT:    retq
+;
+; CHECK-I686-LABEL: maxnum_v8f16:
+; CHECK-I686:       # %bb.0:
+; CHECK-I686-NEXT:    pmaxsw %xmm1, %xmm0
+; CHECK-I686-NEXT:    retl
+  %3 = call fast <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
+  ret <8 x half> %3
+}
+
 attributes #0 = { nounwind }