[X86][FP16] Optimize FMAXNUM/FMINNUM into SMAX/SMIN for FP16 emulation under fast math

[pengfei]

Summary

We don't need to promote it to f32 FMAXNUM/FMINNUM if we can make sure
no NaN in inputs.

Fixes #61271

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

53168–53184

We might need to improve soft float test coverage?

llvm/test/CodeGen/X86/half.ll

1368

It seems a shame to scalarize this when we're already on the FPU, and we have pminsw/pmaxsw since SSE2

[pengfei]

Address review commnets.

llvm/lib/Target/X86/X86ISelLowering.cpp

53168–53184

Good catch! I didn't intend to support soft float. And IIRC, we have problems in supporting soft float. So bail it out.

llvm/test/CodeGen/X86/half.ll

1368

Good point! We can vectorize it first, though we still need to improve the f16 extract.

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

53178

I forget the encoding of exponent. Is the result same for min(vXf16) and min(i16)?

[pengfei]

The negative comparison is not correct.

llvm/lib/Target/X86/X86ISelLowering.cpp

53178

Thanks for the reminding. Review it again, I found it is only correct to positive value. The reason is FP is represented in Sign-Magnitude while integer is 2’s Complement Code. Let me try to think out some way to solve it.